? integrated circuits group lh 28 f 008 sc r -l 85 fla sh me mor y 8 m ( 1 m 8 ) (model no.: lh f 08 ch 2 ) spec no.: el 10 40 2 9 b issue date: feb ru ar y 1 , 19 99 p roduc t s pecific a tions
sharp lhf08ch2 l handle this document carefully for it contains material protected by international copyright law. any reproduction, full or in part, of this material is prohibited without the express written permission of the company. l when using the products covered herein, please observe the conditions written herein and the precautions outlined in the following paragraphs. in no event shall the company be liable for any damages resulting from failure to strictly adhere to these conditions and precautions. (1) the products covered herein are designed and manufactured for the following application areas. when using the products covered herein for the equipment listed in paragraph (z), even for the following application areas, be sure to observe the precautions given in paragraph (2). never use the products for the equipment listed in paragraph (3). *office electronics l instrumentation and measuring equipment .machine tools @audiovisual equipment *home appliance l communication equipment other than for trunk lines (2) those contemplating using the products covered herein for the following equipment which demands hiah reliability, should first contact a sales representative of the company and then accept responsibility for incorporating into the design fail-safe operation, redundancy, and other appropriate measures for ensuring reliability and safety of the equipment and the overall system. *control and safety devices for airplanes, trains, automobiles, and other transportation equipment l mainframe computers atraffic control systems @gas leak detectors and automatic cutoff devices 6escue and security equipment @other safety devices and safety equipment,etc. (3) do not use the products covered herein for the following equipment which demands extremelv hiqh performance in terms of functionality, reliability, or accuracy. *aerospace equipment *communications equipment for trunk lines *control equipment for the nuclear power industry l medical equipment related to life support, etc. (4) please direct all queries and comments regarding the interpretation of the above three paragraphs to a sales representative of the company. *please direct all queries regarding the products covered herein to a sales representative of the company. rev.l.l
sharp lhfosch2 1 contents page page i .o introduction ................................................... 3 1 .l new features ...................................................... 3 1.2 product overview.. .............................................. 3 2.0 principles of operation.. ........................... 7 2.1 data protection ................................................... 7 3.0 bus operation ................................................. 8 3.1 read ................................................................... 8 3.2 output disable .................................................... 8 3.3 standby.. ............................................................. 8 3.4 deep power-down .............................................. 8 3.5 read identifier codes operation.. ....................... 9 3.6 write .................................................................... 9 5.0 design considerations ............................. .2? 5.1 three-line output control ................................ .2? 5.2 ry/by# and block erase, byte write and lock-bit configuration polling ........................................... 25 5.3 power supply decoupling.. ................................ 24 5.4 v,, trace on printed circuit boards.. ............... .2f 5.5 v,,, v,,, rp# transitions ................................. 24 5.6 power-up/down protection ................................ 24 5.7 power dissipation ............................................. .24 1.0 command definitions. ................................... 9 4.1 read array command.. ..................................... 12 4.2 read identifier codes command ...................... 12 4.3 read status register command.. ..................... 12 4.4 clear status register command.. ..................... 12 4.5 block erase command.. .................................... 12 4.6 byte write command ........................................ 13 4.7 block erase suspend command.. ..................... 13 4.8 byte write suspend command.. ....................... 14 4.9 set block and master lock-bit commands.. ..... 14 4.10 clear block lock-bits command.. ................... 15 6.0 electrical specifications.. ..................... .2e 6.1 absolute maximum ratings ............................... 25 6.2 operating conditions ......................................... 25 6.2.1 capacitance ................................................. 25 6.2.2 ac input/output test conditions.. ............... .2e 6.2.3 dc characteristics ........................................ 27 6.2.4 ac characteristics - read-only operations .2e 6.2.5 ac characteristics - write operations.. ....... .34 6.2.6 alternative ce#-controlled writes.. ............. .3e 6.2.7 reset operations ........................................ .3e 6.2.8 block erase, byte write and lock-bit configuration performance.. ........................ .3e 7.0 additional information ............................ .40 7.1 ordering information .......................................... 40 8.0 package and packing specifications ..4 1 j rev. 1.0
lhf08ch2 2 LH28F008SCR-L85 8-mbit (1 mb x 8) smartvoltage flash memory n smartvoltage technology n enhanced automated suspend options - 2.7v(read-only), 3.3v or 5v vcc - byte write suspend to read - 3.3v, 5v or 12v vpp - block erase suspend to byte write - block erase suspend to read n high-performance read access time - 85ns(5v-c0.25v), 90ns(5vk0.5v), n enhanced data protection features 120ns(3.3v=0.3v), 150ns(2.7v-3.6v) - absolute protection with vpp=gnd - flexible block locking n operating temperature - block erase/byte write lockout - 0c to +7o?c during power transitions n high-density symmetrically-blocked n extended cycling capability architecture - 100,000 block erase cycles - sixteen 64-kbyte erasable blocks - 1.6 million block erase cycles/chip n low power management n industry-standard packaging - deep power-down mode - 40-lead tsop (reverse bend) - automatic power savings mode decreases icc in static mode n etoxtm* nonvolatile flash technology i automated byte write and block erase n cmos process - command user interface (p-type silicon substrate) - status register n not designed or rated as radiation i sram-compatible write interface hardened sharp?s lh28f008scfgl85 flash memory with smartvoltage technology is a high-density, low-cost, nonvolatile, ,ead/write storage solution for a wide range of applications. its symmetrically-blocked architecture, flexible voltage ind extended cycling provide for highly flexible component suitable for resident flash arrays, slmms and memory :ards. its enhanced suspend capabilities provide for an ideal solution for code + data storage applications. for secure code storage applications, such as networking, where code is either directly executed out of flash or downloaded to dram, the LH28F008SCR-L85 offers three levels of protection: absolute protection with v,, at ;nd, selective hardware block locking, or flexible software block locking. these alternatives give designers jltimate control of their code security needs. the LH28F008SCR-L85 is manufactured on sharp?s 0.38um etoxtm process technology. it come in ndustry-standard package: the 40-lead tsop, ideal for board constrained applications. based on the 28f008sa architecture, the LH28F008SCR-L85 enables quick and easy upgrades for designs demanding the state-of-the-art. etox is a trademark of intel corporation. rev.1.11
sharf=@ lhf08ch2 3 1 introduction this datasheet contains lh28f008scrl85 specifications. section 1 provides a flash memory overview. sections 2, 3, 4, and 5 describe the memory organization and functionality. section 6 covers electrical specifications. lh28f008scrl85 flash memory documentation also includes application notes and design tools which are referenced in section 7. 1.1 new features the lh28f008scrl85 smartvoltage flash memory maintains backwards-compatibility with sharp?s ?8f008sa. key enhancements over the 28f008sa nclude: *smartvoltage technology *enhanced suspend capabilities *in-system block locking 30th devices share a compatible pinout, status ,egister, and software command set. these similarities enable a clean upgrade from the !8f008sa to LH28F008SCR-L85. when upgrading, t is important to note the following differences: *because of new feature support, the two devices have different device codes. this allows for software optimization. l vpplk has been lowered from 69 to 1.5v to support 3.3v and 5v block erase, byte write, and lock-bit configuration operations. the v,, voltage transitions to gnd is recommended for designs that switch v,, off during read operation. *to take advantage of smartvoltage technology, allow v,, connection to 3.3v or 5v. i .2 product overview ?he LH28F008SCR-L85 is a high-performance 8-mbit ;martvoltage flash memory organized as 1 mbyte of i bits. the 1 mbyte of data is arranged in sixteen ickbyte blocks which are individually erasable, jckable, and unlockable in-system. the memory lap is shown in figure 3. smartvoltage technology provides a choice of v,, and v,, combinations, as shown in table 1, to meet system performance and power expectations. 2.7v vc, consumes approximately one-fifth the power of 5v voo. but, 5v voo provides the highest read performance. v,, at 3.3v and 5v eliminates the need for a separate 12v converter, while v,,=12v maximizes block erase and byte write performance in addition to flexible erase and program voltages the dedicated v,, p in ives complete data protectior g when v,, i vpplk. table 1. v,, and vp, voltage combinations > note: 1. block erase, byte write and lock-bit configuratior operations with vcoc3.ov are not supported. internal vcc and vp, detection circuit4 automatically configures the device for optimizec read and write operations. a command user interface (cui) serves as the interface between the system processor and interna operation of the device. a valid command sequence written to the cui initiates device automation. ar internal write state machine (wsm) automatically executes the algorithms and timings necessary for block erase, byte write, and lock-bit configuratior operations. a block erase operation erases one of the device?s 64-kbyte blocks typically within 0.3 s (5v v,,, 12v v,,) independent of other blocks. each block can be independently erased 100,000 times (1.6 million block erases per device). block erase suspend mode allows system software to suspend block erase to read or write data from any other block. writing memory data is performed in byte increments typically within 6 us (5v voo, 12v vp,). byte write suspend mode enables the system to read data or execute code from any other flash memory array location. rev. 1.2
sham= lhf08ch2 4 individual block locking uses a combination of bits, sixteen block lock-bits and a master lock-bit, to lock and unlock blocks. block lock-bits gate block erase and byte write operations, while the master lock-bit gates block lock-bit modification. lock-bit configuration operations (set block lock-bit, set master lock-bit, and clear block lock-bits commands) set and cleared lock-bits. the status register indicates when the wsm?s block erase, byte write, or lock-bit configuration operation is finished. the ry/by# output gives an additional indicator of wsm activity by providing both a hardware signal of status (versus software polling) and status masking (interrupt masking for background block erase, for example). status polling using ry/by# minimizes both cpu overhead and system power consumption. when low, ry/by# indicates that the wsm is oerforming a block erase, byte write, or lock-bit zonfiguration. ry/by#-high indicates that the wsm is ?eady for a new command, block erase is suspended [and byte write is inactive), byte write is suspended, or the device is in deep power-down mode. the access time is 85 ns (t,.,,,*,,) over the commercia temperature range (0c to +70x) and vco supply voltage range of 4.75v-5.25v. at lower vco voltages, the access times are 90 ns (4.5v-5sv), 120 ns (3.ov-3.6v) and 150 ns (2.7v-3.6v). the automatic power savings (aps) feature substantially reduces active current when the device is in static mode (addresses not switching). in aps mode, the typical i,,, current is 1 ma at 5v vcc. when ce# and rp# pins are at voc, the icc cmos standby mode is enabled. when the rp# pin is al gnd, deep power-down mode is enabled which minimizes power consumption and provides write protection during reset. a reset time (tphqv) is required from rp# switching high until outputs are valid. likewise, the device has a wake time (tphel) from rp#-high until writes to the cui are recognized. with rp# at gnd, the wsm is reset and the status register is cleared. the device is available in 40-lead tsop (thin small outline package, 1.2 mm thick, reverse bend). pinout is shown in figure 2. rev.1.0
sharp lhf08ch2 5 r . . 3 + * . . . . . . . . . . fff ce# \ve# (x3 rpb? figure 1. block diagram nc nc we# oe# ry/by# dq7 dq6 dq5 dq4 vcc gnd gnd dq3 dq2 dql dqo 2 a2 a3 49 a16 a17 al6 a15 a14 a13 a12 ce# vcc vpp rp# 41 40 a9 a6 a7 a6 a5 a4 40-lead tsop standard pinout 1 omm x 20mm top view figure 2. tsop 40-lead pinout (reverse bend) rev. 1 .ll
sl-iarp r lhf08ch2 6 1 symbol a& 9 dqc-dq, ce# rp# oe# we# ry/by# ?pp ?cc gnd nc type input input/ output input input input input output supply supply supply table 2. pin descriptions name and function address inputs: inputs for addresses during read and write operations. addresses are internally latched during a write cycle. data input/outputs: inputs data and commands durino cui write cycles; outputs data during memory array, status register, and identifier code read cycles. data pins float to high-impedance when the chip is deselected or outputs are disabled. data is internally latched during a write cycle. chip enable: activates the device?s control logic, input buffers, decoders, and sense amplifiers. ce#-high deselects the device and reduces power consumption to standby levels. reset/deep power-down: puts the device in deep power-down mode and resets internal automation. rp#-high enables normal operation. when driven low, rp# inhibits write operations which provides data protection during power transitions. exit from deep power-down sets the device to read array mode. rp# at v,, enables setting of the master lock-bit and enables configuration of block lock-bits when the master lock-bit is set. rp#=v,, overrides block lock-bits thereby enabling block erase and byte write operations to locked memory blocks. block erase, byte write, or lock-bit configuration with vih |