KM23V8000D(g) cmos mask rom preliminary pin name pin function a 0 - a 19 address inputs q 0 - q 7 data outputs ce chip enable oe output enable v cc power v ss ground n.c no connection 8m-bit (1mx8) cmos mask rom the KM23V8000D(g) is a fully static mask programmable rom organized 1,048,576 x 8 bit. it is fabricated using silicon gate cmos process technology. this device operates with 2.7v to 3.6v power supply, and all inputs and outputs are ttl compatible. because of its asynchronous operation, it requires no external clock assuring extremely easy operation. it is suitable for use in program memory of microprocessor, and data memory, character generator. the KM23V8000D is packaged in a 32-dip and the KM23V8000Dg in a 32-sop. general description features ? 1,048,576 x 8 bit organization ? fast access time 3.3v operation : 100ns(max.) 3.0v operation : 120ns(max.) ? supply voltage : 2.7v to 3.6v ? current consumption operating : 30/25ma(max.) standby : 30 ? (max.) ? fully static operation ? all inputs and outputs ttl compatible ? three state outputs ? package -. KM23V8000D : 32-dip-600 -. KM23V8000Dg : 32-sop-525 a 19 x and decoder buffers a 0 y and decoder buffers memory cell sense amp. control logic matrix (1,048,576x8) buffers ce oe . . . . . . . . q 0 q 7 . . . pin configuration n.c a 16 a 15 a 12 a 7 a 6 a 5 a 4 a 3 a 2 a 1 ce oe q 0 q 1 q 4 q 5 q 6 q 7 a 9 q 10 a 11 dip KM23V8000D(g) functional block diagram 1 2 3 4 5 6 7 8 32 31 9 10 30 29 11 12 28 27 13 14 26 25 15 16 24 23 21 21 20 19 18 17 q 2 v ss v cc a 18 a 17 a 14 a 13 a 8 q 3 & sop a 0
KM23V8000D(g) cmos mask rom preliminary absolute maximum ratings note : permanent device damage may occur if "absolute maximum ratings" are exceeded. functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. exposure to absolute maxim um rating conditions for extended periods may affect device reliability. item symbol rating unit voltage on any pin relative to v ss v in -0.3 to +4.5 v temperature under bias t bias -10 to +85 ? storage temperature t stg -55 to +150 ? recommended operating conditions (voltage reference to v ss , t a = 0 to 70 ? ) item symbol min typ max unit supply voltage v cc 2.7/3.0 3.0/3.3 3.3/3.6 v supply voltage v ss 0 0 0 v mode selection ce oe mode data power h x standby high-z standby l h operating high-z active l operating dout active capacitance ( t a =25 ? , f=1.0mhz) note : capacitance is periodically sampled and not 100% tested. item symbol test conditions min max unit output capacitance c out v out =0v - 12 pf input capacitance c in v in =0v - 12 pf dc characteristics note : minimum dc voltage(v il ) is -0.3v an input pins. during transitions, this level may undershoot to -2.0v for periods <20ns. maximum dc voltage on input pins(v ih ) is v cc +0.3v which, during transitions, may overshoot to v cc +2.0v for periods <20ns. parameter symbol test conditions min max unit operating current i cc ce = oe =v il all outputs open v cc =3.3v ?? 0.3v - 30 ma v cc =3.0v ?? 0.3v - 25 ma standby current(ttl) i sb1 ce =v ih , all outputs open - 500 ? standby current(cmos) i sb2 ce =v cc , all outputs open - 30 ? input leakage current i li v in =0 to v cc - 10 ? output leakage current i lo v out =0 to v cc - 10 ? input high voltage, all inputs v ih 2.0 v cc +0.3 v input low voltage, all inputs v il -0.3 0.6 v output high voltage level v oh i oh = -400 ? 2.4 - v output low voltage level v ol i ol = 2.1ma - 0.4 v
KM23V8000D(g) cmos mask rom preliminary test conditions item value input pulse levels 0.45v to 2.4v input rise and fall times 10ns input and output timing levels 1.5v output loads 1 ttl gate and c l =100pf ac characteristics (t a = 0 ? to +70 ? , v cc = 3.3v/3.0v ?? 0.3v, unless otherwise noted.) read cycle item symbol v cc =3.3v ?? 0.3v v cc =3.0v ?? 0.3v unit min max min max read cycle time trc 100 120 ns chip enable access time tace 100 120 ns address access time taa 100 120 ns output enable access time toe 50 60 ns output or chip disable to output high-z tdf 20 20 ns output hold from address change toh 0 0 ns timing diagram read add ce oe d out note : tdf is defined as the time at which the outputs achieve the open circuit condition and is not referenced to v oh or v ol level. t ace t oe add1 add2 t rc valid data valid data t oh t df(note) t aa
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