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| users manual target device v850e1 (nb85e core) ie-v850e-mc-em1-b, IE-V850E-MC-MM2 (sold separately) in-circuit emulator option boards document no. u14482ej2v0um00 (2nd edition) date published november 2000 n cp(k) printed in japan
users manual u14482ej2v0um00 2 [memo] user?s manual u14482ej2v0um00 3 windows is either a registered trademark or a trademark of microsoft corporation in the united states and/or other countries. pc/at is a trademark of international business machines corporation. ethernet is a trademark of xerox corporation. unix is a registered trademark in the united states and other countries, licensed exclusively through x/open company limited. users manual u14482ej2v0um00 4 m8e 00. 4 the information in this document is current as of august, 2000. the information is subject to change without notice. for actual design-in, refer to the latest publications of nec's data sheets or data books, etc., for the most up-to-date specifications of nec semiconductor products. not all products and/or types are available in every country. please check with an nec sales representative for availability and additional information. no part of this document may be copied or reproduced in any form or by any means without prior written consent of nec. nec assumes no responsibility for any errors that may appear in this document. nec does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of nec semiconductor products listed in this document or any other liability arising from the use of such products. no license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec or others. descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software and information in the design of customer's equipment shall be done under the full responsibility of customer. nec assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. while nec endeavours to enhance the quality, reliability and safety of nec semiconductor products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. to minimize risks of damage to property or injury (including death) to persons arising from defects in nec semiconductor products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment, and anti-failure features. nec semiconductor products are classified into the following three quality grades: "standard", "special" and "specific". the "specific" quality grade applies only to semiconductor products developed based on a customer-designated "quality assurance program" for a specific application. the recommended applications of a semiconductor product depend on its quality grade, as indicated below. customers must check the quality grade of each semiconductor product before using it in a particular application. "standard": computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots "special": transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) "specific": aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. the quality grade of nec semiconductor products is "standard" unless otherwise expressly specified in nec's data sheets or data books, etc. if customers wish to use nec semiconductor products in applications not intended by nec, they must contact an nec sales representative in advance to determine nec's willingness to support a given application. (note) (1) "nec" as used in this statement means nec corporation and also includes its majority-owned subsidiaries. (2) "nec semiconductor products" means any semiconductor product developed or manufactured by or for nec (as defined above). users manual u14482ej2v0um00 5 regional information some information contained in this document may vary from country to country. before using any nec product in your application, piease contact the nec office in your country to obtain a list of authorized representatives and distributors. they will verify: device availability ordering information product release schedule availability of related technical literature development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, ac supply voltages, and so forth) network requirements in addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. nec electronics inc. (u.s.) santa clara, california tel: 408-588-6000 800-366-9782 fax: 408-588-6130 800-729-9288 nec electronics (germany) gmbh duesseldorf, germany tel: 0211-65 03 02 fax: 0211-65 03 490 nec electronics (uk) ltd. milton keynes, uk tel: 01908-691-133 fax: 01908-670-290 nec electronics italiana s.r.l. milano, italy tel: 02-66 75 41 fax: 02-66 75 42 99 nec electronics (germany) gmbh benelux office eindhoven, the netherlands tel: 040-2445845 fax: 040-2444580 nec electronics (france) s.a. velizy-villacoublay, france tel: 01-30-67 58 00 fax: 01-30-67 58 99 nec electronics (france) s.a. madrid office madrid, spain tel: 91-504-2787 fax: 91-504-2860 nec electronics (germany) gmbh scandinavia office taeby, sweden tel: 08-63 80 820 fax: 08-63 80 388 nec electronics hong kong ltd. hong kong tel: 2886-9318 fax: 2886-9022/9044 nec electronics hong kong ltd. seoul branch seoul, korea tel: 02-528-0303 fax: 02-528-4411 nec electronics singapore pte. ltd. united square, singapore tel: 65-253-8311 fax: 65-250-3583 nec electronics taiwan ltd. taipei, taiwan tel: 02-2719-2377 fax: 02-2719-5951 nec do brasil s.a. electron devices division guarulhos-sp brasil tel: 55-11-6462-6810 fax: 55-11-6462-6829 j00.7 users manual u14482ej2v0um00 6 [memo] users manual u14482ej2v0um00 7 introduction target readers this manual is intended for users who wish to design and develop application systems using the v850e1 (nb85e core). purpose this manual is intended to give users an understanding of the basic specifications of the ie-v850e-mc-em1-b and its correct usage method. organization the contents of this manual are broadly divided into the following sections. outline parts and functions cautions how to use this manual it is assumed that the readers of this manual have general knowledge in the fields of electrical circuits, logic circuits, and microcontrollers. the ie-v850e-mc-em1-b is used connected to the ie-v850e-mc-a in-circuit emulator. this manual describes the basic setup procedure and the ie-v850e-mc-em1-b switch settings. for the parts and functions of the ie-v850e-mc-a and details about the connection of component parts, refer to the ie-v850e-mc-a users manual (u14487e) . to learn about the basic specifications and usage method: ? read in the order listed in contents . to learn about software-related settings for the ie-v850-mc-a and ie-v850e-mc- em1-b, including the operation procedure and command functions ? refer to the users manual of the debugger (sold separately) to be used. conventions note : footnote for item marked with note in the text caution : information requiring particular attention remark : supplementary information numerical representation: binaryxxxx or xxxxb decimalxxxx hexadecimalxxxxh prefixes representing a power of 2 (address space, memory capacity) k (kilo): 2 10 = 1024 m (mega): 2 20 = 1024 2 terms the meanings of terms used in this manual are listed below. target device this is the device to be emulated. target system the system to be debugged (system created by user). this includes the target program and hardware created by the user. users manual u14482ej2v0um00 8 related documents when using this manual, refer to the following manuals. the related documents listed below may include preliminary versions. however, preliminary versions are not marked as such. documents related to development tools (users manuals) document name document no. ie-v850e-mc, ie-v850e-mc-a (in-circuit emulator) u14487e ie-v850e-mc-em1-b, IE-V850E-MC-MM2 (sold separately) (in-circuit emulator option boards) this manual operation u13998e c language u13997e ca830, ca850 (c compiler package) project manager u13996e ca850 (c compiler package) assembly language u13828e id850 (ver. 2.00 or later) (integrated debugger) operation windows based u14217e sm850 (ver. 2.00 or later) (system simulator) operation windows based u13759e basics u13430e rx850 (real-time os) installations u13410e fundamental u13773e rx850 pro (real-time os) installations u13774e rd850 (ver. 3.0) (task debugger) u13737e rd850 pro (ver. 3.0) (task debugger) u13916e az850 (system performance analyzer) u14410e user?s manual u14482ej2v0um00 9 contents chapter 1 overview.......................................................................................................... ................13 1.1 hardware configuration ...................................................................................................... ......14 1.2 features .................................................................................................................... ..................15 1.3 function specifications (when connected to ie-v850e-mc-a)............................................16 1.4 system configuration........................................................................................................ ........17 1.5 contents in carton.......................................................................................................... ...........18 1.6 connection of ie-v850e-mc-a and ie-v850e-mc-em1-b ......................................................19 chapter 2 part names and functions ...................................................................................21 2.1 ie-v850e-mc-em1-b part names and functions....................................................................21 chapter 3 list of settings at shipment...............................................................................25 chapter 4 cautions .......................................................................................................... ................27 4.1 reset signal................................................................................................................ ................27 4.2 clock ....................................................................................................................... ....................28 4.2.1 clock supply method ....................................................................................................... ...............28 4.2.2 main clock tuning......................................................................................................... ...................29 4.3 emulation memory............................................................................................................ .........31 4.3.1 standard emulation memory function ........................................................................................ .....31 4.3.2 target substitution memory function....................................................................................... ........32 4.3.3 emulation memory operation timing differences............................................................................. 33 chapter 5 IE-V850E-MC-MM2................................................................................................... ...........35 5.1 IE-V850E-MC-MM2 parts and functions..................................................................................35 5.2 jp1 to jp3 setting examples................................................................................................. ...37 5.3 list of settings at product shipment.......................................................................................4 0 5.4 connection of ie-v850e-mc-em1-b and IE-V850E-MC-MM2 .................................................41 5.5 contents in carton.......................................................................................................... ...........42 appendix a product drawing ................................................................................................. .....43 appendix b udl board interface connector locations .............................................45 appendix c udl interface connector signal table (viewed from ie-v850e-mc-em1-b) .........................................................................47 c.1 con1 to con3 pin assignment ...............................................................................................47 c.1.1 cautions .................................................................................................................. .......................47 users manual u14482ej2v0um00 10 c.2 signal list................................................................................................................. ..................48 c.3 nb85e pin and udl connector correspondence tables .....................................................56 c.4 nb85e500 pins and con1 to con3 correspondence tables ..............................................62 c.5 nu85e502 pins and con1 to con3 correspondence tables ..............................................65 appendix d electrical specifications of udl interface.............................................67 appendix e restrictions..................................................................................................... ............87 user?s manual u14482ej2v0um00 11 list of figures figure no. title page 1-1 system configuration ........................................................................................................................ 17 1-2 contents in carton ............................................................................................................................ 18 1-3 connection of ie-v850e-mc-a and ie-v850e-mc-em1-b ..................................................................... 19 2-1 ie-v850e-mc-em1-b ........................................................................................................................ 21 4-1 reset signal ............................................................................................................................... ...... 27 4-2 oscillator ic socket ........................................................................................................................... 28 4-3 ie-v850e-mc-a and ie-v850-mc-em1-b clock circuit diagram ............................................................ 29 4-4 delay circuit diagram (ie-v850e-mc-a) ............................................................................................. 30 4-5 emulation memory equivalent circuit .................................................................................................. 33 5-1 IE-V850E-MC-MM2 ........................................................................................................................... 35 5-2 ie-v850e-mc-em1-b and IE-V850E-MC-MM2 connection diagram ...................................................... 41 5-3 contents in carton ............................................................................................................................ 42 users manual u14482ej2v0um00 12 list of tables table no. title page 5-1 jp2 setting method ........................................................................................................................... 35 5-2 bits 23 to 25 setting method using jp3 ............................................................................................... 36 users manual u14482ej2v0um00 13 chapter 1 overview the ie-v850e-mc-em1-b is an option board for the ie-v850e-mc-a in-circuit emulator. efficient hardware and software debugging can be performed during system development using the v850e1 by connecting the ie-v850e- mc-em1-b to the ie-v850e-mc-a. this manual describes the basic setup procedure, the switch settings for the ie-v850e-mc-em1-b when it is connected to the ie-v850e-mc-a, and the IE-V850E-MC-MM2 (sold separately) settings. for the parts and functions of the ie-v850e-mc-a and details about the connection of component parts, refer to the ie-v850e-mc-a users manual (u14487e) . chapter 1 overview users manual u14482ej2v0um00 14 1.1 hardware configuration in-circuit emulator (ie-v850e-mc-a) option board (ie-v850e-mc-em1-b) by adding this board, the ie-v850e-mc-a can be used as an in-circuit emulator that supports nb85e core system-on-chip development. pc interface boards ie-70000-cd-if-a ie-70000-pci-if(-a) boards used to connect a pc and the ie-v850e-mc-a. inserted in the expansion slot of pc. ie-70000-pci-if(-a): for pci bus ie-70000-cd-if-a: for pcmcia socket separately sold hardware power supply adapter (ie-70000-mc-ps-b) ac adaptor dedicated to nec in-circuit emulator v850e memory board 2 (IE-V850E-MC-MM2) (sold separately) this board can be used as a substitute for 8 mb target memoy. separately sold hardware cha p t e r 1 o v e r v i e w user s m a n u al u 1 4 482e j 2v0 u m 0 0 15 1.2 features system- o n-c h ip e m u lat i on i s p o ssi b l e b y c o nn e cti n g t h e ie-v 8 50e-mc-a , ie-v850e-mc-em1- b , a n d ud l (user desi g n l o gi c ) b o ard. ope r ati n g fre q ue n c y : 40 mhz (max.) no t e a 20 mhz o s c il l ator i s mo u n te d a t shipm e nt. extreme l y l i ght w e igh t an d comp a ct the f o l l o w i n g pi n s c an b e mas k ed: w a itz, dcresz, hlddrqz, dcnmi0 t o 2 not e the e le c tric a l s pe c if i ca t io n s of t he ud l in t e r f ac e m u st b e c on s ide r ed d u rin g udl/ta r get b o ard d e s i g n . f o r t h e e l e c t r i c a l s p e c i f i c a t i o n s of t h e udl i n t e r f a ce, r e f e r t o appendix d electrical specific a tions of udl inter f a ce. chapter 1 overview users manual u14482ej2v0um00 16 1.3 function specifications (when connected to ie-v850e-mc-a) item specifications internal rom 1 mb emulation memory capacity external memory 4 mb (standard) + 8 mb (option) note internal rom 1 mb in rom-less mode 2 mb execution/pass detection coverage memory capacity external memory when using internal rom 1 mb trace memory capacity 168 bits 32 kframes time measurement function measurement enabled with time tag and timer (3 channels) 8-bit external trace possible external logic probe trace/break event setting possible event break step execution break forced break break function fail-safe break illegal access to peripheral i/o access to guard space write to rom space note if the IE-V850E-MC-MM2 (sold separately) is mounted, an additional 8 mb can be substituted as target memory. however, the IE-V850E-MC-MM2 can be used only when a udl board is connected. caution some of the functions may not be supported, depending on the debugger used. chapter 1 overview users manual u14482ej2v0um00 17 1.4 system configuration the system configuration when connecting the ie-v850e-mc-a to the ie-v850e-mc-em1-b, which is then connected to a pc (pc-9800 series, pc/at or compatibles) is illustrated below. figure 1-1. system configuration <9> <10> <8> <5> <6> <7> <4> <3> <1> <2> target system udl (user design logic) board remarks <1>: pc (pc-9800 series, pc/at or compatibles) <2>: debugger (sold separately) <3>: pc interface board (ie-70000-pci-if(-a), ie-70000-cd-if-a: sold separately) <4>: pc interface cable (provided with ie-v850e-mc-a) <5>: in-circuit emulator (ie-v850e-mc-a: sold separately) <6>: in-circuit emulator option board (ie-850e-mc-em1-b) <7>: external logic probe (provided with ie-v850e-mc-em1-b) <8>: power supply adapter (ie-70000-mc-ps-b: sold separately) <9>: ac100 v power cable (sold separately: provided with ie-70000-mc-ps-b) <10>: ac220 v power cable (sold separately: provided with ie-70000-mc-ps-b) chapter 1 overview users manual u14482ej2v0um00 18 1.5 contents in carton the ie-v850e-mc-em1-b carton contains the main unit, an external logic probe, udl board connectors, spacers, screws, this manual, a guarantee card, and a packing list. the spacers and screws are contained in the same envelope. if there are any missing or damaged items, contact an nec sales representative or an nec distributor. figure 1-2. contents in carton <1> ie-v850e-mc-em1-b <2> external logic probe <3> udl board connector <4> spacer <5> screws <6> users manual <7> guarantee card <8> packing list <1> ie-v850e-mc-em1-b: 1 <5> screws: 8 <2> external logic probe: 1 <6> users manual: 1 <3> udl board connectors: 3 <7> guarantee card: 1 (xh3a-0141-a (made by omron)) <8> packing list: 1 <4> spacers: 4 chapter 1 overview users manual u14482ej2v0um00 19 1.6 connection of ie-v850e-mc-a and ie-v850e-mc-em1-b the procedure for connecting the ie-v850e-mc-a and ie-v850e-mc-em1-b is described below. caution be careful not to break or bend the connector pins when connecting. <1> remove the (upper and lower) pod covers of the ie-v850e-mc-a. <2> set the pga socket lever of the ie-v850e-mc-em1-b to the open position shown in figure 1-3 (b). <3> connect the pga socket on the underside of the pod to the ie-v850e-mc-em1-b. (refer to figure 1-3 (c) .) keep the ie-v850e-mc-a and ie-v850e-mc-em1-b in a horizontal position during connection. <4> set the pga socket lever of the ie-v850e-mc-em1-b to the close position shown in figure 1-3 (b). <5> fix the rear of the pod cover (upper part) with the nylon rivets. figure 1-3. connection of ie-v850e-mc-a and ie-v850e-mc-em1-b (1/2) (a) connection outline ie-v850e-mc-a nylon rivets upper cover ie-v850e-mc-em1-b nylon rivets chapter 1 overview users manual u14482ej2v0um00 20 figure 1-3. connection of ie-v850e-mc-a and ie-v850e-mc-em1-b (2/2) (b) pga socket lever of ie-v850e-mc-em1-b close open (c) connection location (ie-v850e-mc-em1-b) a1 pin location : insertion guide pins : ie-v850e-mc-a insertion locations users manual u14482ej2v0um00 21 chapter 2 part names and functions this chapter describes the name and functions of each part of the ie-v850e-mc-em1-b, as well as the switch settings. for more information about the pod, jumper, and switch positions, refer to the ie-v850e-mc-a users manual (u14487e) . 2.1 ie-v850e-mc-em1-b part names and functions figure 2-1. ie-v850e-mc-em1-b (a) top view (b) bottom view con1 jp9 jp10 con5 jp1 ic1 d1 (led) tp4 con2 con4 ic3 ic4 jp2 jp3 jp4 31313131 42424242 jp5 jp6 jp7 jp8 ic23 con3 con1 con2 ic3 con3 chapter 2 part names and functions users manual u14482ej2v0um00 22 (1) jp1 this pin is used for testing before shipment. do not change this setting. (2) jp2 1-2 shorted: enables use of the internal memory controller. 1-2 open: enables use of the vsb bus. (3) jp3 this pin is used for testing before shipment. do not change this setting. (4) jp4 this pin is used for testing before shipment. do not change this setting. (5) jp5 this pin is used for testing before shipment. do not change this setting. (6) jp6 this pin is used for testing before shipment. do not change this setting. (7) jp7 this pin is used for testing before shipment. do not change this setting. (8) jp8 this pin is used for testing before shipment. do not change this setting. (9) jp9 1-2 shorted: interrupt edge detection. 1-2 open: interrupt level detection. (10) jp10 1-2 shorted: enables stbc circuit operation. 1-2 open: stops stbc circuit operation. (11) tp4 this pin enables measurement of the clkout output signal of the evaluation chip. (12) d1 this led is used for testing before shipment, and is therefore always off. (13) con1 to con3 udl board connectors chapter 2 part names and functions users manual u14482ej2v0um00 23 (14) con4 this connector is used to connect the external sense probe to monitor signals on the udl board, record them as trace data, and incorporate them in event sources. signals can be received at the 3.3 v cmos level, but up to 5 v is tolerated. the timing used to fetch signals is the program fetch timing. signals monitored with the external logic probe can also be fetched from the udl interface connectors (con3, con093 to con100). (15) con5 connector used to mount the target substitution memory board (IE-V850E-MC-MM2) (16) ic3 socket used to connect the ie-v850e-mc-a (17) ic23 socket used to mount an oscillator users manual u14482ej2v0um00 24 [memo] users manual u14482ej2v0um00 25 chapter 3 list of settings at shipment item setting remark jp1 10 9 2 1 setting other than shipment default setting prohibited jp2 1 2 internal memory controller used jp3 12 setting other than shipment default setting prohibited jp4 10 9 2 1 setting other than shipment default setting prohibited jp5 4 3 2 1 setting other than shipment default setting prohibited jp6 4 3 2 1 setting other than shipment default setting prohibited jp7 4 3 2 1 setting other than shipment default setting prohibited jp8 4 3 2 1 setting other than shipment default setting prohibited jp9 1 2 interrupt edge detection jp10 1 2 stbc circuit operation enabled users manual u14482ej2v0um00 26 [memo] users manual u14482ej2v0um00 27 chapter 4 cautions 4.1 reset signal be sure to use the emulator output signal eresetz as the reset signal for circuits on the udl board. if the eresetz signal is not used, software reset from the debugger is not enabled for the udl board. figure 4-1. reset signal intc-evachip eresetz (con3 to con11) (con3 to con10) dcresz other udl reset circuit on udl board/target udl board/target ie-v850e-mc-em1-b ie-v850e-mc-a reset from debugger connector reset processing circuit cpu evachip chapter 4 cautions users manual u14482ej2v0um00 28 4.2 clock 4.2.1 clock supply method the clock used by the emulator can be supplied using one of two methods, selectable by the debugger. (1) supply vbclk to emulator from udl board be sure to use the oscillator output clock for vbclk. (2) supply clock from oscillator mounted on emulator a 20 mhz oscillator (8-pin type) is mounted on the emulator at shipment. the output clock of this oscillator can be used as the main clock. the emulator can be operated at the desired frequency by removing the already mounted 20 mhz oscillator and installing an oscillator of the desired frequency (40 mhz max.). caution if supplying the emulator clock from the udl board, do not stop the clock supply even when going into the standby mode. if the clock supply stops, the emulator and debugger become deadlocked. figure 4-2. oscillator ic socket ic23 (ic socket) 8 pin type pin 1 n.c. pin 4 gnd pin 8 v dd pin 5 oscout 14 pin type pin 1 n.c. pin 7 gnd pin 14 v dd pin 8 oscout remark the emulator uses either one of the above clocks as the main clock and outputs it to the udl board as vbclki. use vbclki for the clock distributed on the udl board. chapter 4 cautions users manual u14482ej2v0um00 29 figure 4-3. ie-v850e-mc-a and ie-v850-mc-em1-b clock circuit diagram tp4 intc-evachip vbclki (con1 to con76) (con2 to con76) vbclk other udl udl board/target ieport0 (clock selection signal) cpuckin clkem vbclki clkem1 clkout internal clock oscillator connector clock ic 74fct388915t (max. delay 10 ns) cpu evachip ie-v850e-mc-em1-b ie-v850e-mc-a clock generator circuit on udl board/target delay circuit 4.2.2 main clock tuning as the effect of an excessive load and two or more buffering stages on the udl board, a timing delay may occur for the cpuckin and clkem1 signals in relation to vbclki. in such a case, the timing of the cpuckin and clkem1 signals can be delayed by setting jp2 of the ie-v850e-mc-a so as to tune the phase with vbclki. there are three types of tuning. (a) 1-2 shorted and 7-8 shorted: shipment default setting (b) 3-4 shorted and 9-10 shorted: 6 ns (typ.) phase delay in relation to shipment default setting (c) 5-6 shorted and 11-12 shorted: 12 ns (typ.) phase delay in relation to shipment default setting when tuning the main clock, monitor the clock at the following two points and adjust the phase difference. point serving as reference on udl board tp4 on ie-v850e-mc-em1-b (not output during reset) cautions 1. when manipulating jp2 of the ie-v850e-mc-a, ensure that the same number of buffering stages is inserted for cpuckin and clkem1. 2. the evaluation chip operation clock (clkout) is approximately 10 ns later than vbclki. therefore, when distributing vbclki on the udl board, it is recommended to do so after the first buffer stage. moreover, as long as there is no excessive load and no more than one buffer stage, use the shipment default setting of jp2 of the ie-850e-mc-a. chapter 4 cautions users manual u14482ej2v0um00 30 figure 4-4. delay circuit diagram (ie-v850e-mc-a) 1 2 3 4 5 6 7 9 11 8 jp2 selected by jumper the 74vhc244 is used as the buffer. the delay is 6 ns (typ.). cpuckin clkem clkem1 default default vbclki 10 12 chapter 4 cautions users manual u14482ej2v0um00 31 4.3 emulation memory a standard emulation memory that can always be used as well as a target substitution memory that can be used by mounting the IE-V850E-MC-MM2 (sold separately) are available for the ie-v850e-mc-em1-b. the emulation memory can only be used only when the memory controller is selected; it cannot be used when the vsb bus is selected. 4.3.1 standard emulation memory function memory capacity: 4 mb mapping unit: 1 mb (mapping of 1 mb 4 banks max. is possible.) bus size: 16 bits or 32 bits (8-bit bus size is not supported.) mapping method: specify the area to be mapped with the debugger as emulation ram/rom. (there is no jumper setting.) wait insertion: if the operating frequency is 25 mhz or higher, insertion of 1 wait or more is required. the number of waits for the emulation memory is not influenced by the _wait signal; it is determined by debugger setting or wait control register setting. (0 wait/1 wait/programmable wait (1 to 7 waits).) for id850 the following three selections are available on the configuration screen. (a) wait mask ? access is performed with 0 waits. (b) 1 wait (default) ? access is performed with 1 wait. (c) target wait ? access is performed with the number of waits set with the dwc0/1 register. however, the number of waits is always 1 wait if 0/1 wait is set. for multi the following three selections are available using the pinmask command. (a) wait mask ? access is performed with 0 waits. emwait mask (wait signals to the external memory are masked) (b) wait mask ? access is performed with 1 wait. emwait unmask (wait signals to the external memory are masked) wait unmask ? access is performed with 1 wait. emwait mask (wait signals to the external memory are enabled) (c) wait unmask ? access is performed with the number of waits set by the dwc0/1 register. emwait unmask however, the number of waits is always 1 wait if 0/1 wait is set. (wait signals to the external memory are enabled) chapter 4 cautions users manual u14482ej2v0um00 32 4.3.2 target substitution memory function memory capacity: 8 mb mapping specifications: emulation can be performed by selecting the mapping area using one of the chip select signals of the memory controller. the start address mapped in the memory block is determined by jp3 of the IE-V850E-MC-MM2. bus size: 16 bits or 32 bits (8-bit bus size is not supported.) mapping method: set jp2 and jp3 note of the IE-V850E-MC-MM2. specify the area to be mapped with the debugger as target memory. note for how to set jp2 and jp3, refer to chapter 5 IE-V850E-MC-MM2. cautions 1. if the target substitution memory is mapped to an area overlapping the standard emulation memory, the standard emulation memory has priority. 2. to access the target memory when the IE-V850E-MC-MM2 (sold separately) is mounted, make sure that the memory blocks to which the target memory is allocated and the memory blocks specified by setting jp2 and jp3 of the IE-V850E-MC-MM2 do not match. 3. the target substitution memory can used only when the udl board is connected. chapter 4 cautions users manual u14482ej2v0um00 33 4.3.3 emulation memory operation timing differences when the dram, sdram, and page rom areas in the target system are allocated to the emulation memory, the access timing used is that of the sram. when measuring the performance using emulation memory, perform wait settings so as to match the access timing of the memory actually used. figure 4-5. emulation memory equivalent circuit target emulation memory emulation memory 4 mb 8 mb IE-V850E-MC-MM2 (option) evaluation chip d0 to d31 a0 to a25 we rd cs users manual u14482ej2v0um00 34 [memo] users manual u14482ej2v0um00 35 chapter 5 IE-V850E-MC-MM2 this chapter describes the parts and functions of the IE-V850E-MC-MM2 (sold separately) as well as the jumper settings. 5.1 IE-V850E-MC-MM2 parts and functions figure 5-1. IE-V850E-MC-MM2 (a) top view (b) bottom view tp2 tp1 jp3 jp1 con1 jp4 jp2 (1) jp1 jumper for bus size selection 1-2 shorted: 32 bits 1-2 open: 16 bits (2) jp2 jumper for target substitution memory mapping setting the setting method is as follows. table 5-1. jp2 setting method jp2 setting target substitution memory mapping area 1-2 shorted memory block 0 (select csz0) 3-4 shorted memory block 1 (select csz1) 5-6 shorted memory block 2 (select csz2) 7-8 shorted memory block 3 (select csz3) 9-10 shorted memory block 4 (select csz4) 11-12 shorted memory block 5 (select csz5) 13-14 shorted memory block 6 (select csz6) 15-16 shorted memory block 7 (select csz7) all pins open target substitution memory cannot be mapped. chapter 5 IE-V850E-MC-MM2 users manual u14482ej2v0um00 36 (3) jp3 this jumper is used to specify bits 23 to 25 of the memory block addresses to be mapped to the target substitution memory. table 5-2. bits 23 to 25 setting method using jp3 jp3 setting value of a25 to a23 1-2 3-4 5-6 a25 a24 a23 open open open h h h open open shorted h h l open shorted open h l h open shorted shorted h l l shorted open open l h h shorted open shorted l h l shorted shorted open l l h shorted shorted shorted l l l (4) jp4 pin block for testing before shipment. use the shipment default settings. (5) tp1 ground pin (6) tp2 pin used for testing before shipment (7) con1 connector for interface with ie-v850e-mc-em1-b chapter 5 IE-V850E-MC-MM2 users manual u14482ej2v0um00 37 5.2 jp1 to jp3 setting examples setting examples of jp1 to jp3 in the 64 mb mode are described below. example 1 csz4 ( 16 bits) 32 mb 3 f f f f f f h 2 f f f f f f h 2 0 0 0 0 0 0 h 1 f f f f f f h 0 7 f f f f f h 0 3 f f f f f h 0 2 0 0 0 0 0 h 0 0 0 0 0 0 0 h csz3 (32 bits) 24 mb csz2 (32 bits) 4 mb csz1 (32 bits) 2 mb csz0 (32 bits) 2 mb area 1 area 1. the jumper settings when substituting this area are as follows. jp1: open jp2: 9-10 open jp3: 1-2 open 3-4 shorted 5-6 open chapter 5 IE-V850E-MC-MM2 users manual u14482ej2v0um00 38 example 2. area 2 csz4 (16 bits) 32 mb 3 f f f f f f h 2 f f f f f f h 2 0 0 0 0 0 0 h 1 f f f f f f h 0 7 f f f f f h 0 3 f f f f f h 0 2 0 0 0 0 0 h 0 0 0 0 0 0 0 h csz3 (32 bits) 24 mb csz2 (32 bits) 4 mb csz1 (32 bits) 2 mb csz0 (32 bits) 2 mb area 2. the jumper settings when substituting this area are as follows. jp1: shorted jp2: 3-4 shorted jp3: 1-2 shorted 3-4 shorted 5-6 shorted chapter 5 IE-V850E-MC-MM2 users manual u14482ej2v0um00 39 a jp1 to jp3 setting example when the 256 mb mode is used is described below. f f f f f f f h csz7 (32 bits) 2 mb csz6 (32 bits) 4 mb csz1 (32 bits) 4 mb csz0 (32 bits) 4 mb f d f f f f f h f 9 f f f f f h b f f f f f f h 7 f f f f f f h 5 f f f f f f h 5 8 0 0 0 0 0 h 3 f f f f f f h 0 7 f f f f f h 0 3 f f f f f h 0 0 0 0 0 0 0 h csz3 (32 bits) 64 mb area 3 csz5 (32 bits) 58 mb csz4 (32 bits) 64 mb csz2 (32 bits) 56 mb area 3. the jumper settings when substituting this area are as follows. jp1: shorted jp2: 7-8 shorted jp3: 1-2 shorted 3-4 shorted 5-6 shorted chapter 5 IE-V850E-MC-MM2 users manual u14482ej2v0um00 40 5.3 list of settings at product shipment item setting remark jp1 2 1 sets bus size to 32 bits. jp2 16 15 2 1 maps memory block 0 to expanded emulation memory. jp3 6 5 2 1 a25 = 1, a24 = a23 = 0 jp4 10 9 2 1 use of settings other than the shipment default setting is prohibited. chapter 5 IE-V850E-MC-MM2 users manual u14482ej2v0um00 41 5.4 connection of ie-v850e-mc-em1-b and IE-V850E-MC-MM2 <1> set jp1, jp2, and jp3 of the IE-V850E-MC-MM2 as desired. <2> connect the screws and spacers to the IE-V850E-MC-MM2. <3> connect con1 of the IE-V850E-MC-MM2 and con5 of the ie-v850e-mc-em1-b. <4> secure the IE-V850E-MC-MM2 with the screws from the back of the ie-v850e-mc-em1-b. figure 5-2. ie-v850e-mc-em1-b and IE-V850E-MC-MM2 connection diagram con5 con1 chapter 5 IE-V850E-MC-MM2 user?s manual u14482ej2v0um00 42 5.5 contents in carton the IE-V850E-MC-MM2 box contains the IE-V850E-MC-MM2 in-circuit emulator board, spacers, screws, a guarantee card, and a packing list. the spacers and screws are contained in the same envelope. if there are any missing or damaged items, contact an nec sales representative or an nec distributor. figure 5-3. contents in carton <2> spacers <3> screws <1> IE-V850E-MC-MM2 <4> guarantee card <5> packing list <1> IE-V850E-MC-MM2: 1 <2> spacers: 2 <3> screws: 4 <4> guarantee card: 1 <5> packing list: 1 users manual u14482ej2v0um00 43 appendix a product drawing the drawing of the ie-v850e-mc-em1-b is shown below. (unit: mm) socket 3.2 4 5 104.6175 10.0025 114.7775 125 (the ie-v850e-mc-a is on this side.) con3 con2 con1 37.305 69.34 44.355 38.575 69.34 151 5 15 43.085 f remark the udl board is connected by con1 to con3, but the stacking height is 12 mm. do not place parts with a height of 8 mm or more on the part where the udl board and ie-v850e-mc- em1-b overlap. users manual u14482ej2v0um00 44 [memo] users manual u14482ej2v0um00 45 appendix b udl board interface connector locations the following figure shows the top view of the udl board. the following part is used for the connector. xh3a-0141-a (made by omron) con3 users manual u14482ej2v0um00 46 [memo] users manual u14482ej2v0um00 47 appendix c udl interface connector signal table (viewed from ie-v850e-mc-em1-b) c.1 con1 to con3 pin assignment the udl interface connector signal table is shown from the next page. c.1.1 cautions (1) the i/o attributes are as follows. i/o: bidirectional i: input signal to emulator. o: output signal from emulator. (2) signals assigned to connector the signals assigned to the connector can be of two groups, as shown below. (a) when vsb bus is selected pins for vsb, pins for npb, pins for system control, pins for dmac, pins for intc (b) when memory controller is selected pins for nb85e500, pins for nu85e502, pins for npb, pins for system control, pins for dmac, pins for intc (3) handling of unused pins no special handling of unused pins is required on the udl board side, but to achieve greater pin status stability, perform the following processing on the udl board. input pin to udl board: leave open output pin from udl board: fix to inactive i/o pin to udl board: leave open (4) since the emulator and udl board interfaces are all performed using 3.3 v, to perform an interface at a voltage other than 3.3 v, convert the signal level on the udl board side. since the emulator input pins support 5 v, inputting 5 v signals does not represent a problem. appendix c udl interface connector signal table (viewed from ie-v850e-mc-em1-b) users manual u14482ej2v0um00 48 c.2 signal list signal list (1/8) when memory controller is used pin no. when vsb bus is used sram sdram i/o processing on emulator side con1-con001 3 v cc note 1 con1-con002 3 v cc note 1 con1-con003 dmactv2 o con1-con004 dmactv0 o con1-con005 v cc note 2 con1-con006 v cc note 2 con1-con007 vbd30 d30 i/o 5.1 k pull-up con1-con008 vbd28 d28 i/o 5.1 k pull-up con1-con009 vbd26 d26 i/o 5.1 k pull-up con1-con010 vbd24 d24 i/o 5.1 k pull-up con1-con011 vbd22 d22 i/o 5.1 k pull-up con1-con012 vbd20 d20 i/o 5.1 k pull-up con1-con013 vbd18 d18 i/o 5.1 k pull-up con1-con014 vbd16 d16 i/o 5.1 k pull-up con1-con015 gnd con1-con016 gnd con1-con017 vbd14 d14 i/o 5.1 k pull-up con1-con018 vbd12 d12 i/o 5.1 k pull-up con1-con019 vbd10 d10 i/o 5.1 k pull-up con1-con020 vbd8 d8 i/o 5.1 k pull-up con1-con021 vbd6 d6 i/o 5.1 k pull-up con1-con022 vbd4 d4 i/o 5.1 k pull-up con1-con023 vbd2 d2 i/o 5.1 k pull-up con1-con024 vbd0 d0 i/o 5.1 k pull-up con1-con025 gnd con1-con026 gnd con1-con027 gnd con1-con028 gnd con1-con029 vbbstr - note 3 - note 3 o con1-con030 vbdc rdz o con1-con031 vbbenz2 wrz2 dqm2 o con1-con032 vbbenz0 wrz0 dqm0 o con1-con033 gnd con1-con034 gnd con1-con035 pcm4 - note 3 refrqz o 33 k pull-down con1-con036 pcm2 hldakz o 33 k pull-down con1-con037 pcm0 waitz i 5.1 k pull-up notes 1. 3.3 v power supply of emulator 2. 5 v power supply of emulator 3. leave open or perform pin processing according to (3) handling of unused pins in c.1.1 cautions appendix c udl interface connector signal table (viewed from ie-v850e-mc-em1-b) users manual u14482ej2v0um00 49 signal list (2/8) when memory controller is used pin no. when vsb bus is used sram sdram i/o processing on emulator side con1-con038 gnd con1-con039 gnd con1-con040 vba26 - note 1 o con1-con041 vba24 a24 o con1-con042 vba22 a22 o con1-con043 vba20 a20 o con1-con044 vba18 a18 o con1-con045 vba16 a16 o con1-con046 vba14 a14 o con1-con047 gnd con1-con048 gnd con1-con049 vba12 a12 o con1-con050 vba10 a10 o con1-con051 vba8 a8 o con1-con052 vba6 a6 o con1-con053 vba4 a4 o con1-con054 vba2 a2 o con1-con055 vba0 a0 o con1-con056 gnd con1-con057 gnd con1-con058 gnd con1-con059 gnd con1-con060 vdcsz6 csz6 csz6 o con1-con061 vdcsz4 csz4 csz4 o con1-con062 vdcsz2 csz2/iowrz csz2/iowrz o con1-con063 vdcsz0 csz0 csz0 o con1-con064 pcd2 - note 1 sdcasz o 33 k pull-down con1-con065 pcd0 - note 1 cke o 33 k pull-down con1-con066 vbctyp2 - note 1 o con1-con067 vbctyp0 - note 1 o con1-con068 vaack - note 1 o con1-con069 vbahld - note 1 i 33 k pull-down con1-con070 vblock - note 1 o con1-con071 vbsize1 - note 1 o con1-con072 vbttyp1 - note 1 o con1-con073 vbwrite - note 1 o con1-con074 gnd con1-con075 gnd con1-con076 vbclki note 2 o con1-con077 gnd notes 1. leave open or perform pin processing according to (3) handling of unused pins in c.1.1 cautions 2. clock signal supplied to udl board from emulator. appendix c udl interface connector signal table (viewed from ie-v850e-mc-em1-b) users manual u14482ej2v0um00 50 signal list (3/8) when memory controller is used pin no. when vsb bus is used sram sdram i/o processing on emulator side con1-con078 gnd con1-con079 vpd14 i/o 5.1 k pull-up con1-con080 vpd12 i/o 5.1 k pull-up con1-con081 vpd10 i/o 5.1 k pull-up con1-con082 vpd8 i/o 5.1 k pull-up con1-con083 vpd6 i/o 5.1 k pull-up con1-con084 vpd4 i/o 5.1 k pull-up con1-con085 vpd2 i/o 5.1 k pull-up con1-con086 vpd0 i/o 5.1 k pull-up con1-con087 gnd con1-con088 gnd con1-con089 gnd con1-con090 gnd con1-con091 vpa12 o con1-con092 vpa10 o con1-con093 vpa8 o con1-con094 vpa6 o con1-con095 vpa4 o con1-con096 vpa2 o con1-con097 vpa0 o con1-con098 vpubenz o con1-con099 vplock o con1-con100 - note con2-con001 3 v cc con2-con002 3 v cc con2-con003 dmactv3 o con2-con004 dmactv1 o con2-con005 v cc con2-con006 v cc con2-con007 vbd31 d31 i/o 5.1 k pull-up con2-con008 vbd29 d29 i/o 5.1 k pull-up con2-con009 vbd27 d27 i/o 5.1 k pull-up con2-con010 vbd25 d25 i/o 5.1 k pull-up con2-con011 vbd23 d23 i/o 5.1 k pull-up con2-con012 vbd21 d21 i/o 5.1 k pull-up con2-con013 vbd19 d19 i/o 5.1 k pull-up con2-con014 vbd17 d17 i/o 5.1 k pull-up con2-con015 gnd con2-con016 gnd con2-con017 vbd15 d15 i/o 5.1 k pull-up con2-con018 vbd13 d13 i/o 5.1 k pull-up note leave open or perform pin processing according to (3) handling of unused pins in c.1.1 cautions appendix c udl interface connector signal table (viewed from ie-v850e-mc-em1-b) users manual u14482ej2v0um00 51 pin list (4/8) when memory controller is used pin no. when vsb bus is used sram sdram i/o processing on emulator side con2-con019 vbd11 d11 i/o 5.1 k pull-up con2-con020 vbd9 d9 i/o 5.1 k pull-up con2-con021 vbd7 d7 i/o 5.1 k pull-up con2-con022 vbd5 d5 i/o 5.1 k pull-up con2-con023 vbd3 d3 i/o 5.1 k pull-up con2-con024 vbd1 d1 i/o 5.1 k pull-up con2-con025 gnd con2-con026 gnd con2-con027 gnd con2-con028 gnd con2-con029 vbstz bcystz bcystz o con2-con030 vdselpz - note sdwez o con2-con031 vbbenz3 wrz3 dqm3 o con2-con032 vbbenz1 wrz1 dqm1 o con2-con033 gnd con2-con034 gnd con2-con035 pcm5 - note selfref i 33 k pull-down con2-con036 pcm3 hldrqz i 5.1 k pull-up con2-con037 pcm1 - note i/o 33 k pull-down con2-con038 gnd con2-con039 gnd con2-con040 vba27 - note o con2-con041 vba25 a25 o con2-con042 vba23 a23 o con2-con043 vba21 a21 o con2-con044 vba19 a19 o con2-con045 vba17 a17 o con2-con046 vba15 a15 o con2-con047 gnd con2-con048 gnd con2-con049 vba13 a13 o con2-con050 vba11 a11 o con2-con051 vba9 a9 o con2-con052 vba7 a7 o con2-con053 vba5 a5 o con2-con054 vba3 a3 o con2-con055 vba1 a1 o con2-con056 gnd con2-con057 gnd con2-con058 gnd con2-con059 gnd note leave open or perform pin processing according to (3) handling of unused pins in c.1.1 cautions appendix c udl interface connector signal table (viewed from ie-v850e-mc-em1-b) users manual u14482ej2v0um00 52 signal list (5/8) when memory controller is used pin no. when vsb bus is used sram sdram i/o processing on emulator side con2-con060 vdcsz7 csz7 csz7 o con2-con061 vdcsz5 csz5/iordz csz5/iordz o con2-con062 vdcsz3 csz3 csz3 o con2-con063 vdcsz1 csz1 csz1 o con2-con064 pcd3 - note sdrasz o 33 k pull-down con2-con065 pcd1 - note sdclk o 33 k pull-down con2-con066 pbs3 - note i/o 33 k pull-down con2-con067 vbctyp1 - note o con2-con068 vareq - note i 33 k pull-down con2-con069 vblast - note i 33 k pull-down con2-con070 vbsize0 - note o con2-con071 vbttyp0 - note o con2-con072 vbwait - note i 33 k pull-down con2-con073 gnd con2-con074 gnd con2-con075 gnd con2-con076 vbclk i con2-con077 gnd con2-con078 gnd con2-con079 vpd15 i/o 5.1 k pull-up con2-con080 vpd13 i/o 5.1 k pull-up con2-con081 vpd11 i/o 5.1 k pull-up con2-con082 vpd9 i/o 5.1 k pull-up con2-con083 vpd7 i/o 5.1 k pull-up con2-con084 vpd5 i/o 5.1 k pull-up con2-con085 vpd3 i/o 5.1 k pull-up con2-con086 vpd1 i/o 5.1 k pull-up con2-con087 gnd con2-con088 gnd con2-con089 gnd con2-con090 gnd con2-con091 vpa13 o con2-con092 vpa11 o con2-con093 vpa9 o con2-con094 vpa7 o con2-con095 vpa5 o con2-con096 vpa3 o con2-con097 vpa1 o con2-con098 vpwrite o con2-con099 vpstb o con2-con100 vpretr i 500 pull-down note leave open or perform pin processing according to (3) handling of unused pins in c.1.1 cautions appendix c udl interface connector signal table (viewed from ie-v850e-mc-em1-b) users manual u14482ej2v0um00 53 signal list (6/8) when memory controller is used pin no. when vsb bus is used sram sdram i/o processing on emulator side con3-con001 dmarq3 i 33 k pull-down con3-con002 dmarq2 i 33 k pull-down con3-con003 dmarq1 i 33 k pull-down con3-con004 dmarq0 i 33 k pull-down con3-con005 dmtco3 o con3-con006 dmtco2 o con3-con007 dmtco1 o con3-con008 dmtco0 o con3-con009 idmastp i 33 k pull-down con3-con010 dcresz i 5.1 k pull-up con3-con011 eresetz note o con3-con012 gnd con3-con013 gnd con3-con014 gnd con3-con015 dcnmi2 i 50 k pull-down con3-con016 dcnmi1 i 50 k pull-down con3-con017 dcnmi0 i 50 k pull-down con3-con018 int63 i 50 k pull-down con3-con019 int62 i 50 k pull-down con3-con020 int61 i 50 k pull-down con3-con021 int60 i 50 k pull-down con3-con022 int59 i 50 k pull-down con3-con023 int58 i 50 k pull-down con3-con024 int57 i 50 k pull-down con3-con025 int56 i 50 k pull-down con3-con026 int55 i 50 k pull-down con3-con027 int54 i 50 k pull-down con3-con028 int53 i 50 k pull-down con3-con029 int52 i 50 k pull-down con3-con030 int51 i 50 k pull-down con3-con031 int50 i 50 k pull-down con3-con032 int49 i 50 k pull-down con3-con033 int48 i 50 k pull-down con3-con034 int47 i 50 k pull-down con3-con035 int46 i 50 k pull-down con3-con036 int45 i 50 k pull-down con3-con037 int44 i 50 k pull-down con3-con038 int43 i 50 k pull-down con3-con039 int42 i 50 k pull-down con3-con040 int41 i 50 k pull-down con3-con041 int40 i 50 k pull-down note reset signal supplied to udl board from emulator. appendix c udl interface connector signal table (viewed from ie-v850e-mc-em1-b) users manual u14482ej2v0um00 54 signal list (7/8) when memory controller is used pin no. when vsb bus is used sram sdram i/o processing on emulator side con3-con042 int39 i 50 k pull-down con3-con043 int38 i 50 k pull-down con3-con044 int37 i 50 k pull-down con3-con045 int36 i 50 k pull-down con3-con046 int35 i 50 k pull-down con3-con047 int34 i 50 k pull-down con3-con048 int33 i 50 k pull-down con3-con049 int32 i 50 k pull-down con3-con050 int31 i 50 k pull-down con3-con051 int30 i 50 k pull-down con3-con052 int29 i 50 k pull-down con3-con053 int28 i 50 k pull-down con3-con054 int27 i 50 k pull-down con3-con055 int26 i 50 k pull-down con3-con056 int25 i 50 k pull-down con3-con057 int24 i 50 k pull-down con3-con058 int23 i 50 k pull-down con3-con059 int22 i 50 k pull-down con3-con060 int21 i 50 k pull-down con3-con061 int20 i 50 k pull-down con3-con062 int19 i 50 k pull-down con3-con063 int18 i 50 k pull-down con3-con064 int17 i 50 k pull-down con3-con065 int16 i 50 k pull-down con3-con066 int15 i 50 k pull-down con3-con067 int14 i 50 k pull-down con3-con068 int13 i 50 k pull-down con3-con069 int12 i 50 k pull-down con3-con070 int11 i 50 k pull-down con3-con071 int10 i 50 k pull-down con3-con072 int9 i 50 k pull-down con3-con073 int8 i 50 k pull-down con3-con074 int7 i 50 k pull-down con3-con075 int6 i 50 k pull-down con3-con076 int5 i 50 k pull-down con3-con077 int4 i 50 k pull-down con3-con078 int3 i 50 k pull-down con3-con079 int2 i 50 k pull-down con3-con080 int1 i 50 k pull-down con3-con081 int0 i 50 k pull-down con3-con082 gnd con3-con083 gnd con3-con084 gnd appendix c udl interface connector signal table (viewed from ie-v850e-mc-em1-b) users manual u14482ej2v0um00 55 signal list (8/8) when memory controller is used pin no. when vsb bus is used sram sdram i/o processing on emulator side con3-con085 gnd con3-con086 cgrel i 50 k pull-down con3-con087 hwstoprq o con3-con088 swstoprq o con3-con089 stprq o con3-con090 stpak i 4.7 k pull-up con3-con091 dcstopz i 5.1 k pull-up con3-con092 tgtv dd note 1 i 33 k pull-down con3-con093 extd7 note 2 i 33 k pull-down con3-con094 extd6 note 2 i 33 k pull-down con3-con095 extd5 note 2 i 33 k pull-down con3-con096 extd4 note 2 i 33 k pull-down con3-con097 extd3 note 2 i 33 k pull-down con3-con098 extd2 note 2 i 33 k pull-down con3-con099 extd1 note 2 i 33 k pull-down con3-con100 extd0 note 2 i 33 k pull-down notes 1. udl board power on/off detection signal 2. external logic probe signal appendix c udl interface connector signal table (viewed from ie-v850e-mc-em1-b) users manual u14482ej2v0um00 56 c.3 nb85e pin and udl connector correspondence tables correspondence between nb85e pins and udl connectors (1/6) nb85e pins pin no. vpa0 con1-con097 vpa1 con2-con097 vpa2 con1-con096 vpa3 con2-con096 vpa4 con1-con095 vpa5 con2-con095 vpa6 con1-con094 vpa7 con2-con094 vpa8 con1-con093 vpa9 con2-con093 vpa10 con1-con092 vpa11 con2-con092 vpa12 con1-con091 vpa13 con2-con091 vpd0 con1-con086 vpd1 con2-con086 vpd2 con1-con085 vpd3 con2-con085 vpd4 con1-con084 vpd5 con2-con084 vpd6 con1-con083 vpd7 con2-con083 vpd8 con1-con082 vpd9 con2-con082 vpd10 con1-con081 vpd11 con2-con081 vpd12 con1-con080 vpd13 con2-con080 vpd14 con1-con079 vpd15 con2-con079 vpwrite con1-con098 vpstb con2-con099 vplock con1-con099 vpubenz con2-con098 vpretr con1-con100 pins for npb vpdact - note vareq con2-con068 vaack con1-con068 vba0 con1-con055 pins for vsb vba1 con2-con055 note indicates that the corresponding pin does not exist in emulator. appendix c udl interface connector signal table (viewed from ie-v850e-mc-em1-b) users manual u14482ej2v0um00 57 correspondence between nb85e pins and udl connectors (2/6) nb85e pins pin no. vba2 con1-con054 vba3 con2-con054 vba4 con1-con053 vba5 con2-con053 vba6 con1-con052 vba7 con2-con052 vba8 con1-con051 vba9 con2-con051 vba10 con1-con050 vba11 con2-con050 vba12 con1-con049 vba13 con2-con049 vba14 con1-con046 vba15 con2-con046 vba16 con1-con045 vba17 con2-con045 vba18 con1-con044 vba19 con2-con044 vba20 con1-con043 vba21 con2-con043 vba22 con1-con042 vba23 con2-con042 vba24 con1-con041 vba25 con2-con041 vba26 note con1-con040 vba27 note con2-con040 vbd0 con1-con024 vbd1 con2-con024 vbd2 con1-con023 vbd3 con2-con023 vbd4 con1-con022 vbd5 con2-con022 vbd6 con1-con021 vbd7 con2-con021 vbd8 con1-con020 vbd9 con2-con020 vbd10 con1-con019 vbd11 con2-con019 vbd12 con1-con018 vbd13 con2-con018 vbd14 con1-con017 pins for vsb vbd15 con2-con017 note undefined operation in the 64 mb mode. only used in the 256 mb mode. appendix c udl interface connector signal table (viewed from ie-v850e-mc-em1-b) users manual u14482ej2v0um00 58 correspondence between nb85e pins and udl connectors (3/6) nb85e pins pin no. vbd16 con1-con014 vbd17 con2-con014 vbd18 con1-con013 vbd19 con2-con013 vbd20 con1-con012 vbd21 con2-con012 vbd22 con1-con011 vbd23 con2-con011 vbd24 con1-con010 vbd25 con2-con010 vbd26 con1-con009 vbd27 con2-con009 vbd28 con1-con008 vbd29 con2-con008 vbd30 con1-con007 vbd31 con2-con007 vbttyp0 con2-con071 vbttyp1 con1-con072 vbstz con2-con029 vbbenz0 con1-con032 vbbenz1 con2-con032 vbbenz2 con1-con031 vbbenz3 con2-con031 vbsize0 con2-con070 vbsize1 con1-con071 vbwrite con2-con073 vblock con1-con070 vbctyp0 con2-con067 vbctyp1 con1-con067 vbctyp2 con2-con066 vbseq0 - note vbseq1 - note vbseq2 - note vbbstr con1-con029 vbwait con2-con072 vblast con2-con069 vbahld con1-con069 vbdc con1-con030 vdcsz0 con1-con063 vdcsz1 con2-con063 vdcsz2 con1-con062 pins for vsb vdcsz3 con2-con062 note indicates that the corresponding pin does not exist in emulator. appendix c udl interface connector signal table (viewed from ie-v850e-mc-em1-b) users manual u14482ej2v0um00 59 correspondence between nb85e pins and udl connectors (4/6) nb85e pins pin no. vdcsz4 con1-con061 vdcsz5 con2-con061 vdcsz6 con1-con060 vdcsz7 con2-con060 pins for vsb vdselpz con2-con030 dcresz con3-con010 vbclk con2-con076 swstoprq con3-con088 hwstoprq con3-con087 dcstopz con3-con091 stprq con3-con089 stpak con3-con090 pins for system control cgrel con3-con086 idmastp con3-con009 dmarq0 con3-con004 dmarq1 con3-con003 dmarq2 con3-con002 dmarq3 con3-con001 dmtco0 con3-con008 dmtco1 con3-con007 dmtco2 con3-con006 dmtco3 con3-con005 dmactv0 con1-con004 dmactv1 con2-con004 dmactv2 con1-con003 pins for dmac dmactv3 con2-con003 dcnmi0 con3-con017 dcnmi1 con3-con016 dcnmi2 con3-con015 int0 con3-con081 int1 con3-con080 int2 con3-con079 int3 con3-con078 int4 con3-con077 int5 con3-con076 int6 con3-con075 int7 con3-con074 int8 con3-con073 int9 con3-con072 int10 con3-con071 int11 con3-con070 int12 con3-con069 int13 con3-con068 pins for intc int14 con3-con067 appendix c udl interface connector signal table (viewed from ie-v850e-mc-em1-b) users manual u14482ej2v0um00 60 correspondence between nb85e pins and udl connectors (5/6) nb85e pins pin no. int15 con3-con066 int16 con3-con065 int17 con3-con064 int18 con3-con063 int19 con3-con062 int20 con3-con061 int21 con3-con060 int22 con3-con059 int23 con3-con058 int24 con3-con057 int25 con3-con056 int26 con3-con055 int27 con3-con054 int28 con3-con053 int29 con3-con052 int30 con3-con051 int31 con3-con050 int32 con3-con049 int33 con3-con048 int34 con3-con047 int35 con3-con046 int36 con3-con045 int37 con3-con044 int38 con3-con043 int39 con3-con042 int40 con3-con041 int41 con3-con040 int42 con3-con039 int43 con3-con038 int44 con3-con037 int45 con3-con036 int46 con3-con035 int47 con3-con034 int48 con3-con033 int49 con3-con032 int50 con3-con031 int51 con3-con030 int52 con3-con029 int53 con3-con028 int54 con3-con027 int55 con3-con026 int56 con3-con025 int57 con3-con024 pins for intc int58 con3-con023 appendix c udl interface connector signal table (viewed from ie-v850e-mc-em1-b) users manual u14482ej2v0um00 61 correspondence between nb85e pins and udl connectors (6/6) nb85e pins pin no. int59 con3-con022 int60 con3-con021 int61 con3-con020 int62 con3-con019 pins for intc int63 con3-con018 caution the following pins are not supported by the emulator: pins for vfb, pins for vdb, pins for instruction cache, pins for data cache, pins for rcu, pins for peripheral evaluation chip mode, pins for operation mode settings, pins for test mode, pins for vsb (only when nb85e500/nu85e502 are used). appendix c udl interface connector signal table (viewed from ie-v850e-mc-em1-b) users manual u14482ej2v0um00 62 c.4 nb85e500 pins and con1 to con3 correspondence tables correspondence between nb85e500 pins and con1 to con3 (1/3) nb85e500 pins pin no. a0 con1-con055 a1 con2-con055 a2 con1-con054 a3 con2-con054 a4 con1-con053 a5 con2-con053 a6 con1-con052 a7 con2-con052 a8 con1-con051 a9 con2-con051 a10 con1-con050 a11 con2-con050 a12 con1-con049 a13 con2-con049 a14 con1-con046 a15 con2-con046 a16 con1-con045 a17 con2-con045 a18 con1-con044 a19 con2-con044 a20 con1-con043 a21 con2-con043 a22 con1-con042 a23 con2-con042 a24 con1-con041 a25 con2-con041 d0 con1-con024 d1 con2-con024 d2 con1-con023 d3 con2-con023 d4 con1-con022 d5 con2-con022 d6 con1-con021 d7 con2-con021 d8 con1-con020 d9 con2-con020 d10 con1-con019 d11 con2-con019 d12 con1-con018 d13 con2-con018 pins for external memory connection d14 con1-con017 appendix c udl interface connector signal table (viewed from ie-v850e-mc-em1-b) users manual u14482ej2v0um00 63 correspondence between nb85e500 pins and con1 to con3 (2/3) nb85e500 pins pin no. d15 con2-con017 d16 con1-con014 d17 con2-con014 d18 con1-con013 d19 con2-con013 d20 con1-con012 d21 con2-con012 d22 con1-con011 d23 con2-con011 d24 con1-con010 d25 con2-con010 d26 con1-con009 d27 con2-con009 d28 con1-con008 d29 con2-con008 d30 con1-con007 d31 con2-con007 rdz con1-con030 wrz0 con1-con032 wrz1 con2-con032 wrz2 con1-con031 wrz3 con2-con031 iordz note 1 con2-con061 iowrz note 1 con1-con062 waitz con1-con037 hldrqz con2-con036 hldakz con1-con036 dc0 - note 2 dc1 - note 2 dc2 - note 2 dc3 - note 2 csz0 con1-con063 csz1 con2-con063 csz2 note 1 con1-con062 csz3 con2-con062 csz4 con1-con061 csz5 note 1 con2-con061 csz6 con1-con060 csz7 con2-con060 benz0 - note 2 pins for external memory connection benz1 - note 2 notes 1. cs5z and iordz are mutually exclusive, as are cs2z and iowrz i.e., only one pin in each pair can be used. 2. indicates that the corresponding pin does not exist in emulator. appendix c udl interface connector signal table (viewed from ie-v850e-mc-em1-b) users manual u14482ej2v0um00 64 correspondence between nb85e500 pins and con1 to con3 (3/3) nb85e500 pins pin no. benz2 - note benz3 - note bcystz con2-con029 refrqz con1-con035 selfref con2-con035 pins for external memory connection sdclk con2-con065 note indicates that the corresponding pin does not exist in emulator. caution the following pins are not supported by the emulator: pins for nb85e connection, pins for initial setting, pins for nu85e502 connection, pins for test mode appendix c udl interface connector signal table (viewed from ie-v850e-mc-em1-b) users manual u14482ej2v0um00 65 c.5 nu85e502 pins and con1 to con3 correspondence tables correspondence between nu85e502 pins and con1 to con3 (1/2) nu85e502 pins pin no. a0 con1-con055 a1 con2-con055 a2 con1-con054 a3 con2-con054 a4 con1-con053 a5 con2-con053 a6 con1-con052 a7 con2-con052 a8 con1-con051 a9 con2-con051 a10 con1-con050 a11 con2-con050 a12 con1-con049 a13 con2-con049 a14 con1-con046 a15 con2-con046 a16 con1-con045 a17 con2-con045 a18 con1-con044 a19 con2-con044 a20 con1-con043 a21 con2-con043 a22 con1-con042 a23 con2-con042 a24 con1-con041 a25 con2-con041 d0 con1-con024 d1 con2-con024 d2 con1-con023 d3 con2-con023 d4 con1-con022 d5 con2-con022 d6 con1-con021 d7 con2-con021 d8 con1-con020 d9 con2-con020 d10 con1-con019 d11 con2-con019 d12 con1-con018 d13 con2-con018 pins for external memory connection d14 con1-con017 appendix c udl interface connector signal table (viewed from ie-v850e-mc-em1-b) users manual u14482ej2v0um00 66 correspondence between nu85e502 pins and con1 to con3 (2/2) nu85e502 pins pin no. d15 con2-con017 d16 con1-con014 d17 con2-con014 d18 con1-con013 d19 con2-con013 d20 con1-con012 d21 con2-con012 d22 con1-con011 d23 con2-con011 d24 con1-con010 d25 con2-con010 d26 con1-con009 d27 con2-con009 d28 con1-con008 d29 con2-con008 d30 con1-con007 d31 con2-con007 sdrasz con2-con064 sdcasz con1-con064 sdwez con2-con030 cke con1-con065 dqm0 con1-con032 dqm1 con2-con032 dqm2 con1-con031 pins for external memory connection dqm3 con2-con031 caution the following pins are not supported by the emulator: pins for nb85e connection, pins for nb85e500 connection, pins for test mode user?s manual u14482ej2v0um00 67 appendix d electrical specifications of udl interface the electrical specifications of the udl interface when this product is connected to the ie-v850e-mc-a are described below. a voltage of 3.3 v 10% is supplied from the emulator as v dd . absolute maximum ratings (t a = 25 c) parameter symbol conditions ratings unit supply voltage (emulator) v dd ? 0.5 to +4.6 v supply voltage (target pin) tv dd ? 0.5 to +4.6 v input voltage v i1 v dd = 3.0 v to 3.6 v ? 0.5 to v dd +0.5 v clock input voltage v k v dd = 3.0 v to 3.6 v ? 0.5 to v dd +1.0 v per pin 40 ma low-level output current i ol total of all pins 400 ma per pin ? 40 ma high-level output current i oh total of all pins ? 400 ma output voltage v o v dd = 3.0 v to 3.6 v ? 0.5 to v dd +0.5 v operating ambient temperature t a 0 to +45 c capacitance (t a = 25 c, v dd = v ss = 0 v) parameter symbol conditions min. typ. max. unit input capacitance c i 10 pf i/o capacitance c io 10 pf output capacitance c o f c = 1 mhz 0 v for unmeasured pins 10 pf dc characteristics (t a = -40 c to +85 c, v dd 3.0 v to 3.6 v, v ss = 0 v) parameter symbol conditions min. typ. max. unit high-level input voltage v ih 0.65 v dd v dd +0.3 v low-level input voltage v il ? 0.5 0.2 v dd v high-level clock input voltage v xh x1 pin 0.8 v dd v dd +0.3 v low-level clock input voltage v xl x1 pin ? 0.3 0.15 v dd v high-level output voltage v oh i oh = ? 2 ma v dd ? 0.2 v low-level output voltage v ol i ol = 10 ma 0.4 v high-level input leak current i lih v i = v dd 10 a low-level input leak current i lil v i = 0 v ? 10 a high-level output leak current i loh v o = v dd ? 0.4 v 10 a low-level output leak current i lol v o = 0.4 v ? 10 a high-level output current i oh v o = v dd ? 0.4 v 2 ma low-level output current i ol v o = 0.4 v ? 12 ma remark typ. values are reference values when t a = 25 c and v dd = 3.3 v. appendix d electrical specifications of udl interface user?s manual u14482ej2v0um00 68 ac test input waveform (other than reset) measurement points v dd 0.4 v 0.65 v dd 0.2 v dd 0.65 v dd 0.2 v dd ac test input waveform (reset) measurement points 0.8 v dd 0.15 v dd 0.8 v dd 0.15 v dd v dd 0 v ac test output measurement points measurement points 0.8 v dd 0.15 v dd 0.8 v dd 0.15 v dd v dd 0 v load conditions c l = 50 pf dut note note dut stands for device under test. caution if the load capacitance exceeds 50 pf due to the circuit configuration, the load capacitance of this device must be maintained at 50 pf or lower using buffers. appendix d electrical specifications of udl interface user ? s manual u14482ej2v0um00 69 clock timing <1> <2> <3> <4> <5> <6> t vbclk vbclki cpuclk clock timing (t a = 0 to 40 c, output pin load capacitance c l = 50 pf) parameter symbol min. max. unit vbclk low-level width t wkil <1> 11 ns vbclk high-level width t wkih <2> 11 ns vbclki low-level width t wkol <3> 11 ns vbclki high-level width t wkoh <4> 11 ns vbclki delay time (from vbclk )t cld1 <5> 18 ns cpuclk delay time (from vbclki )t cld2 <6> 10 ns remark cpuclk: clock used inside evaluation chip reset timing 4t <7> <8> <9> vbclki dcresz eresetz eresetz timing (t a = 0 to 40 c, output pin load capacitance c l = 50 pf) asynchronous synchronous in relation to vbclki parameter symbol min. max. min. max. unit dcresz setup (to vbclki )t skrst <7> 12 17 ns eresetz delay time (from vbclki )t dkerst <8> 12 17 ns eresetz delay time (from dcresz )t drst <9> 4t-5 17 ns appendix d electrical specifications of udl interface users manual u14482ej2v0um00 70 target interface sram/page rom cycle (other than bus mode) t1 t2 <10> <11> <11> <12> <15> <16> <18> <20> <19> <21> <21> <22> <22> <18> <15> <17> <13> <14> <12> vbclki a (25:0) cs (7:0) z rdz d (31:0) (read) wr (3:0) z d (31:0) (write) bcystz waitz iordz iowrz appendix d electrical specifications of udl interface users manual u14482ej2v0um00 71 sram/page rom cycle (t a = 0 to 40 c, output pin load capacitance c l = 50 pf) synchronous in relation to vbclki parameter symbol min. max. unit a (25:0) delay time (from vbclki - )t ad <10> 18 ns cs (7:0) z delay time (from vbclki - )t cszd <11> 18 ns rdz delay time (from vbclki) t rdzd <12> 13 ns d (31:0) setup time (to vbclki - )t ds <13> - 15 ns d (31:0) hold time (from vbclki - )t dh <14> 11 ns wr (3:0) z delay time (from vbclki )t wrzd <15> 13 ns d (31:0) delay time 1 (from vbclki - )t dd1 <16> 26 ns d (31:0) delay time 2 (from vbclki - )t dd2 <17> 23 ns bcystz delay time (from vbclki - )t bcyd <18> 13 ns waitz setup time (to vbclki - )t wts <19> - 7ns waitz hold time (from vbclki - )t wth <20> 11 ns iordz delay time (from vbclki )t iord <21> 13 ns iowrz delay time (from vbclki )t iowr <22> 13 ns appendix d electrical specifications of udl interface users manual u14482ej2v0um00 72 dram cycle (fast page) trpw t1 t2 te tb te vbclki oez waitz a (25:0) ras (7:0) z cas (3:0) z we (3:0) z d (31:0) (read) d (31:0) (write) <23> <24> <24> <25> <25> <26> <26> <26> <26> <27> <27> <27> <27> <28> <28> <28> <28> <29> <30> <29> <30> <31> <32> <33> <32> <33> dram cycle (fast page) (t a = 0 to 40 c, output pin load capacitance c l = 50 pf) synchronous in relation to vbclki parameter symbol min. max. unit row address delay time (from vbclki - )t rad <23> 17 ns column address delay time (from vbclki - )t cad <24> 17 ns ras (7:0) z delay time (from vbclki )t rasd <25> 13 ns cas (3:0) z delay time (from vbclki )t casd <26> 14 ns oez delay time (from vbclki )t oed <27> 13 ns we (3:0) z delay time (from vbclki )t wed <28> 13 ns d (31:0) setup time (to vbclki )t ds3 <29> - 13 ns d (31:0) hold time (from vbclki )t dh3 <30> 11 ns d (31:0) delay time 1 (from vbclki - )t dd1 <31> 26 ns waitz setup time (to vbclki - )t wts <32> - 7ns waitz hold time (from vbclki - )t wth <33> 11 ns appendix d electrical specifications of udl interface users manual u14482ej2v0um00 73 dram cycle (hyper page (edo)) <26> <26> <26> <29> <30> <29> <30> <23> <25> <24> <24> <27> <27> <28> <28> <25> trpw t1 t2 tb te <31> vbclki a (25:0) ras (7:0) z cas (3:0) z oez we (3:0) z d (31:0) (read) d (31:0) (write) dram cycle (hyper page (edo)) (t a = 0 to 40 c, output pin load capacitance c l = 50 pf) synchronous in relation to vbclki parameter symbol min. max. unit row-address delay time (from vbclki - )t rad <23> 17 ns column address delay time (from vbclki - )t cad <24> 17 ns ras (7:0) z delay time (from vbclki )t rasd <25> 13 ns cas (3:0) z delay time (from vbclki) t casd <26> 14 ns oez delay time (from vbclki )t oed <27> 13 ns we (3:0) z delay time (from vbclki )t wed <28> 13 ns d (31:0) setup time (to vbclki )t ds3 <29> - 13 ns d (31:0) hold time (from vbclki )t dh3 <30> 11 ns d (31:0) delay time 1 (from vbclki - )t dd1 <31> 26 ns appendix d electrical specifications of udl interface users manual u14482ej2v0um00 74 sdram cycle (read) tprec vbclki a (25:0) cs (7:0) z sdrasz sdcasz sdwez dqm (3:0) d (31:0) cke tbcw tact tbcw tread tread tlate <34> <34> <35> <35> <11> <11> <36> <36> <36> <36> <37> <37> <38> <38> <39> <39> <40> <41> <42> <42> sdram cycle (read) (t a = 0 to 40 c, output pin load capacitance c l = 50 pf) synchronous in relation to vbclki parameter symbol min. max. unit row address delay time (from vbclki - )t sdrad <34> 14 21 ns column address delay time (from vbclki - )t sdcad <35> 14 21 ns cs (7:0) z delay time (from vbclki - )t cszd <11> 18 ns sdrasz delay time (from vbclki - )t srd <36> 11.5 13 ns sdcasz delay time (from vbclki - )t scd <37> 11.5 13 ns sdwez delay time (from vbclki - )t swd <38> 11.5 13 ns dqm (3:0) delay time (from vbclki - )t dqd <39> 11.5 13 ns d (31:0) setup time (to vbclki - )t ds4 <40> 0.5 ns d (31:0) hold time (from vbclki - )t dh4 <41> 11 ns cke delay time (from vbclki - )t cked <42> 11.5 13 ns appendix d electrical specifications of udl interface users manual u14482ej2v0um00 75 sdram cycle (write) tprec vbclki a (25:0) cs (7:0) z sdrasz sdcasz sdwez dqm (3:0) d (31:0) cke tbcw tact tbcw twrite twrite wend <34> <34> <35> <35> <11> <11> <36> <36> <36> <36> <37> <37> <38> <38> <38> <38> <39> <39> <39> <39> <31> <43> <42> <42> sdram cycle (write) (t a = 0 to 40 c, output pin load capacitance c l = 50 pf) synchronous in relation to vbclki parameter symbol min. max. unit row address delay time (from vbclki - )t sdrad <34> 14 21 ns column address delay time (from (vbclki - )t sdcad <35> 14 21 ns cs (7:0) z delay time (from vbclki - )t cszd <11> 18 ns sdrasz delay time (from vbclki - )t srd <36> 11.5 13 ns sdcasz delay time (from vbclki - )t scd <37> 11.5 13 ns sdwez delay time (from vbclki - )t swd <38> 11.5 13 ns dqm (3:0) delay time (from vbclki - )t dqd <39> 11.5 13 ns d (31:0) delay time 1 (from vbclki - )t dd1 <31> 26 ns d (31:0) delay time 2 (from vbclki - )t dd2 <43> 23 ns cke delay time (from vbclki - )t cked <42> 11.5 13 ns appendix d electrical specifications of udl interface users manual u14482ej2v0um00 76 bus arbitration interface vbclki vareq vaack stprq stpak refrqz hldrqz hldakz selfref <44> <44> <45> <46> <47> <48> <49> <49> <50> <50> <51> <52> <53> <53> <54> <55> bus arbitration interface (t a = 0 to 40 c, output pin load capacitance c l = 50 pf) synchronous in relation to vbclki parameter symbol min. max. unit vareq delay time (from vbclki - )t arqd <44> 12 ns vaack setup time (to vbclki - )t aks <45> - 8ns vaack hold time (from vbclki - )t akh <46> 11 ns stprq setup time (to vbclki - )t strqs <47> - 8ns stprq hold time (from vbclki - )t strqh <48> 11 ns stpak delay time (from vbclki )t stakd <49> 12 ns refrqz delay time (from vbclki )t rerqd <50> 12 ns hldrqz setup time (to vbclki )t hlrqs <51> - 8ns hldrqz hold time (from vbclki )t hlrqh <52> 11 ns hldakz delay time (from vbclki - )t hlakd <53> 12 ns selfref setup time (to vbclki - )t slrfs <54> - 8ns selfref hold time (from vbclki - )t slrfh <55> 11 ns appendix d electrical specifications of udl interface users manual u14482ej2v0um00 77 soc interface vsb arbitration timing vbclki vareq vaack vblock na85e initializes bus external bus master initializes bus <56> <58> <57> <59> soc interface vsb arbitration timing (t a = 0 to 40 c, output pin load capacitance c l = 50 pf) synchronous in relation to vbclki parameter symbol min. max. unit vareq setup time (to vbclki )t skq <56> - 6ns vareq hold time (from vbclki - )t hkq <57> 13 ns vaack delay time (from vbclk )t dkack <58> 12 17 ns vblock delay time (from vbclki - )t dkblock <59> 12 17 ns appendix d electrical specifications of udl interface users manual u14482ej2v0um00 78 vsb master read timing n seq vbclki vbttyp (1:0) vbsize (1:0) vbbenz (3:0) vbseq (2:0) vbctyp (2:0) vbdc vdselpz "h" vbd (31:0) vdcsz (7:0) vbwait vbahld vblast vblock vbwrite vba (27:26) vba (25:0) vbstz seq seq seq seq seq address1 address2 address3 address4 address1 byte en1 ctyp1 ctyp2 ctyp3 ctyp4 byte en2 byte en3 byte en4 size1 size2 size3 size4 address2 address3 address4 d1 d2 d3 d4 <61> <60> <62> <63> <64> <65> <66> <67> <68> <69> <70> <71> <72> <73> <74> <75> <76> <77> <78> <79> <80> <81> <82> <83> <84> <85> <86> <87> appendix d electrical specifications of udl interface users manual u14482ej2v0um00 79 vsb timer read timing (t a = 0 to 40 c, output pin load capacitance c l = 50 pf) synchronous in relation to vbclki parameter symbol min. max. unit vbttyp (1:0) delay time (from vbclki - )t dkt1 <60> 12 17 ns vbttyp (1:0) hold time (from vbclki )t hkt1 <61> 11 ns vbstz delay time (from vbclki - )t dkt2 <62> 12 17 ns vbstz hold time (from vbclki - )t hkt2 <63> 11 ns vba (27:26) delay time (from vbclki - )t dka1 <64> 19.5 24.5 ns vba (27:26) hold time (from vbclki - )t hka1 <65> 18.5 ns vba (25:0) delay time (from vbclki - )t dka2 <66> 12 17 ns vba (25:0) hold time (from vbclki - )t hka2 <67> 11 ns vbsize (1:0) delay time (from vbclki - )t dks1 <68> 12 17 ns vbsize (1:0) hold time (from vbclki - )t hks1 <69> 11 ns vbwrite delay time (from vbclki - )t dks2 <70> 12 17 ns vbwrite hold time (from vbclki - )t hks2 <71> 11 ns vbbenz (3:0) delay time (from vbclki - )t dks3 <72> 12 17 ns vbbenz (3:0) hold time (from vbclki - )t hks3 <73> 11 ns vbseq (2:0) delay time (from vbclki - )t dks4 <74> 12 17 ns vbseq (2:0) hold time (from vbclki - )t hks4 <75> 11 ns vblock delay time (from vbclki - )t dks5 <76> 12 17 ns vblock hold time (from vbclki - )t hks5 <77> 11 ns vbctyp (2:0) delay time (from vbclki - )t dks6 <78> 12 17 ns vbctyp (2:0) hold time (from vbclki - )t hks6 <79> 11 ns vdcsz (7:0) delay time (from vbcli - )t dkc <80> 12 17 ns vdcsz (7:0) hold time (from vbclki - )t hkc <81> 11 ns vbd (31:0) setup time (to vbclki - )t skd <82> 2 ns vbd (31:0) hold time (from vbclki )t hkdi <83> 13 ns vbwait setup time (to vbclki - )t skw <84> - 6ns vbwait hold time (from vbclki - )t hkw <85> 13 ns vbahld setup time (to vbclki - )t skw <84> - 6ns vbahld hold time (from vbclki - )t hkw <85> 13 ns vblast setup time (to vbclki - )t skw <84> - 6ns vblast hold time (from vbclki - )t hkw <85> 13 ns vbdc delay time (from vbclki )t dks7 <86> 4.6 ns vbdc hold time (from vbclki )t hks7 <87> 0 ns appendix d electrical specifications of udl interface users manual u14482ej2v0um00 80 vsb master write timing n seq vbclki vbttyp (1:0) vbsize (1:0) vbbenz (3:0) vbseq (2:0) vbctyp (2:0) vbdc vbd (31:0) vdcsz (7:0) vbwait vbahld vblast vblock vbwrite vba (27:26) vba (25:0) vbstz seq seq seq seq seq address1 address2 address3 address4 address1 byte en1 ctyp1 ctyp2 data2 data3 data4 ctyp3 ctyp4 byte en2 byte en3 byte en4 size1 size2 size3 size4 address2 address3 address4 data1 vdselpz "h" <60> <61> <63> <62> <64> <65> <67> <66> <69> <68> <70> <71> <72> <73> <75> <74> <77> <76> <79> <78> <80> <81> <88> <89> <84> <85> <87> <86> appendix d electrical specifications of udl interface users manual u14482ej2v0um00 81 vsb master write timing (t a = 0 to 40 c, output pin load capacitance c l = 50 pf) synchronous in relation to vbclki parameter symbol min. max. unit vbttyp (1:0) delay time (from vbclki - )t dkt1 <60> 12 17 ns vbttyp (1:0) hold time (from vbclki - )t hkt1 <61> 11 ns vbstz delay time (from vbclki - )t dkt2 <62> 12 17 ns vbstz hold time (from vbclki - )t hkt2 <63> 11 ns vba (27:26) delay time (from vbclki - )t dka1 <64> 19.5 24.5 ns vba (27:26) hold time (from vbclki - )t hka1 <65> 18.5 ns vba (25:0) delay time (from vbclki - )t dka2 <66> 12 17 ns vba (25:0) hold time (from vbclki - )t hka2 <67> 11 ns vbsize (1:0) delay time (from vbclki - )t dks1 <68> 12 17 ns vbsize (1:0) hold time (from vbclki - )t hks1 <69> 11 ns vbwrite delay time (from vbclki - )t dks2 <70> 12 17 ns vbwrite hold time (from vbclki - )t hks2 <71> 11 ns vbbenz (3:0) delay time (from vbclki - )t dks3 <72> 12 17 ns vbbenz (3:0) hold time (from vbclki - )t hks3 <73> 11 ns vbseq (2:0) delay time (from vbclki - )t dks4 <74> 12 17 ns vbseq (2:0) hold time (from vbclki - )t hks4 <75> 11 ns vblock delay time (from vbclki - )t dks5 <76> 12 17 ns vblock hold time (from vbclki - )t hks5 <77> 11 ns vbctyp (2:0) delay time (from vbclki - )t dks6 <78> 12 17 ns vbctyp (2:0) hold time (from vbclki - )t hks6 <79> 11 ns vdcsz (7:0) delay time (from vbclki - )t dkc <80> 12 17 ns vdcsz (7:0) hold time (from vbclki - )t hkc <81> 11 ns vbd (31:0) delay time (from vbclki - )t dkd0 <88> 12 25 ns vbd (31:0) delay time (from vbclki )t dkd1 <89> 12 25 ns vbwait setup time (to vbclki - )t skw <84> - 6ns vbwait hold time (from vbclki - )t hkw <85> 13 ns vbahld setup time (to vbclki - )t skw <84> - 6ns vbahld hold time (from vbclki - )t hkw <85> 13 ns vblast setup time (to vbclki - )t skw <84> - 6ns vblast hold time (from vbclki - )t hkw <85> 13 ns vbdc delay time (from vbclk )t dks7 <86> 4.6 ns vbdc hold time (from vbclki )t hks7 <87> 0 ns appendix d electrical specifications of udl interface users manual u14482ej2v0um00 82 npb interface timing npb interface write timing vpa (13:0) vpd (15:0) vpstb vpretr vpwrite vpubenz vplock t sret t hret t acc addr1 data1 addr2 t wstb t ad t hwd t sdsad npb interface read timing vpd (15:0) vpstb data1 t srd t hrd npb interface timing (during write) (t a = 0 to 40 c, output pin load capacitance c l = 50 pf) parameter symbol min. max. unit access time t acc t - 5ns address decoding time t ad t+0.5t - 5ns vpstb high-level width t wstb nt+t - 5 note ns write vpd setup time (to vpstb - )t sdsad 0.5t - 2ns write vpd hold time (from vpstb )t hwd 0ns vpretr setup time (to vpstb )t sret 10 ns vpretr hold time (from vpstb )t hret 0ns read vpd setup time t srd 10 ns read vpd hold time t hrd 0ns notes n = 1 when the operating frequency is up to 25 mhz n = 2 when the operating frequency is 25 to 33 mhz n = 4 when the operating frequency is 33 to 50 mhz n = 5 when the operating frequency is 50 to 66 mhz appendix d electrical specifications of udl interface users manual u14482ej2v0um00 83 dma req/ack timing vbclki dmarq (3:0) dmtco (3:0) dmactv (3:0) t srqk t hrqk t dkd t dkd dma req/ack timing (t a = 0 to 40 c, output pin load capacitance c l = 50 pf) synchronous in relation to vbclki parameter symbol min. max. unit dmarq setup time (to vbclki )t srqk 4ns dmarq hold time (from vbclki )t hrqk 3ns dmactv/dmtco delay time (from vbclki - )t dkd 12 17 ns dma stop request timing t skds t hkds vbclki idmastp dma stop request timing (t a = 0 to 40 c, output pin load capacitance c l = 50 pf) synchronous in relation to vbclki parameter symbol min. max. unit idmastp setup time (to vbclki - )t skds - 6ns idmastp hold time (from vbclki - )t hkds 3ns appendix d electrical specifications of udl interface users manual u14482ej2v0um00 84 int/nmi request timing t wih int/dcnmi t wil t cyi int/nmi request timing (t a = 0 to 40 c, output pin load capacitance c l = 50 pf) synchronous parameter symbol min. max. unit int/nmi high-level width t wih 10 ns int/nmi low-level width t wil 10 ns int interval t cyi 3t ns appendix d electrical specifications of udl interface users manual u14482ej2v0um00 85 software stop timing <90> <91> <92> <93> <96> <94> <95> vbclki stprq stpak swstoprq int/dcnmi cgrel hardware stop timing vbclki stprq stpak hwstoprq dcstopz cgrel <97> <96> <95> <90> <91> <92> <93> software/hardware stop timing (t a = 0 to 40 c, output pin load capacitance c l = 50 pf) asynchronous synchronous in relation to vbclki parameter symbol min. max. min. max. unit stprq delay time (from vbclki - )t dksq <90> 12 17 ns stpak setup time (to vbclki )t sksa <91> 0 ns stpak hold time (from stprq )t hqsa <92> 7 ns stop status delay time (from vbclki )t dkss <93> 12 17 ns stop release delay time t drsr <94> 0 15 ns cgrel setup time (to vbclki - )t sksg <95> t ns cgrel hold time (from vblcki - )t hksg <96> 13 ns dcstopz setup time (to vbclki - )t skst <97> 10 ns appendix d electrical specifications of udl interface users manual u14482ej2v0um00 86 external probe timing operation sampling timing write/fetch t sked t hked data vbclki extd (7:0) external probe timing (operation sampling timing write/fetch) (t a = 0 to 40 c, output pin load capacitance c l = 50 pf) synchronous in relation to vbclki parameter symbol min. max. unit extd (7:0) setup time (to vbclki - )t sked 4ns extd (7:0) hold time (from vbclki - )t hked 0ns operation sampling timing read t sred rdz t sked t hked data vbclki extd (7:0) external probe timing (operation sampling timing read) (t a = 0 to 40 c, output pin load capacitance c l = 50 pf) asynchronous synchronous in relation to vbclki parameter symbol min. max. min. max. unit extd (7:0) setup time (to vbclki - )t sked 4ns extd (7:0) hold time (from vbclki - )t hked 0ns rdz setup time t sred 6ns users manual u14482ej2v0um00 87 appendix e restrictions (1) the vsb bus and memory controller bus cannot be used together. the memory controller bus (equivalent to nb85e500/nu85e502) incorporated in the emulator and the vsb bus cannot be used together. (2) when vpstb is not enabled, an undefined signal is output to vpretr. make vpretr input to the emulator from the udl board hi-z while the vpstb signal is low level. (3) when using the emulator in the 64 mb mode, do not use vba (27:26). when using the emulator in the 64 mb mode, vba (27:26) becomes undefined and must therefore not be used. (4) not all the pins of the v850e1 can be emulated by the emulator. the emulator cannot perform emulation of the following pins because they are not included in the emulator. vbseq (2:0) pin among pins for vsb (sequential status) vpdact pin among pins for npb (active level from external address decoder) pins for vfb (pins for internal rom access) pins for vdb (pins for internal ram access) pins for instruction cache pins for data cache pins for rcu (pins for debugging circuit) pins for operation mode setting pins for test mode (5) not all the pins of the nb85e500/nu85e502 can be emulated by the emulator. the emulator cannot perform emulation of the following pins because they are not included in the emulator. pins for nb85e connection pins for initial setting dc0 to dc3 pins among pins for external memory connection (for data bus control) benz0 to benz3 pins among pins for external memory connection (byte enable) pins for nb85e500/nu85e502 connection pins for test mode appendix e restrictions users manual u14482ej2v0um00 88 (6) the iordz, iowrz pins are also used as the csz2, csz5 pins. if the memory controller contained in the emulator is used, the iordz, iowrz pins and the csz2, csz5 pins provided for the nb85e500 cannot be used together. they must be exclusively switched. since csz5/csz2 are set after reset, the following instruction must be executed on the program after each reset in order to use iordz, iowrz. st.b 0xzz, 0xfffff049 remark zz = 00h: use as csz5/csz2 (initial value after reset) = 20h: use as iordz/csz2 = 04h: use as csz5/iowrz = 24h: use as iordz/iowrz (7) emulation memory cannot be used with an 8-bit bus size. the standard emulation memory provided in the ie-v850e-mc-em1-b, and the target substitution memory provided in the IE-V850E-MC-MM2 (sold separately) cannot be used with an 8-bit bus size. use a 16-bit or 32- bit bus. although nec has taken all possible steps to ensure that the documentation supplied to our customers is complete, bug free and up-to-date, we readily accept that errors may occur. despite all the care and precautions we've taken, you may encounter problems in the documentation. please complete this form whenever you'd like to report errors or suggest improvements to us. hong kong, philippines, oceania nec electronics hong kong ltd. fax: +852-2886-9022/9044 korea nec electronics hong kong ltd. seoul branch fax: 02-528-4411 taiwan nec electronics taiwan ltd. fax: 02-2719-5951 address north america nec electronics inc. corporate communications dept. fax: 1-800-729-9288 1-408-588-6130 europe nec electronics (europe) gmbh technical documentation dept. fax: +49-211-6503-274 south america nec do brasil s.a. fax: +55-11-6462-6829 asian nations except philippines nec electronics singapore pte. ltd. fax: +65-250-3583 japan nec semiconductor technical hotline fax: 044-435-9608 i would like to report the following error/make the following suggestion: document title: document number: page number: thank you for your kind support. if possible, please fax the referenced page or drawing. excellent good acceptable poor document rating clarity technical accuracy organization cs 00.6 name company from: tel. fax facsimile message |
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