View AD5282-EVAL_1175358.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

rev. 0 a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 www.analog.com fax: 781/326-8703 ? analog devices, inc., 2002 ad5280/ad5282 * 15 v, i 2 c compatible 256-position digital potentiometers features 256 position ad5280: 1-channel ad5282: 2-channel (independently programmable) potentiometer replacement 20 k , 50 k , 200 k low temperature coefficient 30 ppm/ c internal power-on midscale preset 5 v to 15 v single-supply; 5.5 v dual-supply operation i 2 c compatible interface applications multimedia, video, and audio communications mechanical potentiometer replacement instrumentation: gain, offset adjustment programmable voltage source programmable current source line impedance matching functional block diagrams 8 rdac register output register pwr on reset address decode serial input register ad5280 shdn v dd v ss v l scl sda gnd ad0 ad1 aw b o 1 o 2 shdn v dd v ss v l scl gnd rdac1 register rdac2 register output register serial input register ad5282 ad0 ad1 o 1 pwr on reset 8 address decode sda a 1 w 1 b 1 a 2 w 2 b 2 general description the ad5280/ad5282 provides a single-/dual-channel, 256-position digitally controlled variable resistor (vr) device. 1 these devices perform the same electronic adjustment function as a potenti- ometer, trimmer, or variable resistor. each vr offers a completely programmable value of resistance between the a terminal and the wiper or the b terminal and the wiper. the fixed a-to-b terminal resistance of 20 k ? , 50 k ? , or 200 k ? has a 1% chan- nel-to-channel matching tolerance. nominal temperature coefficient of both parts is 30 ppm/ c. another key feature of these parts is that they can operate up to +15 v or 5 v. wiper position programming defaults to midscale at system power-on. once powered, the vr wiper position is programmed by an i 2 c compatible 2-wire serial data interface. both parts have additional programmable logic outputs that enable users to drive digital loads, logic gates, led drivers, and analog switches in their system. the ad5280/ad5282 are available in thin surface-mount 14-lead and 16-lead tssop packages. all parts are guaranteed to operate over the extended industrial temperature range of 40 c to +85 c. for 3-wire spi compatible interface appli- cations, see ad5260/ad5262 products. * patent pending. note 1 the terms digital potentiometer, vr, and rdac are used interchangeably.
rev. 0 e2e ad5280/ad5282especifications (v dd = +15 v, v ss = 0 v or v dd = +5 v, v ss = e5 v; v logic = 5 v, v a = +v dd , v b = 0 v; e40 c < t a < +85 c, unless otherwise noted.) electrical characteristics 20 k , 50 k , 200 k version parameter symbol conditions min typ 1 max unit dc characteristicserheostat mode specifications apply to all vrs resistor differential nl 2 r-dnl r wb , v a = nc e1 1/4 +1 lsb resistor nonlinearity 2 r-inl r wb , v a = nc e1 1/4 +1 lsb nominal resistor tolerance 3 r ab t a = 25 c e30 +30 % resistance temperature coefficient r ab / tv ab = v dd , wiper = no connect 30 ppm/ c wiper resistance r w i w = v dd /r, v dd = 3 v or 5 v 60 150 dc characteristicsepotentiometer divider mode specifications apply to all vrs resolution n 8 bits integral nonlinearity 4 inl e1 1/4 +1 lsb differential nonlinearity 4 dnl e1 1/4 +1 lsb voltage divider temperature v w / tc ode = 80 h 5 ppm/ c coefficient full-scale error v wfse code = ff h e2 e1 0 lsb zero-scale error v wzse code = 00 h 0+1+ 2 lsb resistor terminals voltage range 5 v a,b,w v ss v dd v capacitance 6 a, b c a,b f = 5 mhz, measured to 25 pf gnd, code = 80 h capacitance 6 wc w f = 1 mhz, measured to 55 pf gnd, code = 80 h common-mode leakage i cm v a = v b = v w 1na shutdown current i shdn 5 a digital inputs and outputs input logic high v ih 2.4 v input logic low v il 0.8 v input logic high v ih v logic = 3 v, v ss = 0 2.1 v input logic low v il v logic = 3 v, v ss = 0 0.6 v output logic high (sdo) v ih 4.9 v output logic low (sdo) v il 0.4 v input current i il v in = 0 v or 5 v 1 a input capacitance 6 c il 5pf power supplies logic supply v logic 2.7 5.5 v power single-supply range v dd range v ss = 0 v 5 15 v power dual-supply range v dd/ss range 4.5 5.5 v logic supply current i logic v logic = 5 v 60 a positive supply current i dd v ih = 5 v or v il = 0 v 0.1 1 a negative supply current i ss 0.1 1 a power dissipation 7 p diss v ih = 5 v or v il = 0 v, v dd = +5 v, 0.2 0.3 mw v ss = e5 v power supply sensitivity pss 0.002 0.01 %/% dynamic characteristics 6, 8, 9 bandwidth e3 db bw_20k r ab = 20 k , code = 80 h 310 khz bw_50k r ab = 50 k , code = 80 h 150 khz bw_200k r ab = 200 k , code = 80 h 35 khz total harmonic distortion thd w v a = 1 v rms, r ab = 20 k 0.014 % v b = 0 v dc, f = 1 khz v w settling time t s v a = 5 v, v b = 5 v, 5 s 1 lsb error band crosstalk ct v a = v dd , v b = 0 v, measure 15 nv-s vw1 with adjacent rdac making full-scale code change analog crosstalk cta measure v w1 with v w2 = 5 v p-p e62 db @ f = 10 khz resistor noise voltage e n_wb r wb = 20 k , f = 1 khz 18 nv/ hz
rev. 0 ad5280/ad5282 e3e parameter symbol conditions min typ 1 max unit interface timing characteristics applies to all parts 6, 10 scl clock frequency f scl 400 khz t buf bus free time between stop and start t 1 1.3 s t hd:sta hold time (repeated start) t 2 after this period, the first 0.6 s clock pulse is generated t low low period of scl clock t 3 1.3 s t high high period of scl clock t 4 0.6 50 s t su:sta setup time for start condition t 5 0.6 s t hd:dat data hold time t 6 0.9 s t su:dat data setup time t 7 100 ns t f fall time of both sda and scl signals t 8 300 ns t r rise time of both sda and scl signals t 9 300 ns t su:sto setup time for stop condition t 10 0.6 s notes 1 typicals represent average readings at 25 c, v dd = +5 v, v ss = e5 v. 2 resistor position nonlinearity error r-inl is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. r-dnl measures the relative step change from ideal between successive tap positions. parts are guaranteed monotonic. 3 v ab = v dd , wiper (v w ) = no connect. 4 inl and dnl are measured at v w with the rdac configured as a potentiometer divider similar to a voltage output d/a converter. v a = v dd and v b = 0 v. dnl specification limits of 1 lsb maximum are guaranteed monotonic operating conditions. 5 resistor terminals a, b, w have no limitations on polarity with respect to each other. 6 guaranteed by design and not subject to production test. 7 p diss is calculated from (i dd v dd ). cmos logic level inputs result in minimum power dissipation. 8 bandwidth, noise, and settling time are dependent on the terminal resistance value chosen. the lowest r value results in the fa stest settling time and highest bandwidth. the highest r value results in the minimum overall power consumption. 9 all dynamic characteristics use v dd = 5 v. 10 see timing diagram for location of measured values. specitcations subject to change without notice.
rev. 0 e4e ad5280/ad5282 caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the ad5280/ad5282 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. warning! esd sensitive device absolute maximum ratings 1 (t a = 25 c, unless otherwise noted.) v dd to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . . e0.3 v, +15 v v ss to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 v, e7 v v dd to v ss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 v v a , v b , v w to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . v ss , v dd a x e b x , a x e w x , b x e w x intermittent 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 ma continuous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 ma v logic to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 v, 7 v output voltage to gnd . . . . . . . . . . . . . . . . . . . . . . 0 v, 7 v operating temperature range . . . . . . . . . . . e40 c to +85 c thermal resistance 3 ja , tssop-14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 c/w tssop-16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 c/w ordering guide number of r ab package package parts per branding model channels (k ) temp description option container information * ad5280bru20 1 20 e40 c to +85 ct ssop-14 ru-14 96 ad5280b20 ad5280bru20-reel7 1 20 e40 c to +85 ct ssop-14 ru-14 1000 ad5280b20 ad5280bru50 1 50 e40 c to +85 ct ssop-14 ru-14 96 ad5280b50 ad5280bru50-reel7 1 50 e40 c to +85 ct ssop-14 ru-14 1000 ad5280b50 ad5280bru200 1 200 e40 c to +85 ct ssop-14 ru-14 96 ad5280b200 ad5280bru200-reel7 1 200 e40 c to +85 ct ssop-14 ru-14 1000 ad5280b200 ad5282bru20 2 20 e40 c to +85 ct ssop-16 ru-16 96 ad5282b20 ad5282bru20-reel7 2 20 e40 c to +85 ct ssop-16 ru-16 1000 ad5282b20 ad5282bru50 2 50 e40 c to +85 ct ssop-16 ru-16 96 ad5282b50 ad5282bru50-reel7 2 50 e40 c to +85 ct ssop-16 ru-16 1000 ad5282b50 ad5282bru200 2 200 e40 c to +85 ct ssop-16 ru-16 96 ad5282b200 ad5282bru200-reel7 2 200 e40 c to +85 ct ssop-16 ru-16 1000 ad5282b200 the ad5280/ad5282 die size is 75 mm 120 mm, 9,000 sq. mm. contains 3077 transistors. * line 1 contains model number, line 2 contains adi logo followed by the end-to-end resistance value, and line 3 contains date co de yyww. maximum junction temperature (t j max) . . . . . . . . . 150 c storage temperature . . . . . . . . . . . . . . . . . . e65 c to +150 c lead temperature ru-14, ru-16 (vapor phase, 60 sec) . . . . . . . . . . . . 215 c ru-14, ru-16 (infrared, 15 sec) . . . . . . . . . . . . . . . . 220 c notes 1 stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 maximum terminal current is bound by the maximum current handling of the switches, maximum power dissipation of the package, and maximum applied voltage across any two of the a, b, and w terminals at a given resistance. 3 package power dissipation (t j max e t a )/ ja
rev. 0 ad5280/ad5282 e5e ad5282 pin function description pin mnemonic description 1o 1 logic output terminal o 1 2a 1 resistor terminal a 1 3w 1 wiper terminal w 1 4b 1 resistor terminal b 1 5v dd positive power supply. specified for operation from 5 v to 15 v (sum of |v dd | + |v ss | 15 v). 6 shdn aa ww ada shdn s s sda sd ad a dadad ad a dadad nd ss nss s dd ss sn ad w ww a a adnnndsn d a a w ww dd ss s dd ss shdn aa ww ada shdn s s sda sd a d a dadad a d a dadad nd ss nss s dd ss sn ad nnan adnnan w ns w dd s hdn s sda ss nd ad ad a ad adnnan w ns a w dd s hdn s sda a w ss nd ad ad ad
rev. 0 ? ad5280/ad5282 ?ypical performance characteristics code ?decimal rheostat mode inl ?lsb 0 32 160 256 0 ?.6 64 96 128 192 224 ? ?.8 ?.4 ?.2 0.6 1 0.8 0.4 0.2 r ab = 20k t a = 25 c 5v +15v +5v tpc 1. r-inl vs. code vs. supply voltages code ?decimal potentiometer mode dnl ?lsb 0 32 160 256 0 ?.3 64 96 128 192 224 ?.5 ?.4 ?.2 ?.1 0.3 0.5 0.4 0.2 0.1 t a = +85 c r ab = 20k t a = +125 c t a = +25 c t a = ?0 c tpc 4. dnl vs. code, v dd /v ss = 5 v |v dd ?v ss | ?v inl ?lsb 0 20 0 ?.5 51015 ?.0 1.0 0.5 r ab = 20k t a = 25 c avg + 3 avg avg ?3 tpc 7. inl over supply voltage code ?decimal rheostat mode dnl ?lsb 0 32 160 256 0 ?.3 64 96 128 192 224 ?.5 ?.8 ?.2 ?.1 0.3 0.5 0.4 0.2 0.1 5v +5v +15v r ab = 20k t a = 25 c tpc 2. r-dnl vs. code vs. supply voltages code ?decimal potentiometer mode inl ?lsb 0 32 160 256 0 ?.6 64 96 128 192 224 ? ?.8 ?.4 ?.2 0.6 1 0.8 0.4 0.2 r ab = 20k t a = 25 c +5v 5v +15v tpc 5. inl vs. code vs. supply voltages |v dd ?v ss | ?v rinl ?lsb 0 20 0 ?.5 51015 ?.0 2.0 1.0 r ab = 20k t a = 25 c avg + 3 avg avg ?3 ?.5 1.5 0.5 ?.0 tpc 8. rinl over supply voltage code ?decimal potentiometer mode inl ?lsb 0 32 160 256 0 ?.6 64 96 128 192 224 ? ?.8 ?.4 ?.2 0.6 1 0.8 0.4 0.2 t a = +85 c r ab = 20k t a = +125 c t a = +25 c t a = ?0 c tpc 3. inl vs. code, v dd /v ss = 5 v code ?decimal potentiometer mode dnl ?lsb 0 32 160 256 0 ?.3 64 96 128 192 224 ?.5 ?.4 ?.2 ?.1 0.3 0.5 0.4 0.2 0.1 r ab = 20k t a = 25 c +5v 5v +15v tpc 6. dnl vs. code vs. supply voltages temperature ? c full-scale error ?lsb ?0 100 ?.0 ?.2 40 60 80 ?.0 0 ?.6 r ab = 20k ?.6 ?.2 ?.8 ?.4 v dd /v ss = 5v/0v v dd /v ss = 5v v dd /v ss = 15v/0v ?.4 ?.8 20 0 ?0 tpc 9. full-scale error
rev. 0 ad5280/ad5282 ? temperature ? c zero-scale error ?lsb ?0 100 1.0 0.8 40 60 80 0 2.0 1.4 r ab = 20k 0.4 1.8 1.2 0.6 v dd /v ss = 15v/0v v dd /v ss = 5v v dd /v ss = 5v/0v 1.6 0.2 20 0 ?0 tpc 10. zero-scale error v ih ?v i logic ? a 0 5 34 10 1000 100 2 1 r ab = 20k t a = 25 c v dd /v ss = 5v/0v v logic = 5v v dd /v ss = 5v/0v v logic = 3v tpc 13. v logic supply current vs. digital input voltage frequency ?hz gain ?db 1m ?0 0 100k 10k ?2 ?0 ? 1k ?2 ?8 ?4 ?6 ?8 ?4 t a = 25 c v a = 50mv rms v dd /v ss = 5v 01h 02h 80h 40h 20h 04h 08h 10h tpc 16. gain vs. frequency vs. code, r ab = 20 k ? temperature ? c i dd /i ss supply current ?na ?0 125 100 59 92 1 1000 10 26 ? v logic = 5v v ih = 5v v il = 0v r ab = 20k i ss @ v dd /v ss = 5v i ss @ v dd /v ss = 15v/0v i dd @ v dd /v ss = 5v tpc 11. supply current vs. temperature code ?decimal rheostat mode tempco ?ppm/ c 256 ?00 700 96 64 32 ?00 0 t a = 25 c 128 192 224 20k 50k 0 100 200 600 500 400 300 200k tpc 14. rheostat mode tempco r wb / t vs. code, v dd /v ss = 5 v frequency ?hz gain ?db 1m ?0 0 100k 10k ?2 ?0 ? 1k ?2 ?8 ?4 ?6 ?8 ?4 t a = 25 c v a = 50mv rms v dd /v ss = 5v 01h 02h 80h 40h 20h 04h 08h 10h tpc 17. gain vs. frequency vs. code, r ab = 50 k ? temperature ? c i logic ? a ?0 125 24.0 59 92 23.0 26.0 24.5 r ab = 20k 25.0 25.5 23.5 v dd /v ss = 5v 26 ? v dd /v ss = 15v/0v tpc 12. v logic supply current vs. temperature code ?decimal potentiometer mode tempco ?ppm/ c 256 ?0 96 64 32 ?0 0 t a = 25 c 128 192 224 50k 0 20 40 120 100 80 60 200k 20k tpc 15. potentiometer mode tempco v wb / t vs. code, v dd /v ss = 5 v frequency ?hz gain ?db ?0 0 100k 10k ?2 ?0 ? 1k ?2 ?8 ?4 ?6 ?8 ?4 t a = 25 c v a = 50mv rms v dd /v ss = 5v 01h 02h 80h 40h 20h 04h 08h 10h tpc 18. gain vs. frequency vs. code, r ab = 200 k ?
rev. 0 ? ad5280/ad5282 frequency ?hz gain ?db 1m ?0 0 100k 10k ?2 ?0 ? 1k ?2 ?8 ?4 ?6 ?8 ?4 t a = 25 c v dd /v ss = 5v v a = 50mv rms r = 20k 310khz r = 200k 35khz r = 50k 150khz tpc 19. ? db bandwidth frequency ?mhz psrr ??b 1000000 0 80 100000 10000 1000 20 40 60 code = 80 h , v a = v dd , v b = 0v 100 ?srr @ v dd /v ss = 5v dc 10% p-p ac + psrr @ v dd /v ss = 5v dc 10% p-p ac tpc 22. psrr vs. frequency 1.50 s 33.41 s 1.0v a2 tpc 25. digital feedthrough vs. time frequency ?hz nomalized gain flatness ?0.1db/div 100k 10k 1k 100 ?db t a = 25 c v dd /v ss = 5v r = 20k r = 50k r = 200k tpc 20. normalized gain flatness vs. frequency 2.04 s 852.0 s 1.2v a2 tpc 23. midscale glitch energy code 80 h to 7f h code ?decimal theoretical i wb_max ?ma 256 0.01 100 96 64 32 0.1 1 10 0 v a = v b = open t a = 25 c 128 192 224 r ab = 20k r ab = 50k r ab = 200k tpc 26. i max vs. code frequency ?hz i logic ? a 10000000 0 500 100 1000000 100000 10000 200 300 400 v dd /v ss = 5v t a = 25 c code = 55 h code = ff h tpc 21. v logic supply current vs. frequency tpc 24. large signal settling time long term channel-to-channel rab match ?% frequency ?mhz 0 40 10 20 30 codes set to midscale 3 lots sample size = 135 ?.5 ?.45 ?.4 ?.35 ?.3 ?.25 ?.2 ?.15 ?.1 ?.05 0.1 0.15 0.2 0 0.05 tpc 27. channel-to-channel resistance matching (ad5282)
rev. 0 ad5280/ad5282 e9e test circuits test circuits 1 to 11 define the test conditions used in the product specification table. v ms a w b dut v v+ = v dd 1lsb = v+/2 n test circuit 1. potentiometer divider nonlinearity error (inl, dnl) no connect i w v ms a w b dut test circuit 2. resistor position nonlinearity error (rheostat operation; r-inl, r-dnl) v ms1 i w = v dd /r nominal v ms2 v w r w = [v ms1 e v ms2 ]/i w a w b dut test circuit 3. wiper resistance v ms % v dd % pss (%/%) = v+ = v dd 10% psrr (db) = 20 log v ms v dd ( ) v dd v a v ms a w b v+ test circuit 4. power supply sensitivity (pss, pssr) op279 w 5v b v out offset gnd offset bias a dut v in test circuit 5. inverting gain b a v in op279 w 5v v out offset gnd offset bias dut test circuit 6. noninverting gain +15v e15v w a 2.5v b v out offset gnd dut ad8610 v in test circuit 7. gain vs. frequency w b v ss to v dd dut i sw code = h r sw = 0.1v i sw 0.1v test circuit 8. incremental on resistance w b v cm i cm a nc gnd nc v ss v dd dut nc = no connect test circuit 9. common-mode leakage current i logic scl sda v logic digital input voltage test circuit 10. v logic current vs. digital input voltage v dd v in n/c rdac 1 rdac 2 v ss v out b 1 b 2 w 1 w 2 a 1 a 2 c ta = 20 log [v out / v in ] test circuit 11. analog crosstalk (ad5282 only)
rev. 0 e10e ad5280/ad5282 t 8 t 1 t 8 t 3 t 2 t 6 t 9 t 5 t 10 s p t 7 t 4 s p sda scl figure 1. detailed timing diagram data of ad5280/ad5282 is accepted from the i 2 c bus in the following serial format: s 01011ad1ad0r/ w a a s sd a d d d d d d d d a sa d w s s s a a a a aa a w w a aaa a shdn d dddddddd d adad w a s sd d d d d dd dd a adad a adad a adad s as sa as a saaddss a nsn a daa s sda wda adad w d d d d d d d d a adad na as s as sa as a saaddss a daassd dasnwd s sda a dsdaw
rev. 0 ad5280/ad5282 ?1 operation the ad5280/ad5282 provides a single-/dual-channel, 256- position, digitally controlled variable resistor (vr) device. to program the vr settings, refer to the digital interface sec tion. both parts have an internal power-on preset that places the wiper at midscale during power-on, which simplifies the fault condi tion recovery at power-up. operation of the power-on preset function also depends on the state of the v l p in. in addition, the shutdown shdn pin of the ad5280/ad5282 places the rdac in an almost zero power consumption state where terminal a is open cir cuited and the wiper w is connected to terminal b, resulting in only leakage currents being consumed in the vr structure. during shutdown, the vr latch settings are maintained or new settings can be programmed. when the part is returned from shutdown, the corresponding vr setting will be applied to the rdac. rdac latch and decoder ax s hdn d7 d6 d5 d4 d3 d2 d1 d0 r s r s r s r s wx bx figure 4. ad5280/ad5282 equivalent rdac circuit programming the variable resistor rheostat operation the nominal resistance of the rdac between terminals a and b is available in 20 k ? , 50 k ? , and 200 k ? . the final two or three digits of the part number determine the nominal resistance value, e.g., 20 k ? = 20; 50 k ? = 50; 200 k ? = 200. the nominal resistance (r ab ) of the vr has 256 contact points accessed by the wiper terminal, plus the b terminal contact. the 8-bit data in the rdac latch is decoded to select one of the 256 possible settings. assuming a 20 k ? part is used, the wiper? first con- nection starts at the b terminal for data 00 h . since there is a 60 ? wiper contact resistance, such a connection yields a minimum of 60 ? resistance between terminals w and b. the second connection is the first tap point that corresponds to 138 ? (r wb = r ab /256 + r w = 78 ? + 60 ? ) for data 01 h . the third connection is the next tap point representing 216 ? (78 2 + 60) for data 02 h , and so on. each lsb data value increase moves the wiper up the resistor ladder until the last tap point is reached at 19982 ? [r ab ?1 lsb + r w ]. figure 4 shows a simplified diagram of the equivalent rdac circuit where the last resistor string will not be accessed; therefore, there is 1 lsb less of the nominal resistance at full scale in addition to the wiper resis tance. the general equation determining the digitally programmed output resistance between w and b is: rd d rr wb ab w () =+ 256 (1) where: d is the decimal equivalent of the binary code loaded in the 8-bit rdac register. r ab is the nominal end-to-end resistance. r w is the wiper resistance contributed by the on resistance of the internal switch. again, if r ab = 20 k ? and the a terminal is open circuited, the following output resistance values, r wb , will be set for the fol- lowing rdac latch codes. table i. codes and corresponding resistances d (dec) r wb ( )o utput state 255 19982 full scale (r ab ?1 lsb + r w ) 128 10060 midscale 1 138 1 lsb 06 0 zero-scale (wiper contact resistance) note that in the zero-scale condition, a finite wiper resistance of 60 ? is present. care should be taken to limit the current flow between w and b in this state to a maximum pulse current of no more than 20 ma. otherwise, degrada- tion or possible destruction of the internal switch contact can occur. similar to the mechanical potentiometer, the resistance of the rdac between the wiper w and terminal a also produces a digitally controlled complementary resistance, r wa . when these terminals are used, the b terminal can be opened. setting the resistance value for r wa starts at a maximum value of resistance and decreases as the data loaded in the latch increases in value. the general equation for this operation is: rd d rr wa ab w () =+ 256 256 (2) for r ab = 20 k ? and b terminal open circuited, the following output resistance, r wa , will be set for the following rdac latch codes. table ii. codes and corresponding resistances d (dec) r wa ( )o utput state 255 138 full scale 128 10060 midscale 1 19982 1 lsb 0 20060 zero scale the typical distribution of the nominal resistance, r ab , from channel-to-channel matches within 1%. device-to-device matching is process lot dependent and is possible to have 30% variation. since the resistance element is processed in thin film technology, the change in r ab with temperature has a very low 30 ppm/ c temperature coefficient.
rev. 0 e12e ad5280/ad5282 programming the potentiometer divider voltage output operation the digital potentiometer easily generates a voltage divider at wiper-to-b and wiper-to-a to be proportional to the input voltage at a-to-b. unlike the polarity of v dd ev ss , which must be posi tive, voltage across aeb, wea, and web can be at either polarity provided that v ss is powered by a negative supply. if ignoring the effect of the wiper resistance for approximation, connecting a terminal to 5 v and b terminal to ground produces an output voltage at the wiper-to-b starting at 0 v up to 1 lsb less than 5 v. each lsb of voltage is equal to the voltage applied across aeb divided by the 256 positions of the potenti- ometer divider. since ad5280/ad5282 can be supplied by dual supplies, the general equation defining the output voltage at v w with respect to ground for any valid input voltage applied to terminals a and b is: for a more accurate calculation, which includes the effect of wiper resistance, v w can be found as: operation of the digital potentiometer in the divider mode results in a more accurate operation overtemperature. unlike the rheostat mode, the output voltage is dependent mainly on the ratio of the internal resistors r wa and r wb and not on the absolute values; therefore, the temperature drift reduces to 5 ppm/ c. digital interface 2-wire serial bus the ad5280/ad5282 are controlled via an i 2 c compatible serial bus. the rdacs are connected to this bus as slave devices. referring to figures 2 and 3, the first byte of ad5280/ad5282 is a slave address byte. it has a 7-bit slave address and an r/ w s adadad ad sa sdas sa w sda aa w w a sw sas a daa dada ads a ad ssa wa w da ssda a sd shdn shdn a shdn adsd w da d sd a wdd a sdas s d sad w as sda s s ws as sdas wsda s na sda sda s a da d dada da da wsa ds da vd d v d v wa b () =+ 256 256 256 e (3) vd rd r v rd r v w wb ab a wa ab b () = () + () (4)
rev. 0 ad5280/ad5282 e13e readback rdac value ad5280/ad5282 allows the user to read back the rdac values in the read mode. however, for the ad5282 dual-channel device, the channel of interest is the one that is previously selected in the write mode. in the case where users need to read the rdac values of both channels in ad5282, they can program the first s ubaddress in write mode and then change to read mode to read the first channel value. after that, they can change back to write mode with the second subaddress and finally read the second channel value in read mode again. note that it is not necessary for users to issue the frame 3 data byte in write mode for subsequent readback operation. users should refer to figures 2 and 3 for the programming format. additional programmable logic output ad5280/ad5282 features additional programmable logic outputs, o 1 and o 2 , which can be used to drive a digital load, analog switches, and logic gates. o 1 and o 2 default to logic 0. the logic states of o 1 and o 2 can be programmed in frame 2 under the write mode (see figure 2). these logic outputs have adequate current driving capability to sink/source milliamperes of load. users can also activate o 1 and o 2 in three different ways without affecting the wiper settings. they may do the following: 1. start, slave address byte, acknowledge, instruction byte with o 1 and o 2 specified, acknowledge, stop. 2. complete the write cycle with stop, then start, slave address byte, acknowledge, instruction byte with o 1 and o 2 speci fied, acknowledge, stop. 3. do not complete the write cycle by not issuing the stop, then start, slave address byte, acknowledge, instruction byte with o 1 and o 2 specified, acknowledge, stop. self-contained shutdown function shutdown can be activated by strobing the shdn sdw s z sda shdn s d s dsnns ad ad ad da sdas ad ad ad sda s sdas ad ad ad sdas ad ad ad sdas ad ad ad as add shdnana w zw a n dn dd sd sd ad s sda dd s sda dd sd shnaaan adad dd ss nd sda s shd shd n
rev. 0 ?4 ad5280/ad5282 however, the digital inputs must also be level shifted to allow proper operation since the ground is now referenced to the negative potential. as a result, figure 9 shows one implementation with a few transistors and a few resistors. when v in is below q3? threshold value, q3 is off, q1 is off, and q2 is on. in this state, v out approaches 0 v. when v in is above 2 v, q3 is on, q1 is on, and q2 is turned off. in this state, v out is pulled down to v ss . beware that proper time shifting is also needed for successful communication with the device. +5v 0 q3 v dd r2 10k r3 10k v ss = ?v v out ?v 0 q1 q2 v in 0 0 figure 9. level shift for bipolar potential operation esd protection all digital inputs are protected with a series input resistor and parallel zener esd structures shown in figure 10; applies to digital input pins, sda, scl, and shdn . logic v ss 340 figure 10a. esd protection of digital pins v ss a, b, w figure 10b. esd protection of resistor terminals terminal voltage operating range the ad5280/ad5282 positive v dd and negative v ss power supply defines the boundary conditions for proper 3-terminal digital potentiometer operation. supply signals present on ter- minals a, b, and w that exceed v dd or v ss will be clamped by the internal forward biased diodes (see figure 11). v dd a w b v ss figure 11. maximum terminal voltages set by v dd and v ss power-up sequence since there are esd protection diodes that limit the voltage compliance at terminals a, b, and w (see figure 11), it is im- portant to power v dd /v ss before applying any voltage to terminals a, b, and w. otherwise, the diode will be forward biased such that v dd /v ss will be powered unintentionally and may affect the rest of the user? circuit. the ideal power-up sequence is in the following order: gnd, v dd , v ss , digital inputs, and v a/b/w . the order of powering v a , v b , v w , and digital inputs is not important as long as they are powered after v dd /v ss . layout and power supply bypassing it is a good practice to employ compact, minimum lead length layout design. the leads to the input should be as direct as possible with a minimum conductor length. ground paths should have low resistance and low inductance. similarly, it is also a good practice to bypass the power supplies with quality capacitors for optimum stability. supply leads to the device should be bypassed with 0.01 f to 0.1 f disc or chip ceramics capacitors. low esr 1 f to 10 f tantalum or electrolytic capacitors should also be applied at the supplies to minimize any transient disturbance and filter low frequency ripple (see figure 12). notice the digital ground should also be joined remotely to the analog ground at one point to minimize the digital ground bounce. v dd v ss + c3 10 f c4 10 f + c1 0.1 f c2 0.1 f v dd v ss gnd ad5280/ad5282 figure 12. power supply bypassing applications bipolar dc or ac operation from dual supplies the ad5280/ad5282 can be operated from dual supplies enabling control of ground referenced ac signals or bipolar operation. the ac signal, as high as v dd /v ss , can be applied directly across terminals a? with the output taken from terminal w. see figure 13 for a typical circuit connection. v ss +5.0v scl gnd v dd sda gnd v dd ?.0v sclk mosi c 5v p-p 2.5v p-p d = 80 h a 1 w 1 b 1 a 2 w 2 b 2 ad5282 figure 13. bipolar operation from dual supplies
rev. 0 ad5280/ad5282 e15e gain control compensation the digital potentiometer is commonly used in gain control such as the noninverting gain amplifier shown in figure 14. u1 v i a b w 200k c2 4.7pf v o 25pf 47k c 1 r1 figure 14. typical noninverting gain amplifier notice the rdac b terminal parasitic capacitance is connected to the op amp noninverting node. it introduces a zero for the 1/ term with 20 db/dec, whereas a typical op amp gbp has e20 db/dec characteristics. a large r2 and finite c1 can cause this zero?s frequency to fall well below the crossover frequency. thus the rate of closure becomes 40 db/dec and the system has 0 phase margin at the crossover frequency. the output may ring or oscillate if the input is a rectangular pulse or step function. similarly, it is also likely to ring when switching between two gain values because this is equivalent to a step change at the input. depending on the op amp gbp, reducing the feedback resistor may extend the zero?s frequency far enough to overcome the problem. a better approach is to include a compensation capacitor c2 to cancel the effect caused by c1. optimum com- pensation occurs when r1 c1 = r2 c2. this is not an option because of the variation of r2. as a result, one may use the relationship above and scale c2 as if r2 is at its maximum value. doing so may overcompensate and compromise the per- formance slightly when r2 is set at low values. however, it will avoid the gain peaking, ringing, or oscillation at the worst case. for critical applications, c2 should be found empirically to suit the need. in general, c2 in the range of a few pf to no more than a few tenths of pf is usually adequate for the compensa- tion. similarly, there are w and a terminal capacitances connected to the output (not shown); fortunately their effect at this node is less significant and the compensation can be avoided in most cases. programmable voltage reference for voltage divider mode operation, figure 15, it is common to buffer the output of the digital potentiometer unless the load is much larger than r wb . not only does the buffer serve the purpose of impedance conversion, it also allows a heavier load to be driven. ad8601 v in v out gnd ad1582 1 2 3 a b w a 1 v+ ve 5v 5v v o ad5280 u 1 figure 15. programmable voltage reference 8-bit bipolar dac figure 16 shows a low cost, 8-bit, bipolar dac. it offers the same number of adjustable steps but not the precision as compared to the conventional dacs. the linearity and temperature coeffi- cients, especially at low value codes, are skewed by the effects of the digital potentiometer wiper resistance. the output of this circuit is: v d v o ref = 2 256 1 e (5) 5v ref op2177 a 2 e15v op2177 ba w a 1 v o +15v u 2 +5v ref v in gnd v out trim v i adr425 r r u 1 u 2 = ad5280 e15v +15v figure 16. 8-bit bipolar dac bipolar programmable gain amplifier for applications that require bipolar gain, figure 17 shows one implementation similar to the previous circuit. the digital po- tentiometer, u 1 , sets the adjustment range. the wiper voltage at w 2 can therefore be programmed between v i and ekv i at a given u 2 setting. configuring a 2 in the noninverting mode allows linear gain and attentuation. the transfer function is: v v r r d kk o i =+ + 1 2 1 2 256 1 ()e (6) where k is the ratio of r wb1 /r wa1 set by u 1 . v+ ve op2177 ad5282 v o v+ ve op2177 v i a 1 w 1 b 1 ekvi a2 b 2 w 2 v dd v ss r1 r2 v dd v ss a 1 a 2 c1 u 2 ad5282 u 1 figure 17. bipolar programmable gain amplifier similar to the previous example, in the simpler (and much more usual) case, where k = 1, a single digital potentiometer ad5280 is used and u 1 is replaced by a matched pair of resistors to apply v i and e v i at the ends of the digital potentiometer. the relationship becomes: v r r d v oi =+ 1 2 1 22 256 1 e (7) if r2 is large, a few pf compensation capacitor may be needed to avoid any gain peaking.
rev. 0 e16e ad5280/ad5282 table iii shows the result of adjusting d, with a2 configured as a unity gain, a gain of 2, and a gain of 10. the result is a bipolar amplifier with linearly programmable gain and 256-step resolution. table iii. result of bipolar gain amplifier dr1 = , r2 = 0 r1 = r2 r2 = 9r1 0e1 e 2 e10 64 e0.5 e1 e5 128 0 0 0 192 0.5 1 5 255 0.968 1.937 9.680 programmable voltage source with boosted output for applications that require high current adjustments such as a laser diode driver or tunable laser, a boosted voltage source can be considered (see figure 18). v+ ve w a 1 v o 5v a b v i n 1 r bias signal c c ld i l u 1 = ad5280 a 1 = ad8601, ad8605, ad8541 n 1 = fdv301n, 2n7002 u 1 figure 18. programmable booster voltage source in this circuit, the inverting input of the op amp forces the v bias to be equal to the wiper voltage set by the digital potentiometer. the load current is then delivered by the supply via the n-ch fet n1. n1?s power handling must be adequate to dissipate (v i ev o ) i l power. this circuit can source a maximum of 100 ma with a 5 v supply. a1 needs to be a rail-to-rail input type. fore precision applications, a voltage reference such as adr423, adr292, or ad1584 can be applied at the input of the digital potentiometer. programmable 4 to 20 ma current source a programmable 4 to 20 ma current source can be implemented with the circuit shown in figure 19. ref191 is a unique, low supply headroom and high current handling precision reference that can deliver 20 ma at 2.048 v. the load current is simply the voltage across terminals b to w of the digital potentiometer divided by r s : i vd r l ref s n = 2 (8) v+ ve op8510 u2 v in sleep ref191 gnd v out 3 2 4 6 u 1 c1 1 f ad5280 w a b r s 102 r l 100 v l i l +5v e2.048v to v l e5v 0 to (2.048 + v l ) +5v + e figure 19. programmable 4 to 20 ma current source the circuit is simple, but beware of two things. first, dual sup- ply op amps are ideal because the ground potential of ref191 can swing from e2.048 v at zero scale to v l at full scale of the potentiometer setting. although the circuit works under single supply, the programmable resolution of the system will be reduced. for applications that demand higher current capabilities, a few changes to the circuit in figure 19 will produce an adjustable current in the range of hundreds of ma. first, the voltage reference needs to be replaced with a high current, low dropout regulator, such as the adp3333, and the op amp needs to be swapped with a high current dual-supply model, such as the ad8532. depending on the desired range of current, an appropriate value for r s must be calculated. because of the high current flowing to the load, the user must pay attention to the load impedance so as not to drive the op amp beyond the positive rail. programmable bidirectional current source for applications that require bidirectional current control or higher voltage compliance, a howland current pump can be a solution (see figure 20). if the resistors are matched, the load current is: i rr r r v l ab b w = + () 22 1 2 (9) e15v op2177 v+ ve +15v + e c1 10pf r2 15k r1 150k r2 b 50 r l 500 v l r2 a 14.95k r1 150k i l op2177 v+ ve +15v + e e15v a 1 ad5280 a w +5v e5v a 2 figure 20. programmable bidirectional current source
rev. 0 ad5280/ad5282 e17e r2 b in theory can be made as small as needed to achieve the current needed within a 2 ?s output current driving capability. in this circuit, op2177 can deliver 5 ma in either direction, and the voltage compliance approaches 15 v. it can be shown that the output impedance is: z rrrr rr rr r o ba ab =
+
+ 1212 12 12 2 () e( ) (10) this output impedance can be infinite if resistors r1 ' and r2 ' match precisely with r1 and r2 a + r2 b , respectively. on the other hand, it can be negative if the resistors are not matched. as a result, c 1 in the range of 1 pf to 10 pf, is needed to pre- vent the oscillation. programmable low-pass filter in a/d conversion applications, it is common to include an antialiasing filter to band-limit the sampling signal. dual-chan- nel digital potentiometers can be used to construct a second order sallen key low-pass filter (see figure 21). the design equations are: v v s q s o i o o o = ++ 2 2 2 (11) o rrcc = 1 1212 (12) q rc r c =+ 1 11 1 22 (13) users can first select some convenient values for the capacitors. to achieve maximally flat bandwidth where q = 0.707, let c1 be twice the size of c2 and let r1 = r2 . as a result, the user can adjust r1 and r2 to the same settings to achieve the desirable bandwidth. a b v i ad8601 +2.5v v o adjusted to same setting e2.5v v+ ve w r r2 r1 a b w r c1 c2 c c u 1 figure 21. sallen key low-pass filter programmable oscillator in a classic wien-bridge oscillator (figure 22), the wien net- work (r, r', c, c') provides positive feedback, while r1 and r2 provide negative feedback. at the resonant frequency, fo , the overall phase shift is zero, and the positive feedback causes the circuit to oscillate. with r = r', c = c', and r2 = r2 a //(r2 b + r diode ), the oscillation frequency is: oo rc or f rc == 11 2 (14) where r is equal r wa such that: r d r ab = 256 256 e (15) at resonance, setting: r r 2 1 2 = (16) balances the bridge. in practice, r2 / r1 should be set slightly larger than 2 to ensure the oscillation can start. on the other hand, the alternate turn-on of the diodes d1 and d2 ensures that r2 / r1 are smaller than 2 momentarily, and therefore stabi- lizes the oscillation. once the frequency is set, the oscillation amplitude can be tuned by r 2 b since: 2 3 2 vir v odbd =+ (17) v 0 , i d , and v d are interdependent variables. with proper selection of r2 b , an equilibrium will be reached such that v o converges. r2 b can be in series with a discrete resistor to increase the amplitude, but the total resistance cannot be too large to prevent saturation of the output. +2.5v op1177 v+ ve v o e2.5v r2 a 2.1k d1 d2 r2 b 10k vn r1 1k a b w r1 = r1' = r2b = ad5282 d1 = d2 = 1n4148 c 2.2nf r 10k ab w vp c 2.2nf r 10k a b w u 1 frequency adjustment amplitude adjustment figure 22. programmable oscillator with amplitude control
rev. 0 e18e ad5280/ad5282 resistance scaling ad5280/ad5282 offers 20 k , 50 k , and 200 k nominal resistance. users who need a lower resistance and the same number of step adjustments can place multiple devices in paral- lel. for example, figure 23 shows a simple scheme of paralleling both channels of the ad5282. to adjust half of the resistance lin early per step, users need to program both channels to the same settings. a 1 b 1 w 1 w 2 a 2 b 2 ld v dd figure 23. reduce resistance by half with linear adjustment characteristics applicable only to the voltage divider mode, by paralleling a discrete resistor as shown in figure 24, a proportionately lower voltage appears at terminal a. this translates into a finer degree of precision because the step size at terminal w will be smaller. the voltage can be found as: v d r2 rr2 w d v rr dd ab ab () = + 256 3 // (//) (18) r2 r1 w vdd 0 r3 a b figure 24. lowering the nominal resistance figures 23 and 24 show that the digital potentiometers change steps linearly. on the other hand, log taper adjustment is usu- ally preferred in applications like volume control. figure 25 shows another way of resistance scaling. in this circuit, the smaller the r2 with respect to r ab , the more the pseudo log taper characteristic behaves. r1 r2 v o a b w v i figure 25. resistor scaling with log adjustment characteristics rdac circuit simulation model a b r dac 20k w c w 55pf c b 25pf c a 25pf figure 26. rdac circuit simulation model for rdac = 20 k the internal parasitic capacitances and the external capacitive loads dominate the ac characteristics of the rdacs. configured as a potentiometer divider, the e3 db bandwidth of the ad5280 (20 k resistor) measures 310 khz at half scale. tpc 19 pro- vides the large signal bode plot characteristics of the three available resistor versions?20 k , 50 k , and 200 k . a para- sitic simulation model is shown in figure 26. a macro model net list for the 20 k rdac is provided. macro model net list for rdac .param d=256, rdac=20e3 * .subckt dpot (a,w,b) * ca a 0 25e-12 rwa a w {(1-d/256) * rdac+60} cw w 0 55e-12 rwb w b {d/256 * rdac+60} cb b 0 25e-12 * .ends dpot
rev. 0 ad5280/ad5282 e19e resistance tolerance, drift, and temperature coefficient mismatch considerations in a rheostat mode operation such as gain control, figure 27, the tolerance mismatch between the digital potentiometer and the discrete resistor can cause repeatability issues among various systems. because of the inherent matching of the silicon pro- cess, it is practical to apply the dual-channel device in this type of application. as such, r1 should be replaced by one of the channels of the digital potentiometer. r1 should be programmed to a specific value while r2 can be used for the adjustable gain. although it adds cost, this approach minimizes the tolerance and temperature coefficient mismatch between r1 and r2. in addition, this approach also tracks the resistance drift over time. as a result, these nonideal parameters become less sensitive to the system variations. ad8601 v i r2 c1 v o r1 * * replaced with another channel of rdac u 1 a b w figure 27. linear gain control with tracking resistance tolerance and drift notice the circuit in figure 28 can also be used to track the tolerance, temperature coefficient, and drift in this particular application. however, the characteristics of the transfer function change from a linear to pseudo-logarithmic gain function. ad8601 v i r c1 v o u 1 b a w figure 28. nonlinear gain control with tracking resistance tolerance and drift
rev. 0 c02929e0e10/02(0) printed in u.s.a. e20e ad5280/ad5282 outline dimensions 14-lead thin shrink small outline package (tssop) (ru-14) dimensions shown in millimeters 4.50 4.40 4.30 14 8 7 1 6.40 bsc pin 1 5.10 5.00 4.90 0.65 bsc seating plane 0.15 0.05 0.30 0.19 1.20 max 1.05 1.00 0.80 0.20 0.09 8 0 0.75 0.60 0.45 compliant to jedec standards mo-153ab-1 coplanarity 0.10 16-lead thin shrink small outline package (tssop) (ru-16) dimensions shown in millimeters 16 9 8 1 pin 1 seating plane 8 0 4.50 4.40 4.30 6.40 bsc 5.10 5.00 4.90 0.65 bsc 0.15 0.05 1.20 max 0.20 0.09 0.75 0.60 0.45 0.30 0.19 coplanarity 0.10 compliant to jedec standards mo-153ab

▲Up To Search▲

Price & Availability of AD5282-EVAL

	To Download AD5282-EVAL Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .