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1/29 AN1451 application note february 2002 introduction the l6208 is a highly integrated, mixed-signal power ic that allows the user to easily design a complete motor control system for two-phase bipolar stepper motors. figure 1 shows the l6208 block diagram. the ic inte- grates eight power dmos, a centralized logic circuit which implements the phase generation and a constant t off pwm current control technique ( quasi-synchronous mode ) for each of the two phases of the motor plus other added features for safe operation and flexibility. figure 1. l6208 block diagram. gate logic stepping sequence generation over current detection over current detection gate logic v cp v boot en control cw/ccw gnd gnd gnd gnd vref a v boot 5v 10v v sa v sb out1 a out2 a out1 b out2 b sense a charge pump volta ge regulator one shot monostable masking time thermal protection v boot v boot ocd b ocd a 10v 10v bridge a sense comparator bridge b d01in1226 rc a + - sense b vref b rc b half/full clock reset l6208 pwm by domenico arrigo, vincenzo marano and thomas hopkins l6208 fully integrated two phase stepper motor driver modern motion control applications need more flexibility that can be addressed only with specialized ic products. the l6208 is a fully integrated stepper motor driver ic specifically developed to drive a wide range of two phase (bipolar) stepper motors. this ic is a one-chip cost effective solution that includes several unique circuit design features. these features, including a decoding logic that can generate three different stepping sequences, allow the device to be used in many applications including mi- crostepping. the principal aim of this development project was to produce an easy to use, fully protected power ic. in addition several key functions such as protection circuit and pwm current control drastically reduce external components count to meet requirements for many different applications.
AN1451 application note 2/29 designing an application with l6208 current ratings with mosfet (dmos) devices, unlike bipolar transistors, current under short circuit conditions is, at first ap- proximation, limited by the r ds(on) of the dmos themselves and could reach very high values. l6208 out pins and the two v sa and v sb pins are rated for a maximum of 2.8a r.m.s. and 5.6a peak, corresponding to a total (for the whole ic) 5.6a rms (11.2a peak). these values are meant to avoid damaging metal structures, including the metallization on the die and bond wires. in practical applications, though, maximum allowable current is less than these limits ( see power management section ). the device has a built-in over current detection (ocd) that provides protection against short circuits between the outputs and between an output and ground ( see over current protection section ). voltage ratings and operating range the l6208 requires a single supply voltage (v s ), for the motor supply. internal voltage regulators provide the 5v and 10v required for the internal circuitry. the operating range for v s is 8 to 52v. to prevent working into undesirable low voltage supply an under voltage lock out ( uvlo ) circuit shuts down the device when supply voltage falls below 6v; to resume normal operating conditions, v s must then exceed 7v. the hysteresis is pro- vided to avoid false intervention of the uvlo function during fast v s ringings. it should be noted, however, that dmos's r ds(on) is a function of the v s supply voltage. actually, when v s is less than 12v, r ds(on) is adversely affected, and this is particularly true for the high side dmos that are driven from v boot supply. this supply is obtained through a charge pump from the internal 10v supply, which will tend to reduce its output voltage below 10v when v s goes below 12v. figure 2 shows the normalized r ds(on) of the high side dmos versus the supply voltage of their gate drivers (v boot -v s ). figure 2. normalized high-side r ds(on) versus gate drivers supply voltage. note that v s must be connected to both v sa and v sb since the bootstrap voltage (at v boot pin) is the same for the two h-bridges. the integrated dmos have a rated drain-source breakdown voltage of 60v. however v s should be kept below 52v, since in normal working conditions the dmos see a v ds voltage that will exceed v s supply. in particular, when using the fast decay mode, at the beginning of the off-time (when all the dmos are off during dead-time) the sense pin sees a negative spike due to an inevitable parasitic inductance of the pcb path from the pin to gnd. this spike is followed by a stable negative voltage due to the drop on r sense .one of the two out pins of the bridge sees a similar behavior, but with a slightly larger voltage due to the forward recovery time of the integrated freewheeling diode and the forward voltage drop across it (see figure 3). typical duration of this spike is 30ns. at the same time, the other out pin of the same bridge sees a voltage above v s , due to the pcb inductance and voltage drop across the high-side (integrated) freewheeling diode, as the current 1 1.005 1.01 1.015 1.02 1.025 1.03 1.035 1.04 1.045 1.05 1.055 1.06 1.065 678910 v 10 @ ) ( ) ( on ds on ds r r v boot -v s [v]
3/29 AN1451 application note reverses direction and flows into the bulk capacitor. it turns out that, in fast decay, the highest differential voltage is observed between the two out pins of the same bridge, at the beginning of the off-time, and this must always be kept below 60v [3]. the same high voltage condition exists when a step is made and the direction of current flow reverses in the bridge. figure 3. currents and voltages during the dead time at the beginning of the off-time . figure 4 shows the voltage waveforms at the two out pins referring to a possible practical situation, with a peak output current of 2.8a, v s =52v,r sense = 0.33 w ,t j =25 c (approximately) and a good pcb layout. below ground spike amplitude is -2.65v for one output; the other out pin is at about 57v. in these conditions, total differential voltage reaches almost 60v, which is the absolute maximum rating for the dmos. keeping differen- tial voltage between two output pins belonging to the same full bridge within rated values is a must that can be accomplished with proper selection of bulk capacitor value and equivalent series resistance (esr), accord- ing to current peaks and chopping style and adopting good layout practices to minimize pcb parasitic induc- tances (see below) [3]. figure 4. voltage at the two outputs at the beginning of the off-time. v s sense out 1 out 2 r sens e *i r sens e *i+v f(diode) pcb parasitic inductance pcb parasitic inductance bulk capacitor equivalent circuit esr esl r s ense v s +v f(diode) dangerous high differential voltage out 2 out 1
AN1451 application note 4/29 choosing the bulk capacitor since the bulk capacitor, placed between v s and gnd pins, is charged and discharged during ic operation, its ac current capability must be greater than the r.m.s. value of the charge/discharge current. this current flows from the capacitor to the ic during the on-time (t on ) and from the ic (in fast decay; from the power supply in slow decay) to the capacitor during the off-time (t off ). the r.m.s. value of the current flowing into the bulk ca- pacitor depends on peak output current, output current ripple, switching frequency, duty-cycle and chopping style. it also depends on power supply characteristics. a power supply with poor high frequency performances (or long, inductive connections to the ic) will cause the bulk capacitor to be recharged slowly: the higher the current control switching frequency, the higher the current ripple in the capacitor; r.m.s. current in the capacitor, however, does not exceed the r.m.s. output current. bulk capacitor value ( c ) and the esr determine the amount of voltage ripple on the capacitor itself and on the ic. in slow decay, neglecting the dead-time and output current ripple, and assuming that during the on-time the capacitor is not recharged by the power supply, the voltage at the end of the on-time is: , so the supply voltage ripple is: , where i out is the output current. with fast decay, instead, recirculating current recharges the capacitor, causing the supply voltage to exceed the nominal voltage. this can be very dangerous if the nominal supply voltage is close to the maximum recommended supply voltage (52v). in fast decay the supply voltage ripple is about : , always assuming that the power supply does not recharge the capacitor, and neglecting the output current ripple and the dead-time. usually (if c > 100 m f) the capacitance role is much less than the esr, then supply voltage ripple can be estimated as: i out esr in slow decay 2i out esr in fast decay for example, if a maximum ripple of 500mv is allowed and i out = 2a, the capacitor esr should be lower than: in slow decay, and in fast decay. actually, current sunk by v sa and v sb pins of the device is subject to higher peaks due to reverse recovery charge of internal freewheeling diodes. duration of these peaks is, tough, very short, and can be filtered using a small value (100 200 nf), good quality ceramic capacitor, connected as close as possible to the v sa ,v sb and gnd pins of the ic. bulk capacitor will be chosen with maximum operating voltage 25% greater than the maximum supply voltage, considering also power supply tolerances. for example, with a 48v nominal power supply, with 5% tolerance, maximum voltage is 50.4v, then operating voltage for the capacitor should be at least 63v. v s i out esr t on c --------- + ?? ?? ? i out esr t on c --------- + ?? ?? ? i out 2esr ? t on t off + c ---------------------------- + ?? ?? ? esr 0.5v 2a ------------ < 250m w = esr 1 2 -- - 0.5v 2a ------------ ? < 125m w =
5/29 AN1451 application note layout considerations working with devices that combine high power switches and control logic in the same ic, careful attention has to be paid to the pcb layout. in extreme cases, power dmos commutation can induce noises that could cause improper operation in the logic section of the device. noise can be radiated by high dv/dt nodes or high di/dt paths, or conducted through gnd or supply connections. logic connections, especially high-impedance nodes (actually all logic input, see further), must be kept far from switching nodes and paths. with the l6208, in par- ticular, external components for the charge pump circuitry should be connected together through short paths, since these components are subject to voltage and current switching at relatively high frequency (750khz). pri- mary mean in minimizing conducted noise is working on a good gnd layout (see figure 5). figure 5. typical application and layout suggestions. high current gnd tracks (i.e. the tracks connected to the sensing resistors) must be connected directly to the negative terminal of the bulk capacitor. a good quality, high-frequency bypass capacitor is also required (typi- cally a 100nf 200nf ceramic would suffice), since electrolytic capacitors show a poor high frequency perfor- mance. both bulk electrolytic and high frequency bypass capacitors have to be connected with short tracks to v sa ,v sb and gnd. on the l6208 gnd pins are the logic gnd, since only the quiescent current flows through them. logic gnd and power gnd should be connected together in a single point , the bulk capacitor, to keep noise in the power gnd from affecting logic gnd. specific care should be paid layouting the path from the sense pins through the sensing resistors to the negative terminal of the bulk capacitor (power ground). these tracks must be as short as possible in order to minimize parasitic inductances that can cause dangerous voltage spikes on sense and out pins (see the voltage ratings and operating range section); for the same reason the capacitors on v sa ,v sb and gnd should be very close to the gnd and supply pins. refer to the sensing resistors section for information on selecting the sense resistors. traces that connect to v sa ,v sb , sense a , sense b , and the four out pins must be designed with adequate width, since high currents are flowing through these traces, and layer changes should be avoided. should a layer change prove necessary, multiple and large via holes have to be used. a wide gnd copper area can be used to improve power dissipation for the device. figure 6 shows two typical situations that must be avoided. an important consideration about the location of the bulk capacitors is the ability to absorb the inductive energy from the load, without allowing the supply voltage to exceed the maximum rating. the diode shown in figure 6 prevents the recirculation current from reaching the capacitors and will result in a high voltage on the ic pins that can destroy the device. having a switch or a power + - v s =8 52 v v ref =0 1v en clock half / full reset control cw / ccw v re fa v refb rc a rc b gnd gnd g nd gnd sense a sense b v sa v sb v boot cp out 1b out 2b out 1a out 2a d1 d2 r1 r2 r3 r4 r5 r6 c1 c2 c3 c4 c7 c8 c5 c6 l6208 m c or custom logic 2-phase stepper motor + - logic supply 3.3 5v
AN1451 application note 6/29 connection that can disconnect the capacitors from the ic, while there is still current in the motor, will also result in a high voltage transient since there is no capacitance to absorb the recirculation current. figure 6. two situations that must be avoided. sensing resistors each motor winding current is flowing through the corresponding sensing resistor, causing a voltage drop that is used, by the logic, to control the peak value of the load current. two issues must be taken into account when choosing the r sense value: the sensing resistor dissipates energy and provides dangerous negative voltages on the sense pin during the current recirculation. for this reason the resistance of this component should be kept low. the voltage drop across r sense is compared with the reference voltage (on v ref pin) by the internal comparator. the lower is the r sense value, the higher is the peak current error due to noise on vref pin and to the input offset of the current sense comparator: too small values of r sense must be avoided. a good compromise is calculating the sensing resistor value so that the voltage drop, corresponding to the peak current in the load (i peak ), is about 0.5 v: r sense = 0.5 v / i peak . it should be clear that sensing resistor must absolutely be non-inductive type in order to avoid dangerous neg- ative spikes on sense pins. wire-wounded resistors cannot be used here, while metallic film resistors are rec- ommended for their high peak current capability and low inductance. for the same reason the connections between the sense pins, c6, c7, v sa ,v sb and gnd pins (see figure 5) must be taken as short as possible (see also the layout considerations section). the power rating of the sensing resistors can be calculated as follows: fast decay recirculation: p r i rms 2 r sense slow decay recirculation: p r i rms 2 r sense d, since in this case the current does not flow through r sense during the current recirculation. d is the duty-cycle of the pwm current control, i rms is the r.m.s. value of the load current. using multiple resistors in parallel will help to obtain the required power rating with standard resistors, and re- gnd gnd gnd gnd sense a sense b v sa v sb r5 r6 c7 c8 c6 l6208 don't connect the logic gnd here voltage drop due to current in sense path can disturb logic gnd. don't put a diode here! recirculating current cannot flow into the bulk capacitor and causes a high voltage spike that can destroy the ic.
7/29 AN1451 application note duce the inductance. r sense tolerance reflects on the peak current error: 1% resistors should be preferred. the following table shows r sense recommended values and power ratings for typical r.m.s. and peak current values. charge pump external components an internal oscillator, with its output at cp pin, switches from gnd to 10v with a typical frequency of 750khz (see figure 7). figure 7. charge pump. when the oscillator output is at ground, c 5 is charged by v s through d 2 . when it rises to 10v, d 2 is reverse biased and the charge flows from c 5 to c 8 through d 1 , so the v boot pin, after a few cycles, reaches the max- imum voltage of v s +10v-v d1 -v d2 , which supplies the high-side gate drivers. with a differential voltage between v s and v boot of about 9v and both the bridges switching at 50khz, the typ- ical current drawn by the v boot pin is 1.85 ma. resistor r4 is added to reduce the maximum current in the external components and to reduce the slew rate of the rising and falling edges of the voltage at the cp pin, in order to minimize interferences with the rest of the circuit. for the same reason care must be taken in realizing the pcb layout of r4 , c5 , d1 , d2 connections (see also the layout considerations section). recommended values for the charge pump circuitry are: d1, d2 : 1n4148 r4 : 100 w c5 : 10nf 100v ceramic c8 : 220nf 100v ceramic i pk - i rms [a] r sense value [ w ] r sense power rating [w] (fast decay) alternatives 0.5 - 0.45 1 0.25 1 - 0.9 0.5 0.5 2 x 1 w , 0.25w paralleled 1.5 1.35 0.33 0.75 3 x 1 w , 0.25w paralleled 2 1.8 0.25 1 4 x 1 w , 0.25w paralleled l6208 v s +10v-v d1 v s -v d1 f = 750 khz v sa v sb v boot cp d1 d2 r4 c8 c5 r ds(on) =70 w 10 v 10 v 5v r ds(on) =70 w to high-side gate drivers 10 v f = 750 khz charge pump oscillator v s +10v-v d1 -v d2
AN1451 application note 8/29 due to the high charge pump frequency, fast diodes are required. using slow diodes (like 1n4001) will cause the ic quiescent current to increase up to 30ma or more (instead of 5.5ma), and the boot volt- age to be much lower. figure 8. current in the charge pump diodes. with r4 = 100 w , during operation at v s = 52v, the maximum current in the external diodes is limited to a typical value of 25ma (see figure 8), while at star- tup, when v s is provided to the ic, the current peak in the diodes and its duration depends on the value of the bulk capacitor and the power supply imped- ance (i.e. the slew rate of the supply voltage; figure 9 reports an example). 1n4148 diodes withstand more than 3a for 1 m s, and the maximum reverse volt- age is 75v, so they should fit for the majority of appli- cations. figure 9. example of the current peak in the charge pump diodes at startup. if high current peaks in the diodes are experienced at startup (when the supply voltage is applied), r4 can be reduced to 50 w and a second 50 w resistor (r14) can be introduced in series with d2, as in figure 10. figure 10. adding a second resistor allows re- ducing current peak in the diodes at startup. if more than one device is used in the application, it's possible to use the charge pump from one l6208 to supply the v boot pins of several ics. the unused cp pins on the slaved devices are left unconnected, as shown in figure 11. a 100nf capacitor (c8) should be connected to the v boot pin of each device. the higher the number of devices sharing the same charge pump, the lower will be the differential voltage available for gate drive (v boot -v s ), causing a high- er r ds(on) for the high side dmos, so higher dissi- pating power. in this case it's recommended to omit the resistor on the cp pin, obtaining a higher current capability of the charge pump circuitry. better performance can also be obtained using a 33nf capacitor for c5 and using schottky diodes (bat49 are recommended). figure 12 shows the high side r ds(on) (normalized at only one device) versus the number of devices sharing the same charge pump, considering each device working in normal drive (which is the worst case since both the two bridges are switching at the same time) at a switching frequency of 50khz. sharing the same charge pump circuitry for more than 3 4 devices is not recommended. v boot i diode i diode v boot l6208 v sa v sb v boot cp d1 d2 c8 c5 to high-side gate drivers r4=50 w r14=50 w
9/29 AN1451 application note figure 11. sharing the charge pump circuitry. figure 12. normalized high side r ds(on) versus number of ics using the same charge pump cir- cuitry. reference voltage the device has two analog inputs, v refa and v refb , connected to the internal sense comparators, to control the peak value of the motor current through the integrated pwm circuitry. in typical applications these pins are con- nected together, in order to obtain the same current in the two motor windings (one exception is the microstep- ping operation; see the related section). a fixed reference voltage can be easily obtained with a resistive divider from an available 5 v voltage rail (maybe the one supplying the m c or the rest of the application) and gnd. a very simple way to obtain a variable voltage without using a dac is to low-pass filter a pwm output of a m c (see figure 13). assuming that this output swings from 0 to 5v, the resulting voltage will be: l6208 v sa v sb v boot cp d1 d2 c8 = 100 nf c5 l6208 v sa v sb v boot c18 = 100nf to high-side gate drivers to other devices l6208 cp to high-side gate drivers r ds on () r ds on () @1device --------------------------------------------------- - 1 1.005 1.01 1.015 1.02 1.025 1.03 1.035 1.04 123 4 number of device s
AN1451 application note 10/29 where d m c is the duty-cycle of the pwm output of the m c. with r lp = 5.6k w ,r div = 1.5k w ,c lp = 100nf and a m c pwm frequency of 100khz, the remaining ripple on the v ref voltage will be about 20mv. using higher values for r lp ,r div and c lp will reduce the ripple, but the refer- ence voltage will take more time to vary after changing the duty-cycle of the m c pwm, and too high values of r lp will also increase the impedance of the v ref net at low frequencies, causing a poor noise immunity. as sensing resistor values are typically kept small, a small noise on v ref input pins might cause a considerable error in the output current. it's then recommended to decouple these pins with ceramic capacitors of some tens of nf, placed very close to v ref and gnd pins. note that v ref pins cannot be left unconnected, while, if connected to gnd, zero current is not guaranteed due to voltage offset in the sense comparator. the best way to cut down (ic) power consumption and clear the load current is pulling down the en pin. in slow decay, with very small reference voltage, pwm integrated circuitry can loose control of the current due to the minimum allowed dura- tion of t on (see the programmable off-time monostable section). figure 13. obtaining a variable voltage through a pwm output of a m c. input logic pins cw/ccw, control, reset, half/full, clock are cmos/ttl compatible logic input pins. the input compar- ator has been realized with hysteresis to ensure the required noise immunity. typical values for turn-on and turn-off thresholds are v th,on = 1.8v and v th,off = 1.3v. pins are esd protected (see figure 14), and can be directly con- nected to the logic outputs of a m c; a series resistor is generally not recommended, as it could help inducted noise to disturb the inputs. all logic pins enforce a specific behavior and cannot be left unconnected. figure 14. logic input pins. en pin the en pin is, actually , bi-directional: as an input, with a comparator similar to the other logic input pins (ttl/cmos with hysteresis), it controls the state of the powerdmos. when this pin is at a low logic level, all the powerdmos are turned off. the en pin is also connected to the open drain output of the protection circuit that will pull the pin to gnd if over current or over temperature conditions exist. for this reason, en pin must be driven through a series resistor v ref 5v d m c r div ?? r lp r div + ---------------------------------------- - = r lp c lp v ref gnd pwm output of a m c r div 5v control, half/full, clock, reset, cw/ccw esd protection
11/29 AN1451 application note of 500 w minimum (for 5v logic ), to allow the voltage at the pin to be pulled below the turn-off threshold. a capacitor (c1 in figure 5) connected between the en pin and gnd is also recommended, to reduce the r.m.s. value of the output current when overcurrent conditions persist (see over current protection section). en pin must not be left unconnected. figure 15. en input pin. programmable off-time monostable the ic incorporates a constant off-time pwm circuit to control load current, separately, in each motor winding. each channel has a sensing comparator that monitors the current in the motor phase by comparing the voltage drop across the external sense resistor to v ref , and a programmable off-time set by a one shot flip-flop trig- gered on positive edges of the sensing comparator output. schematic showing one pwm control circuit is found in figure 16. the off-time can be set by the value of the resistance and the capacitance connected to the rc a and rc b pins and is calculated using the equation: t off = 0.69rc + 1 m s. the additional 1 m s is due to the internal dead time circuit that prevents cross conduction. figure 17 shows typical values of the off-time versus resistive value, for a selected range of capacitor values. when the monostable times out, the capacitor connected at rc pin is recharged by a 5ma current source. typ- ical end-of-charge voltage is 4.5v. rc pin remains at this voltage until the monostable is again triggered by the sense comparator (see figure 18). for proper operation the external capacitor value has to be small enough to guarantee it will be completely re- charged before monostable is triggered again. if capacitor has not been fully charged, the off-time will be shorter than predicted using t off = 0.69rc + 1 m s. table below shows typical charge time for selected capacitive values, together with minimum and maximum achievable off-time (with resistors of 20k w and 100k w , respectively). rc pins must always be connected to an rc network with 20k w < r < 100k w , 0.1nf < c < 100nf. they cannot be driven by an external oscillator and they must not be left unconnected nor shorted to gnd. the minimum allowable on-time is about 2 m s, due to internal blanking time (see figure 16) and propagation delay. in some conditions (slow decay selected, short off-time, very low regulated current, high motor winding l / r) the system may need an on-time shorter than 2 m s. in these cases the pwm current controller can loose the regulation. c [nf] minimum off-time [ m s] maximum off-time [ m s] charge time [ m s] 0.1 2.38 7.9 0.04 1 14.8 70 0.4 10 139 691 4 100 1381 6901 40 5v en esd protection
AN1451 application note 12/29 figure 16. pwm current control circuitry. figure 19 shows the operation of the circuit in this condition. when the current first reaches the threshold, the bridge is turned off for a fixed time and the current decays. during the following on-time current increases above the threshold, but the bridge cannot be turned off until the minimum 2 m s on-time expires. since current increases more in each on-time than it decays during the off-time, it keeps growing during each cycle, with steady state asymptotic value set by duty-cycle and load dc resistance: the resulting peak current will be i pk =v s d/r load , where d = t on /(t on +t off ) is the duty-cycle and r load is the load dc resistance. figure 17. off-time selection. sense a (orb) sense comparator v ref a (or b) r sen se blanking time monostable 1 m s rc a (or b) q r s 2.5 v 5ma to gate logic rc a (or b) monostable comparator output blanker monostable set from the low-side gate drivers (0) (1) t off [ m s ] r[k w ] 3.3nf 20 30 40 50 60 70 80 90 100 1 10 100 2.2nf 1.5nf 1nf 680pf 470pf 330pf 220pf 150pf 100pf
13/29 AN1451 application note figure 18. monostable. figure 19. minimum on-time can cause the pwm controller to loose the regulation. over current protection to implement an over current (i.e. short circuit) protection, a dedicated over current detection (ocd) circuitry (see figure 20 for a simplified schematic) senses the current in each high side. power dmos are actually made up with thousands of individual identical cells, each carrying a fraction of the total current flowing. the current sensing element, connected in parallel to the power dmos, is made only with few such cells, having a 1:n ratio compared to the power dmos. the total drain current is split between the output and the sense element ac- cording to the cell ratio. sensed current is, then, a small fraction of the output current and will not contribute significantly to power dissipation. output current voltage at rc pin charge time on-time (t on ) 1 m s 2.5 v end of charge voltage off-time (t off ) v re f /r sen se needed t on is less than 2 m s minimum t on is about 2 m s v ref /r sense
AN1451 application note 14/29 figure 20. over current detection simplified circuitry. this sensed current is compared to an internally generated reference to detect an over current condition. figure 21 shows the device operating in overcurrent condition. when an over current is detected the internal open drain mosfet pulls the en pin to gnd switching off all 8 power dmos of the device and allowing the current to decay. under a persistent over current condition, like a short to ground or a short between two output pins, the external rc network on the en pin (see figure 20) reduces the r.m.s. value of the output current by imposing a fixed disable-time after each over current occurrence. the values of r en and c en are selected to insure proper op- eration of the device under a short circuit condition. when the current flowing through the high side dmos reaches the ocd threshold (5.6a typ.), the open drain starts discharging c en after an internal propagation delay of about 250ns. when the en pin voltage falls below the turn-off threshold (v th,off ) all the power dmos turn off after the internal propagation delay (en to turn-off). the current begins to decay as it circulates through the freewheeling diodes. since the dmos are off, there is no current flowing through them and no current to sense so the ocd circuit switches the internal open drain off, and r en can charge c en . the voltage at en pin (v en,low ) reached before the disable time depends on the value of c en . if this capacitor is small enough, the voltage can fall to gnd before the dmos switch off. for larger values of capacitance the voltage will decay to a value between gnd and the turn-off threshold (as in figure 21). the behavior is the same for the voltage at the end of the recharging time (v en,high ): small capacitor values will allow the voltage to reach 5v before the next overcurrent event and larger capacitors will limit the peak voltage between the turn-on threshold and 5v. since the thresholds are near 1.5v the behavior of the voltage is the same with 5v or 3.3v logic. + over temperature i ref (i 1a +i 2a )/n i 1a /n power sense 1 cell power sense 1 cell power dmos n cells power dmos n cells high side dmoss of the bridge a out 1a out 2a v sa i 1a i 2a i 2a /n from the bridge b ocd comparator ocd comparator to gate logic internal open-drain r ds(on) 60 w typ. c en . r en .en +5v m c or logic d01in1337
15/29 AN1451 application note figure 21. over current operation. the time the device remains disabled is given by: . since r en value is much greater than the r ds(on) of the pull down, the discharge time is approximately given by the equation: , where r ds(on)od is the on-resistance of the internal open drain mosfet (60 w typ.), v th,on = 1.8v typ., v th,off = 1.3v typ. if c en is small enough to be charged and discharged completely, so that the voltage at en pin swings from gnd to 5 v, the relations become: in the following table are shown typical t disch and t disable , for a selected range of c en ,r en . c en [nf] t disch [ns] t disable [ m s] r en = 2.2k w r en = 4.7k w r en = 10k w r en = 22k w 0.1 7.2 0.1 0.2 0.5 1 1 72 1 2 4.5 10 10 720 10 21 45 99 100 7200 99 212 450 990 t disable r en c en 5v v en low , 5v v th,on --------------------------------------- ?? ?? ?? ln ?? = t disch r ds on () od @ c en v en high , v th off , --------------------------- ?? ?? ?? ln ?? t disable 0.45 r en c en ?? @ t disch 1.2 r ds on () od ? @ c en ?
AN1451 application note 16/29 r en must be at least 500 w , in order to allow the en pin voltage to fall below the turn-off threshold when the open drain turns on. the recommended range is between 2.2k w and 22k w . the recommended t disable for safe ocd operation is at least 100 m s; in any case the r.m.s. value of the output current must not exceed 2.8a. the open drain can also be turned on if the device experiences an over temperature (ovt) condition. the ovt will cause the device to shut down when the die temperature exceeds the ovt threshold (t j >175 c typ.). since the ovt is also connected directly to the gate drive circuit, all the powerdmos will shut down, even if en pin voltage is still over v th,off . when the junction temperature falls below the ovt turn-off threshold (155 c typ.), the open drain turns off, c en is recharged up to v th,on and then the powerdmos are turned on back . power management even when operating at current levels well below the maximum ratings of the device, the operating junction tem- perature must be kept below 125 c. figures 22 to 25 are screenshots of a spreadsheet that helps calculating power dissipation in specified condi- tions (application and motor data), and estimates the resulting junction temperature for a given package and copper area available on the pcb [6]. the model considers power dissipation during the on-time and the off- time, taking into account the selected decay, rise and fall time (when a phase change occurs) considering the operating sequence, the switching losses and the quiescent current power dissipation. figure 22. definition of parameters for the three different sequences. the current in only one phase is shown. t r t f t lo ad d i i pk i t t i load normal t r t f t lo ad d i i pk i t t/2 i load wave t r t f t lo ad d i i pk i t t i load half step
17/29 AN1451 application note figure 23. input data. inputdata maximumdrain-source on resistance ron = 5.60e-01 [ohm] average value between high-side and low-side maximumdiodevoltage vd = 1.20e+00 [v] quiescent current iq = 5.50e-03 [ma] maximumbemf voltage vb = 1.50e+01 [v] motor inductance lm = 7.90e-03 [h] motor resistance rm = 6.60e+00 [ohm] supply voltage vs = 2.40e+01 [v] peak current ipk = 1.00e+00 [a] off-time toff = 1.50e-05 [s] step frequency fck = 1.00e+03 [hz] sensing resistance rs = 5.00e-01 [ohm] decay type - oslowo = synchronousslowdecay ofasto = quasi-synchronous fast decay st epping s equence - o normalo, ohalfo or owaveo slow wave device input values motor input values applicationinput values
AN1451 application note 18/29 figure 24. power dissipation formulas and results. result powerdmos commutation time tcom = 9.60e-08 [s] vs / (250v/ m s) rise time trise = 4.03e-04 [s] fall time tfall = 3.16e-04 [s] normal mode half or wave mode duty cycle d = 6.25e-01 - vb / vs (vs + vb) / 2vs sync. slow decay quasi-syncfast decay switching frequency fsw = 2.50e+04 [hz] (1-d) / toff current ripple d i = 2.85e-02 [a] (vs - vb)*d / (lm* fsw) period t = 2.00e-03 [s] 2 / fck 4 / fck 2 / fck normal mode half mode wave mode load time tload= 5.97e-04 [s] t-trise-tfall (3/4)t-rise (t/2)-trise normal mode half mode wave mode average cur- rent during load time i = 9.86e-01 [a] r.m.s. current during load time irms = 9.86e-01 [a] rise time dissipating energy erise = 1.50e-04 [j] fall time dissipating energy efall = 3.62e-04 [j] mormal mode half or wave mode load time diss. energy eload = 6.50e-05 [j] 2ron irms 2 tload 2ron irms 2 d tload + (ron irms 2 + vd i) (1 - d) tload sync. slow decay quasi-syncfast decay commutatiion time dissipatingpw ecom = 6.78e-05 [j] 2vs i tcom tload fsw quiescent dissipatingpw pq = 1.32e-01 [w] vs iq total dissi- pating power p = 1.36e+00 [w] (eri se + efall + eload + ecom) + pq ipk rm 2 2ipk ron ipk rs vs + ? ? ? ? () vs ------------------------------------------------------------------------------------------------------------------ - lm rm rs 2ron ++ --------------------------------------------- - ? ln vs ipk r 2 + ipk ron ipk rs vs + ? + ??? () ------------------------------------------------------------------------------------------------------- lm rm 2 ron rs + ? + () ------------------------------------------------------ - ? ln vs 2 vd ? () ipk rm ipk rs vs 2 vd ? + ? + ? () ------------------------------------------------------------------------------------------ - lm rm rs + () ---------------------------- ? ln ipk i d 2 ---- - ipk ipk i d () i 2 d 3 ------- + ? ron ipk 2 trise 3 -------------- - ?? 2ron ipk 2 tfall 3 ------------ - ?? 2vdtfall vs 2vd ? + () rm rs + () -------------------------------------- lm ipk rm ipk rs vs 2 vd ? + ? + ? () 1 t fall lm --------------- - rm rs + () ? exp rm rs + () 2 -------------------------------------------------------------------------------- - ?? + ? ? 2 t -- -
19/29 AN1451 application note figure 25. thermal data inputs and results. choosing the decay mode l6208 can operate in either fast or slow decay mode, each having a specific recirculation path for the current during off-time. in slow decay mode only the lower dmos is turned off and the current recirculates around the upper half of the bridge so that voltage across the coil is essentially 0. in fast decay mode both dmos are turned off and the current recirculates back to the power supply rail so that voltage across the coil is essentially power supply voltage itself. slow decay operation provides several advantages: for a given peak current and off-time, current ripple is min- imized, and the same is true for acoustic noise and losses in the motor iron (achieving the same current ripple with fast decay mode would require a shorter off-time resulting in a higher switching frequency and higher power dissipation in the ic). as current recirculates in the upper half of the bridge and both the high side dmos in the same bridge are on, synchronous rectification is realized, minimizing power dissipation in the power switches. also, as no output pin goes below gnd (see supply voltage ratings and operating range section), no power is dissipated on the sense resistor during the off-time (see sensing resistors section). on the other hand, slow decay can be undesirable in some situations, for example when current has to be reg- ulated at very low values or motor winding l / r ratio is high. in these cases a very short on-time may be re- quested to regulate the current, and the minimum t on (about 2 m s) can cause the pwm controller to loose the regulation (refer to the programmable off-time monostable section). another situation where fast decay is to be preferred to slow decay is with regulated current expected to vary over time with a given profile (enforced providing a variable voltage on the v ref pins, see also microstepping section). here fast decay helps following fast decreasing edges in the desired profile. input data package so20 copper area 4.0 1 10 sq. cm copper area is on same side of the device ground layer n/a ambient temperature 50 -25 100 c results thermal resistance junction to ambient 53.36 c/w thermal resistance junction to pins / slug 14.00 c/w estimated junction temperature 122.66 c estimated pins / slug temperature 103.60
AN1451 application note 20/29 choosing the stepping sequence the device can provide three different sequences to run a stepper motor: full step two phase on (normal drive), full step one phase on (wave drive) and half step. if half step driving is used, the motor advances by half a step after each clock pulse, obtaining a higher position resolution and avoiding instability due to low-torque regions in certain motors' speed-torque diagrams, when used in full step mode (see figure 26). figure 26. torque instability in full step mode. using this driving method the torque is affected by ripple, because in odd-numbered states, when both coils are driven, the total current in the motor windings is double than in even-numbered states. a way to avoid the high torque ripple in half step mode is to supply to the motor a higher current (by a factor of ) during the even numbered states, in which only one winding is energized, simply by applying a higher reference voltage at the v refa ,v refb pins during these states (see figure 27) [2]. figure 27. balanced half step for low torque ripple. torque speed 2 2 clock 8 23456 7 1 i a i b v refa =v refb v ref v ref * 2 1 2 345 6 7 8 balanced half step startup or reset
21/29 AN1451 application note a simple circuit to generate two different reference voltages is shown in figure 28. r 1 and r 2 should be chosen to have and r 3 should be a simi lar circuit can also be used to modify the reference voltage in other situations. for example it's possible, at con- stant rotation speed, to reduce the motor torque, and to increase it during accele ration and deceleration. adding a second transistor is possib le to implement 4 different reference voltages, selec table by two logic signals . figure 28. realizing half step current shaping. normal and wave drive are full step modes. in wave drive mode the two motor windings are alternately ener- gized, while in normal drive both the windings are energized in each state, increasing the torque by a factor of . in wave drive mode the torque ripple is higher than in normal drive mode. on the other hand the torque increases only by a factor of , versus a double total current in the motor: so even if the produced torque is higher in normal drive, wave drive mode is more efficient. figure 29 and figure 30 show the ic average power consumption and the ic and motor windings average power dissipation versus the needed motor torque, for the three different sequences plus for the balanced half step. wave mode is the most efficient driving sequence; normal mode is also good for the low power dissipation, but it's the worst sequence considering the power consumption, so the efficiency. figure 29. ic power consumption vs. motor torque. in half step mode average torque has been considered. v ref high , v ref 2 ? 5v r 2 r 1 r 2 + -------------------- ? == r 3 r 1 r 2 ? 21 () r 1 r 2 + () ? --------------------------------------------------- - = 5v during odd numbered states 0v during even numbered states gnd +5v r 1 r 2 r 3 4.7k w 15k w to v ref pin(s) 2 2 supply power torque normal wave half step balanced half step
AN1451 application note 22/29 figure 30. ic and motor windings power dissipation versus motor torque. in half step mode aver- age torque has been considered. microstepping microstepping operation gives several advantages, including the absence of instability phenomena due to low- torque regions in certain motors' speed-torque diagrams (see figure 26), reduction of mechanical noise and in- creased position resolution. the l6208 can be used as two-phase microstepping driver ic [5]. the controller circuitry allows for an easy and inexpensive design with such device. by controlling the v ref input it is possible to get in the two phases variable output currents with a sine-wave shape. a variable voltage proportional to the desired output current is applied to each reference pin. for the microstepping, the two inputs are rectified sine- wave voltages with a phase delay of 90 . the l6208 is operated in the normal drive mode and the frequency of the two sine-wave voltages must be 1/4 of the clock frequency. figure 31 shows a circuit to generate the two sine-wave signals using low-pass filters and two pwm outputs of a m c. figure 32 shows the v ref voltages, the clock signal and the output currents. figure 31. microstepping application. torque normal, wave half step balanced half step ic & motor windings power dissipation m c l6208 v refa v refb en control cw/ccw clock reset 5.6k w 5.6k w 100nf 2.2k w 100n f half/full pwm a pwm b out 1 out 2 out 3 out 4 out 5 100nf 1.5k w 1.5k w
23/29 AN1451 application note figure 32. microstepping reference voltages, output currents and clock signal. especially at high rotation speeds, slow decay mode can be inadequate since it does not allow the motor current to decay fast enough, following the decreasing slope of the desired sine wave. in this case it's possible to apply the fast decay mode just during the negative slope of the current (see figure 33). the disadvantage is an in- creased current ripple in the other winding (where the current is increasing and fast decay in not needed). figure 33. using fast decay during high negative current slope. . . . . . v refa v refb i outb i outa clock i max *r sense 0v i max *r sense 0v i max -i max i max -i max 5v 0v 90 slow decay selected fast decay selected 5v 0v control clock v refa v refb i outa i outb
AN1451 application note 24/29 application example application data motor data rotation speed: 300 rpm (f ck = 1khz) winding resistance: 6.6 w winding peak current: 1a winding inductance: 7.9mh maximum ripple: 50ma step angle: 1.8 /step supply voltage: 24v 5% maximum bemf at 300rpm: 15v sequence: wave mode decay mode, sensing resistors and reference voltage. the first step is choosing the decay type. let's suppose to implement slow decay, which allows lower power dissipation, lower ripple and avoids voltages below gnd at output pins during recirculation. referring to approx- imated formulas in figure 24, it's possible to calculate the duty-cycle (d), the switching frequency (f sw ), the current ripple ( d i). with a 15 m s off-time, we will have: d @ 63%, f sw @ 25khz, d i @ 29ma. the on-time is t on =d/f sw @ 25 m s, which is far from the minimum allowed (2 m s), so slow decay can be used. the bulk capacitor need to withstand at least 24v + 5% + 25% @ 32v. a 50v capacitor will be used. allowing a voltage ripple of 200mv, the capacitor esr should be lower than 200mv / 1a = 200m w ; the ac current capa- bility should be about 1a. providing a reference voltage of 0.5v, 0.5 w sensing resistor are needed. in slow decay mode the resistors pow- er rating is about p r @ i rms 2 r sense d @ 0.32w. two 1 w - 0.25w - 1 % resistors in parallel are used. the charge pump uses recommended components (1n4148 diodes, ceramic capacitors and a 100 w resistor to re- duce emi). r = 18k w , c = 1.2 nf are connected to the rc pins, obtaining t off @ 16 m s. on the en pin a 10nf has been placed, and the pin is driven by the m c through a 22k w resistor. with these values, in case of short circuit between two out pins or an out pin and gnd, the powerdmos turns off after about 1.2 m s, and t disable @ 100 m s. figure 34. application example. + - v s =24v v ref = 0.5v en control half / full reset clock cw / ccw v refa v refb rc a rc b gnd gnd gnd gnd sense a sense b v sa v sb v boot cp out 1b out 2b out 1a out 2a 1n4148 1n4148 22 k w 1.2 nf ceramic 18 k w 5% 100 w 0.25w 100 nf ceramic 47nf ceramic 18 k w 5% 1.2 nf ceramic 100nf 50v ceramic 220nf 63v ceramic 10nf 50v ceramic 100 m f 50v esr<200m w l6208 m c or custom logic 2-phase stepper motor + - 4x 1 w , 0.25w, 1% 2k w 0.25w 1% 18 k w 0.25 w 1% logic supply 5v
25/29 AN1451 application note with wave drive selected, referring to figure 23, 24, 25, the dissipating power is about 1.36 w. if the ambient temperature is lower than 50 c, with 4cm 2 of copper area on the pcb and a so24 package, the estimated junc- tion temperature is about 123 c. using more copper area or a powerdip package will reduce the junction tem- perature. evaluation board an evaluation board has been produced to help the evaluation of the device in powerdip package. it imple- ments a typical application with several added components. figure 35 shows the electrical schematic of the board; in the table below the part list is reported. cn1, cn2, cn3, cn4 2-poles connector r1 100 w resistor cn5 34-poles connector r2 820 w 0.6w resistor c1 220nf/100v ceramic or polyester capacitor r3, r4, r5, r6, r7, r8 10k w resistor c2 220nf/100v ceramic or polyester capacitor r9 4.7k w resistor c3 100 m f/63v capacitor r10, r21 20k w 1% resistor c4 10nf/100v ceramic capacitor r11, r12 100k w trimmer c5 10 m f/16v capacitor r13, r22 2.2k w resistor c6 100nf capacitor r14, r15, r16, r17, r18, r191 w 0.4w resistor c7, c8 68nf capacitor r20, r24 5k w trimmer c9, c10 820pf capacitor s1 quad switch d1, d2 1n4448 diode u1 l6208n d3 bzx79c5v1 5.1v zener diode jp1 3-pin jumper the evaluation board provides external connectors for the supply voltage, an external 5v reference for the logic inputs, four outputs for the motor and a 34-pin connector to control the main functions of the board through an external m c board. running the evaluation board in stand-alone mode, instead, four switches (s1) allow enabling the device, set- ting the direction of the rotation, the type of current decay, the stepping sequence. r20 and r24 set the refer- ence voltage separately for the two bridges, while r13, c7 and r22, c8 are low-pass filters to provide an external reference voltage by a pwm output of a m c (see also the microstepping section). using these inputs r10, r20, r21, r24 must be disconnected. r11, c9 and r12, c10 are used to set the off-time of the two chan- nels of the ic. the 5v voltage for logic inputs and for references (v refa and v refb ) is obtained from r2, d3. for supply voltages greater than 24v, r2 must be replaced with a 3.7k w , 0.6w resistor. the jumper jp1 allows choosing the 5v voltage from the internal zener diode network or pin 11 of cn5 (for example an external m c board can provide 5v to the evaluation board). also cn2 connector can be used to provide an external 5v voltage to the board (in that case r2, d3 must be disconnected). cn2, or pin 1 of cn5, can also be used to provide a 5v voltage to external circuits. in this case the current that can be drawn form the board depends on the supply voltage. con- sidering that the voltage across d3 is about 4.5v with only 1ma in it, and supposing that no current flows in r3, r4, r5, r6, r7, r8, and r10 and r21 need 0.5ma maximum to generate the reference voltage, with v s = 12v, 8ma can be drawn by an external circuit. figure 36, 37, 38 show the component placement and the two layers layout of the l6208n evaluation board. a large gnd area has been used, to guarantee minimal noise and good power dissipation for the device.
AN1451 application note 26/29 figure 35. l6208n evaluation board electrical schematic. +5v pullup pullup pullup pullup pullup pullup vccref pullup +5v int. ext. cw cw l6208 powerdip cw cw cn1 1 2 cn2 1 2 cn4 1 2 cn5 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 c5 r10 r3 r21 r13 r4 r8 r7 r5 c1 c4 r6 r22 s1 9 11 16 8 1 15 10 14 2 13 3 12 4 5 6 7 r9 c6 jp1 1 3 2 c7 r14 cn3 1 2 d1 d2 r17 r1 c2 r2 c3 r12 c10 r11 c9 r16 c8 u1 l6208powerdip sensea 3 rca 4 clock 1 rcb 9 control 13 vref a 24 cw/ccw 2 vrefb 11 senseb 10 en 14 reset 23 half/full 12 out1a 5 gnd 6 gnd 7 out1b 8 vboot 15 out2b 16 vsb 17 gnd 18 gnd 19 vsa 20 out2a 21 vcp 22 r19 d3 r15 r20 r24 r18 vrefa reset rca en half/ full cw/ccw vrefb vrefa control clock half/full en reset rca cw/ccw control clock diag diag clock vrefb
27/29 AN1451 application note figure 36. l6208 evaluation board component placement. figure 37. l6208 evaluation board top layer layout. power gnd signal gnd bulk capacitor
AN1451 application note 28/29 figure 38. l6208 evaluation board bottom layer layout. references 1] d. arrigo, a. genova, t. hopkins, v. marano, a. novelli, oa new fully integrated stepper motor driver ico, proceedings of pcim 2001, septermber 2001, intertech communication. 2] h. sax, ostepper motor drivingo (an235). 3] t. hopkins, ocontrolling voltage transients in full bridge driver applicationso (an280). 4] t. hopkins, ostepper motor drive considerations, common problems and solutionso (an460). 5] t. hopkins, k. kim, omicrostepping stepper motor drive using peak detecting current controlo (an1495). 6] p. casati and c. cognetti, oa new high power ic surface mount package familyo (an668). short sense path
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