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FUJITSU SEMICONDUCTOR DATA SHEET
DS07-16202-2E
32-bit Proprietary Microcontroller
CMOS
FR Family MB91191/192 Series
MB91191R/MB91192/MB91F191A/MB91F192
s DESCRIPTION
The MB91191/192 series is a single-chip microcontroller using a 32-bit RISC-CPU (FR series) as its core. It contains peripheral I/O resources suitable for software servo control in applications such as VTRs that require high-speed CPU processing.
s FEATURES
CPU * 32-bit RISC (FR series) , load/store architecture, 5-stage pipeline * General-purpose registers : 16 x 32-bit * 16-bit fixed-length instructions (basic instructions) , 1 instruction per cycle * Includes memory-to-memory transfer, bit manipulation, and barrel shift instructions : Optimized for embedded applications * Includes function entry/exit instructions and multiple-register load/store instructions : Instruction set supports high level languages * Register interlock function : For efficient assembly language coding * Branch instructions with delay slots : Reduced overhead for branch operations * Internal multiplier unit is supported at instruction level Signed 32-bit multiplication : 5 cycles Signed 16-bit multiplication : 3 cycles * Interrupts (PC and PS saving) : 6 cycles, 16 priority levels
(Continued)
s PACKAGE
Plastic, LQFP, 120-pin Plastic, FLGA, 144-pin
(FPT-120P-M05)
(LGA-144P-M02)
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MB91191/192 Series
Bus Interface * 16-bit address output, 8/16-bit data input and output * Basic bus cycle : 2 clock cycles * Supports interfaces for various types of memory * Multiplexed data/address input/output * Automatic wait cycles : Between 0 and 7 wait cycles can be specified independently for each memory area * Unused data/address pins can be configured as input/output ports * Supports little endian mode Bit Search Module * Searches, starting from the MSB, for the position of the first 1/0 bit transition in a word. The operation is performed in one cycle. Serial I/O * 3 channels with internal buffer RAM (automatic transfer of up to 128 bytes) * Independent send and receive buffer mode (automatic transfer of up to 64 bytes) A/D Converter (Successive Approximation Type) * 10-bit x 16 channels * Uses successive approximation conversion method (conversion time : 8.4 s @ 20 MHz) * Channel scan function * Hardware and software conversion start functions * Internal FIFO (Software conversion : 6 stages, Hardware conversion : 6 stages) Timers * 16-bit x 4 channels * 16-bit timer/counter x 1 channel (with square wave output) * 8/16-bit timer/counter x 1 channel (with square wave output) FG input unit * Incorporates capstan, drum, and reel input circuits Capture unit * Internal 24-bit free-run counter (Minimum resolution = 50 ns @ 20 MHz) * Internal FIFO (Data : 21-bit x 8, Detection : 8-bit x 8) Programmable pattern generator * Internal RAM buffer (PPG0 : 256 bytes, PPG1 : 64 bytes) * Output timing resolution : 800 ns @ 20 MHz * Includes an A/D converter hardware start function Realtime timing generator * RTG : 3 circuits * Output timing resolution : 400 ns or 800 ns selectable * Timing output ports : 5 ports PWM * 12-bit PWM x 6 channels (rate, multi-type) * Base frequency = 78.1 kHz or 39.0 kHz (@ 20 MHz) selectable
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MB91191/192 Series
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PWC * 8-bit PWC x 1 channel (with mask input) * Measurement resolution : 400 ns @ 20 MHz General-purpose prescaler * 10-bit prescaler x 1 channel (with square wave and pulse outputs) * Dedicated internal oscillator circuit * Includes load function driven by PPG output Interrupt control * External interrupts : 3 inputs * Key input interrupt : 8 inputs
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MB91191/192 Series
s PIN ASSIGNMENT
(TOP VIEW)
90
85
80
75
70
65
PA1/AN-9/KEY1 PA2/AN-A/KEY2 PA3/AN-B/KEY3 PA4/AN-C/KEY4 PA5/AN-D/KEY5 PA6/AN-E/KEY6 PA7/AN-F/KEY7 PD0/SI2 PD1/SO2 PD2/SCK2 PD3/SI1/INT2 PD4/SO1 PD5/SCK1 PD6/SCS0 PD7/SI0 PC0/SO0 PC1/SCK0 PC2/PWM5/SCS1 PC3/PWM4/SCS2 PC4/PWM3 PC5/PWM2 PC6/PWM1 PC7/PWM0 VSS OSCI/PCK OSCO VDD P90/P0 P91/PPG00 P92/PPG01
10
15
20
25
A00/D24 A01/D25 A02/D26 A03/D27 A04/D28 A08/D24 A09/D25 A10/D26 A11/D27 A12/D28
ALE P62 WR0 RD P20 P21 P22 P23 P24 P25 P26 P27
X0 X1 VSS MD2 MD1 MD0 RST P70/XOUT P67/T40 P66/T501 P65 P64 P63 P62 P61 P60 P20 P21 P22 P23 P24 P25 P26 P27 VDD P30 P31 P32 P33 P34 8-bit MPX mode ALE WR1 WR0 RD A00/D16 A01/D17 A02/D18 A03/D19 A04/D20 A05/D21 A06/D22 A07/D23 16-bit MPX mode
(FPT-120P-M05)
30
5
PA0/AN-8/KEY0 PB7/AN-7 PB6/AN-6 PB5/AN-5 PB4/AN-4 PB3/AN-3 PB2/AN-2 PB1/AN-1 PB0/AN-0 AVDD AVRH AVSS VSS P17/RTG4 P16/RTG3 P15/RTG2 P14/RTG1 P13/RTG0 P12/EC5/INT1 P11/EC4/INT0 P10/PMSK P07/EXI2/PMI P06/EXI1 P05/EXI0 P04/CFG P03/DFG P02/DPG P01/RFG0 P00/RFG1 VDD
60
95 55
100 50
105 45
110 40
115 35
120
P93/PPG02 P94/PPG03 P80/PPG04 P81/PPG05 P82/PPG06 P83/PPG07 P84/PPG08 P85/PPG09 P86/PPG10 P87/PPG11 P40/PPG12 P41/PPG13 P42/PPG14 P43/PPG15 P44/PPG16 P45/PPG17 P46/PPG18 P47 A15 P57 P57 A14 P56 P56 A13 P55 P55 A12 P54 P54 A11 P53 P53 A10 P52 P52 A09 P51 P51 A08 P50 P50 VSS D31/A07 D31/A15 P37 D30/A06 D30/A14 P36 D29/A05 D29/A13 P35
(Continued)
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MB91191/192 Series
(Continued)
59 56 53 50 47 44 41 38 35 32 P94 P82 P85 P40 P43 P46 P56 P53 P50 P36 58 55 52 49 46 45 42 39 36 33 P80 P83 P86 P41 P44 P45 P57 P54 P51 P37 62 P91 63 61 60 57 54 51 48 43 40 37 34 31 P90 P92 P93 P81 P84 P87 P42 P47 P55 P52 VSS P35 30 P34 27 P31 24 P27 21 P24 28 29 P32 P33 25 26 VDD P30 22 23 P25 P26 19 20 P22 P23 16 17 P60 P20 15 14 P61 P62 12 11 P64 P65
65 66 64 OSCO OSCI VDD 68 PC7 71 PC4 74 PC1 77 PD6 80 PD3 83 PD0 86 PA5 89 PA2 69 67 PC6 VSS 72 70 PC3 PC5 75 73 PC0 PC2 76 78 PD7 PD5 79 81 PD4 PD2 82 84 PD1 PA7 85 87 PA6 PA4 88 90 PA3 PA1 91 94 97 100 103 PA0 PB5 PB2 AVDD VSS
Top View
18 P21 13 P63 10 P66
7 9 8 RST P67 P70 4 6 5 MD2 MD0 MD1 108 111 114 117 120 1 P13 P10 P05 P02 VDD X0 3 2 VSS X1
93 96 99 102 105 106 109 112 115 118 PB6 PB3 PB0 AVSS P16 P15 P12 P07 P04 P01 92 95 98 101 104 107 110 113 116 119 PB7 PB4 PB1 AVRH P17 P14 P11 P06 P03 P00
(LGA-144P-M02)
Note : The FLGA-144 package is not supplied for the MB91191 series. It is supplied only for the MB91192 series.
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MB91191/192 Series
s PIN DESCRIPTIONS
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 X0 X1 VSS MD2 MD1 MD0 RST P70/XOUT P67/T40 P66/T501 P65 P64 P63/ALE/ALE P62/P62/WR1 P61/WR0/WR0 P60/RD/RD P20/P20/D16 : A00 P21/P21/D17 : A01 P22/P22/D18 : A02 P23/P23/D19 : A03 P24/P24/D20 : A04 P25/P25/D21 : A05 P26/P26/D22 : A06 P27/P27/D23 : A07 VDD P30/D24 : A00/D24 : A08 P31/D25 : A01/D25 : A09 P32/D26 : A02/D26 : A10 P33/D27 : A03/D27 : A11 P34/D28 : A04/D28 : A12 P35/D29 : A05/D29 : A13 P36/D30 : A06/D30 : A14 P37/D31 : A07/D31 : A15 VSS VSS pin C Shared external bus pins and high-current I/O ports. CMOS inputs. Power supply pin C General-purpose I/O ports. CMOS inputs. C B C Reset input pin. CMOS Schmitt input. Shared pin with clock output (X0/2, PCK/2) . CMOS input. Shared pin with timer 4 square wave output. CMOS input. Shared pin with timer 5 square wave output. CMOS input. General-purpose I/O port. CMOS input. General-purpose I/O port. CMOS input. Shared pin with address strobe output. CMOS input. Shared pin with write strobe output 1. CMOS input. Shared pin with write strobe output 0. CMOS input. Shared pin with read strobe output. CMOS input. B Operation mode setting pins CMOS Schmitt inputs Pin Name (I) (O) Circuit Type A Crystal oscillator pins VSS pin Function
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MB91191/192 Series
Pin No. 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67
Pin Name P50/A08/P50 P51/A09/P51 P52/A10/P52 P53/A11/P53 P54/A12/P54 P55/A13/P55 P56/A14/P56 P57/A15/P57 P47 P46/PPG18 P45/PPG17 P44/PPG16 P43/PPG15 P42/PPG14 P41/PPG13 P40/PPG12 P87/PPG11 P86/PPG10 P85/PPG09 P84/PPG08 P83/PPG07 P82/PPG06 P81/PPG05 P80/PPG04 P94/PPG03 P93/PPG02 P92/PPG01 P91/PPG00 P90/P0 VDD OSCO OSCI/PCK VSS (O) (I)
Circuit Type
Function
C
Shared external bus pins and high-current I/O ports. CMOS inputs.
General-purpose I/O port. CMOS input.
C
Shared pins with PPG outputs. CMOS inputs.
C
Shared pins with PPG outputs. CMOS inputs.
C
Shared pins with PPG outputs. CMOS inputs. Shared pins with PPG outputs. CMOS inputs. Shared pin with general-purpose prescaler output. CMOS input.
C A
Power supply pin Crystal oscillator pins for dedicated general-purpose prescaler oscillation. VSS pin
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MB91191/192 Series
Pin No. 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91
Pin Name PC7/PWM0 PC6/PWM1 PC5/PWM2 PC4/PWM3 PC3/PWM4/SCS2 PC2/PWM5/SCS1 PC1/SCK0 PC0/SO0 PD7/SI0 PD6/SCS0 PD5/SCK1 PD4/SO1 PD3/SI1/INT2
Circuit Type
Function
C
Shared pins with PWM outputs. CMOS inputs.
Shared pin with PWM output and serial 2 chip select. CMOS Schmitt input. F Shared pin with PWM output and serial 1 chip select. CMOS Schmitt input. Shared pin with serial 0 shift clock. CMOS Schmitt input. C Shared pin with serial 0 serial output. CMOS input. Shared pin with serial 0 serial input. CMOS Schmitt input. F Shared pin with serial 0 chip select input. CMOS Schmitt input. Shared pin with serial 1 shift clock. CMOS Schmitt input. C Shared pin with serial 1 serial output. CMOS input. Shared pin with serial 1 serial input and external interrupt 2. CMOS Schmitt input. Shared pin with serial 2 shift clock. CMOS Schmitt input. Shared pin with serial 2 serial output. CMOS input. Shared pin with serial 2 serial input. CMOS Schmitt input.
F PD2/SCK2 PD1/SO2 PD0/SI2 PA7/AN-F/KEY7 PA6/AN-E/KEY6 PA5/AN-D/KEY5 PA4/AN-C/KEY4 PA3/AN-B/KEY3 PA2/AN-A/KEY2 PA1/AN-9/KEY1 PA0/AN-8/KEY0 E C F
Shared pins with analog inputs and key inputs. CMOS Schmitt inputs
(Continued)
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MB91191/192 Series
(Continued)
Pin No. 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 Pin Name PB7/AN-7 PB6/AN-6 PB5/AN-5 PB4/AN-4 PB3/AN-3 PB2/AN-2 PB1/AN-1 PB0/AN-0 AVDD AVRH AVSS VSS P17/RTG4 P16/RTG3 P15/RTG2 P14/RTG1 P13/RTG0 P12/EC5/INT1 P11/EC4/INT0 P10/PMSK P07/EXI2/PMI P06/EXI1 P05/EXI0 P04/CFG P03/DFG P02/DPG P01/RFG0 P00/RFG1 VDD F F Shared pin with timer 5 clock input and external interrupt input. CMOS Schmitt input. Shared pin with timer 4 clock input and external interrupt input. CMOS Schmitt input. Shared pin with PWC mask input. CMOS Schmitt input. Shared pin with external capture input and PWC input. CMOS Schmitt input. Shared pin with external capture input. CMOS Schmitt input. Shared pin with capstan FG input. CMOS Schmitt input. Shared pin with drum FG input. CMOS Schmitt input. Shared pin with drum pulse input. CMOS Schmitt input. Shared pins with reel FG inputs. CMOS Schmitt inputs. Power supply pin C Shared pins with RTG outputs. CMOS inputs. A/D converter power supply pin A/D converter reference power supply pin A/D converter VSS pin VSS pin D Shared pins with analog inputs. CMOS Schmitt inputs. Circuit Type Function
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MB91191/192 Series
s I/O CIRCUITS
Type Circuit Remarks * Oscillation feedback resistor : 1 M approx.
X0,OSCI Clock input
A
Standby control signal X1,OSCO
* CMOS Schmitt input
B
Input
Output data DC test DC test
* CMOS level output * CMOS input No standby control
C
Input
Standby control signal = 1 (fixed)
Output data DC test DC test
* CMOS level output * CMOS input with input control * Analog input
D
Analog input CH selection Digital input Input control
(Continued)
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MB91191/192 Series
(Continued) Type
Circuit
Input data DC test DC test
Remarks * CMOS level output * CMOS Schmitt input with input control * Analog input
E
Analog input CH selection Digital input Input control
Output data DC test DC test
* CMOS level output * CMOS Schmitt input No standby control
F
Input Standby control signal = 1 (fixed)
Output data DC test DC test
* CMOS level output * CMOS Schmitt input No standby control
H
Input
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MB91191/192 Series
s BLOCK DIAGRAM
P47 P46/PPG18 P45/PPG17 P44/PPG16 P43/PPG15 P42/PPG14 P41/PPG13 P40/PPG12 P87/PPG11 P86/PPG10 P85/PPG09 P84/PPG08 P83/PPG07 P82/PPG06 P81/PPG05 P80/PPG04 P94/PPG03 P93/PPG02 P92/PPG01 P91/PPG00 P90/P0 PD0/SI2 PD1/SO2 PD2/SCK2 PD3/SI1/INT2 PD4/SO1 PD5/SCK1 PD6/SCS0 PD7/SI0 PC0/S00 PC1/SCK0 PC2/PWM5/SCS1 PC3/PWM4/SCS2 PC4/PWM3 PC5/PWM2 PC6/PWM1 PC7/PWM0
RAM 256 byte PPG0 P37/D31 to P30/D24 P27/D23 to P20/D16 P57/A15 to P50/A08 P60/RD P61/WR0 P62/WR1 P63/ALE P64 P65 P66/T501 P67/T40 Port 5 RAM 2 KB Port 2/3 I-bus D-bus FR20 CPU core RAM 64 byte PPG1
Bit search I-bus D-bus C-bus MB91191R :RAM 6 KB MB91192 :RAM 8 KB MB91F191A :RAM 6 KB MB91F192 :RAM 8 KB D-bus R-bus Port 8/9 Port C/D Port A/B
Port 6
MB91191R :ROM 254 KB MB91192 :ROM 384 KB MB91F191A :FLASH 254 KB MB91F192 :FLASH 384 KB
RAM 128 byte RAM 128 byte RAM 128 byte
Serial ch 0 Serial ch 1 Serial ch 2
External bus control P70/XOUT Port 7
12-bit PWM00-02 16-bit timers 0 to 3 12-bit PWM10-12
P17/RTG4 P16/RTG3 P15/RTG2 P14/RTG1 P13/RTG0 P12/EC5/INT1 P11/EC4/INT0 P10/PMSK P07/EXI2/PMI P06/EXI1 P05/EXI0 P04/CFG P03/DFG P02/DPG P01/RFG0 P00/RFG1 X0 X1 OSCI OSCO
Port 1
8/16-bit timer 16-bit timer 4 8-bit PWC
Interrupt controller
External interrupts
16-bit RTG0-2 PA7/AN-F/KEY7 PA6/AN-E/KEY6 PA5/AN-D/KEY5 PA4/AN-C/KEY4 PA3/AN-B/KEY3 PA2/AN-A/KEY2 PA1/AN-9/KEY1 PA0/AN-8/KEY0 PB7/AN-7 PB6/AN-6 PB5/AN-5 PB4/AN-4 PB3/AN-3 PB2/AN-2 PB1/AN-1 PB0/AN-0
Port 0
CFG DFG RFG0 RFG1 FIFO 29-bit x 8 24-bit FRC
External interrupts (key inputs)
10-bit A/DC FIFO FIFO (software) (hardware)
OSC
C-unit 10-bit programmable prescaler
OSC
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Port 4
MD0 MD1 MD2 RST
Mode control
INT2 to INT0 (from port 1, D)
RTG4 to RTG0 (to port 1)
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MB91191/192 Series
(Bus names) * I bus : 16-bit bus for internal instructions. As the FR family of CPUs use the Harvard architecture, instructions and data use separate buses. A bus converter is connected to the I bus. * D bus : Internal 32-bit data bus. The internal peripherals are connected to the D bus. * C bus : Internal multiplexed bus. Connected to the I and D buses via a switch. An external interface module is connected to the C bus. Data and instructions are multiplexed on the external data bus. * R bus : Internal 16-bit data bus. The R bus connects to the D bus via an adapter. The I/O, clock oscillator, and interrupt controller are connected to the R bus. As the R bus is only 16 bits wide, address and data are multiplexed on the bus and therefore multiple cycles are required when the CPU accesses these resources.
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MB91191/192 Series
s MEMORY MAP
00000000H
to
00000000H I/O area PPG0 Data RAM area 256 bytes SIO0 Data RAM area 128 bytes PPG1 Data RAM area 64 bytes I/O area I/O area Access inhibited SIO1 Data RAM area 128 bytes SIO2 Data RAM area 128 bytes Access inhibited Internal RAM area 6 Kbytes I/O area PPG0 Data RAM area 256 bytes SIO0 Data RAM area 128 bytes PPG1 Data RAM area 64 bytes I/O area I/O area Access inhibited SIO1 Data RAM area 128 bytes SIO2 Data RAM area 128 bytes Access inhibited Internal RAM area 8 Kbytes Access inhibited Internal RAM area 2 Kbytes Access inhibited
to
000001FFH 00000200H 000002FFH 00000300H
to to
000001FFH 00000200H
to
0000037FH 00000380H
to
Direct access area
000002FFH 00000300H
to
0000037FH 00000380H
to
000003BFH 000003C0H
to
000003BFH 000003C0H
to
000003FFH 00000400H
to
000003FFH 00000400H
to
000007FFH 00000800H
to
000007FFH 00000800H
to
00000FFFH 00001000H
to
00000FFFH 00001000H
to
0000107FH 00001080H
to
0000107FH 00001080H
to
000010FFH 00001100H
to
000010FFH 00001100H
to
0000E7FFH 0000E800H
to
0000DFFFH 0000E000H
to
0000FFFFH 00010000H
0000FFFFH 00010000H
to
0007FFFFH 00080000H
to
to
Access inhibited
000807FFH 00080800H
to
000BFFFFH 000C0000H
to to
0009FFFFH 000A0000H
to
000C07FFH 000C0800H 000FFFFBH 000FFFFCH 00100000H
to
Internal RAM area 2 Kbytes Internal ROM area 254 Kbytes Reset vector External extended area MB91191R
Internal ROM area 384 Kbytes
1 KB Initial vector area
Reset vector External extended area MB91192
000FFFFBH 000FFFFCH 00100000H
to
FFFFFFFFH
FFFFFFFFH
Note : The single chip mode does not allow access to the external extended area. For access to the external extended area, use the mode register to select the internal ROM external bus mode.
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MB91191/192 Series
s FLASH MEMORY MAP AND SECTOR CONFIGURATION
Flash memory is address-mapped differently between when accessed from the FR-CPU and when accessed from the ROM programmer.* Shown below is address mapping at access from the CPU. * : While the on-board flash memory uses the little endian format, the FR-CPU interface circuit converts data into big endian. As this conversion function does not work during access from the ROM programmer, address mapping is different from that in CPU mode. * MB91F191A
MSB side 16 bit LSB side 16 bit
31 16 15 0
00000000H 000007C0H
000C0800H
000C0801H 000C0802H
000C0803H
Status resistor
000C0000H Internal RAM area 000C0800H
SA0 (63 Kbyte)
SA5 (63 Kbyte)
Flash Memory area
000FFFFFH 000E0000H 000E0001H 000E0002H 000E0003H
SA1 (32 Kbyte)
SA6 (32 Kbyte)
000F0000H
000F4001H 000F4000H SA3 (8 Kbyte) 000F8000H 000F8001H
SA2 (8 Kbyte)
000F0001H
000F0002H 000F4002H 000F8002H
SA7 (8 Kbyte) SA8 (8 Kbyte) SA9 (16 Kbyte)
000F0003H 000F4003H 000F8003H
SA4 (16 Kbyte)
FFFFFFFFH 000FFFFCH 000FFFFDH 000FFFFEH
000FFFFFH
Memory Map * MB91F192
00000000H 000007C0H 000A0000H
31
Sector Configuration (SA = Sector address)
MSB side 16 bit
16
LSB side 16 bit
15 0
000A0001H
000A0002H
000A0003H
Status resistor SA0 (64 Kbyte) SA6 (64 Kbyte)
00080000H 00080800H 000A0000H
Internal RAM area
000C0000H 000C0001H 000C0002H 000C0003H
Flash Memory area
000FFFFFH
SA1 (64 Kbyte)
SA7 (64 Kbyte)
000E0000H
000E0001H
000E0002H
000E0003H
SA2 (32 Kbyte)
000F0000H 000F0001H SA3 (8 Kbyte) 000F4000H 000F4001H 000F8000H FFFFFFFFH 000FFFFCH 000F0002H 000F4002H 000F8002H
SA8 (32 Kbyte)
000F0003H 000F8003H 000FFFFFH
SA4 (8 Kbyte)
000F8001H
SA9 (8 Kbyte) 000F4003H SA10 (8 Kbyte) SA11 (16 Kbyte)
SA5 (16 Kbyte)
000FFFFDH 000FFFFEH
Memory Map
Sector Configuration (SA = Sector address)
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MB91191/192 Series
s ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
Parameter Power supply voltage Analog power supply voltage Analog reference voltage Input voltage Output voltage "L" level maximum output current "L" level average output current "L" level total maximum output current "L" level total average output current "H" level maximum output current "H" level average output current "H" level total maximum output current "H" level total average output current Power consumption Operating temperature Storage temperature Symbol VDD AVDD AVRH VI VO IOL IOLAV IOL IOLAV IOH IOHAV IOH IOHAV PD TA Tstg Rating Min VSS - 0.3 VSS - 0.3 VSS - 0.3 VSS - 0.3 VSS - 0.3 -20 -55 Max VSS + 3.5 VSS + 3.5 VSS + 3.5 VSS + 3.5 VSS + 3.5 10 8 100 50 -10 -4 -50 -20 500 +70 +150 Unit V V V V V mA mA mA mA mA mA mA mA mW C C *5 *5 *3 *4 *1 *1 *2 *2 *3 *4 (VSS = AVSS = 0 V) Remarks
*1 : Care must be taken that AVDD and AVRH do not exceed VDD + 0.3 V such as when turning on the device. Also care must be taken that AVRH does not exceed AVDD. *2 : VI and VO may not exceed VDD + 0.3 V. *3 : The maximum output current is the peak value for a single pin. *4 : The average output current is the average current for a single pin over a period of 100 ms. *5 : The total average output current is the average current for all pins over a period of 100 ms. WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
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MB91191/192 Series
2. Recommended Operating Conditions
Parameter Symbol Value Min 2.7 Power supply voltage Analog power supply voltage Analog reference voltage Operating temperature VDD AVDD AVRH TA 2.0 VSS - 0.3 AVSS -20 Max 3.3 3.3 VDD + 0.2 AVDD 70 V V V C Unit
(VSS = AVSS = 0 V) Remarks Normal operation Maintaining RAM state in stop mode
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand.
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MB91191/192 Series
3. DC Characteristics
Parameter
Symbol
Pin Name *3 *1 *2 MD2 to MD0 *3 *1 *2 MD2 to MD0 *4 *5, *6 *4 *5, *6 *4, *5, *6 *2 X0, OSCI
(VDD = 3.0 V 0.3 V, VSS = AVSS = 0 V, TA = -20 C to +70 C) Value Condition Unit Remarks Min Typ Max VDD = 3.0 V, IOH = -4.0 mA VDD = 3.0 V, IOH = -8.0 mA VDD = 3.0 V, IOL = 4.0 mA VDD = 3.0 V, IOL = 8.0 mA VDD = 3.0 V, IOL = 1.0 mA VDD = 3.0 V, VSS < VI < VDD VDD = 3.0 V, *7 0.7 VDD VDD - 0.4 0.8 VDD VDD VSS - 0.3 VSS - 0.3 VSS - 0.3 VSS - 0.3 2.4 2.4 2.4 2.4 1 8 50.1 16 24 13 1 10 VDD + 0.3 VDD + 0.3 VDD + 0.3 VDD + 0.3 0.2 VDD VSS + 0.4 0.2 VDD VSS 0.6 0.6 0.3 5 20 60 25 36 18 240 300 V V V V V V V V V V V V V V V A A mA MB91F191A mA MB91191R mA MB91F191A mA MB91191R A MB91F191A A MB91191R MB91191R MB91F191A MB91191R MB91F191A MB91191R
VIH "H" level input voltage VIHS VIHM VIL "L" level input voltage VILS VILM "H" level output voltage VOH1 VOH2 VOL1 "L" level output voltage VOL2 VOL3 Input leak current ILI1 ILIX IDD Power supply current IDDS IDDH
VDD
VDD = 3.0 V, *8 VDD = 3.0 V, TA = 25 C, *9
Other than VDD, VSS, Input 10 pF CIN AVDD, AVSS, and AVRH capacitance *1 : X0, X1, OSCI, OSCO *2 : RST, PC3 to PC1, PD6, PD5, PD3, PD2, PA7 to PA0, P12 to P10, P07 to P00, PD7, PD0 *3 : Inputs other than *1, *2, MD2 to MD0 *4 : P07 to P00, P17 to P10, P27 to P20, P47 to P40, P67 to P60, P70, P87 to P80, P94 to P90, PA7 to PA0, PB7 to PB0, PC7 to PC2, PD7, PD6, PD3, PD0 *5 : P37 to P30, P57 to P50 *6 : PD5, PD4, PD2, PD1, PC1, PC0 *7 : Operating current for X0 = 20 MHz, OSCI = VSS (fixed) , all port outputs = low, gear selection : CPU = 10 MHz, peripherals = 20 MHz *8 : Operating current in sleep mode for X0 = 20 MHz, OSCI = VSS (fixed), all port outputs = low, gear selection : CPU = 10 MHz, peripherals = 20 MHz *9 : Operating current in stop mode for X0 = 20 MHz, OSCI = VSS (fixed) , all port outputs = low, gear selection : CPU = 10 MHz, peripherals = 20 MHz 18
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4. AC Characteristics
(1) Clock Timings (VDD = 3.0 V 0.3 V, VSS = AVSS = 0 V, TA = -20 C to +70 C) Value Condition Unit Remarks Min Max 10 50 20 5 When wait controller set to 1 wait cycle 10 50 50 20 100 10 8 20 20 200 100 MHz ns % ns ns MHz MHz ns ns
Parameter Clock frequency Clock cycle time Frequency fluctuation* (PLL locked) Input clock pulse width Input clock rise/fall time Internal operating clock CPU frequency Peripherals Internal operating clock CPU cycle time Peripherals
Symbol fC tC r PWH PWL tCR tCF fCP fCPP tCP tCPP
* : The frequency fluctuation value is the maximum percentage deviation from the preset center frequency when using the multiplier (when PLL is locked) .
+ f = || f0 x 100 (%) Center frequency f0 - +
- tc
PWH tcf
PWL tcr
Power supply voltage (V)
3.3
Guaranteed operation range fcpp
2.7 fcp
10 M 20 M Frequency (Hz)
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The figure below shows the relationship between the X0 input and the internal clock based on the GCR (Gear Control Register) , CHC, CCK1, and CCK0 bit settings.
X0 input Source oscillation x 1 (CHC bit in GCR = 0) (a) gear x 1 CCK1/0:00 (b) gear x 1/2 CCK1/0:01 (c) gear x 1/4 CCK1/0:10 (d) gear x 1/8 CCK1/0:11 Source oscillation x 1/2 (CHC bit in GCR = 1) (a) gear x 1 CCK1/0:00 (b) gear x 1/2 CCK1/0:01 (c) gear x 1/4 CCK1/0:10 (d) gear x 1/8 CCK1/0:11 Internal clock tCYC Internal clock tCYC Internal clock tCYC Internal clock tCYC Internal clock tCYC Internal clock tCYC Internal clock tCYC Internal clock tCYC
Where tCYCH is the H level width of the internal clock and tCYCL is the L level width. For example, when set to source oscillation x 1/2, gear x 1/4 and X0 input frequency = 20 MHz : tCYC = 400 ns, tCYCH = 350 ns, tCYCL = 50 ns
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(2) Multiplex Bus Read/Write Operation
Parameter ALE pulse width Address delay time Address clear time Data delay time RD delay time RD pulse width WR0, WR1 delay time WR0, WR1 pulse width Data setup RD time RD Data hold time
Symbol tEHEL tEHAV tEHAX tELDV tELRL tRLRH tELWL tWLWH tDSRH tRHDX
(VDD = +3.0 V 0.3 V, VSS = AVSS = 0 V, TA = -20 C to +70 C) Value CondiRePin Name Unit tion marks Min Typ Max tCYC - 10 tCYCH - 15 tCYCL - 2 tCYC - 11 tCYC - 11 tCYC - 11 tCYC - 11 15 0 tCYCH tCYCL tCYC tCYC tCYC tCYC tCYCH + 15 tCYCL + 10 tCYCL + 26 tCYC + 11 tCYC + 11 tCYC + 11 tCYC + 11 ns ns ns ns ns ns ns ns ns ns *1 *1 *2 *2 *2
ALE A15 to A0, D31 to D16 D31 to D16 RD WR0, WR1 RD, D31 to D16
*1 : When the bus is delayed by automatic wait insertion, add (tCYC x number of wait cycles) to this value. *2 : This value is for gear setting = x1 For the value for gear settings 1/2, 1/4, and 1/8, substitute 1/2, 1/4, and 1/8 respectively for n in the formula below. Formula : tCYCH = (1 - n / 2) x tCYC tCYCL = (n / 2) x tCYC
Internal clock
tEHEL
ALE
tEHAV tELAX tDSRH tRHDX
Read time D31 to D16 MPX bus
RD
tELRL tRLRH
Write time D31 to D16 MPX bus
tELDV
tWHDX
WR0 , WR1
tELWL tWLWH
A15 to A08 When not multiplexed
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(3) Reset Input Ratings
Parameter Reset input time
Symbol tRSTL
Pin Name RST
(VDD = 3.0 V 0.3 V, VSS = AVSS = 0 V, TA = -20 C to +70 C) Value Unit Remarks Min Max 5 tCP ns
tRSTL RST 0.2 VDD
(4) Power-On Reset
Paramete Power supply rise time Power supply cutoff time
Symbol tR tOFF
(VDD = 3.0 V 0.3 V, VSS = AVSS = 0 V, TA = -20 C to +70 C) Value Pin Name Unit Remarks Min Max VDD 2 20 ms ms
tR 2.7 V
tOFF
VDD
0.2 V
Sudden changes in the power supply voltage may cause a power-on reset. The recommended practice if you wish to change the power supply voltage while the device is operating is to raise the voltage smoothly.
3.0 V
VDD
2.0 V Maintain RAM data
Recommended rate of voltage rise is 50 mV/ms or less.
VSS
VDD
RST
tRSTL
When turning on the power, start with the RST pin in the "L" level state and allow a time of tRSTL after reaching the VDD power supply level before changing the pin to the "H" level.
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(5) Serial I/O (CH0 to 2) Symbol tSCYC tSLOV tIVSH tSHIX tSHSL tSLSH tSLOV tIVSH tSHIX tBUSY tCLZO tCLSL tCHOZ External clock Internal clock
Parameter Serial clock cycle time SCK SO delay time Valid SI SCK SCK valid SI hold time Serial clock "H" pulse width Serial clock "L" pulse width SCK SO delay time Valid SI SCK SCK valid SI hold time Serial busy time SCS SCK, SO delay time SCS SCK input mask time SCS SCK, SO Hi-Z time
(VDD = +3.0 V 0.3 V, VSS = AVSS = 0 V, TA = -20 C to +70 C) Value Condition Unit Remarks Min Max 8 tCPP -10 50 50 4 tCPP - 10 4 tCPP - 10 0 50 50 50 50 50 6 tCPP 50 3 tCPP ns ns ns ns ns ns ns ns ns ns ns ns ns
* Internal shift clock mode
tSCYC
SCK
tSLOV
SO SI
tIVSH tSHIX
* External shift clock mode
tCLZO tSLSH tSHSL tBUSY tCHOZ
SCK
tSLOV
SO SI
tIVSH
SCS
tCLSL
tSHIX
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(6) FG Pulse Input
Parameter Servo input "H" pulse width Servo input "L" pulse width
Symbol tSPWH tSPWL
(VDD = 3.0 V 0.3 V, VSS = AVSS = 0 V, TA = -20 C to +70 C) Value Pin Name Unit Remarks Min Max CFG, DFG, DPG, RFG0, RFG1, EXI0 to EXI2 tC + 50 tC + 50 ns ns
Note : tC is the clock cycle time of the X0 and X1 pin oscillation.
CFG DFG, DPG RFG0, RFG1 EXI0 to EXI2
tSPWH tf tSPWL tr
(7) Timer External Clock Input
Parameter Timer 4 input "H" pulse width Timer 4 input "L" pulse width Timer 5 input "H" pulse width Timer 5 input "L" pulse width
Symbol tECWH tECWL tECWH tECWL EC4 EC5
(VDD = +3.0 V 0.3 V, VSS = AVSS = 0 V, TA = -20 C to +70 C) Value Pin Name Unit Remarks Min Max 4 tC + 50 4 tC + 50 4 tCPP 4 tCPP ns ns ns ns
EC4, EC5
tECWH tf
tECWL tr
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(8) General-Purpose Prescaler
Parameter PCK input clock frequency PCK input "H" pulse width PCK input "L" pulse width PCK input Fall time Rise time
Symbol fCP tSPWH tSPWL tf tr tPOPI PCK PO PCK
(VDD = 3.0 V 0.3 V, VSS = AVSS = 0 V, TA = -20 C to +70 C) Value Pin Name Unit Remarks Min Max 33 33 12 100 80 MHz ns ns ns ns
PO output delay time
tSPWH
tf
tSPWL
tr
PCK
tPOPI
PO
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5. Electrical Characteristics for the A/D Converter
Parameter Resolution Conversion time Total error Linearity error Differential linearity error Zero transition error Full-scale transition error Analog input current Analog input voltage Reference voltage Power supply current Reference voltage supply current During conversion Conversion halted During conversion Conversion halted Symbol VOT VFST IAIN VAIN AVRH IA AVDD IAH IR AVRH IRH AN-0 to AN-F VDD = AVDD = 3.0 V VDD = AVDD = 3.0 V, AVRH = 3.0 V 100 5.0 10 4 A A A LSB Pin Name
(VDD = 3.0 V + 0.3 V, VSS = AVSS = 0 V, TA = -20 C to +70 C) Value Condition Unit Remarks Min Typ Max 8.4 AVSS - 1.5 AVRH - 5.5 AVSS AVSS + 0.5 AVRH - 1.5 0.1 3.0 10 4.0 3.5 2.0 AVSS + 2.5 AVRH + 0.5 10 AVRH AVDD bit s LSB LSB LSB LSB LSB A V V mA
VDD = AVDD = 3.0 V, AVRH = 3.0 V
AN-0 to AN-F VDD = AVDD = 3.0 V, AN-0 to AVRH = 3.0 V AN-F AN-0 to AN-F AN-0 to AN-F AVRH
Variation between channels
Notes : * The relative error increases as |AVRH| becomes smaller. * Ensure that the output impedance of the external circuit connected to the analog input meets the following condition : Output impedance of external circuit < 7 k (approx.) If the output impedance of the external circuit is too high, the analog voltage sampling time may be too short. (Sampling time = 6.4 s for a 20 MHz machine clock)
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6. Flash Memory Erase and Programming performance
Parameter Sector erase time TA = +25 C, VCC = 3.0 V Condition Value Min 10,000 100,000 Typ 1 10 12 16 Max 15 3,600 s Unit s Remarks Excludes 00H programming prior erasure MB91F191A Excludes 00H programming prior MB91F192 erasure Excludes system-level overhead
Chip erase time Half word (16 bit width) programming time Erase/Program cycle Data holding time
s cycle h
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7. A/D Converter Glossary
* Resolution : The change in analog voltage that can be recognized by the A/D converter. * Linearity error The deviation between the actual conversion characteristics and the line linking the zero transition point ("00 0000 0000B" "00 0000 0001B") and the full scale transition point ("11 1111 1110B" "11 1111 1111B") . * Differential linearity error The variation from the ideal input voltage required to change the output code by 1 LSB. * Total error The total error is the difference between the actual value and the theoretical value. Includes the zero transition error, full-scale transition error and linearity error.
Total Error 3FF 3FE 3FD Actual conversion characteristic {1 LSB' x (N - 1) + 0.5 LSB'} 1.5 LSB'
Digital Output
004 003 002 001 0.5 LSB' AVSS AVRH VNT (Measured value) Actual conversion characteristic Theoretical characteristic
Analog Input
1 LSB' (Theoretical) =
AVRH - AVSS [V] 1024 Total error for digital output N = VNT - {1 LSB' x (N - 1) + 0.5 LSB'} 1 LSB' VOT' (Theoretical) = AVSS + 0.5 LSB' [V] VFST' (Theoretical) = AVRH - 1.5 LSB' [V] VNT : Voltage at which digital output changes from (N + 1) to N
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Linearity Error 3FF Actual conversion characteristic 3FE 3FD Digital Output {1 LSB x (N - 1) + VoT'} VFST (Measured value) Digital Output N N+1
Differential Linearity Error
Actual conversion characteristic
Theoretical characteristic
004 003 002 001 VOT (Measured value) Analog Input VNT (Measured value) Actual conversion characteristic Theoretical characteristic
N-1
VFST (Measured VNT value) (Measured value) Actual conversion characteristic
N-2
AVSS
AVRH
AVSS
Analog Input
AVRH
Linearity error for = digital output N
VNT - {1 LSB x (N - 1) + VOT} 1 LSB' - 1 LSB [LSB]
[LSB]
Differential linearity error V (N+1) T - VNT = for digital output N 1 LSB'
VOT' (Theoretical) = VFST - VOT [V] 1022 VOT : Voltage at which digital output changes from (000) H to (001) H. VFST : Voltage at which digital output changes from (3FE) H to (3FF) H.
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s ORDERING INFOMATION
Part No. MB91191RPFF MB91192PFF MB91F191APFF MB91F192PFF MB91192LGA MB91F192LGA Package Plastic LQFP, 120-pin (FPT-120P-M05) Plastic FLGA, 144-pin (LGA-144P-M02) Remarks
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s PACKAGE DIMENSION
Plastic LQFP, 120-pin (FPT-120P-M05)
16.000.20(.630.008)SQ
* 14.000.10(.551.004)SQ
90 61
Note 1) * : These dimensions do not include resin protrusion. Note 2) Pins width and pins thickness include plating thickness. Note 3) Pins width do not include tie bar cutting remainder.
91
60
0.08(.003)
Details of "A" part 1.50 -0.10
+0.20 +.008
(Mounting height)
INDEX
.059 -.004
120
31
"A"
0~8
LEAD No.
1
30
0.40(.016)
0.160.03 (.006.001)
0.07(.003)
M
0.1450.055 (.006.002)
0.500.20 (.020.008) 0.600.15 (.024.006)
0.100.10 (.004.004) (Stand off) 0.25(.010)
C
2003 FUJITSU LIMITED F120006S-c-4-5
Dimensions in mm (inches). (Continued)
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(Continued) Plastic FLGA, 144-pin (LGA-144P-M02)
11.000.10(.433.004)SQ 0.65(.026)TYP 5.175(.204)
11.000.10 (.433.004) INDEX AREA
9.100.10 (.358.004) REF
15 14 13 5.175 12 (.204) 11 10 9 8 7 6 5 4 3 0.45(.018) 2 1 RPNMLKJHGFEDCBA
1.40(.055) Max. 144-o0.35 (144-o.014) 0.08(.003) 3-o0.45 (3-o.018) 0.08(.003)
M
0.45(.018)
C
2001 FUJITSU LIMITED L144002S-c-1-1
Dimensions in mm (inches).
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FUJITSU LIMITED
All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose of reference to show examples of operations and uses of Fujitsu semiconductor device; Fujitsu does not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information. Fujitsu assumes no liability for any damages whatsoever arising out of the use of the information. Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use or exercise of any intellectual property right, such as patent right or copyright, or any other right of Fujitsu or any third party or does Fujitsu warrant non-infringement of any thirdpartyAfs intellectual property right or other right by using such information. Fujitsu assumes no liability for any infringement of the intellectual property rights or other rights of third parties which would result from the use of information contained herein. The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). Please note that Fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the prior authorization by Japanese government will be required for export of those products from Japan.
F0302 (c) FUJITSU LIMITED Printed in Japan
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