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| 8/12/2003 Errata: CS42406 Silicon Errata Rev CB Silicon * The left channel of the ADC is delayed by one ADC_LRCK cycle. This is true for all speed modes, in both Master and Slave. Therefore, the group delay for the left channel is increased by one ADC_LRCK cycle: Left Channel Group Delay 13/Fs 10/Fs 6/Fs Right Channel Group Delay 12/Fs 9/Fs 5/Fs Single-Speed Mode Double-Speed Mode Quad-Speed Mode * Analog performance of the ADC does not meet datasheet specifications. The affected specifications are listed below: Datasheet Specification -95 dB 102 dB 90 dB Current Silicon Performance -80 dB 98 dB 73 dB Parameter THD+N (-1dBFS Input) Dynamic Range (A-wgted) Interchannel Isolation Note: Performance shown is for Single-Speed Mode, Fs = 48 kHz, VA = 5.0 V. * A 10mA current source or sink on the MCLK, AINL, and AINR pins (pins 3, 24, and 26 respectively) may cause an internal latch-up condition. The device will recover if the current is then dropped below 10mA. Contacting Cirrus Logic Support For all product questions and inquiries contact a Cirrus Logic Sales Representative. To find one nearest you go to www.cirrus.com. Cirrus Logic www.cirrus.com Copyright (c) Cirrus Logic, Inc. 2003 (All Rights Reserved) ER614A1 JUL `03 1 |
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