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| 8BIT 30MSPS ADC GENERAL DESCRIPTION FEATURES BW1237X The BW1237X is a CMOS 8-bit A/D converter for video applications. It is a three-stage pipelined A/D converter which consists of sample-and-hold circuit, two multiplying DACs, and three flash ADCs. The maximum conversion rate of BW1237X is 30MSPS and supply voltage is 2.0V single. * * * * * * * * Process : CMOS Resolution : 8Bit Maximum Conversion Rate : 30MSPS Power Supply : 2.0V Single Power Consumption : 40mW Differential Linearity Error : 0.3 LSB (Typ) Integral Linearity Error : 0.5 LSB (Typ) Sample and Hold Function Implemented TYPICAL * * * * * * * APPLICATIONS Multi-media Applications Frame-grabber Scanner Camcorder Digital Video (TV/VCR) Broadcasting and Studio Equipments. Medical Electronics (ultra-sound and imaging) High Speed Instruments (digital scope, radar) FUNCTIONAL BLOCK DIAGRAM VSSA VBB VDDD VSSD VDDA AINT SAH AINC 3 BIT MDAC 3 BIT MDAC UDF DO[0] (LSB) DO[1] DO[2] 3 BIT MDAC 3 BITS CLK 3 BIT MDAC 3 BITS 3 BIT MDAC 4 BITS DO[3] DO[4] DO[5] DO[6] STBY DIGITAL CORECTION LOGIC DO[7] (MSB) OVF REFT REFB CML ITEST Ver 1.1 (Feb. 2000) No responsibility is assumed by SEC for its use nor for any infringements of patents or other rights of third parties that may result from its use. The content of this datasheet is subject to change without any notice. 8BIT 30MSPS ADC CORE PIN DESCRIPTION BW1237X NAME REFT REFB CML VDDA VBB VSSA AINT I/O TYPE AB AB AB AP AG AG AI I/O PAD poa_bb poa_bb poa_bb vdda vbba vssa piar10_bb PIN DESCRIPTION +1.1V Reference Top Bias. +0.5V Reference Bottom Bias. Internal Bias (Test Pin). +2.0V Analog Power. Sub Bias. Analog Ground. Analog Input. Input Span : 0.0V ~ 1.2V Analog Input. Input : Analog Ground Open (Use Internal Bias) High (Power Saving Standby Mode) Low (Normal Operation) Clock Input. Digital Output. UnderFlow Indication. OverFlow Indication. Digital Ground. +2.0V Digital Power. I/O TYPE ABBR. * * * * * * * * * * AI : Analog Input DI : Digital Input AO : Analog Output DO : Digital Output AB : Analog Bidirectional DB : Digital Bidirectional AP DP AG DG : : : : Analog Power Digital Power Analog Ground Digital Ground AINC ITEST STBY CLK DO[7:0] UDF OVF VSSD VDDD AI AB DI DI DO DO DO DG DP piar10_bb poa_bb picc_bb picc_bb pot2_bb pot2_bb pot2_bb vssd vddd CORE CONFIGURATION VDDA VSSA VBB VSSD VDDD DO[0] (LSB) DO[1] DO[2] DO[3] AINT AINC BW1237X REFT REFB STBY 2 / 10 DO[4] DO[5] DO[6] DO[7] (MSB) CLK UDF OVF CML ITEST SEC ASIC ANALOG 8BIT 30MSPS ADC ABSOLUTE M AXIM UM RATINGS BW1237X Characteristic Supply Voltage Analog Input Voltage Digital Input Voltage Digital Output Voltage Reference Voltage Storage Temperature Range Symbol VDD AINT CLK VOH, VOL REFT, REFB Tstg Value -0.3 to 4.5 -0.3 to VDD+0.3 -0.3 to VDD+0.3 -0.3 to VDD+0.3 -0.3 to VDD+0.3 -45 to 125 Unit V V V V V C NOTES 1. ABSOLUTE MAXIMUM RATING specifies the values beyond which the device may be damaged permanently. Exposure to ABSOLUTE MAXIMUM RATING conditions for extended periods may affect reliability. Each condition value is applied with the other values kept within the following operating conditions and function operation under any of these conditions is not implied. 2. All voltages are measured with respect to VSS unless otherwise specified. 3. 100pF capacitor is discharged through a 1.5k resistor (Human body model) RECOMM ENDED OPERATING CONDITIONS Characteristics Supply Voltage Supply Voltage Difference Reference Input Voltage Analog Input Voltage Positive Port Analog Input Voltage Negative Port Operating Temperature Symbol VDDA - VSSA VDDD - VSSD VDDA - VDDD REFT REFB AINT AINC Topr Min 1.95 -0.1 0.0 0 Typ 2.0 0.0 1.1 0.5 0.0 25 Max 2.4 0.1 1.2 70 Unit V V V V V C NOTES 1. It is strongly recommended that all the supply pins (VDDA, VDDD, VDDP) be powered from the same source to avoid power latch-up. SEC ASIC 3 / 10 ANALOG 8BIT 30MSPS ADC DC ELECTRICAL CHARACTERISTICS BW1237X Characteristics Resolution Reference Current Differential Linearity Error Symbol IREF DLE Min - Typ 8 1 Max - Unit Bits mA LSB - Conditions 0.3 0.5 2.5 1.5 0.4 0.7 4 2 AINT : 0.0V ~ 1.2V (Ramp Input) AINC : 0.0V (GND) Fs : 1MHz EOB = AIN(0,1) - REFB EOT = REFT - AIN(254,255) Integral Linearity Error Bottom Offset Voltage Error Top Offset Voltage Error ILE EOB EOT - LSB LSB LSB NOTES 1. Converter Specifications (unless otherwise specified) VDDA=2.0V VDDD=2.0V VSSA=GND VSSD=GND REFT=1.1V REFB=0.5V Ta=25C 2. TBD : To Be Determined AC ELECTRICAL CHARACTERISTICS Characteristics Conversion Rate Symbol Fs Min 30 Typ - Max 34 Unit MSPS Conditions AINT : 1MHz Sine Waveform (source resolution 10bit) Is = I(VDDA) + I(VDDD) + IREF Fs : 30MHz AIN : 1MHz (Sine Input) Fs : 30MHz AIN : 1MHz (Sine Input) Fs : 30MHz Dynamic Supply Current Is (IREF) - 20 (0.94) 20.5 mA Signal to Noise Distortion Ratio (SNDR) Total Harmonic Distortion (THD) SNDR 40 44 - dB THD 50 56 - dB SEC ASIC 4 / 10 ANALOG 8BIT 30MSPS ADC FUNCTIONAL DESCRIPTION BW1237X any other circuit. SAH amp is designed to have open-loop dc gain higher than 80dB and phase margin higher than 60 degree. Its input block is designed to be the rail-to-rail architecture using complementary differential pair. 2. FLASH The flash converter compares analog signal(SAH output) with reference voltage, and the result are transferred to MDAC and digital correction logic block. Its 8 comparators are fully differential. The comparators charge the reference voltage at the sampling capacitors (Q2) before comparing it with the SAH output (Q1). The output during Q1 is stored at the pre-latch block by Q1P clock signal. 3. MDAC MDAC is the most important block and it governs the overall performances of ADC. MDAC consists of amp, selection logic and capacitor array (c_array). c_array is made up of the sampling capacitors and switches. Selection logic controls the internal switches of c_array. If Q1 is high, selection's output is all low, the switches of tsw1 are off and the switches of tsw2 are all on. Therefore the capacitors of c_array charges analog input values held at SAH and it is reversed during Q2 high. 1. BW1237X is a three step A/D Converter comprising three flash ADC each of which yields 3, 3 and 4 bits and two multiplying DAC. The N-bit flash ADC is composed of 2n latching comparators, and multiplying DAC is composed of N+2 capacitors and a fully-differential amplifier. 2. BW1237X operates as follows. During the first "L" cycle of external clock the analog input data is tracked and sampled, and the input is held from the rising edge of the external clock, which is fed to the first 3-bit flash ADC, and the first multiplying DAC (MDAC). The first MDAC reconstructs a voltage corresponding to the first 3-bit flash ADC's output, and finally amplifies the residue voltage which is the voltage difference between the output of the first MDAC and the reconstructed voltage by the gain of 22. The second 3-bit flash ADC, and MDAC operate as the same manner and finally amplifies a residue voltage by 22. The third 4-bit flash ADC converts the output of the second MDAC and feed the result to the Digital Correction Logic (DCL). 3. BW1237X has the error correction scheme, which handles the offset error which stems from the mismatch between the first, second and third flash ADC's comparator. MAIN BLOCK DESCRIPTION 1. SAH SAH(sample and hold) is the circuit that samples the analog input signal and holds that value until next sample-time. It is required that the difference between the analog input signal and the output signal be as small as it can be. This SAH consists of fully differential op amp, switching transistors. and sampling capacitors. The sampling clocks are non-overlapping clocks(Q1, Q2) and sampling capacitor is 1.4pF. SAH uses its own bias to avoid interference of SEC ASIC 5 / 10 ANALOG 8BIT 30MSPS ADC TIM ING DIAGRAM BW1237X A4 AINT A5 A6 A7 A8 CLK SAH track hold track hold track hold track hold track FLASH1 REF sample Amplify Preset Latch Track Latch Encode MDAC1 AIN sample Residue amplify FLASH2 REF sample Amplify Preset Latch Track Latch Encode MDAC2 Residue sample Residue amplify FLASH3 REF sample Amplify Preset Latch Track Latch Encode Digital Correction Track Latch DO A1 A2 A3 A4 A5 A4 2.5 CLOCK PIPELINE DELEY SEC ASIC 6 / 10 ANALOG BW1237X 1. ADC function is evaluated by external check on the bidirectional pads connected to input nodes of HOST DSP back-end circuit. +2.0V Analog Power GND +2.0V Digital Power NOTES : 10uF ELECTROLYTIC CAPACITOR UNLESS OTHERWISE SPECIFIED : 0.1uF CERAMIC CAPACITOR UNLESS OTHERWISE SPECIFIED VDDA VSSA VBB VSSD VDDD DO[0] (LSB) DO[1] DO[2] DO[3] AINT AINC DO[6] DO[7] (MSB) HOST UDF OVF CLK REFT REFB STBY CML ITEST DSP GUIDE CORE EVALUATION BIDIRECTIONAL PAD 1.1V 0.5V GND GND 8BIT 30MSPS ADC ADC Function Measuring & Digital Input Forcing CORE SEC ASIC 7 / 10 BW1237X DO[4] DO[5] MUX ANALOG 8BIT 30MSPS ADC PACKAGE CONFIGURATION BW1237X +0.5V Reference Bottom +1.1V Reference Top +2.0V Digital Power GND 48 47 46 45 4 NC CML VDDA VDDA VBB VSSA VSSA AINT NC AINC NC NC ITEST STBY VDDP VSSP CLK NC 21 3 REFB 2 REFT 1 NC VDDD VDDD VSSD VSSD 5 +2.0V Analog Power 6 7 8 9 GND Analog Input (Input Span =0~+1.2V) 10 11 12 13 14 15 16 17 18 +2.0V PAD Power Clock Signal 19 20 NC NC NC OVF UDF NC NC 44 43 42 41 40 OverFlow UnderFlow 39 38 37 36 35 BW1237X NC DO[7] DO[6] DO[5] DO[4] DO[3] DO[2] DO[1] Digital Output Bits 34 33 32 31 30 29 NC 22 NC 23 NC 24 NC 25 NC 26 NC 27 NC 28 DO[0] NOTES : 10uF ELECTROLYTIC CAPACITOR UNLESS OTHERWISE SPECIFIED : 0.1uF CERAMIC CAPACITOR UNLESS OTHERWISE SPECIFIED NOTES 1. You can test ADC function by checking external bidirectional pad connected to internal signal path. 2. ESD (ElectroStatic Discharge) sensitive device. Although the digital control inputs are diode protected, permanent damage may occur on devices subjected to high electrostatic discharges. It is recommended that unused devices be stored in conductive foam or shunts to avoid performance degradation or loss of functionality. The protective foam should be discharged to the destination socket before devices are inserted. 3. NC denotes "No Connection". SEC ASIC 8 / 10 ANALOG 8BIT 30MSPS ADC PACKAGE PIN DESCRIPTION BW1237X NAME NC REFT REFB NC CML VDDA VBB VSSA AINT NC AINC NC ITEST STBY VDDP VSSP CLK NC DO[7:0] NC UDF OVF NC VSSD VDDD PIN NO. 1 2 3 4 5 6, 7 8 9, 10 11 12 13 14, 15 16 17 18 19 20 21~28 36~29 37~39 40 41 42~44 45, 46 47, 48 I/O TYPE AB AB AB AP AG AG AI AI AB DI DP DG DI DO DO DO DG DP PIN DESCRIPTION No Connection +1.1V Reference Top Bias. +0.5V Reference Bottom Bias. No Connection Internal Bias (Test Pin). +2.0V Analog Power. Sub Bias. Analog Ground. Positive Analog Input. Input Span = 0.0V ~ +1.2V. No Connection Negative Analog Input. Input = GND (Analog Ground). No Connection Open (Use Internal Bias) High (Power Saving Standby Mode) Low (Normal Operation) PAD Power PAD Ground Clock Input. No Connection Digital Output. No Connection UnderFlow Indication OverFlow Indication No Connection Digital Ground. Digital Power. I/O TYPE ABBR. * * * * * * * * * * AI : Analog Input DI : Digital Input AO : Analog Output DO : Digital Output AB : Analog Bidirectional DB : Digital Bidirectional AP DP AG DG : : : : Analog Power Digital Power Analog Ground Digital Ground SEC ASIC 9 / 10 ANALOG 8BIT 30MSPS ADC FEEDBACK REQUEST BW1237X It should be quite helpful to our ADC core development if you specify your system requirements on ADC in the following characteristic cheking table and fill out the additional questions. We appreciate your interest in our products. Thank you very much. Characteristic Analog Power Supply Voltage Digital Power Supply Voltage Bit Resolution Reference Input Voltage Analog Input Voltage Operating Temperature Integral Non-linearity Error Differential Non-linearity Error Bottom Offset Voltage Error Top Offset Voltage Error Maximum Conversion Rate Dynamic Supply Current Power Dissipation Signal-to-noise+distortion Ratio Pipeline Delay Min Typ Max Unit V V Bit V Vpp C LSB LSB LSB LSB MSPS mA mW dB CLK Remarks Digital Output Format (Provide detailed description & timing diagram) 1. Between single input-output and differential input-output configurations, which one is suitable for your system and why? 2. Please comment on the internal/external pin configurations you want our ADC to have, if you have any reason to prefer some type of configuration. 3. Freely list those functions you want to be implemented in our ADC, if you have any. SEC ASIC 10 / 10 ANALOG |
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