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TPS2100, TPS2101 VAUX POWER-DISTRIBUTION SWITCHES
SLVS197D - JUNE 1999 - REVISED JUNE 2000
features
typical applications
D D D D D D D D D D
Dual-Input, Single-Output MOSFET Switch With No Reverse Current Flow (No Parasitic Diodes) IN1 . . . 250-m, 500-mA N-Channel; 16-A Max Supply Current IN2 . . . 1.3-, 10-mA P-Channel; 1.5-A Max Supply Current (VAUX Mode) Advanced Switch Control Logic CMOS- and TTL-Compatible Enable Input Controlled Rise, Fall, and Transition Times 2.7-V to 4 V Operating Range SOT-23-5 and SOIC-8 Package - 40C to 70C Ambient Temperature Range 2-kV Human-Body-Model, 750-V CDM, 200-V Machine-Model ElectrostaticDischarge Protection
D D
Notebook and Desktop PCs Palmtops and PDAs
TPS2100 3.3 V VCC 3.3 V VAUX D3 or PME Status Control Signal IN1 3.3 V IN2 EN Controller (CardBus, 1394, PCI, et al.)
Hold-Up Capacitor
Figure 1. Typical Dual-Input Single-Output Application
description
The TPS2100 and TPS2101 are dual-input, single-output power switches designed to provide uninterrupted output voltage when transitioning between two independent power supplies. Both devices combine one n-channel (250 m) and one p-channel (1.3 ) MOSFET with a single output. The p-channel MOSFET (IN2) is used with auxiliary power supplies that deliver lower current for standby modes. The n-channel MOSFET (IN1) is used with a main power supply that delivers higher current required for normal operation. Low on-resistance makes the n-channel the ideal path for higher main supply current when power-supply regulation and system voltage drops are critical. When using the p-channel MOSFET, quiescent current is reduced to 0.75 A to decrease the demand on the standby power supply. The MOSFETs in the TPS2100 and TPS2101 do not have the parasitic diodes, found in discrete MOSFETs, which allow the devices to prevent back-flow current when the switch is off.
TPS2100 DBV PACKAGE (TOP VIEW) PCI Bus VAUX 3.3 V D PACKAGE (TOP VIEW)
EN GND IN2
1 2 3
5 4
IN1 OUT
VGA VCC
TPS210x D3-STAT DBV PACKAGE (TOP VIEW)
IN2 GND EN NC
TPS2101
1 2 3 4
8 7 6 5
OUT OUT NC IN1
PCI12xx / PCI14xx CardBus Controller
D PACKAGE (TOP VIEW)
Figure 2. VAUX CardBus Implementation
EN GND IN2
1 2 3
5 4
IN1 OUT
IN2 GND EN NC
1 2 3 4
8 7 6 5
OUT OUT NC IN1
NC - No internal connection Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright (c) 2000, Texas Instruments Incorporated
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TPS2100, TPS2101 VAUX POWER-DISTRIBUTION SWITCHES
SLVS197D - JUNE 1999 - REVISED JUNE 2000
AVAILABLE OPTIONS PACKAGED DEVICES TJ DEVICE TPS2100 TPS2101 ENABLE EN EN SOT-23-5 (DBV) TSP2100DBV TPS2101DBV SOIC-8 (D) TPS2100D TPS2101D
- 40C to 85C
Both packages are available left-end taped and reeled. Add an R suffix to the D device type (e.g., TPS2101DR). Add T (e.g., TPS2100DBVT) to indicate tape and reel at order quantity of 250 parts. Add R (e.g., TPS2100DBVR) to indicate tape and reel at order quantity of 3000 parts.
TPS2100 functional block diagram
SW1 250 m IN1 OUT
Pullup Circuit EN VCC Select
Charge Pump
Discharge Circuit
Driver
IN2
SW2 1.3 GND Driver
TPS2101 functional block diagram
SW1 250 m IN1 OUT
Charge Pump VCC Select Discharge Circuit
EN
Driver
IN2 Pulldown Circuit
SW2 1.3 GND Driver
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TPS2100, TPS2101 VAUX POWER-DISTRIBUTION SWITCHES
SLVS197D - JUNE 1999 - REVISED JUNE 2000
Function Tables
TPS2100 VIN1 0V 0V 3.3 V 3.3 V 0V 3.3 V 3.3 V VIN2 0V 3.3 V 3.3 V 0V 3.3 V 0V 3.3 V EN XX L L L H H H OUT GND GND VIN1 VIN1 VIN2 VIN2 VIN2 VIN1 0V 0V 3.3 V 3.3 V 0V 3.3 V 3.3 V TPS2101 VIN2 0V 3.3 V 3.3 V 0V 3.3 V 0V 3.3 V EN XX H H H L L L OUT GND GND VIN1 VIN1 VIN2 VIN2 VIN2
XX = don't care
Terminal Functions
TERMINAL NO. NAME EN EN GND IN1 IN2 OUT NC 1 2 5 3 4 3 2 5 1 7, 8 4, 6 2 5 3 4 2 5 1 7, 8 4, 6 TPS2100 DBV D TPS2101 DBV 1 D 3 I I I I O Active-high enable for IN1-OUT switch Active-low enable for IN1-OUT switch Ground Main Input voltage, NMOS drain (250 m) Auxilliary input voltage, PMOS drain (1.3 ) Power switch output No connection I/O DESCRIPTION
detailed description
power switches n-channel MOSFET The IN1-OUT n-channel MOSFET power switch has a typical on-resistance of 250 m at 3.3-V input voltage, and is configured as a high-side switch.
p-channel MOSFET
The IN2-OUT p-channel MOSFET power switch with typical on-resistance of 1.3 at 3.3-V input voltage and is configured as a high-side switch. When operating, the p-channel MOSFET quiescent current is reduced to less than 1.5 A. charge pump An internal charge pump supplies power to the driver circuit and provides the necessary voltage to pull the gate of the MOSFET above the source. The charge pump operates from input voltages as low as 2.7 V and requires very little supply current. driver The driver controls the gate voltage of the IN1-OUT and IN2-OUT power switches. To limit large current surges and reduce the associated electromagnetic interference (EMI) produced, the drivers incorporate circuitry that controls the rise times and fall times of the output voltage.
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TPS2100, TPS2101 VAUX POWER-DISTRIBUTION SWITCHES
SLVS197D - JUNE 1999 - REVISED JUNE 2000
detailed description (continued)
enable The logic enable will turn on the IN2-OUT power switch when a logic high is present on EN (TPS2100) or logic low is present on EN (TPS2101). A logic low input on EN (TPS2100) or logic high on EN (TPS2101) restores bias to the drive and control circuits and turns on the IN1-OUT power switch. The enable input is compatible with both TTL and CMOS logic levels. the VAUX application for CardBus controllers The PC Card specification requires the support of VAUX to the CardBus controller as well as to the PC Card sockets. Both are 3.3-V requirements; however the CardBus controller's current demand from the VAUX supply is limited to 10 A, whereas the PC Card may consume as much as 200 mA. In either implementation, if support of a wake-up event is required, the controller and the socket will transition from the 3.3-V VCC rail to the 3.3-V VAUX rail when the equipment moves into a low power mode such as D3. The transition from VCC to VAUX needs to be seamless in order to maintain all memory and register information in the system. If VAUX is not supported, the system will lose all register information when it transitions to the D3 state.
absolute maximum ratings over operating free-air temperature (unless otherwise noted)
Input voltage range, VI(IN1) (see Note1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.3 V to 5 V Input voltage range, VI(IN2) (see Note1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.3 V to 5 V Input voltage range, VI at EN or EN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.3 V to 5 V Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.3 V to 5 V Continuous output current, IO(IN1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 700 mA Continuous output current, IO(IN2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 mA Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See dissipation rating table Operating virtual junction temperature range, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 40C to 85C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 65C to 150C Lead temperature soldering 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . 260C Electrostatic discharge (ESD) protection: Human body model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 kV Machine model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 V Charged device model (CDM) . . . . . . . . . . . . . . . . . . . . . . . . . 750 V
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: All voltages are with respect to GND. DISSIPATION RATING TABLE PACKAGE DBV D TA < 25C POWER RATING 309 mW 568 mW DERATING FACTOR ABOVE TA = 25C 3.1 mW/C 5.7 mW/C TA = 70C POWER RATING 170 mW 313 mW TA = 85C POWER RATING 123 mW 227 mW
recommended operating conditions
MIN Input voltage, VI(INx) Input voltage, VI at EN and EN Continuous output current, IO(IN1) Continuous output current, IO(IN2) 2.7 0 MAX 4 4 500 10 UNIT V V mA mA
Operating virtual junction temperature, TJ - 40 85 C The device can deliver up to 220 mA at IO(IN2). However, operation at the higher current levels will result in greater voltage drop across the device, and greater voltage droop when switching between IN1 and IN2.
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TPS2100, TPS2101 VAUX POWER-DISTRIBUTION SWITCHES
SLVS197D - JUNE 1999 - REVISED JUNE 2000
electrical characteristics over recommended operating junction temperature range, VI(IN1) = V(IN2) = 3.3 V, IO = rated current (unless otherwise noted)
power switch
PARAMETER IN1-OUT IN1 OUT rDS(on) DS( ) On-state On state resistance IN2 OUT IN2-OUT TEST CONDITIONS TJ = 25C TJ = 85C TJ = 25C TJ = 85C MIN TYP 250 300 1.3 1.5 2.1 375 MAX UNIT m
Pulse-testing techniques maintain junction temperature close to ambient termperature; thermal effects must be taken into account separately.
enable input (EN and EN)
PARAMETER VIH VIL II High-level input voltage Low-level input voltage Input current TEST CONDITIONS 2.7 V VI(INx) 4 V 2.7 V VI(INx) 4 V TPS2100 TPS2101 EN = 0 V or EN = VI(INx) EN = 0 V or EN = VI(INx) -0.5 -0.5 MIN 2 0.8 0.5 0.5 TYP MAX UNIT V V A A
supply current
PARAMETER TEST CONDITIONS EN = H, IN2 selected TPS2100 EN = L, IN1 selected II Supply current EN = L, , IN2 selected TPS2101 EN = H, , IN1 selected TJ = 25C -40C TJ 85C TJ = 25C -40C TJ 85C TJ = 25C -40C TJ 85C TJ = 25C -40C TJ 85C MIN TYP 0.75 1.5 10 16 0.75 1.5 10 16 MAX UNIT A A A A
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TPS2100, TPS2101 VAUX POWER-DISTRIBUTION SWITCHES
SLVS197D - JUNE 1999 - REVISED JUNE 2000
switching characteristics, TJ = 25C, VI(IN1) = VI(IN2) = 3.3 V (unless otherwise noted)
PARAMETER IN1-OUT tr Output rise time IN2-OUT VI(IN1) = 0 ( ) TEST CONDITIONS CL = 1 F, VI(IN2) = 0 ( ) CL = 10 F, CL = 1 F, CL = 1 F, CL = 10 F, CL = 1 F, CL = 1 F, IN1-OUT tf Output fall time IN2-OUT IN1-OUT IN2-OUT IN1-OUT IN2-OUT VI(IN1) = 0 ( ) VI(IN2) = 0 VI(IN1) = 0 VI(IN2) = 0 VI(IN1) = 0 VI(IN2) = 0 ( ) CL = 10 F, CL = 1 F, CL = 1 F, CL = 10 F, CL = 1 F, tPLH tPHL Propagation delay time, low-to-high output time low to high Propagation delay time, high-to-low output time high to low CL = 10 F F, CL = 10 F F, IL = 500 mA IL = 500 mA IL = 10 mA IL = 10 mA IL = 10 mA IL = 1 mA IL = 500 mA IL = 500 mA IL = 10 mA IL = 10 mA IL = 10 mA IL = 1 mA IL = 10 mA IL = 10 mA MIN TYP 830 840 640 5.5 70 5.5 8 93 23 690 6900 6900 75 2 3 370 s s s s MAX UNIT
All timing parameters refer to Figure 3.
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TPS2100, TPS2101 VAUX POWER-DISTRIBUTION SWITCHES
SLVS197D - JUNE 1999 - REVISED JUNE 2000
PARAMETER MEASUREMENT INFORMATION
OUT CL IO
LOAD CIRCUIT
EN or EN
50%
EN or EN tPHL
50%
tPLH VO GND 10%
VI
VI 90% GND
VO
Propagation Delay Time, Low-to-High-Level Output tr VO 90% 10%
Propagation Delay Time, High-to-Low-Level Output tf VI GND
Rise/Fall Time
EN or EN ton VO GND
50%
EN or EN toff
50%
VI 90% VO
VI 10% Turn-off Transition Time GND
Turn-on Transition Time WAVEFORMS
Figure 3. Test Circuit and Voltage Waveforms
Table of Timing Diagrams
FIGURE Propagation Delay and Rise Time With 0.1-F Load, IN1 Propagation Delay and Rise Time With 0.1-F Load, IN2 Propagation Delay and Fall Time With 0.1-F Load, IN1 Propagation Delay and Fall Time With 0.1-F Load, IN2 Propagation Delay and Rise Time With 1-F Load, IN1 Propagation Delay and Rise Time With 1-F Load, IN2 Propagation Delay and Fall Time With 1-F Load, IN1 Propagation Delay and Fall Time With 1-F Load, IN2 Waveforms shown in Figures 4-11 refer to TPS2100 at TJ = 25C 4 5 6 7 8 9 10 11
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TPS2100, TPS2101 VAUX POWER-DISTRIBUTION SWITCHES
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PARAMETER MEASUREMENT INFORMATION
VI(IN1) = 3.3 V VI(IN2) = 0 V CL = 0.1 F RL = 330 EN (2 V/div) EN (2 V/div)
VO (2 V/div) t - Time - 250 s/div
VO (2 V/div)
VI(IN1) = 0 V VI(IN2) = 3.3 V CL = 0.1 F RL = 330 t - Time - 1 s/div
Figure 4. Propagation Delay and Rise Time With 0.1-F Load, IN1
Figure 5. Propagation Delay and Fall Time With 0.1-F Load, IN2
EN (2 V/div)
VI(IN1) = 3.3 V VI(IN2) = 0 V CL = 0.1 F RL = 330
VI(IN1) = 0 V VI(IN2) = 3.3 V CL = 0.1 F RL = 330 EN (2 V/div)
VO (2 V/div) t - Time - 5 s/div
VO (2 V/div) t - Time - 50 s/div
Figure 6. Propagation Delay and Fall Time With 0.1-F Load, IN1
Figure 7. Propagation Delay and Fall Time With 0.1-F Load, IN2
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TPS2100, TPS2101 VAUX POWER-DISTRIBUTION SWITCHES
SLVS197D - JUNE 1999 - REVISED JUNE 2000
PARAMETER MEASUREMENT INFORMATION
VI(IN1) = 3.3 V VI(IN2) = 0 V CL = 1 F RL = 330 EN (2 V/div) EN (2 V/div)
VO (2 V/div) t - Time - 250 s/div
VO (2 V/div)
VI(IN1) = 0 V VI(IN2) = 3.3 V CL = 1 F RL = 330 t - Time - 2.5 s/div
Figure 8. Propagation Delay and Rise Time With 1-F Load, IN1
Figure 9. Propagation Delay and Rise Time With 1-F Load, IN2
EN (2 V/div)
VI(IN1) = 3.3 V VI(IN2) = 0 V CL = 1 F RL = 330
VI(IN1) = 0 V VI(IN2) = 3.3 V CL = 1 F RL = 330 EN (2 V/div)
VO (2 V/div) t - Time - 10 s/div
VO (2 V/div) t - Time - 250 s/div
Figure 10. Propagation Delay and Fall Time With 1-F Load, IN1
Figure 11. Propagation Delay and Fall Time With 1-F Load, IN2
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TPS2100, TPS2101 VAUX POWER-DISTRIBUTION SWITCHES
SLVS197D - JUNE 1999 - REVISED JUNE 2000
TYPICAL CHARACTERISTICS
Table of Graphs
FIGURE IN1 Switch Rise Time IN2 Switch Fall Time IN1 Switch Fall Time IN2 Switch Fall Time Output Voltage Droop Inrush Current IN1 Supply Current IN1 Supply Current IN2 Supply Current IN2 Supply Current IN1-OUT On-State Resistance IN2-OUT On-State Resistance vs Output Current vs Output Current vs Output Current vs Output Current vs Output Current When Output Is Switched From IN2 to IN1 vs Output Capacitance vs Junction Temperature (IN1 Enabled) vs Junction Temperature (IN1 Disabled) vs Junction Temperature (IN2 Enabled) vs Junction Temperature (IN2 Disabled) vs Junction Temperature vs Junction Temperature 12 13 14 15 16 17 18 19 20 21 22 23
IN1 SWTICH RISE TIME vs OUTPUT CURRENT
900 850 800 t r - Rise Time - s 750 700 650 600 550 500 0.01 CL = 0.1 F CL = 1 F CL = 10 F VI(IN1) = 3.3 V VI(IN2) = 0 V TJ = 25C 1000
IN2 SWTICH RISE TIME vs OUTPUT CURRENT
CL = 100 F CL = 47 F 100 t r - Rise Time - s
CL = 100 F CL = 47 F
CL = 10 F 10 CL = 1 F 1 CL = 0.1 F 0.1 0 1 2 VI(IN1) = 0 V VI(IN2) = 3.3 V TJ = 25C 9 10
0.1
100 1 10 IO - Output Current - mA
1000
7 8 3 4 5 6 IO - Output Current - mA
Figure 12
Figure 13
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TPS2100, TPS2101 VAUX POWER-DISTRIBUTION SWITCHES
SLVS197D - JUNE 1999 - REVISED JUNE 2000
TYPICAL CHARACTERISTICS
IN1 SWITCH FALL TIME vs OUTPUT CURRENT
10000 VI(IN1) = 3.3 V VI(IN2) = 0 V TJ = 25C 1000 CL = 100 F 100 CL = 10 F CL = 1 F CL = 0.1 F 1 VI(IN1) = 0 V VI(IN2) = 3.3 V TJ = 25C CL = 47 F 10
IN2 SWITCH FALL TIME vs OUTPUT CURRENT
CL = 100 F
100
CL = 10 F
t f - Output Fall Time - ms 1000
1000 t f - Fall Time - s
CL = 47 F
10
CL = 1 F 10 CL = 0.1 F 1 0.01
0.1
100 1 10 IO - Output Current - mA
0.1 0.01
1 0.1 IO - Output Current - mA
Figure 14
OUTPUT VOLTAGE DROOP vs OUTPUT CURRENT WHEN OUTPUT IS SWITCHED FROM IN2 TO IN1
1 VI(IN1) = 3.3 V VI(IN2) = 3.3 V TJ = 25C 1.6 CL = 0.1 F CL = 1 F 1.4 1.2 0.6 CL = 47 F 0.4 CL = 100 F CL = 10 F Inrush Current - A 1 0.8 0.6 0.4 0.2 0.2 0 0.01 0 0.1 1 IO - Output Current - mA 10 0
Figure 15
INRUSH CURRENT vs OUTPUT CAPACITANCE
VI(IN1) = 3.3 V VI(IN2) = 0 V RL = 6.6 TJ = 25C
VO- Output Voltage Droop - V
0.8
400 100 200 300 Co - Output Capacitance - F
500
Figure 16
Figure 17
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TPS2100, TPS2101 VAUX POWER-DISTRIBUTION SWITCHES
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TYPICAL CHARACTERISTICS
IN1 SUPPLY CURRENT vs JUNCTION TEMPERATURE (IN1 ENABLED)
14 0.25
IN1 SUPPLY CURRENT vs JUNCTION TEMPERATURE (IN1 DISABLED)
I CC - Supply Currenmt - A
12 VI(INx) = 3.3 V 10
I CC - Supply Currenmt - A
VI(INx) = 4 V
0.23 VI(INx) = 4 V 0.21 VI(INx) = 3.3 V 0.19
VI(INx) = 2.7 V 8
0.17
VI(INx) = 2.7 V
6 -40
-20
60 80 0 20 40 TJ Junction Temperature - C
100
0.15 -40
-20
60 80 0 20 40 TJ Junction Temperature - C
100
Figure 18
IN2 SUPPLY CURRENT vs JUNCTION TEMPERATURE (IN2 ENABLED)
0.75 0.6
Figure 19
IN2 SUPPLY CURRENT vs JUNCTION TEMPERATURE (IN2 DISABLED)
0.7 I CC - Supply Currenmt - A VI(INx) = 4 V 0.65 VI(INx) = 3.3 V 0.6 VI(INx) = 2.7 V 0.55 I CC - Supply Currenmt - A
0.56
0.52
VI(INx) = 4 V
0.48 VI(INx) = 3.3 V 0.44 VI(INx) = 2.7 V
0.5 -40
-20
0 20 40 60 80 TJ Junction Temperature - C
100
0.4 -40
-20
60 80 0 20 40 TJ Junction Temperature - C
100
Figure 20
Figure 21
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TPS2100, TPS2101 VAUX POWER-DISTRIBUTION SWITCHES
SLVS197D - JUNE 1999 - REVISED JUNE 2000
TYPICAL CHARACTERISTICS
IN1-OUT ON-STATE RESISTANCE vs JUNCTION TEMPERATURE
305 r on - IN1-OUT On-State resistance - m r on - IN1-OUT On-State resistance - 2
IN2-OUT ON-STATE RESISTANCE vs JUNCTION TEMPERATURE
1.75 VI(INx) = 2.7 V 1.5 VI(INx) = 3.3 V
280
255
1.25 VI(INx) = 4 V 1
VI(INx) = 2.7 V 230 VI(INx) = 3.3 V 205 VI(INx) = 4 V 180 -40 -20 60 80 0 20 40 TJ Junction Temperature - C 100
0.75
0.5 -40
-20
0
20
40
60
80
100
TJ Junction Temperature - C
Figure 22
Figure 23
APPLICATION INFORMATION
TPS2100 CardBus or System Controller 0.1 F EN 3.3 V VCC IN1 3.3 V VAUX IN2 OUT 0.1 F GND 3.3 V xx F
0.1 F
Figure 24. Typical Application
power supply considerations
A 0.01-F to 0.1-F ceramic bypass capacitor between IN and GND, close to the device is recommended. The output capacitor should be chosen based on the size of the load during the transition of the switch. A 47-F capacitor is recommended for 10-mA loads. Typical output capacitors (xx F, shown in Figure 24) required for a given load can be determined from Figure 16 which shows the output voltage droop when output is switched from IN2 to IN1. The output voltage droop is insignificant when output is switched from IN1 to IN2. Additionally, bypassing the output with a 0.01-F to 0.1-F ceramic capacitor improves the immunity of the device to short-circuit transients.
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TPS2100, TPS2101 VAUX POWER-DISTRIBUTION SWITCHES
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APPLICATION INFORMATION power supply considerations (continued)
switch transition The n-channel MOSFET on IN1 uses a charge-pump to create the gate-drive voltage, which gives the IN1 switch a rise time of approximately 1 ms. The p-channel MOSFET on IN2 has a simpler drive circuit that allows a rise time of approximately 8 s. Because the device has two switches and a single enable pin, these rise times are seen as transition times, from IN1 to IN2, or IN2 to IN1, by the output. The controlled transition times help limit the surge currents seen by the power supply during switching. thermal protection Thermal protection provided on the IN1 switch prevents damage to the IC when heavy-overload or short-circuit faults are present for extended periods of time. The increased dissipation causes the junction temperature to rise to dangerously high levels. The protection circuit senses the junction temperature of the switch and shuts it off at approximately 125C (TJ). The switch remains off until the junction temperature has dropped. The switch continues to cycle in this manner until the load fault or input power is removed. undervoltage lockout An undervoltage lockout function is provided to ensure that the power switch is in the off state at power-up. Whenever the input voltage falls below approximately 2 V, the power switch quickly turns off. This function facilitates the design of hot-insertion systems that may not have the capability to turn off the power switch before input power is removed. Upon reinsertion, the power switch will be turned on with a controlled rise time to reduce EMI and voltage overshoots.
power dissipation and junction temperature
The low on-resistance on the n-channel MOSFET allows small surface-mount packages, such as SOIC, to pass large currents. The thermal resistances of these packages are high compared to that of power packages; it is good design practice to check power dissipation and junction temperature. First, find ron at the input voltage, and operating temperature. As an initial estimate, use the highest operating ambient temperature of interest and read ron from Figure 22 or Figure 23. Next calculate the power dissipation using: P D
+ ron
I2
Finally, calculate the junction temperature: T Where: TA = Ambient temperature RJA = Thermal resistance Compare the calculated junction temperature with the initial estimate. If they do not agree within a few degrees, repeat the calculation using the calculated value as the new estimate. Two or three iterations are generally sufficient to obtain a reasonable answer. J
+ PD
R
qJA
) TA
ESD protection
All TPS2100 and TPS2101 terminals incorporate ESD-protection circuitry designed to withstand a 2-kV human-body-model discharge as defined in MIL-STD-883C.
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TPS2100, TPS2101 VAUX POWER-DISTRIBUTION SWITCHES
SLVS197D - JUNE 1999 - REVISED JUNE 2000
MECHANICAL DATA
DBV (R-PDSO-G5) PLASTIC SMALL-OUTLINE
0,95 5 4
0,50 0,30
0,20 M
1,70 1,50
3,00 2,60
0,15 NOM
1 3,00 2,80
3
Gage Plane
0,25 0-8 0,55 0,35
Seating Plane 1,45 0,95 0,05 MIN 0,10 4073253-4/E 05/99
NOTES: A. B. C. D.
All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion. Falls within JEDEC MO-178
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
15
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TPS2100, TPS2101 VAUX POWER-DISTRIBUTION SWITCHES
SLVS197D - JUNE 1999 - REVISED JUNE 2000
MECHANICAL DATA
D (R-PDSO-G**)
14 PINS SHOWN
PLASTIC SMALL-OUTLINE PACKAGE
0.050 (1,27) 0.020 (0,51) 0.014 (0,35) 14 8 0.008 (0,20) NOM 0.244 (6,20) 0.228 (5,80) 0.157 (4,00) 0.150 (3,81) 0.010 (0,25) M
Gage Plane
0.010 (0,25) 1 A 7 0- 8 0.044 (1,12) 0.016 (0,40)
Seating Plane 0.069 (1,75) MAX 0.010 (0,25) 0.004 (0,10) 0.004 (0,10)
PINS ** DIM A MAX
8 0.197 (5,00) 0.189 (4,80)
14 0.344 (8,75) 0.337 (8,55)
16 0.394 (10,00) 0.386 (9,80) 4040047 / D 10/96
A MIN
NOTES: A. B. C. D.
All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15). Falls within JEDEC MS-012
16 POST OFFICE BOX 655303 Powered by ICminer.com Electronic-Library Service CopyRight 2003
* DALLAS, TEXAS 75265
IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. Customers are responsible for their applications using TI components. In order to minimize risks associated with the customer's applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI's publication of information regarding any third party's products or services does not constitute TI's approval, warranty or endorsement thereof.
Copyright (c) 2000, Texas Instruments Incorporated
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