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| ECOG1 Microcontroller Low Power Communications Processor PRELIMINARY The ECOG1 microcontroller is a low-power microcontroller based on a 16-bit Harvard architecture with a 24-bit word code linear address space (32Mbyte) and 16-bit word linear data address space (128Kbytes). It is available in a 128-pin LQFP with or without the IntAct high-speed serial interface. A comprehensive toolset and C Compiler are available. ChA 0 to 25MHz 3.3V processor Powerful arithmetic operations Barrel Shifter Harvard Architecture 64Kx16 Data Memory 16Mx16 Program Memory Built in Emulator (eICE) Low power operation 64Kbytes FLASH EPROM 4Kbytes SRAM MMU Power-saving code cache Code security feature External Host Interface External Memory Interface Fast Vectored Interrupts Dual UART Dual USART Smart Card Interface SPI I2C Consumer IR/IRDA 4 channel 12-bit A/D Parallel Interface ChB Stream Up Down 5 Multi Purpose Timers Watchdog Timer Long Interval Timer Real Time Clock PWM timers Temperature Sensor Supply Voltage Sensor Power-On Reset General Purpose I/O 25MHz from watch XTAL Interfaces to 8/16/32-bit parts USART/SPI/IR /IrDA/I2C/ Smart Card IF Dual UART 4KBytes iRAM IntAct EHI Data Control PWM Switching Multiplexer EMI 24 Bit Addr/Data 8 Bit Data 12 Bit ADC Vdd Sensor MUX Temp Sensor 4 Vin PIF 64K Bytes Flash EPROM 16/32 Bit Interface MMU GPIO 29 Bit I/O or Control Power On Reset Interupt Requests Register Block Code Cache System Clock Timers External Triggers Clock Inputs IRC ECOG1 CPU Core eICE eICE_miso eICE_mosi eICE_Clock eICE_Load# eICE_CS Reset_In Figure 1 - Internal Block Diagram This document describes a device that is currently at pre-production status. Some specifications or descriptions may change. V3.1 www.cyantechnology.com 1-Mar-2002 PRELIMINARY CPU Core * * * 16-bit 25MHz register-based core Harvard architecture Supports a full array of 16-bit arithmetic operations, including both signed and unsigned MULtiply and DIVide instructions 32MByte linear program memory 128KByte linear data memory Vectored interrupts 64Kbytes organized as 32Kx16 Organized as eight 4Kx16 banks Individual Flash banks can be read and/or write protected Built in programming algorithm is available under application software control 512 line cache Reduces power consumption while improving performance Both deterministic and non-deterministic modes Individual cache lines can be locked Can cache both User and Interrupt Mode * * * * * * * * * * * * * * * * * * * Flash EPROM Full modem support (CTS, RTS, DSR, DTR, DCD, and RI) Supporting 5, 6, 7, or 8-bits of data 1, 1.5, or 2 stop bits Even, odd or no parity Automatic end-of-frame guard time insertion of 0- to 64-bit periods Receive time-out detection 0 to 64-bit periods Software Line Break generation Programmable Baud rate generator Interrupts generated on full and empty Receiver error detection for false start bits, parity errors and frame errors Configurable data polarity Over-sampling of received data for noise immunity Two synchronous/asynchronous doublebuffered serial ports Programmable baud rate generator End of frame guard time insertion of 0 to 64-bit periods Receive time-out detection 0 to 64-bit periods Receiver error detection for false Start bits, Parity errors, Frame errors and Buffer overflow Configurable data and clock polarity Configurable data packing, MSB or LSB first Over sampling receive data for noise immunity DUSART * * * * * * * * Code Cache * * * * * MMU * * Performs logical to physical address translations Translates between RAM, Program Memory, and external memory devices for both code and data accesses concurrently Lookup tables in RAM or Flash can be mapped between each memory area Up to 2 concurrent translations to external devices from code addresses Up to 3 concurrent translations to external devices from data addresses Wait states automatically generated Concurrent accesses to same device are prioritized Translations are prioritized to allow overlapped translations Two independent RS232 compatible asynchronous double-buffered serial ports * * * * * * Asynchronous Interface: * Asynchronous frames supporting 5, 6, 7, or 8-bits of data * 1, 1.5, or 2 stop bits * Even, odd or no parity * Full modem support (CTS, RTS, DSR, DTR, DCD, and RI) * Software Line Break generation Synchronous Interface: * Local or external transmit and receive clock * Full or half duplex * Frame sizes from 1 to 16-bits with larger frames possible * Support for NRZ, RZ * PM, PWM and ASK modulation if used in conjunction with PWM timer DUART * V3.1 www.cyantechnology.com 2 PRELIMINARY Host Control Port (HCP) * * * * * * Provides direct access internal registers of each USART Custom serial protocols may be emulated Up to 255 symbols per frame Parity may be automatically inserted or tested at the end of each frame Start bit edge detection Tx/Rx interrupts Multi-slave SPI system Four slave select lines Both master and slave roles Programmable clock polarity and clock/data phase ISO 7816 compatible smart card interface Multiprocessor support Byte level support for T=0 and T=1 transmission protocols Detection and generation of the transmission error signal for T=0 protocol Automatic retransmission of corrupted bytes for T=0 protocol Independent controls for power and ground switching Hardware state machine for power up, reset and shutdown sequences Programmable baud rates Support for low rate (<115.2 kbps) IrDA framing and modulation Compatible with common ASK, PM, PPM (e.g. RC-5) modulation schemes Variable frame lengths up to 255 bits Variable length multi-byte frames Half duplex operation supported using an integral transceiver frame duration (maximum 1023 symbols) to separate transmit and receive exchanges Raw IR mode (software modem) supported Programmable start, stop, data length, frame length and polarities Programmable start and stop sequences Support for current and future frame formats Carrier frequency generation I2C * * * * * Two wire I2C compatible port Address matching ACK bit and wait state insertion Multi-master arbitration Supports 10-bit addressing and fast mode Provides a DMA interface to an external host or FIFO Memory mapped peripheral port Supports master and slave mode timing 16/32-bit data bus Request & Acknowledge control lines Configurable master mode timing Direct DMA connection into internal SRAM (11-bit block address, max 256 byte block size) Internal DMA controller supports circular buffer and link list buffer models 8-bit external address with 16-bit data 3-bit external address with 32-bit data Three control lines: chip select, direction and wait Configurable control line senses Interrupt generated upon transfer 29 memory mapped GPIO pins Configured as Input, Output, bidirectional Directly drive or open drain outputs Direct drive LEDs Each input can generate an interrupt Any GPIO configured as an Input can generate an interrupt Level or edge sensitive interrupts Two 16-bit parallel data ports Directly drive, open drain, or tri-state outputs 16-bit Watch Dog Timer 16-bit Real Time Clock 24-bit Long Interval Timer Two 16-bit PWMs CGT1 and CGT2 Two 16-bit General Purpose Timers/event counters (GPT) 16-bit timer (CPT) with multiple event capture registers 16-bit ripple counter Most timers have pre-scalars External Host Interface (EHI) * * * * * * * * * * * * * * * * * * * * * * SPI * * * * Smart Card Interface * * * * * * * General Purpose I/O (GPIO) Consumer IR / IrDA * * * * * * External Interrupts Parallel Interface (PIO) * * * * * Timers * * * * * * * * V3.1 www.cyantechnology.com 3 PRELIMINARY IntAct External Memory Interface * * * * * * * * * * * * * * * * * Operates as bus Master and Slave Big-endian or little-endian Allows both DMA and non DMA accesses to internal memory and I/O registers 8, 16 or 32-bit data bus as Master 24-bit address bus as Master Multiplexed address/data for 16 and 32bit data busses as Master Supports 8-bit and 16-bit transfers as Slave 16 and 32-bit data bus and accesses as Slave Flag Register for software generated interrupt Supports up to 128M Single Data Rate 16-bit wide SDRAMs Four Row/Column SDRAM address multiplexing schemes SDRAM auto and self refresh supported Configurable timing Low power SDRAM suspend/standby mode SDRAM can be mapped into both code and data space Single cycle data space access, code space burst access in conjunction with Code Cache Hardware support for software initialization and refresh of SDRAM 12-bit ADC with 8KHz sampling, differential input On-chip temperature sensor On-chip Power Supply Monitor 4 channel analog multiplexer with four input modes: i) Four channel inputs to the ADC for single ended use, using internal voltage reference ii) Three channel inputs to the ADC, one input as external reference iii) Three channel inputs to the ADC, one port as output of the internal reference voltage iv) Two differential inputs * * * * * * * * * Amino Communications proprietary IntAct interface Secure, high speed communications Typically 180Mbit/s data rate Provides virtual circuit connections between IntAct devices Permits inter-processor communications Two crystal oscillators Low cost 32KHz watch crystal can generate 25MHz internal clock Internal PLL Second oscillator uses a 5MHz crystal to generate 25MHz internal clock with low jitter ANSI C Compiler Validated to ANSI/ISO/FIPS-160 ANSI Standard Library Macro Assembler Software Simulator and debugger Real-time debug port Can program internal Flash When BREAK command is locked in the cache, can provide virtually unlimited address breakpoints Commands include Reset, Stop, Run, Run to Break Non-intrusive read and write to any core register, including PC Read and write of any memory location Sleep mode with wake on interrupts All peripherals have individual clock domains and can be stopped when not in use Peripherals are connected to multiple device pins Each port has a unique multiplexing scheme to select port configuration Two 4-bit ports Ten 8-bit ports Clocks C Compiler suite * * * * * * * * * * * * * eICE Debugger Interface Analog Functions * * * * Power Saving Features External Ports * * * * V3.1 www.cyantechnology.com 4 PRELIMINARY Programmer's Model 16 bits 16 bits AL 8 bits AH/AL or A 24 bits AH Flags T 7 B 6 I 5 U 4 C 3 S 2 N 1 Z 0 Debug Interrupt Arithmetic / Flags Flags Logic Flags UX User Mode Index X Index Y Index X Index Y Program ctr. UXH UY IXH IX Interrupt Mode IY PC 16 bits Data space User Mode: Indexed IY Scratchpad RAM FFFF FFE0 64K-16 words 0000 16 bits Program space FFFFFF large address range: 16320K words 00FFFF : End of small address range small address range: 64K words 000004 : Interrupt Routine start address 000000 : Reset Address V3.1 www.cyantechnology.com 5 PRELIMINARY Instruction Set 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 Operand Opcode Reg Mode T B I U C S N Z Operand not H'00 H'00 H'00 H'00 H'00 H'00 H'01 H'FF H'FE - Opcode H'0 H'0 H'0 H'0 H'0 H'0 H'0 H'0 H'0 H'0 H'0 H'0 H'0 H'0 H'0 Reg Mode 00 00 01 10 11 00 01 11 10 10 10 10 00 01 10 00 00 00 00 00 01 01 01 01 01 01 01 10 10 10 Assembler PREFIX NOP BRK SLEEP SIF ST flags LD flags RTI @( Operation ARG_EXT = (ARG_EXT<<8) + operand None Stop for debug Enter sleep mode Perform ESIF access during instruction @( Flags ALL ALL - UNSIGNED SIGNED BC BRXL ST UX LD UX ST XH @( - @( - {IX[23:16], UX[23:16]} H'0 11 10 LD XH @( - @( @( NZ NZ NZ NZ NZ LD.BU PRINT ST ST.B reg, data regd,AL regx,AH rega, Y X:,A MOV MOV MOV MOV24 V3.1 www.cyantechnology.com 6 PRELIMINARY Reg Register Access Field Reg field 00 01 10 11 reg AH AL X Y regd regx rega AH XH X Y XH X AL Indicates UNSIGNED prefix instruction required for this instruction. Operation reg ! reg + data reg ! reg + data + C reg ! reg - data reg ! reg - data - C reg ! -reg + data flags ! reg - data A ! AL * data Sign Extend. A ! AL * data AL ! A / data; AH ! rem Sign Extend. AL ! A / data; AH ! rem flags ! data X ! PC + 1; PC ! branch_addr C![AH, AL]!0 C![AH, AL]!0 AH[15]"[AH, AL]"C 0"[AH,AL]"C C![AH,AL]!C C"[AH,AL]"C reg ! reg | data reg ! reg & data reg ! reg ^ data PC ! branch_addr if S = 1 PC ! branch_addr if N = 0 PC ! branch_addr if N = 1 PC ! branch_addr if Z = 0 PC ! branch_addr if Z = 1 PC ! branch_addr if C = 0 PC ! branch_addr if C = 1 PC ! branch_addr Flags CSNZ CSNZ CSNZ CSNZ CSNZ CSNZ NZ C C C C C C NZ NZ NZ - reg, data reg, data reg, data reg, data reg, data reg, data data data data data data addr data data data data data data reg, data reg, data reg, data addr addr addr addr addr addr addr addr ROL ROR OR AND XOR BRA BLT BPL BMI BNE BEQ BCC BCS V3.1 www.cyantechnology.com 7 PRELIMINARY Mode Field mode 00 01 10 11 mode 00 01 10 11 unused Direct Indexed X Indexed Y data = 8-bit value @ 17-bit operand byte address data = 8-bit value @ 17-bit byte address in {XH,X}+17-bit operand byte address data = 8-bit value @ 16-bit word address in Y+17-bit operand byte address Indexed Y Immediate Direct Data Mode : source or destination data = 16-bit sign extended operand data = 16-bit value @ 16-bit operand address data = 16-bit value @ X+16-bit operand address data = 16-bit value @ Y+16-bit operand address Address Mode: Branch Address PC relative Direct X Relative Indexed Y PC + 24-bit operand {XH, @ 16-bit operand address} {XH, X} + 24-bit sign extended operand {XH, @(Y + 16-bit operand)} Data Mode Byte Accesses: source or destination V3.1 www.cyantechnology.com 8 PRELIMINARY Pin Out of Port K version. 128 pin LQFP. Pin pitch 0.4mm. 14x14mm body. 16x16mm at pin edge. PortG_0 PortG_1 PortG_2 PortG_3 PortG_4 PortG_5 PortG_6 PortG_7 PortH_0 PortH_1 PortH_2 PortH_3 PortH_4 PortH_5 PortH_6 PortH_7 PortF_0 PortF_1 PortF_2 PortF_3 PortF_4 PortF_5 PortF_6 PortF_7 PortI_0 PortI_1 PortI_2 GND PortI_3 GND Vdd Vdd PortE_7 PortE_6 PortE_5 PortE_4 PortE_3 PortE_2 PortE_1 PortE_0 Test CPU_Break Vdd GND PortK_7 PortK_6 NC Vdd GND GND PortK_5 PortK_4 Vdd GND eICE_miso eICE_mosi eICE_Clock eICE_Load# eICE_CS Low_XTAL_Out Low_XTAL_In High_XTAL_Out High_XTAL_In AGND PortI_4 PortI_5 PortI_6 PortI_7 PortJ_7 PortJ_6 PortJ_5 PortJ_4 PortJ_3 PortJ_2 PortJ_1 PortJ_0 PortK_3 PortK_2 GND ECOG1 Vdd GND NC PortK_1 PortK_0 GND Vdd PortL_7 PortL_6 PortL_5 PortL_4 PortL_3 PortL_2 PortL_1 PortL_0 PortD_3 PortD_2 PortC_1 PortC_2 PortC_3 PortD_0 PortA_5 PortA_6 PortA_7 PortB_0 PortB_1 PortB_2 PortB_3 PortB_4 PortB_5 PortB_6 PortB_7 Reset_Out Reset_In PortC_0 PortA_0 PortA_1 PortA_2 PortA_3 PortA_4 PortD_1 AVdd GND Vin1 Vin2 Vin3 Vin4 Vdd Vdd V3.1 www.cyantechnology.com 9 PRELIMINARY Pin Out of IntAct version. 128 pin LQFP. Pin pitch 0.4mm. 14x14mm body. 16x16mm at pin edge. PortG_0 PortG_1 PortG_2 PortG_3 PortG_4 PortG_5 PortG_6 PortG_7 PortH_0 PortF_0 PortF_1 PortH_1 PortH_2 PortH_3 PortH_4 PortH_5 PortH_6 PortH_7 PortF_2 PortF_3 PortF_4 PortF_5 PortF_6 PortF_7 PortI_0 PortI_1 PortI_2 GND PortI_3 GND Vdd Vdd PortE_7 PortE_6 PortE_5 PortE_4 PortE_3 PortE_2 PortE_1 PortE_0 Test CPU_Break Vdd GND IntAct_D_Fin IntAct_D_Din IntAct_D_Cout Vdd GND IntAct_D_Cin IntAct_D_Dout IntAct_D_Fout Vdd GND eICE_miso eICE_mosi eICE_Clock eICE_Load# eICE_CS Low_XTAL_Out Low_XTAL_In High_XTAL_Out High_XTAL_In AGND PortI_4 PortI_5 PortI_6 PortI_7 PortJ_7 PortJ_6 PortJ_5 PortJ_4 PortJ_3 PortJ_2 PortJ_1 PortJ_0 IntAct_U_Fout IntAct_U_Dout IntAct_U_Cin ECOG1i Vdd GND IntAct_U_Cout IntAct_U_Din IntAct_U_Fin GND Vdd PortL_7 PortL_6 PortL_5 PortL_4 PortL_3 PortL_2 PortL_1 PortL_0 PortD_3 PortD_2 PortC_1 PortC_2 PortC_3 PortD_0 PortA_5 PortA_6 PortA_7 PortB_0 PortB_1 PortB_2 PortB_3 PortB_4 PortB_5 PortB_6 Reset_In PortA_0 PortA_1 PortA_2 PortA_3 PortA_4 PortB_7 Reset_Out PortC_0 PortD_1 AVdd GND GND Vin1 Vin2 Vin3 Vin4 Vdd V3.1 www.cyantechnology.com 10 PRELIMINARY Revision History. V1.0 V1.1 V1.2 V1.3 V1.31 V1.32 V1.4 V1.41 V1.42 V 2.0 V2.0a V3.0/a V3.1 First release. Text corrections. Text corrections and new layout. Final pin out. Final final pin out! 5 volt compliant inputs removed from datasheet. Not available on first rev. Pin descriptions and port mapping added. Minor changes to block diagram. Additional pin description info. EMI pin out changed. Signal names changed in keeping with industry norm. Additional pin description info. Layout cleaned up and list of features revised for clarity. Pin out tables removed for brevity Cleaned up for style - first official outside release 21-Jan-2002 Clarified some text; Used American English spelling 19-Feb-2002 Minor format changes, changed paper size to US Letter Original rights are retained by owners of registered trademarks mentioned in this document 2 I2C, I C, and the I2C interface are patented by Philips Semiconductor. Philips may demand a royalty from designs using the I2C interface. Cyan Technology Ltd Denmark House High Street Willingham Cambridge CB4 5ES Tel: +44 (0)1954 207070 www.cyantechnology.com V3.1 www.cyantechnology.com 11 |
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