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INTEGRATED CIRCUITS
DATA SHEET
TDA8787A 10-bit, 3.0 V, up to 25 Msps analog-to-digital interface for CCD cameras
Product specification Supersedes data of 2000 Oct 12 File under Integrated Circuits, IC02 2000 Nov 14
Philips Semiconductors
Product specification
10-bit, 3.0 V, up to 25 Msps analog-to-digital interface for CCD cameras
FEATURES * Correlated Double Sampling (CDS), Programmable Gain Amplifier (PGA), 10-bit Analog-to-Digital Converter (ADC) and reference regulator included * Fully programmable via a 3-wire serial interface * Sampling frequency up to 25 MHz; (TDA8787AHL = 18 MHz; TDA8787AHL/S1 = 25 MHz) * PGA gain range of 36 dB (in steps of 0.1 dB) * Low power consumption of only 170 mW at 2.7 V * Power consumption in standby mode of 4.5 mW (typical value) * 3.0 V operation; 2.5 to 3.6 V operation for the digital outputs * Active control pulses polarity selectable via serial interface * 8-bit DAC included for analog settings * TTL compatible inputs, CMOS compatible outputs. ORDERING INFORMATION PACKAGE TYPE NUMBER NAME TDA8787AHL TDA8787AHL/S1 LQFP48 LQFP48 DESCRIPTION plastic low profile quad flat package; 48 leads; body 7 x 7 x 1.4 mm VERSION SOT313-2 SOT313-2 APPLICATIONS
TDA8787A
* Low-power, low-voltage CCD camera systems. GENERAL DESCRIPTION The TDA8787A is a 10-bit analog-to-digital interface for CCD cameras. The device includes a correlated double sampling circuit, a PGA, clamp loops and a low-power 10-bit ADC, together with its reference voltage regulator. The PGA gain and the ADC input clamp level are controlled via the serial interface. An additional DAC is provided for additional system controls. Its output voltage range is 1.0 V peak-to-peak which is available at pin OFDOUT.
PIXEL FREQUENCY 18 MHz 25 MHz
2000 Nov 14
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Philips Semiconductors
Product specification
10-bit, 3.0 V, up to 25 Msps analog-to-digital interface for CCD cameras
QUICK REFERENCE DATA SYMBOL VCCA VCCD VCCO ICCA ICCD ICCO ADCres Vi(CDS)(p-p) fpix(max) fpix(min) DRPGA Ntot(rms) Vn(i)(eq)(rms) Ptot PARAMETER analog supply voltage digital supply voltage digital outputs stages supply voltage analog supply current digital supply current digital outputs supply current ADC resolution CDS input amplitude (video signal) (peak-to-peak value) maximum pixel frequency minimum pixel frequency PGA dynamic range total noise (RMS value) at CDS input to ADC output equivalent input noise voltage (RMS value) total power consumption PGA code = 0; see Fig.8 PGA code = 383 VCCA = VCCD = VCCO = 3 V VCCA = VCCD = VCCO = 2.7 V VCC = 2.85 V VCC 3.0 V all clamps active; fpix = 18 MHz fpix = 18 MHz fpix = 18 MHz; CL = 20 pF; input ramp response time is 800 s CONDITIONS MIN. 2.7 2.7 2.5 - - - - 650 800 25 2 - - - - -
TDA8787A
TYP. 3.0 3.0 2.6 50 13 1 10 - - - - 36 0.15 70 190 170
MAX. 3.6 3.6 3.6 60 17 2 - - - - - - - - - -
UNIT V V V mA mA mA bits mV mV MHz MHz dB LSB V mW mW
2000 Nov 14
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2000 Nov 14
SHP 47 SHD 48 VCCD3 1 DGND3 2 VCCA2 18 AGND2 17 13 CDS CLOCK GENERATOR CPCDS1 7 CLAMP CPCDS2 VCCA3 AGND3 IN 8 42 41 4 CORRELATED DOUBLE SAMPLING PGA SHIFT
BLOCK DIAGRAM
Philips Semiconductors
10-bit, 3.0 V, up to 25 Msps analog-to-digital interface for CCD cameras
CLPOB CLPDM 12
AGND5 43
BLK 11
CLK 40
OE 37 20 19 39 38 26 DGND1 VCCD1 DGND2 VCCD2 OGND
TDA8787AHL
36 35 34
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
10-bit ADC SHIFTER BLANKING LATCH OUTPUT BUFFER
33 32 31 30 29
4
VCCA1 AGND1 6 5 input clamp Vref 9-BIT REGISTER DAC 7-BIT REGISTER OFD DAC OFDOUT 9 8-BIT REGISTER SERIAL INTERFACE REGULATOR 14 15 16 3 45 46 23 22 21 24 10 TEST1 TEST2 TEST3 AGND4 OPGA OPGAC SEN SCLK SDATA VSYNC STDBY
28 27
25
VCCO
44
DCLPC
FCE330
Product specification
TDA8787A
Fig.1 Block diagram.
Philips Semiconductors
Product specification
10-bit, 3.0 V, up to 25 Msps analog-to-digital interface for CCD cameras
PINNING SYMBOL VCCD3 DGND3 AGND4 IN AGND1 VCCA1 CPCDS1 CPCDS2 OFDOUT STDBY BLK CLPDM CLPOB TEST1 TEST2 TEST3 AGND2 VCCA2 VCCD1 DGND1 SDATA SCLK SEN VSYNC VCCO OGND D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 OE VCCD2 DGND2 CLK 2000 Nov 14 PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 digital supply voltage 3 digital ground 3 analog ground 4 input signal from CCD analog ground 1 analog supply voltage 1 clamp storage capacitor 1 clamp storage capacitor 2 analog output of the additional 8-bit control DAC DESCRIPTION
TDA8787A
standby mode control input (LOW: TDA8787A active; HIGH: TDA8787A standby) blanking control input clamp pulse input at dummy pixel (should be connected to ground) clamp pulse input for optical black test pin input 1 (should be connected to AGND2) test pin input 2 (should be connected to AGND2) test pin input 3 (should be connected to AGND2) analog ground 2 analog supply voltage 2 digital supply voltage 1 digital ground 1 serial data input for serial interface control serial clock input for serial interface control strobe pin for serial interface control vertical sync pulse input output stages supply voltage digital output ground ADC digital output 0 (LSB) ADC digital output 1 ADC digital output 2 ADC digital output 3 ADC digital output 4 ADC digital output 5 ADC digital output 6 ADC digital output 7 ADC digital output 8 ADC digital output 9 (MSB) output enable control input (LOW: outputs active; HIGH: outputs in high impedance) digital supply 2 digital ground 2 data clock input 5
Philips Semiconductors
Product specification
10-bit, 3.0 V, up to 25 Msps analog-to-digital interface for CCD cameras
SYMBOL AGND3 VCCA3 AGND5 DCLPC OPGA OPGAC SHP SHD PIN 41 42 43 44 45 46 47 48 analog ground 3 analog supply 3 analog ground 5 regulator decoupling pin PGA output (test pin) PGA complementary output (test pin) preset sample-and-hold pulse input data sample-and-hold pulse input DESCRIPTION
TDA8787A
46 OPGAC
39 DGND2
41 AGND3
43 AGND5
38 VCCD2
44 DCLPC
42 VCCA3
45 OPGA
48 SHD
47 SHP
40 CLK
VCCD3 DGND3 AGND4 IN AGND1 VCCA1 CPCDS1 CPCDS2 OFDOUT
37 OE
1 2 3 4 5 6
36 D9 35 D8 34 D7 33 D6 32 D5 31 D4
TDA8787AHL
7 8 9
30 D3 29 D2 28 D1 27 D0 26 OGND 25 VCCO
STDBY 10 BLK 11 CLPDM 12
CLPOB 13
TEST1 14
TEST2 15
TEST3 16
AGND2 17
VCCA2 18
VCCD1 19
DGND1 20
SDATA 21
SCLK 22
SEN 23
VSYNC 24
FCE331
Fig.2 Pin configuration.
2000 Nov 14
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Philips Semiconductors
Product specification
10-bit, 3.0 V, up to 25 Msps analog-to-digital interface for CCD cameras
LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 60134). SYMBOL VCCA VCCD VCCO VCC PARAMETER analog supply voltage digital supply voltage output stages supply voltage supply voltage difference between VCCA and VCCD between VCCA and VCCO between VCCD and VCCO Vi Io Tstg Tamb Tj Note input voltage data output current storage temperature ambient temperature junction temperature referenced to AGND -0.5 -0.5 -0.5 -0.3 - -55 -20 - note 1 note 1 note 1 CONDITIONS MIN. -0.3 -0.3 -0.3
TDA8787A
MAX. +5.0 +5.0 +5.0 +0.5 +1.2 +1.2 +5.0 10 +150 +75 150 V V V V V V V
UNIT
mA C C C
1. The supply voltages VCCA, VCCD and VCCO may have any value between -0.3 and +5.0 V provided that the supply voltage difference VCC remains as indicated. HANDLING Inputs and outputs are protected against electrostatic discharges in normal handling. However, to be totally safe, it is desirable to take normal precautions appropriate to handling integrated circuits. THERMAL CHARACTERISTICS SYMBOL Rth(j-a) PARAMETER thermal resistance from junction to ambient CONDITIONS in free air VALUE 76 UNIT K/W
2000 Nov 14
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Philips Semiconductors
Product specification
10-bit, 3.0 V, up to 25 Msps analog-to-digital interface for CCD cameras
CHARACTERISTICS VCCA = VCCD = 3.0 V; VCCO = 2.6 V; fpix = 18 MHz; Tamb = -20 to +75C; unless otherwise specified. SYMBOL Supplies VCCA VCCD VCCO ICCA ICCD ICCO analog supply voltage digital supply voltage digital outputs stages supply voltage analog supply current digital supply current digital outputs supply current total power consumption all clamps active 2.7 2.7 2.5 - - CL = 20 pF on all data outputs; - input ramp response time is 800 s VCCA = VCCD = VCCO = 3 V VCCA = VCCD = VCCO = 2.7 V Digital inputs INPUTS: PINS STDBY, CLPDM, CLPOB, SCLK, SDATA, SEN, VSYNC, OE, CLK AND BLK VIL VIH Ii VIL VIH Ii Clamps GLOBAL CHARACTERISTICS OF THE CLAMP LOOPS tW(clamp) clamp active pulse width in numbers of pixels PGA input code = 255 for maximum 4 LSB error 12 - LOW-level input voltage HIGH-level input voltage input current 0 Vi VCCD 0 2.2 -2 0 2.2 0 Vi VCCD -10 - - - - - - - - 3.0 3.0 2.6 50 13 1 PARAMETER CONDITIONS MIN. TYP.
TDA8787A
MAX.
UNIT
3.6 3.6 3.6 60 17 2
V V V mA mA mA
Ptot
190 170
- -
mW mW
0.6 5.0 +2
V V A V V A
INPUTS: PINS SHP AND SHD LOW-level input voltage HIGH-level input voltage input current 0.6 5.0 +10
-
pixels
INPUT CLAMP: PIN CLPDM gm(CDS) CDS input clamp transconductance 1.5 2.7 3.5 mS
OPTICAL BLACK CLAMP: PIN CLPOB Gshift ILSB(cp) gain from CPCDS1 and 2 to PGA inputs charge pump current for 1 LSB error at ADC output PGA input code = 0 PGA input code = 383 - - - 0.27 20 0.60 - - - A A
2000 Nov 14
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Philips Semiconductors
Product specification
10-bit, 3.0 V, up to 25 Msps analog-to-digital interface for CCD cameras
SYMBOL PARAMETER CONDITIONS MIN. - - - - 2 TYP.
TDA8787A
MAX. - - - +1 -
UNIT
Correlated Double Sampling (CDS) (pin IN) Vi(CDS)(p-p) CDS input amplitude (video signal) (peak-to-peak value) maximum CDS input reset pulse amplitude input current input capacitance CDS control pulses minimum active time Vi(CDS)(p-p) = 800 mV; black-to-white transition in 1 pixel (2 LSB typical); Tamb = 25 C; note 1 fpix = 18 MHz (TDA8787AHL) fpix = 25 MHz (TDA8787AHL/S1) th(IN-SHP) th(IN-SHD) Amplifier DRPGA GPGA LE(i) LE(d) PGA dynamic range PGA gain step - -0.3 fpix = 18 MHz; ramp input fpix = 18 MHz; ramp input - - 36 - 1.3 0.5 - +0.3 2.5 0.9 dB dB hold time SHP to IN hold time SHD to IN Tamb = 25 C; see Figs 3 and 4 Tamb = 25 C; see Figs 3 and 4 11 9 - - 15 11 1 1 - - 2 2 ns ns ns ns at floating gate level VCC = 2.85 V VCC 3.0 V 650 800 500 -1 - mV mV mV A pF
Vi(rst)(max) Ii Ci tCDS(min)
Analog-to-Digital Converter (ADC) integral non-linearity error differential non-linearity error LSB LSB
Total chain characteristics (CDS, PGA and ADC) fpix(max) fpix(min) tCLKH tCLKL td(SHD-CLK) tsu(BLK-CLK) Vi(IN) Ntot(rms) maximum pixel frequency minimum pixel frequency clock HIGH time clock LOW time time delay SHD to CLK set-up time of BLK compared to CLK video input dynamic signal PGA input code = 0 for ADC full-scale output PGA input code = 383 total noise from CDS input see Fig.8 to ADC output PGA input code = 0 (RMS value) PGA input code = 96 equivalent input noise voltage (RMS value) PGA input code = 383 PGA input code = 0 see Fig.3 25 2 15 15 10 10 800 12.7 - - - - - - - - - - - - 0.15 0.8 70 120 - - - - - - - - - - - - MHz MHz ns ns ns ns mV mV LSB LSB V V
Vn(i)(eq)(rms)
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Philips Semiconductors
Product specification
10-bit, 3.0 V, up to 25 Msps analog-to-digital interface for CCD cameras
SYMBOL OCCD(max) PARAMETER maximum offset between CCD floating level and CCD dark pixel level CONDITIONS MIN. -80 - TYP.
TDA8787A
MAX. +80
UNIT mV
Digital-to-Analog Converter (OFDOUT DAC) RL = 1 M VOFDOUT(p-p) additional 8-bit control DAC (OFD) output voltage (peak-to-peak value) VOFDOUT TCOFD ZOFDOUT IOFDOUT DC output voltage OFD output range temperature coefficient OFD output impedance OFD output drive current static IOH = -1 mA IOL = 1 mA 0.5 V < VOZ < VCCO VCCO = 3.0 V VCCO = 2.7 V CL fSCLK(max) Note 1. Depending on application environments and especially in case of high gain operation and digital supply with jitter, it is preferable to apply 12 ns or higher CDS pulses. load capacitance Serial interface maximum frequency pin SCLK 5 - - MHz OFD input code 0 OFD input code 255 - 1.0 - V
- - - - -
AGND 250 2000 -
- - - 100
V V ppm/C A
AGND + 1.0 -
Digital outputs (fpix = 18 MHz; CL = 10 pF); see Figs 3 and 4 VOH VOL IOZ th(o) td(o) HIGH-level output voltage LOW-level output voltage OFF-state output current output hold time output delay time VCCO - 0.5 - 0 -20 9 - - - - - - 17 19 - VCCO V 0.5 +20 - 23 25 22 V A ns ns ns pF
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Philips Semiconductors
Product specification
10-bit, 3.0 V, up to 25 Msps analog-to-digital interface for CCD cameras
TDA8787A
handbook, full pagewidth
IN N N+1 t CDS(min) 2.2 V SHP 0.6 V t h(IN-SHP) 0.6 V t CDS(min) 2.2 V SHD 0.6 V t h(IN-SHD) t CLKH 2.2 V CLK 0.6 V t d(SHD-CLK) 0.6 V 0.6 V 0.6 V N+2 N+3
DATA
50%
N-1
N
t h(o) 2.2 V BLK 0.6 V t d(o)
FCE337
t su(BLK-CLK)
Fig.3 Pixel frequency timing diagram with active HIGH-level polarities.
2000 Nov 14
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Philips Semiconductors
Product specification
10-bit, 3.0 V, up to 25 Msps analog-to-digital interface for CCD cameras
TDA8787A
handbook, full pagewidth
IN N N+1 N+2 N+3
2.2 V SHP 0.6 V t h(IN-SHP) 2.2 V SHD 0.6 V t h(IN-SHD) 2.2 V CLK 0.6 V t CLKL t d(SHD-CLK) t CDS(min) 2.2 V 0.6 V t CDS(min) 2.2 V 0.6 V
DATA
50%
N-1
N
t h(o) 2.2 V BLK 0.6 V t d(o)
FCE328
t su(BLK-CLK)
Fig.4 Pixel frequency timing diagram with active LOW-level polarities.
2000 Nov 14
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Philips Semiconductors
Product specification
10-bit, 3.0 V, up to 25 Msps analog-to-digital interface for CCD cameras
TDA8787A
handbook, full pagewidth
FCE332
1.0 VOFDOUT (V)
0 0 OFD control DAC input code 255
Fig.5 DAC output voltage output as a function of DAC input code.
handbook, full pagewidth
4 pixels(1) CLPOB WINDOW PGA output VIDEO OPTICAL BLACK HORIZONTAL FLYBACK DUMMY VIDEO
CLPOB (active HIGH)
BLK (active HIGH) BLK window
FCE333
(1) In case the number of clamp pixels is limited to 18 x (tW(clamp)); otherwise this timing interval can be smaller.
Fig.6 Line frequency timing diagram.
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Philips Semiconductors
Product specification
10-bit, 3.0 V, up to 25 Msps analog-to-digital interface for CCD cameras
TDA8787A
42 Total gain (dB) 36 30 24 18 12 6
FCE327
0
0
64
128
192
256 320 383 PGA input code
ADC input range is 1 Vpp.
Fig.7 Total gain as a function of PGA input code.
handbook, halfpage
6
FCE329
Ntot(rms) (LSB)
5
4
3
2
1
0 0 64 128 192 256 320 383 PGA input code
Noise measurement at ADC outputs; coupling capacitor at input is grounded, so only noise contribution of the front-end is evaluated. Front-end works at 18 Mpixels with line of 1024 pixels whose first 40 are used to run CLPOB and the last 40 for CLPDM. Data at the ADC outputs are measured during the other pixels. As a result of this, the standard deviation of the codes statistic is computed, resulting in the noise.
Fig.8 Typical total noise performance as a function of PGA gain.
2000 Nov 14
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Philips Semiconductors
Product specification
10-bit, 3.0 V, up to 25 Msps analog-to-digital interface for CCD cameras
TDA8787A
handbook, full pagewidth
SDATA
SHIFT REGISTER
SD0 SD1 SD2 SD3 SD4 SD5 SD6 SD7 SD8 SD9 A0 A1
SCLK LSB 10 SEN MSB LATCH SELECTION
8
9
7
6 CONTROL PULSE POLARITY LATCHES VSYNC control pulses polarity settings
OFDOUT DAC LATCHES
PGA GAIN LATCHES
ADC CLAMP LATCHES
FLIP-FLOP
FLIP-FLOP
FLIP-FLOP
8-bit DAC
PGA control
ADC clamp control
FCE334
Fig.9 Serial interface block diagram.
handbook, full pagewidth
t su2 MSB t hd4 SD8 SD7 SD6 SD5 SD4 SD3 SD2 SD1 LSB SD0
SDATA
A1
A0
SD9
SCLK
SEN t su1 t su3 t hd3
FCE335
tsu1 = tsu2 = tsu3 = 10 ns (minimum); thd3 = thd4 = 10 ns (minimum).
Fig.10 Loading sequence of control input data via the serial interface.
2000 Nov 14
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Philips Semiconductors
Product specification
10-bit, 3.0 V, up to 25 Msps analog-to-digital interface for CCD cameras
Table 1 Serial interface programming; see Figs 9 and 10 ADDRESS BITS DATA BITS SD9 TO SD0 A1 0 0 1 1 Table 2 A0 0 1 0 1 Polarity settings PIN 47 and 48 40 12 (connected to ground) 13 11 24 SERIAL CONTROL BIT(1) SD0 SD1 SD2 SD3 SD5 SD6
TDA8787A
PGA gain control (bits SD8 to SD0); bit SD9 should be set to logic 0 DAC OFDOUT output control (bits SD7 to SD0); bits SD8 and SD9 should be set to logic 0 ADC clamp reference control (SD6 to SD0); from code 0 to 127; bits SD7, SD8 and SD9 should be set to logic 0 control pulses polarity settings (pins SHP, SHD, CLPDM, CLPOB, BLK and CLK)
SYMBOL SHP and SHD CLK CLPDM CLPOB BLK VSYNC Note 1. Bit SD4 is not used. Table 3
ACTIVE EDGE OR LEVEL 1 = HIGH; 0 = LOW 1 = HIGH; 0 = LOW always 0 = LOW 1 = HIGH; 0 = LOW 1 = HIGH; 0 = LOW 0 = rising; 1 = falling
Standby mode selection; pin STDBY ADC DIGITAL OUTPUTS; PINS D9 TO D0 logic state LOW active Output enable (OE) pin 37 ADC DIGITAL OUTPUTS; PINS D9 TO D0 active, binary high impedance ICCA + ICCO + ICCD (typical) 1.5 mA 64 mA
STDBY 1 0 Table 4
OE 0 1
2000 Nov 14
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Philips Semiconductors
Product specification
10-bit, 3.0 V, up to 25 Msps analog-to-digital interface for CCD cameras
APPLICATION INFORMATION Power and grounding recommendations When designing a printed-circuit board for applications such as PC cameras, surveillance cameras, camcorders and digital still cameras, care should be taken to minimize the noise. For the front-end integrated circuit, the basic rules of printed-circuit board design and implementation of analog components (such as additional operational amplifiers) must be respected, particularly with respect to power and ground connections. The following additional recommendation is given for the CDS input pin(s) which is /are internally connected to the programmable gain amplifier. The connections between the CCD interface and CDS input should be as short as possible and a ground ring protection around these connections can be beneficial. Separate analog and digital supplies provide the best solution. If this is not possible to do this on the board then the analog supply pins must be decoupled effectively from the digital supply pins. If the same power supply and ground are used for all the pins then the decoupling capacitors must be placed as close as possible to the IC package.
TDA8787A
In order to minimize the noise due to package and die parasitics in a two-ground system, the following measures must be implemented: * All the analog and digital supply pins must be decoupled to the analog ground plane. Only the ground pin associated with the digital outputs must be connected to the digital ground plane. All the other ground pins should be connected to the analog ground plane. The analog and digital ground planes must be connected together at one point as close as possible to the ground pin associated with the digital outputs. * The digital output pins and their associated lines should be shielded by the digital ground plane which can then be used as a return path for digital signals.
2000 Nov 14
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Philips Semiconductors
Product specification
10-bit, 3.0 V, up to 25 Msps analog-to-digital interface for CCD cameras
Application diagram
TDA8787A
handbook, full pagewidth
VCCA 100 nF 1 F
(2) (2)
VCCD 100 nF
VCCD OPGAC AGND5 DGND2 AGND3 DCLPC VCCD2 VCCA3 OPGA
CCD SHD SHP
(2)
CLK
1 F VCCD VCCD3 1 F DGND3 AGND4 IN 100 nF AGND1 VCCA1 CPCDS1 1 F 1 F CPCDS2 OFDOUT STDBY BLK CLPDM 1 2 3 4 5 6 7 8 9 10 11 12
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 OGND VCCO 100 nF VCCD
VCCA
TDA8787AHL
30 29 28 27 26 25 13 14 15 16 17 18 19 20 21 22 23 24 CLPOB AGND2 VCCA2 VCCD1 DGND1 SDATA SCLK SEN VSYNC TEST1 TEST2 TEST3
VCCD
OE
(1)
serial interface 100 nF VCCA 100 nF VCCD
FCE336
(1) Pins SEN and VSYNC should be interconnected when no vertical synchronization signal is available, while control pin VSYNC should be programmed by serial interface as LOW-level active. (2) The timing of the signals on pins IN, SHD and SHP has to comply with the hold times th(IN-SHP) and th(IN-SHD) (see Fig.3).
Fig.11 Application diagram.
2000 Nov 14
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Philips Semiconductors
Product specification
10-bit, 3.0 V, up to 25 Msps analog-to-digital interface for CCD cameras
PACKAGE OUTLINE LQFP48: plastic low profile quad flat package; 48 leads; body 7 x 7 x 1.4 mm
TDA8787A
SOT313-2
c
y X
36 37
25 24 ZE
A
e
E HE
A A2
A1
(A 3) Lp L detail X
wM pin 1 index 48 1 12 ZD bp D HD wM B vM B vM A 13 bp
e
0
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT313-2 REFERENCES IEC 136E05 JEDEC MS-026 EIAJ EUROPEAN PROJECTION A max. 1.60 A1 0.20 0.05 A2 1.45 1.35 A3 0.25 bp 0.27 0.17 c 0.18 0.12 D (1) 7.1 6.9 E (1) 7.1 6.9 e 0.5 HD 9.15 8.85 HE 9.15 8.85 L 1.0 Lp 0.75 0.45 v 0.2 w 0.12 y 0.1 Z D (1) Z E (1) 0.95 0.55 0.95 0.55 7 0o
o
ISSUE DATE 99-12-27 00-01-19
2000 Nov 14
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Philips Semiconductors
Product specification
10-bit, 3.0 V, up to 25 Msps analog-to-digital interface for CCD cameras
SOLDERING Introduction to soldering surface mount packages This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "Data Handbook IC26; Integrated Circuit Packages" (document order number 9398 652 90011). There is no soldering method that is ideal for all surface mount IC packages. Wave soldering is not always suitable for surface mount ICs, or for printed-circuit boards with high population densities. In these situations reflow soldering is often used. Reflow soldering Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several methods exist for reflowing; for example, infrared/convection heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. Typical reflow peak temperatures range from 215 to 250 C. The top-surface temperature of the packages should preferable be kept below 230 C. Wave soldering Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. To overcome these problems the double-wave soldering method was specifically developed. Manual soldering
TDA8787A
If wave soldering is used the following conditions must be observed for optimal results: * Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. * For packages with leads on two sides and a pitch (e): - larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; - smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves at the downstream end. * For packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications.
Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C.
2000 Nov 14
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Philips Semiconductors
Product specification
10-bit, 3.0 V, up to 25 Msps analog-to-digital interface for CCD cameras
Suitability of surface mount IC packages for wave and reflow soldering methods SOLDERING METHOD PACKAGE WAVE BGA, SQFP PLCC(3), SO, SOJ LQFP, QFP, TQFP SSOP, TSSOP, VSO Notes not suitable suitable(2) recommended(3)(4) recommended(5) suitable not not suitable suitable suitable suitable suitable HLQFP, HSQFP, HSOP, HTSSOP, SMS not
TDA8787A
REFLOW(1)
1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the "Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods". 2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink (at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version). 3. If wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. 4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
2000 Nov 14
21
Philips Semiconductors
Product specification
10-bit, 3.0 V, up to 25 Msps analog-to-digital interface for CCD cameras
DATA SHEET STATUS DATA SHEET STATUS Objective specification PRODUCT STATUS Development DEFINITIONS (1)
TDA8787A
This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice. This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product.
Preliminary specification
Qualification
Product specification
Production
Note 1. Please consult the most recently issued data sheet before initiating or completing a design. DEFINITIONS Short-form specification The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. DISCLAIMERS Life support applications These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.
2000 Nov 14
22
Philips Semiconductors
Product specification
10-bit, 3.0 V, up to 25 Msps analog-to-digital interface for CCD cameras
NOTES
TDA8787A
2000 Nov 14
23
Philips Semiconductors - a worldwide company
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For all other countries apply to: Philips Semiconductors, Marketing Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 (c) Philips Electronics N.V. 2000
Internet: http://www.semiconductors.philips.com
SCA 70
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
753504/03/pp24
Date of release: 2000
Nov 14
Document order number:
9397 750 07755

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