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SUMMIT
MICROELECTRONICS, Inc. Highly Programmble Voltage Supervisory Circuit
SMS44
NOTE: THIS PRODUCT HAS REACHED END OF LIFE
FEATURES
! Operational from any of four Voltage Monitoring Inputs ! Programmability allows monitoring any voltage between 0.9V and 6.0V with NO external components ! Programmable Watchdog Timer ! Programmable LongdogTM Timer ! Programmable Reset Pulse Width ! Programmable Power-up sequencing ! Programmable Nonvolatile Combinatorial Logic for generation of reset and interrupt outputs ! Fault Status Register
INTRODUCTION
The SMS44 is a highly programmable voltage supervisory circuit designed specifically for advanced systems needing to monitor multiple voltages. The SMS44 can monitor four separate voltages without the need of any external voltage divider circuitry The SMS44 watchdog timer has a user programmable timeout period and it can be placed in an idle mode for system initialization or system debug. All of the functions are user accessible through an industry standard 2-wire serial interface.
FUNCTIONAL BLOCK DIAGRAM
CONFIGURATION REGISTER
11 RESET#
MR# 1 V0 16
NV DAC REF + - RESET IRQ PROGRAMMABLE RESET PULSE GENERATOR 4 PUP#1 5
V1 2
NV DAC REF + - IRQ RESET PROGRAMMABLE LONGDOG TIMER
PROGRAMMABLE POWER SEQUENCING
PUP#2
13 PUP#3
V2
3 NV DAC REF RESET PROGRAMMABLE WATCHDOG TIMER
+ -
SERIAL BUS CONTROL LOGIC
9 SDA 10 SCL 7 A2 6
A1
IRQ
V3 14
NV DAC REF + - RESET IRQ 12 IRQ# 15 WLDI CONFIGURATION REGISTER 8 4K-BIT NV MEMORY
GND
2047 BD 1.0
(c)SUMMIT MICROELECTRONICS, Inc., 2000 * 300 Orchard City Dr., Suite 131 * Campbell, CA 95008 * Phone 408-378-6461 * FAX 408-378-6586 * www.summitmicro.com
Characteristics subject to change without notice 2047 2.3 10/23/00 EOL 12/16/05
1
SMS44
PIN CONFIGURATION
16-Pin SOIC or 16-Pin SSOP
PIN NAMES
Pin 1 2
V0 WLDI V3 PUP#3 IRQ# RESET# SCL SDA
Name MR# V1 V2 PUP#1 PUP#2 A1 A2 GND SDA SCL RESET# IRQ# PUP#3 V3 WLDI V0
Function Manual reset input Voltage supply and monitor input Voltage supply and monitor input Power up permitted output Power up permitted output Address input Address input Power supply return Serial data I/O Serial data clock Reset out Interrupt out Power up permitted output Voltage supply and monitor input Watchdog/longdog timer interrupt Voltage supply and monitor input
2047 Pins Table 2.0
MR# V1 V2 PUP#1 PUP#2 A1 A2 GND
1 2 3 4 5 6 7 8
16 15 14 13 12 11 10 9
3 4 5 6 7 8 9 10 11 12 13 14 15 16
2047 T PCon 2.0
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SMS44
ABSOLUTE MAXIMUM RATINGS*
Temperature Under Bias ....................... -55C to 125C Storage Temperature ............................ -65C to 150C Lead Solder Temperature (10 secs) ................... 300 C Terminal Voltage with Respect to GND: V0, V1, V2, and V3 ........... -0.3V to 6.0V All Others ........................ -0.3V to 6.0V *COMMENT
Stresses beyond the listed Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions outside those listed in the operational sections of this specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability.
DC OPERATING CHARACTERISTICS
(Over Recommended Operating Conditions; Voltages are relative to GND)
Symbol Parameter Notes 1V min. refers to a valid reset output being generated VCC Operating supply voltage Memory read/write operations: at least one of the V inputs must be at or above VCC min. 3.6V < VCC 5.5V ICC Supply current 3.6V VCC Configuration register or memory access VPTH Range VPTH VHYST Programmable threshold range Programmable threshold VRST hysteresis RESET# low voltage output VOL IRQ# low voltage output ISINK = 1.2mA, VCC = VRST min. ISINK = 1.2mA, VCC 2.7V ISINK = 1.2mA, VCC = VRST min. ISINK = 200A, VCC = 1.2V RTO1 0 tPRTO Programmable reset pulse width 0 1 1 tDRST V in to RESET# delay 100mV overdrive RTO0 0 1 0 1 20 35 65 130 25 50 100 200 20 30 65 135 270 s
2047 Elect TableA 2.1
Min. 1.0 2.7
Typ.
Max. 5.5 5.5
Unit V V A A mA V mV mV
25 25
50 50 2
Reset threshold voltage range V0 to V3 (20mV increments)
0.9 -10 VPTH 50
6.0 10
0.3 0.3 0.3 0.3
V V V V
msec
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SMS44
Symbol
Parameter WD2 0 0 Programmable watchdog timer period
Notes WD1 0 1 0 0 1 1 LD1 0 WD0 0 1 0 1 0 1 LD0 0 1 0 1 PUP#X-0 0 1 0 1
Min.
Typ.
Max.
Unit
OFF 280 560 1120 2240 4480 400 800 1600 3200 6400 520 1040 2080 4160 8320 ms
tPWDTO
1 1 1 1
OFF 1120 2240 4480 1600 3200 6400 2080 4160 8320 ms
tPLDTO
Programmable longdog timer period
0 1 1 PUP#X-1 0
OFF 25 50 100 100 50 100 0.6 0.7 x VCC A ns ns V V
2047 Elect TableB 2.0
tPDLYX
Programmable delay from VPTH to PUP# out
0 1 1
ms
IMR TMR TDMRRST VIL VIH
MR# pullup current MR# input pulse width Delay from MR# low to RESET# low MR# input threshold
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SMS44
PIN DESCRIPTIONS
V0 through V3 These inputs are used as the voltage monitor inputs and as the voltage supply for the SMS44. Internally they are diode ORed and the input with the highest voltage potential will be the default supply voltage. The RESET# output will be true if any one of the four inputs is above 1V. However, for full device operation at least one of the inputs must be at 2.7V or higher. The sensing threshold for each input is independently programmable in 20mV increments from 0.9V to 6.0V. Also, the occurrence of an under- or over-voltage condition that is detected as a result of the threshold setting can be used to generate subsequent action(s), such as RESET# or IRQ#. The programmable nature of the threshold voltage eliminates the need for external voltage divider networks. PUP#1, PUP#2, PUP#3 These are the power-up permitted outputs when the SMS44 is programmed to provide the sequencing of LDOs or DC to DC converters. Each delay is independently enabled and programmable for its duration (configuration register 7). If all PUP# outputs are enabled the sequence would be as follows: V0 above threshold then delay to PUP#1 turning on; V1 above threshold then delay to PUP#2 turning on; V2 above threshold then delay to PUP#3 turning on to end the sequence. MR# The manual reset input always generates a RESET# output whenever it is driven low. The duration of the RESET# output pulse will be initiated when MR# goes low and it will stay low for the duration of MR# low plus the programmed reset timeout period (tPRTO). If MR# is brought low during a power-on-sequence of the PUP#s the sequence will be halted for the reset duration, and will then resume from the point at which it was interrupted. If MR# is low the configuration registers can be read or written to so long as at least one of the VX inputs is 2.7V. RESET# The reset output is an active low open drain output. It will be driven low whenever the MR# input is low or whenever an enabled under-voltage or over-voltage condition exists, or when a longdog timer expiration exists. The four voltage monitor inputs are always functioning, but their ability to generate a reset is programmable (configuration register 4). Refer to figures 1 and 2 for a detailed illustration of the relationship between MR#, IRQ#, RESET# and the VIN levels.
SUMMIT MICROELECTRONICS, Inc.
MR# tDMRRST RESET# tPRTO tPRTO
2047 Fig01 1.0
Figure 1. RESET# Timing with MR# IRQ# The interrupt output is an active low open-drain output. It will be driven low whenever the watchdog timer times out or whenever an enabled under-voltage or over-voltage condition on a V input exists (configuration register 6).
V0 -- V 3
VPTH
VRST
tPRTO RESET#
tD
IRQ#
2047 Fig02 1.1
Figure 2. RESET# Timing with IRQ# WLDI Watchdog and longdog timer interrupt input. A low to high transition on the WLDI input will clear both the watchdog and longdog timers, effectively starting a new timeout period. If WLDI is stuck low and no low-to-high transition is received within the programmed tPWDTO period (programmed watch dog timeout) IRQ# will be driven low. If a transition is still not received within the programmed tPLDTO period (programmed longdog timeout) RESET# will be driven low. Refer to Figure 3 for a detailed illustration. Holding WLDI high will block interrupts from occurring but will not block the longdog from timing out and generating a reset. Refer to Figure 4 for a detailed illustration of the relationship between IRQ#, RESET#, and WLDI.
2047 2.3 10/23/00
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SMS44
tPWDTO t0 IRQ#
t0
t0
t0
t0
A1, A2 A1 and A2 are the address inputs. When addressing the SMS44 memory or configuration registers the address inputs distinguish which one of four possible devices sharing the common bus is being addressed. SDA SDA is the serial data input/output pin. It should be tied to VCC through a pull-up resistor. SCL SCL is the serial clock input. It should be tied to VCC through a pull-up resistor.
RESET# tPLDTO WLDI tPRTO tPLDTO
2047 Fig03 1.0
Figure 3. Watchdog, Longdog and WLDI Timing
t0 IRQ# tPRTO RESET# tPLDTO WLDI t0 t0
2047 Fig04 1.0
Figure 4. Watchdog, Longdog and WLDI Timing
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SMS44
DEVICE OPERATION
SUPPLY AND MONITOR FUNCTIONS
The V0, V1, V2 and V3 inputs are internally diode-ORed so that any one of the four can act as the device supply. The RESET# output will be guaranteed true so long as one of the four pins is at or above 1V. Note: for performing a memory operation (read or write) and to have the ability to change configuration register contents at least one supply input must be above 2.7V. If sequencing is enabled, the designer must insure V0 is the primary supply and is the first to become active. Associated with each input is a comparator with a programmable threshold for detection of under-voltage conditions on any of the four supply inputs. The threshold can be programmed in 20mV increments anywhere within the range of 0.9V to 6.0V. Configuration registers 0, 1, 2, and 3 adjust the thresholds for V0, V1, V2 and V3 respectively. If the value contained in the register is all zeroes, the corresponding threshold will be 0.9V. If the contents were 05HEX the threshold would then be 1.0V [0.9V + (5 x 0.02V)]. All four registers are configured as 8-bit registers.
7 MSB V3 6 V2 5 V1 4 V0 3 V3 2 V2 1 V1 0 LSB V0
RESET Trigger Source
IRQ Trigger Source
2047 Table01 1.0
Table 1. Configuration Register 4 program these options. The high order four bits of configuration register 5 are read only, and their state indicates the sources of interrupts. Whenever an interrupt is generated the status of the V inputs will be recorded in the status register. The status will remain in the register until the device is powered-down
3 MSB V3 Writing a 0 enables undervoltage detection for the selected V input Writing a 1 enables overvoltage detection for the selected V input 0 0 LSB V0 0
2 V2 0
1 V1 0
1
1
1
1
RESET AND IRQ FUNCTIONS
Both the reset and interrupt outputs have four programmable sources for activation. Configuration register 4 is used for selecting the activation source, which can be any combination of V0, V1, V2 and V3. A monitor input can only be programmed to activate on either an under-voltage or over-voltage condition, but not both conditions. The RESET# output has two hardwired sources for activation: the MR# input, and the expiration of the Longdog timer. RESET# will remain active so long as MR# is low, and will continue driving the RESET# output for tPRTO (programmable reset time out) after MR# returns high. The MR# input cannot be bypassed or disabled. The Longdog timer can be bypassed by programming it to the off or idle mode. The watchdog is the sole hardwired source for driving the IRQ# output low. It can effectively be bypassed by programming it to the off or idle mode. Refer to Figures 1, 2, 3 and 4 for a detailed illustration of the relationships among the affected signals. The SMS44 also provides the option of the monitors triggering on either an under-voltage or over-voltage condition. The low-order four bits of configuration register 5
2047 Table02 1.0
Table 2. Configuration Register 5 or another interrupt occurs that overwrites the previous status.
7 MSB V3 0 1
6 V2 0 1
5 V1 0 1
4 LSB V0 0 1 Reading a 1 indicates the source of the interrupt
2047 Table03 1.0
Table 3. Configuration Register 5 If an interrupt occurs and no bits are set the default assumption must be the watchdog generated the interrupt.
WATCHDOG AND LONGDOG TIMERS
The SMS44 contains two timers that can be programmed independently. The Watchdog is intended to be of shorter duration and will generate an interrupt if it times out. The
SUMMIT MICROELECTRONICS, Inc.
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SMS44
Longdog timer will generally be programmed to be of longer duration than the watchdog and it will generate a reset if it times out. Both timers are cleared by a low to high transition on WLDI and they both start simultaneously. If the watchdog should timeout the device status will be recorded in the status register. If the Longdog times out RESET# will drive low either until a WLDI clear is received or until tPRTO (whichever occurs first), at which time it will return high. Refer to Figures 3 and 4 illustrating the action of RESET# and IRQ# with respect to the Watchdog and Longdog timers and the WLDI input. If WLDI is held low the timers will free-run generating a series of interrupts and resets. If WLDI is held high the interrupt (watchdog) output will be disabled and only the reset (Longdog) output will be active.
When the Longdog times out, a reset will be generated. When reset returns high (after tPRTO or after a WLDI strobe) both timers are reset to time zero. Therefore, if the Longdog tPLDTO is equal to or shorter than the watchdog tPWDTO, the reset will effectively clear the interrupt before it can drive the output low.
7 MSB
6
5
4
3
2
1
0 LSB
Address Select Lock AS0 x x 0 0 1 x x
PUP# State PUP#3 1 0 PUP#2 1 0 PUP#1 1 0
Device type address 1010, responds only to biased A2 & A1 combinations Device type address 1011, responds only to biased A2 & A1 combinations Configuration read/write enabled Configuration read/write locked out
2047 Table06 1.0
7 MSB x x x x x x x x 0 1
6
5
4
3
2 WD2
1
0 LSB
1
SEQ RTO1 RTO0 LD1 LD0 x x x x 0 0 1 1 x x x x x x 0 1 0 1 x x 0 0 1 1 x x x x x x 0 1 0 1 x x x x x x
WD1 WD0 1600ms 3200ms 6400ms
Table 6. Configuration Register 7 Register 6 is also used to set the programmable reset timeout period (tPRTO) and to select the sequence option.
Bit 1 0 0 1 1 Bit 0 0 1 0 1 tPDLYX 0ms (no) Delay 25ms Delay 50ms Delay 100ms Delay
2047 Table07 1.0
Longdog Off
tPRTO = 25ms tPRTO = 50ms tPRTO = 100ms tPRTO = 200ms Sequence On Sequence Off
2047 Table04 1.0
Table 7. PUP Delays Sequence Delay Programming The sequence delays are programmed in register 7. Bit 7 of register 6, must be set to a "0" in order to enable the sequencing of the PUP# outputs. Sequencing will not commence until V0 is above its programmed threshold. Each PUP# (-3, -2 and -1) is delayed according to the states of its Bit 1 and Bit 0 as indicated in Table 7. Refer to Figures 5 and 6 for the detailed timing relationship of the programmable power-on sequencing.
Table 4. Configuration Register 6 7 MSB 0 LSB 0 1 0 1 0 1
6
5
4
3 LD0
2
1
SEQ RTO1 RTO0 LD1
WD2 WD1 WD0 0 0 1 1 1 1 0 1 0 0 1 1
OFF 400ms 800ms 1600ms 3200ms 6400ms
2047 Table05 1.0
Table 5. Configuration Register 6
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2047 2.3 10/23/00 SUMMIT MICROELECTRONICS, Inc.
SMS44
V0 VPTH0
tPRTO RESET# tPDLY1 PUP1#
V1
VPTH1
tPDLY2 PUP2#
V2
VPTH2
tPDLY3 PUP3#
V3
VPTH3
IRQ#
2047 Fig05 1.0
Figure 5. VX Input and PUP# Sequence
VPTH0 50ms
V0
PUP1#
V1
"Figure 6. Timing with Register Contents 22HEX
PUP2#
V2
VPTH2 50ms
PUP3#
2047 Fig06 1.0
SUMMIT MICROELECTRONICS, Inc. 2047 2.3 10/23/00
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SMS44
Sequencing Enabled
The delay from VPTH0 until PUP#1 low is tPDLY1. There is a similar tPDLYX delay for V1 to PUP#2 and V2 to PUP#3. They are programmed in register 7. See Figure 5. Sequencing will always occur as indicated in the flow chart.
V0 >VPTH? Yes tPDLY1
No
MEMORY OPERATION
Data for the configuration registers and the memory array are read and written via an industry standard two-wire interface. The bus was designed for two-way, two-line serial communication between different integrated circuits. The two lines are a serial data line (SDA) and a serial clock line (SCL). The SDA line must be connected to a positive supply by a pull-up resistor, located somewhere on the bus. See Memory Operating Characteristics: Table 8 and Figure 8.
Turn On PUP#1
V1 >VPTH? Yes tPDLY2
No
Turn On PUP#2
V2 >VPTH? Yes tPDLY3
No
Turn On PUP#3
2047 Fig07 2.1
Figure 7. Sequence Flow Chart
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SMS44
Input Data Protocol The protocol defines any device that sends data onto the bus as a "transmitter" and any device that receives data as a "receiver." The device controlling data transmission is called the "master" and the controlled device is called the "slave." In all cases the SMS44 will be a "slave" device, since it never initiates any data transfers.
One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during clock high time, because changes on the data line while SCL is high will be interpreted as start or stop condition.
Symbol fSCL tLOW tHIGH tBUF tSU:STA tHD:STA tSU:STO tAA tDH tR tF tSU:DAT tHD:DAT TI tWR
Parameter SCL clock frequency Clock low period Clock high period Bus free time Start condition setup time Start condition hold time Stop condition setup time Clock edge to valid output Data Out hold time SCL and SDA rise time SCL and SDA fall time Data In setup time Data In hold time Noise filter SCL and SDA Write cycle time
Conditions
Min. 0 4.7 4.0
Max. 100
Units kHz s s s s s s
Before new transmission
4.7 4.7 4.0 4.7
SCL low to valid SDA (cycle n) SCL low (cycle n+1) to SDA change
0.3 0.3
3.5
s s
1000 300 250 0 Noise suppression 100 5
ns ns ns ns ns ms
2047 Table08 2.2
Table 8. Memory Operating Characteristics
tR tF tHIGH tLOW
SCL
tSU:STA tHD:STA tHD:DAT tSU:DAT tSU:STO
tBUF
SDA In
tAA
tDH
SDA Out
2047 Fig08 2.1
Figure 8. Memory Operating Characteristics
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SMS44
START and STOP Conditions When both the data and clock lines are HIGH the bus is said to be not busy. A High-to-Low transition on the data line, while the clock is HIGH, is defined as the "START" condition. A Low-to-High transition on the data line, while the clock is HIGH, is defined as the "STOP" condition. See Figure 9.
Read/Write Bit The last bit of the data stream defines the operation to be performed. When set to "1" a read operation is selected; when set to "0" a write operation is selected.
7 MSB 6 5 4 3 2 1 0 LSB R/W x
Address Bits
START Condition SCL STOP Condition
Device Type SMS44 1 1 1
2047 Fig09 1.0
Bus x 1 0 1 x
MSB x
0 0 0
0 1 1
Configuration Register Memory (default) Alternate Memory
2047 Table09 1.0
SDA In
Table 9. Slave Addresses
Figure 9. START and STOP Conditions
WRITE OPERATIONS
The SMS44 allows two types of write operations: byte write and page write. A byte write operation writes a single byte during the nonvolatile write period (tWR). The page write operation, limited to the memory array, allows up to 16 bytes in the same page to be written during tWR. Byte Write After the slave address is sent (to identify the slave device and select either a read or write operation), a second byte is transmitted which contains the low order 8 bit address of any one of the 512 words in the array. Upon receipt of the word address the SMS44 responds with an ACKnowledge. After receiving the next byte of data it again responds with an ACKnowledge. The master then terminates the transfer by generating a STOP condition, at which time the SMS44 begins the internal write cycle. While the internal write cycle is in progress the SMS44 inputs are disabled and the device will not respond to any requests from the master. Page Write (memory only) The SMS44 is capable of a 16-byte page write operation. It is initiated in the same manner as the byte-write operation, but instead of terminating the write cycle after the first data word the master can transmit up to 15 more bytes of data. After the receipt of each byte the SMS44 will respond with an ACKnowledge. The SMS44 automatically increments the address for subsequent data words. After the receipt of each word, the low order address bits are internally incremented by one.
Acknowledge (ACK) Acknowledge is a software convention used to indicate successful data transfers. The transmitting device, either the master or the slave, will release the bus after transmitting eight bits. During the ninth clock cycle the receiver will pull the SDA line low to ACKnowledge that it received the eight bits of data. The SMS44 will respond with an ACKnowledge after recognition of a START condition and its slave address byte. If both the device and a write operation are selected the SMS44 will respond with an ACKnowledge after the receipt of each subsequent 8-bit word. In the READ mode the SMS44 transmits eight bits of data, then releases the SDA line, and monitors the line for an ACKnowledge signal. If an ACKnowledge is detected and no STOP condition is generated by the master, the SMS44 will continue to transmit data. If an ACKnowledge is not detected the SMS44 will terminate further data transmissions and awaits a STOP condition before returning to the standby power mode. Device Addressing Following a start condition the master must output the address of the slave it is accessing. The most significant four bits of the slave address are the device type identifier/ address. For the SMS44 the default is 1010BIN. The next two bits are the Bus Address. The next bit (the 7th) is the MSB of the memory address.
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SMS44
Master SDA Slave
S T A R Device Type Bus T Address Address
Typical Write Operation (Standard memory device type)
R A AA A AA AA 7 65 4 32 10 A C K A C K DDDDDDDD 76543210 A C K
S T O P
1010AAA/ 218W
BB
Up to 15 additional bytes can be written before issuing the stop.
Master SDA Slave
S T A R T
Typical Reading Operation (Alternate memory device type) 10 11 A A A / 218W
A C K BB R A A A A AA AA 7 6 5 4 32 10
A C K DDDDDDDD 76543210
A C K
S T O P
The host may continue clocking out data so long as it provides an ACK response after each byte.
Master SDA Slave
S T A R T
Writing Configuration Registers
R W A C K
S T O P DDDDDDDD 76543210 A C K A C K
1 00 1 A A X/
21
BB
CCCCCCCC 76543210
Master SDA Slave
S T A R T
Reading the Configuration Register
X/ 1 00 1 A A 21 BB R W A C K CCCCCCCC 76543210
S T AA CR KT BB
AS CT KO P
1 00 1 A A X / 21 W
A C K
R
DDDDDDDD 76543210
2047 Fig10 2.1
Figure 10. Read and Write Operations The high order bits of the address byte remain constant. Should the master transmit more than 16 bytes, prior to generating the STOP condition, the address counter will "roll over" and the previously written data will be overwritten. As with the byte-write operation, all inputs are disabled during the internal write cycle. Refer to Figure 10 for the address, ACKnowledge, and data transfer sequence.
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SMS44
Acknowledge Polling When the SMS44 is performing an internal WRITE operation it will ignore any new START conditions. Since the device will only return an acknowledge after it accepts the START the part can be continuously queried until an acknowledge is issued, indicating that the internal WRITE cycle is complete. See the flow diagram for the proper sequence of operations for polling.
Write Cycle In Progress
Current Address Read (memory only) The SMS44 contains an internal address counter which maintains the address of the last word accessed, incremented by one. If the last address accessed (either a read or write) was to address location n, the next read operation would access data from address location n+1 and increment the current address pointer. When the SMS44 receives the slave address field with the R/W bit set to "1," it issues an acknowledge and transmits the 8-bit word stored at address location n+1. The current address byte read operation only accesses a single byte of data. The master does not acknowledge the transfer, but does generate a stop condition. At this point, the SMS44 discontinues data transmission. Random Address Read (Register and Memory) Random address read operations allow the master to access any memory location in a random fashion. This operation involves a two-step process. First, the master issues a write command which includes the start condition and the slave address field (with the R/W bit set to WRITE), followed by the address of the word it is to read. This procedure sets the internal address counter of the SMS44 to the desired address. After the word address acknowledge is received by the master it immediately reissues a start condition, followed by another slave address field with the R/W bit set to READ. The SMS44 will respond with an acknowledge and then transmit the 8 data bits stored at the addressed location. At this point the master does not acknowledge the transmission but does generate the stop condition. The SMS44 discontinues data transmission and reverts to its standby power mode. Sequential READ (Memory Only) Sequential reads can be initiated as either a current address READ or random access READ. The first word is transmitted as with the other byte read modes (current address byte READ or random address byte READ); however, the master now responds with an ACKnowledge, indicating that it requires additional data from the SMS44. The SMS44 continues to output data for each ACKnowledge received. The master terminates the sequential READ operation by not responding with an ACKnowledge, and issues a stop condition. During a sequential read operation the internal address counter is automatically incremented with each ACKnowledge signal. For read operations all address bits are incremented, allowing the entire array to be read using a single read command. After a count of the last memory address the address counter will `roll-over' and the memory will continue to output data.
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Issue Start Issue Stop Issue Slave Address and R/W = 0
ACK Returned Yes
No
Next Operation a Write? Yes Issue Address
No
Issue Stop
Proceed With Write
Await Next Command
2047 Fig11 2.1
Figure 11. Write Flow Chart
READ OPERATIONS
Read operations are initiated with the R/W bit of the identification field set to "1." T here are two different read options: 1. Current Address Byte Read, and 2. Random Address Byte Read
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SMS44
PACKAGES
16 PIN SOIC PACKAGE
0.398 - 0.412 (10.109 - 12.465)
0.394 - 0.419 (10.007 - 10.643)
0.291 - 0.299 (7.391 - 7.595) 0.010 - 0.029 (0.254 - 0.737) 0 to 8 typ x45 0.093 - 0.104 (2.362 - 2.642) 0.037 - 0.045 (0.940 - 1.143
0.009 - 0.013 (0.229 - 0.330)
0.016 - 0.050 (0.406 - 1.270)
0.050 (1.270) 0.014 - 0.019 (0.356 - 0.482)
16 Pin SOIC T
0.004 - 0.012 (0.102 - 0.305)
ORDERING INFORMATION SMS44 Base Part Number G Package G = SSOP S = SOIC
2047 Tree 1.0
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SMS44
16 PIN SSOP PACKAGE
0.189 - 0.196 (4.80 - 4.98)
0.230 - 0.244 (5.84 - 6.20) Pin 1
0.002 - 0.007 0.150 - 0.157 (3.81 - 3.99) 11.5 to 18.5 0.008 - 0.010 (0.19 - 0.25) o o 0 to 8 typ (0.05 - 0.18) 0.061 - 0.068 (1.55 - 1.73) 0.055 - 0.061 (1.40 - 1.55)
0.016 - 0.035 (0.41 - 0.89) 0.25 (0.635) 0.008 - 0.012 (0.20 - 0.31)
0.004 - 0.010 (0.12 - 0.25)
NOTICE SUMMIT Microelectronics, Inc. reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. SUMMIT Microelectronics, Inc. assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contained herein reflect representative operating parameters, and may vary depending upon a user's specific application. While the information in this publication has been carefully checked, SUMMIT Microelectronics, Inc. shall not be liable for any damages arising as a result of any error or omission. SUMMIT Microelectronics, Inc. does not recommend the use of any of its products in life support or aviation applications where the failure or malfunction of the product can reasonably be expected to cause any failure of either system or to significantly affect their safety or effectiveness. Products are not authorized for use in such applications unless SUMMIT Microelectronics, Inc. receives written assurances, to its satisfaction, that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; and (c) potential liability of SUMMIT Microelectronics, Inc. is adequately protected under the circumstances. (c) Copyright 2000 SUMMIT Microelectronics, Inc.
I2C is a trademark of Philips Corporation.
16
2047 2.3 10/23/00 EOL 12/16/05 SUMMIT MICROELECTRONICS, Inc.

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