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87C196LA-20 MHz CHMOS 16-bit Microcontroller
Automotive
Advanced Information Datasheet
Product Features
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Up to 20 MHz operation 24 Kbytes of on-chip OTPROM 768 bytes of on-chip register RAM Register-to-register architecture Peripheral transaction server (PTS) with high-speed, microcoded interrupt service routines Six-channel/10-bit A/D with sample and hold High-speed event processor array -- Six capture/compare channels -- Two compare-only channels -- Two 16-bit software timers Full-duplex serial I/O port with dedicated baud-rate generator
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Enhanced full-duplex, synchronous serial I/O port (SSIO) Programmable 8- or 16-bit external bus Selectable clock doubler with programmable clock output signal SFR register that indicates the source of the last reset Design enhancements for EMI reduction Oscillator failure detection circuitry Watchdog timer (WDT) -40 C to +125 C ambient temperature 52-pin PLCC package
Notice: This document contains information on products in the sampling and initial production phases of development. The specifications are subject to change without notice. Verify with your local Intel sales office that you have the latest datasheet before finalizing a design.
Order Number: 272806-003 March 1998
Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The 87C196LA-20 MHz CHMOS 16-bit Microcontroller may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800548-4725 or by visiting Intel's website at http://www.intel.com. Copyright (c) Intel Corporation, 1998 *Third-party brands and names are the property of their respective owners.
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Automotive -- 87C196LA-20 MHz CHMOS 16-bit Microcontroller
Contents
1.0 2.0 3.0 4.0 5.0 6.0 Introduction .................................................................................................................. 5 Nomenclature Overview .......................................................................................... 7 Pinout..............................................................................................................................8 Signals .......................................................................................................................... 11 Address Map .............................................................................................................. 17 Electrical Characteristics......................................................................................18
6.1 6.2 DC Characteristics .............................................................................................. 19 AC Characteristics (Over Specified Operating Conditions) ............................................. 20 6.2.1 Test Condition ........................................................................................ 20 6.2.2 Explanation of AC Symbols.................................................................... 22
7.0
EPROM Specifications ........................................................................................... 25
7.1 7.2 Operating Conditions........................................................................................... 25 EPROM Programming Waveforms ..................................................................... 26
8.0 9.0
A/D Converter Specifications .............................................................................. 27 AC Characteristics - Serial Port - Shift Register Mode.............................29
9.1 9.2 Test Conditions ................................................................................................... 29 Waveform - Serial Port - Shift Register Mode0 ................................................... 29
10.0 11.0 12.0 13.0
Thermal Characteristics ........................................................................................ 30 Design Considerations .......................................................................................... 30 Device Errata..............................................................................................................30 Datasheet Revision History ................................................................................. 30
Figures
1 2 3 4 5 6 7 8 9 10 11 87C196LA Block Diagram ..................................................................................... 6 Product Nomenclature........................................................................................... 7 87C196LA 52-pin Package ................................................................................... 8 System Bus Timing ............................................................................................. 23 External Clock Drive Waveform .......................................................................... 24 AC Testing Input, Output Waveforms.................................................................. 24 Float Waveform ................................................................................................... 24 Slave Programming Mode Data Program Mode with Single Program Pulse ...... 26 Slave Programming Mode in WORD Dump or Data Verify Mode with Auto Increment .................................................................................................... 26 Slave Programming Mode Timing in Data Program Mode with Repeated Program Pulse and Auto Increment .................................................................... 27 Serial Port Waveform - Shift Register Mode ....................................................... 29
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87C196LA-20 MHz CHMOS 16-bit Microcontroller -- Automotive
Tables
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 Description of Product Nomenclature ................................................................... 7 87C196LA 52-pin Package Pin Assignments ....................................................... 9 Pin Assignment Arranged by Functional Categories........................................... 10 Signal Descriptions ............................................................................................. 11 Address Map ....................................................................................................... 17 Absolute Maximum Ratings ................................................................................ 18 Operating Conditions .......................................................................................... 18 DC Characteristics at VCC = 4.5 V to 5.5 V......................................................... 19 AC Characteristics .............................................................................................. 21 AC Timing Symbol Definitions............................................................................. 22 External Clock Drive............................................................................................ 23 AC EPROM Programming Characteristics.......................................................... 25 DC EPROM Programming Characteristics ......................................................... 25 A/D Operating Conditions - Symbol Descriptions ............................................... 28 A/D Operating Conditions - Parameter Descriptions........................................... 28 Serial Port Timing - Shift Register Mode ............................................................. 29 Thermal Characteristics ...................................................................................... 30 Revision History .................................................................................................. 30
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Automotive -- 87C196LA-20 MHz CHMOS 16-bit Microcontroller
1.0
Introduction
The 87C196LA is a high-performance 16-bit microcontroller. The 87C196LA is composed of a high-speed core with the following peripherals: an asynchronous/synchronous serial I/O port (8096 compatible) with a dedicated 16-bit baud-rate generator; an additional synchronous serial I/O port with full duplex master/slave transceivers; a six-channel A/D converter with sample and hold; a flexible timer/counter structure with prescaler, cascading, and quadrature capabilities; six modularized, multiplexed high-speed I/O for capture and compare (called event processor array) with 200 ns resolution and double buffered inputs; and a sophisticated, prioritized interrupt structure with programmable peripheral transaction server (PTS). The clock doubler circuitry and oscillator output signal enable a 4 MHz resonator to achieve the same internal clock speed as a more costly 8 MHz resonator in previous applications. This same circuitry can drive other devices where a separate resonator was required in the past. Another cost-savings feature is the fact that the I/O ports are driven low at reset, avoiding the need for pull-up resistors.
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87C196LA-20 MHz CHMOS 16-bit Microcontroller -- Automotive
Figure 1. 87C196LA Block Diagram
Port 6
Port 0
Watchdog Timer
Enhanced SSIO
A/D Converter
Peripheral Addr Bus (10)
Peripheral Data Bus (16) Port 2
Bus Control
Memory Data Bus (16)
Memory Addr Bus (16)
Bus Controller
AD15:0
SIO
Baud-rate Generator
Bus-Control Interface Unit Queue Microcode Engine
Peripheral Transaction Server Interrupt Controller EPA
6 Capture/ Compare Channels 2 Timers 2 Compare-only Channels
Source (16) Port 1,6 ALU Register RAM 768 Bytes Memory Interface Unit
Destination (16)
OTPROM 24 Kbytes
Two additional capture/compare channels (EPA6 and EPA7) are available as software timers. They are not connected to package pins.
A3417-01
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Automotive -- 87C196LA-20 MHz CHMOS 16-bit Microcontroller
2.0
Nomenclature Overview
Figure 2. Product Nomenclature
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Table 1. Description of Product Nomenclature
Parameter Temperature and Burn-in Options Packaging Options Program-memory Options Process Information Product Family Device Speed Options A N 7 C 196Lx 20 Description Automotive operating temperature range (-40C to 125C ambient) with Intel standard burn-in. PLCC OTPROM CHMOS 8XC196Lx family of products 20 MHz
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A2815-01
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87C196LA-20 MHz CHMOS 16-bit Microcontroller -- Automotive
3.0
Pinout
Figure 3. 87C196LA 52-pin Package
AD14 / P4.6 / PBUS.14 AD13 / P4.5 / PBUS.13 AD12 / P4.4 / PBUS.12 AD11 / P4.3 / PBUS.11 AD10 / P4.2 / PBUS.10 AD9 / P4.1 / PBUS.9 AD8 / P4.0 / PBUS.8 AD7 / P3.7 / PBUS.7 AD6 / P3.6 / PBUS.6 AD5 / P3.5 / PBUS.5 AD4 / P3.4 / PBUS.4 AD3 / P3.3 / PBUS.3 AD2 / P3.2 / PBUS.2
8 9 10 11 12 13 14 15 16 17 18 19 20
7 6 5 4 3 2 1 52 51 50 49 48 47
AD15 / P4.7 / PBUS.15 P5.2 / PLLEN / WR# / WRL# P5.3 / RD# VPP VSS P5.0 / ADV# / ALE VSS1 XTAL1 XTAL2 P6.7 / SD1 P6.6 / SC1 P6.5 / SD0 P6.4 / SC0
AN87C196LA20 View of component as mounted on PC board
46 45 44 43 42 41 40 39 38 37 36 35 34
P6.1 / EPA9 / COMP1 P6.0 / EPA8 / COMP0 P1.0 / EPA0 / T2CLK P1.1 / EPA1 P1.2 / EPA2 / T2DIR P1.3 / EPA3 VREF ANGND P0.7 / ACH7 / PMODE.3 P0.6 / ACH6 / PMODE.2 P0.5 / ACH5 / PMODE.1 P0.4 / ACH4 / PMODE.0 P0.3 / ACH3
AD1 / P3.1 / PBUS.1 AD0 / P3.0 / PBUS.0 RESET# EA# VSS1 VCC P2.0 / TXD / PVER P2.1 / RXD / PALE# P2.2 / EXTINT / PROG# P2.4 / AINC# P2.6 / ONCE / CPVER P2.7 / CLKOUT / PACT# P0.2 / ACH2
21 22 23 24 25 26 27 28 29 30 31 32 33
A3419-03
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Automotive -- 87C196LA-20 MHz CHMOS 16-bit Microcontroller
Table 2. 87C196LA 52-pin Package Pin Assignments
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 VSS1 P5.0 / ADV# / ALE VSS VPP P5.3 / RD# P5.2 / PLLEN / WR# / WRL# AD15 / P4.7 / PBUS.15 AD14 / P4.6 / PBUS.14 AD13 / P4.5 / PBUS.13 AD12 / P4.4 / PBUS.12 AD11 / P4.3 / PBUS.11 AD10 / P4.2 / PBUS.10 AD9 / P4.1 / PBUS.9 AD8 / P4.0 / PBUS.8 AD7 / P3.7 / PBUS.7 AD6 / P3.6 / PBUS.6 AD5 / P3.5 / PBUS.5 AD4 / P3.4 / PBUS.4 Name Pin 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 Name AD3 / P3.3 / PBUS.3 AD2 / P3.2 / PBUS.2 AD1 / P3.1 / PBUS.1 AD0 / P3.0 / PBUS.0 RESET# EA# VSS1 VCC P2.0 / TXD / PVER P2.1 / RXD / PALE# P2.2 / EXTINT / PROG# P2.4 / AINC# P2.6 / ONCE/CPVER P2.7 / CLKOUT / PACT# P0.2 / ACH2 P0.3 / ACH3 P0.4 / ACH4 / PMODE.0 P0.5 / ACH5 / PMODE.1 Pin 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 Name P0.6 / ACH6 / PMODE.2 P0.7 / ACH7 / PMODE.3 ANGND VREF P1.3 / EPA3 P1.2 / EPA2 / T2DIR P1.1 / EPA1 P1.0 / EPA0 / T2CLK P6.0 / EPA8 / COMP0 P6.1 / EPA9 / COMP1 P6.4 / SC0 P6.5 / SD0 P6.6 / SC1 P6.7 / SD1 XTAL2 XTAL1
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87C196LA-20 MHz CHMOS 16-bit Microcontroller -- Automotive
Table 3. Pin Assignment Arranged by Functional Categories
Addr & Data Name AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 Pin 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 Input/Output (Cont'd) Name P2.1 / RXD P2.2 P2.4 P2.6 P2.7 P3.0 P3.1 P3.2 P3.3 P3.4 P3.5 P3.6 P3.7 P4.0 P4.1 P4.2 P4.3 Input/Output Name P0.2 / ACH2 P0.3 / ACH3 P0.4 / ACH4 P0.5 / ACH5 P0.6 / ACH6 P0.7 / ACH7 P1.0 / EPA0 / T2CLK P1.1 / EPA1 P1.2 / EPA2 / T2DIR P1.3 / EPA3 P2.0 / TXD Pin 33 34 35 36 37 38 44 43 42 41 27 P4.4 P4.5 P4.6 P4.7 P5.0 P5.2 P5.3 P6.0 / EPA8 / COMP0 P6.1 / EPA9 / COMP1 P6.4 / SC0 P6.5 / SD0 P6.6 / SC1 P6.7 / SD1 Pin 28 29 30 31 32 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 2 6 5 45 46 47 48 49 50 Program Control Name AINC# CPVER PACT# PALE# PBUS.0 PBUS.1 PBUS.2 PBUS.3 PBUS.4 PBUS.5 PBUS.6 PBUS.7 PBUS.8 PBUS.9 PBUS.10 PBUS.11 PBUS.12 PBUS.13 PBUS.14 PBUS.15 PMODE.0 PMODE.1 PMODE.2 PMODE.3 PROG# PVER Pin 30 31 32 28 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 35 36 37 38 29 27 Power & Ground Name ANGND VCC VPP VREF VSS VSS1 VSS1 Pin 39 26 4 40 3 1 25 Bus Cont & Status Name ADV# / ALE CLKOUT RD# WR# / WRL# Pin 2 32 5 6 EA# EXTINT PLLEN RESET# XTAL1 XTAL2 Processor Control Name Pin 24 29 6 23 52 51
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4.0
Signals
Table 4. Signal Descriptions (Sheet 1 of 6)
Name Type Analog Channels These signals are analog inputs to the A/D converter. The A/D inputs share package pins with port 0. These pins may individually be used as analog inputs (ACHx) or digital inputs (P0.y). While it is possible for the pins to function simultaneously as analog and digital inputs, this is not recommended because reading port 0 while a conversion is in process can produce unreliable conversion results. The ANGND and VREF pins must be connected for the A/D converter and port 0 to function. ACH7:2 share package pins with the following signals: ACH2/P0.2, ACH3/P0.3, ACH4/P0.4/PMODE.0, ACH5/P0.5/PMODE.1, ACH6/P0.6/PMODE.2, and ACH7/ P0.7/PMODE.3. Address/Data Lines These pins provide a multiplexed address and data bus. During the address phase of the bus cycle, address bits 0-15 are presented on the bus and can be latched using ALE or ADV#. During the data phase, 8- or 16-bit data is transferred. AD7:0 share package pins with P3.7:0 and PBUS.7:0. AD15:8 share package pins with P4.7:0 and PBUS.15:8. Address Valid This active-low output signal is asserted only during external memory accesses. ADV# indicates that valid address information is available on the system address/ data bus. The signal remains low while a valid bus cycle is in progress and is returned high as soon as the bus cycle completes. An external latch can use this signal to demultiplex the address from the address/ data bus. A decoder can also use this signal to generate chip selects for external memory. ADV# shares a package pin with P5.0 and ALE. Auto Increment During slave programming, this active-low input enables the auto-increment feature. (Auto increment allows reading or writing of sequential OTPROM locations, without requiring address transactions across the programming bus for each read or write.) AINC# is sampled after each location is programmed or dumped. If AINC# is asserted, the address is incremented and the next data word is programmed or dumped. AINC# shares a package pin with P2.4. Description
ACH7:2
I
AD15:0
I/O
ADV#
O
AINC#
I
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87C196LA-20 MHz CHMOS 16-bit Microcontroller -- Automotive
Table 4. Signal Descriptions (Sheet 2 of 6)
Name Type Address Latch Enable This active-high output signal is asserted only during external memory cycles. ALE signals the start of an external bus cycle and indicates that valid address information is available on the system address/data bus. An external latch can use this signal to demultiplex the address from the address/ data bus. ALE shares a package pin with P5.0 and ADV#. Analog Ground ANGND GND ANGND must be connected for A/D converter and port 0 operation. ANGND and VSS should be nominally at the same potential. Clock Output CLKOUT O Output of the internal clock generator. You can select one of three frequencies: f, f/2, or f/4. CLKOUT has a 50% duty cycle. CLKOUT shares a package pin with P2.7 and PACT#. Event Processor Array (EPA) Compare Pins COMP1:0 O These signals are the outputs of the EPA compare-only channels. COMP1:0 share package pins with the following signals: COMP0/P6.0/EPA8 and COMP1/P6.1/EPA9. Cumulative Program Verification CPVER O During slave or programming, a high signal indicates that all locations programmed correctly, while a low signal indicates that an error occurred during the program operation. CPVER shares a package pin with P2.6 and ONCE#. External Access This input determines whether memory accesses to special-purpose and program memory partitions are directed to internal or external memory. These accesses are directed to internal memory if EA# is held high and to external memory if EA# is held low. For an access to any other memory location, the value of EA# is irrelevant. EA# also controls entry into the programming modes. If EA# is at VPP voltage (typically +12.5 V) on the rising edge of RESET#, the microcontroller enters a programming mode. EA# is sampled and latched only on the rising edge of RESET#. Changing the level of EA# after reset has no effect. Event Processor Array (EPA) Capture/Compare Channels High-speed input/output signals for the EPA capture/compare channels. EPA9:8 EPA3:0 I/O The EPA signals share package pins with the following signals: EPA0/P1.0/T2CLK, EPA1/P1.1, EPA2/P1.2/T2DIR, EPA3/P1.3, EPA8/P6.0/COMP0, and EPA9/P6.1/ COMP1. EPA7:6 do not connect to package pins. They cannot be used to capture an event, but they can function as software timers. EPA5:4 are not implemented. Description
ALE
O
EA#
I
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Table 4. Signal Descriptions (Sheet 3 of 6)
Name Type External Interrupt In normal operating mode, a rising edge on EXTINT sets the EXTINT interrupt pending bit. EXTINT is sampled during phase 2. The minimum high time is one state time. EXTINT I In powerdown mode, asserting the EXTINT signal causes the device to resume normal operation. The interrupt does not need to be enabled. In idle mode, asserting any enabled interrupt causes the device to resume normal operation. EXTINT shares a package pin with P2.2 and PROG#. Port 0 This is a high-impedance, input-only port. Port 0 pins should not be left floating. The port 0 signals share package pins with the A/D inputs. These pins may individually be used as analog inputs (ACHx) or digital inputs (P0.y). While it is possible for the pins to function simultaneously as analog and digital inputs, this is not recommended because reading port 0 while a conversion is in process can produce unreliable conversion results. ANGND and VREF must be connected for port 0 to function. P0.3:2 share package pins with ACH3:2 and P0.7:4 share package pins with ACH7:4 and PMODE.3:0. Port 1 P1.3:0 I/O This is a standard bidirectional port that shares package pins with individually selectable special-function signals. Port 1 shares package pins with the following signals: P1.0/EPA0/T2CLK, P1.1/ EPA1, P1.2/EPA2/T2DIR, P1.3/EPA3. Port 2 P2.7:6 P2.4 P2.2:0 I/O This is a standard bidirectional port that shares package pins with individually selectable special-function signals. Port 2 shares package pins with the following signals: P2.0/TXD/PVER, P2.1/RXD/ PALE#, P2.2/EXTINT/PROG#, P2.4/AINC#, P2.6/ONCE/CPVER. P2.7/OSCOUT/PACT# is output pin only. Port 3 P3.7:0 I/O This is a memory-mapped, 8-bit, bidirectional port with programmable open-drain or complementary output modes. The pins are shared with the multiplexed address/data bus, which has complementary drivers. P3.7:0 share package pins with AD7:0 and PBUS.7:0. Port 4 P4.7:0 I/O This is a memory-mapped, 8-bit, bidirectional port with open-drain or complementary output modes. The pins are shared with the multiplexed address/ data bus, which has complementary drivers. P4.7:0 share package pins with AD15:8 and PBUS.15:8. Port 5 P5.3:2 P5.0 I/O This is a memory-mapped, bidirectional port. Port 5 shares package pins with the following signals: P5.0/ADV#/ALE, P5.2/WR#/ WRL#/PLLEN, and P5.3/RD#. P5.1 and P5.7:4 are not implemented. Description
P0.7:2
I
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87C196LA-20 MHz CHMOS 16-bit Microcontroller -- Automotive
Table 4. Signal Descriptions (Sheet 4 of 6)
Name P6.7:4 P6.1:0 Type Port 6 O This is a standard bidirectional port. Port 6 shares package pins with the following signals: P6.0/EPA8/COMP0, P6.1/ EPA9/COMP1, P6.4/SC0, P6.5/SD0, P6.6/SC1, and P6.7/SD1. Programming Active PACT# O During auto programming or slave dump, a low signal indicates that programming or dumping is in progress, while a high signal indicates that the operation is complete. PACT# shares a package pin with P2.7 and OSCOUT. Programming ALE PALE# I During slave programming, a falling edge causes the device to read a command and address from the programming bus. PALE# is multiplexed with P2.1 and RXD. Address/Command/Data Bus During slave programming, ports 3 and 4 serve as a bidirectional port with opendrain outputs to pass commands, addresses, and data to or from the device. Slave programming requires external pull-up resistors. During auto programming and ROM-dump, ports 3 and 4 serve as a regular system bus to access external memory. P4.6 and P4.7 are left unconnected; P1.1 and P1.2 serve as the upper address lines. Slave programming: PBUS.7:0 share package pins with AD7:0 and P3.7:0. PBUS.15:8 share package pins with AD15:8 and P4.7:0. Auto programming: PBUS.15:8 share package pins with AD15:8 and P4.7:0; PBUS.7:0 share package pins with AD7:0 and P3.7:0. Phase-locked Loop Enable PLLEN I This active-high input pin enables the on-chip clock multiplier. Tie this pin to VCC at power-up to bypass the on-chip clock multiplier. Programming Mode Select PMODE.3:0 I These pins determine the programming mode. PMODE3:0 are sampled after a device reset and must be static while the microcontroller is operating. PMODE3:0 share package pins with P0.7:4 and ACH7:4. Programming Start During programming, a falling edge latches data on the programming bus and begins programming, while a rising edge ends programming. The current location is programmed with the same data as long as PROG# remains asserted, so the data on the programming bus must remain stable while PROG# is active. During a word dump, a falling edge causes the contents of an OTPROM location to be output on the PBUS, while a rising edge ends the data transfer. PROG# shares a package pin with P2.2 and EXTINT. Program Verification PVER O During slave or auto programming, PVER is updated after each programming pulse. A high output signal indicates successful programming of a location, while a low signal indicates a detected error. PVER shares a package pin with P2.0 and TXD. Description
PBUS.15:0
I/O
PROG#
I
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Table 4. Signal Descriptions (Sheet 5 of 6)
Name Type Read RD# O Read-signal output to external memory. RD# is asserted during external memory reads. RD# shares a package pin with P5.3. Reset A level-sensitive reset input to, and an open-drain system reset output from, the microcontroller. Either a falling edge on RESET# or an internal reset turns on a pull-down transistor connected to the RESET# pin for 16 state times. In the powerdown and idle modes, asserting RESET# causes the microcontroller to reset and return to normal operating mode. After a reset, the first instruction fetch is from 2080H. Receive Serial Data RXD I/O In modes 1, 2, and 3, RXD receives serial port input data. In mode 0, it functions as either an input or an open-drain output for data. RXD shares a package pin with P2.1 and PALE#. Clock Pins for SSIO0 and 1 For handshaking transfers, configure SC1:0 as open-drain outputs. SC1:0 I/O This pin carries a signal only during receptions and transmissions. When the SSIO port is idle, the pin remains either high (with handshaking) or low (without handshaking). SC0 shares a package pin with P6.4, and SC1 shares a package pin with P6.6. Data Pins for SSIO0 and 1 SD1:0 I/O These pins are the data I/O pins for SSIO0 and 1. For transmissions, configure SDx as a complementary output signal. For receptions, configure SDx as a highimpedance input signal. SD0 shares a package pin with P6.5, and SD1 shares a package pin with P6.7. Timer 2 External Clock T2CLK I External clock for timer 2. Timer 2 increments (or decrements) on both rising and falling edges of T2CLK. It is also used in conjunction with T2DIR for quadrature counting mode. T2CLK shares a package pin with P1.0 and EPA0. Timer 2 External Direction T2DIR I External direction (up/down) for timer 2. Timer 2 increments when T2DIR is high and decrements when it is low. It is also used in conjunction with T2CLK for quadrature counting mode. T2DIR shares a package pin with P1.2 and EPA2. Transmit Serial Data TXD O In serial I/O modes 1, 2, and 3, TXD transmits serial port output data. In mode 0, it is the serial clock output. TXD shares a package pin with P2.0 and PVER. Description
RESET#
I/O
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Table 4. Signal Descriptions (Sheet 6 of 6)
Name VCC Type Digital Supply Voltage PWR Connect each VCC pin to the digital supply voltage. Programming Voltage VPP PWR VPP causes the device to exit powerdown mode when it is driven low for at least 50 ns. Use this method to exit powerdown only when using an external clock source because it enables the internal phase clocks, but not the internal oscillator. If you do not plan to use the powerdown feature, connect VPP to VCC. Reference Voltage for the A/D Converter VREF PWR This pin supplies operating voltage to the A/D converter. Digital Circuit Ground VSS, VSS1 GND These pins supply ground for the digital circuitry. Connect each VSS and VSS1 pin to ground through the lowest possible impedance path. VSS pins are connected to the core ground region of the microcontroller, while VSS1 pins are connected to the port ground region. (ANGND is connected to the analog ground region.) Separating the ground regions provides noise isolation. Write This active-low output indicates that an external write is occurring. This signal is asserted only during external memory writes. Forcing WR# high while RESET# is low causes the device to enter PLL-bypass mode. When the device is in PLL-bypass mode, the internal phase clocks operate at one-half the frequency of the frequency on XTAL1. WR# shares a package pin with P5.2, WRL#, and PLLEN.
When
Description
WR#
O
this pin is configured as a special-function signal (P5_MODE.2 = 1), the chip configuration register 0 (CCR0) determines whether it functions as WR# or WRL#. CCR0.2 = 1 selects WR#; CCR0.2 = 0 selects WRL#. Write Low
During 16-bit bus cycles, this active-low output signal is asserted for low-byte writes and word writes to external memory. During 8-bit bus cycles, WRL# is asserted for all write operations. WRL# O WRL# shares a package pin with P5.2, WR#, and PLLEN.
When this pin is configured as a special-function signal (P5_MODE.2 = 1), the chip configuration register 0 (CCR0) determines whether it functions as WR# or WRL#. CCR0.2 = 1 selects WR#; CCR0.2 = 0 selects WRL#. Input Crystal/Resonator or External Clock Input
XTAL1
I
Input to the on-chip oscillator and the internal clock generators. The internal clock generators provide the peripheral clocks, CPU clock, and CLKOUT signal. When using an external clock source instead of the on-chip oscillator, connect the clock input to XTAL1. The external clock signal must meet the VIH specification for XTAL1. Inverted Output for the Crystal/Resonator
XTAL2
O
Output of the on-chip oscillator inverter. Leave XTAL2 floating when the design uses an external clock source instead of the on-chip oscillator.
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5.0
Address Map
Table 5. Address Map
Hex Address Range FFFF 8000 7FFF 2080 207F 2000 1FFF 1FE0 1FDF 1F00 1EFF 0300 02FF 0100 00FF 0000 Description External device (memory or I/O) connected to address/data bus Program memory (internal nonvolatile or external memory); see Note 1. Special-purpose memory (internal nonvolatile or external memory) Memory-mapped SFRs Peripheral SFRs External device (memory or I/O) connected to address/data bus; (future SFR expansion; see Note 2). Upper register file (general-purpose register RAM) Lower register file (register RAM, stack pointer, and CPU SFRs) Addressing Modes Indirect or indexed Indirect or indexed Indirect or indexed Indirect or indexed Indirect, indexed, or windowed direct Indirect or indexed Indirect, indexed, or windowed direct Direct, indirect, or indexed
NOTES: 1. After a reset, the microcontroller fetches its first instruction from 2080H. 2. The content or function of these locations may change in future microcontroller revisions, in which case a program that relies on a location in this range might not function properly.
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17
87C196LA-20 MHz CHMOS 16-bit Microcontroller -- Automotive
6.0
Note:
Electrical Characteristics
This document contains information on products in the design phase of development. Do not finalize a design with this information. Revised information will be published when the product is available. Verify with your local Intel sales office that you have the latest datasheet before finalizing a design.
Table 6. Absolute Maximum Ratings
Parameter Storage Temperature Voltage from VPP or EA# to VSS or ANGND Voltage from any other pin to VSS or ANGND Power Dissipation Maximum Rating -60C to +150C -0.5 V to +13.0 V -0.5 V to +7.0 V 0.5 W
Warning:
Stressing the device beyond the "Absolute Maximum Ratings" may cause permanent damage. These are stress ratings only.
Table 7. Operating Conditions
Parameter TA (Ambient Temperature Under Bias) VCC (Digital Supply Voltage) VREF (Analog Supply Voltage) (Notes 1, 2) FXTAL1 (Input Frequency): - PLL in 2x mode - PLL bypassed NOTES: 1. ANGND and VSS should be nominally at the same potential. 2. VREF should not exceed VCC by more than 0.5 V. Values -40C to +125C 4.75 V to 5.25 V 4.75 V to 5.25 V 4 MHz to 10 MHz 8 MHz to 20 MHz
Warning:
Operation beyond the "Operating Conditions" is not recommended and extended exposure beyond the "Operating Conditions" may affect device reliability.
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6.1
DC Characteristics
Table 8. DC Characteristics at VCC = 4.75 V to 5.25 V (Sheet 1 of 2)
Symbol Parameter VCC supply current ICC (-40C to +125C ambient) Active mode supply current (typical) A/D reference supply current Idle mode current Input low voltage (all pins) Input high voltage (all pins) Output low voltage (outputs configured as complementary) Output high voltage (outputs configured as complementary) Input leakage current (standard inputs) Input leakage current (port 0--A/D inputs) Output low voltage in reset (all pins except P2.6) Output low current in reset (all pins except P2.6) Reset pullup resistor Output low voltage in reset (RESET# pin only) Output low voltage in reset (P2.6 only) 15 30 35 6K VCC - 0.3 VCC - 0.7 VCC - 1.5 8 1 0.5 V 0.7 VCC 50 95 mA FXTAL1 = 20 MHz, VCC = VPP = VREF = 5.25 V (While device is in reset) Min Typical Max Units Test Conditions (Note 1)
ICC1 IREF IIDLE VIL VIH VOL
50 2 15 5 42 0.3 VCC VCC + 0.5 0.3 0.45 1.5
mA mA mA V V V V V V V V A A
FXTAL1 = 20 MHz, VCC = VPP = VREF = 5.25 V
(3) IOL = 200 A (4) IOL = 3.2 mA IOL = 7.0 mA IOH = - 200 A (4) IOH = - 3.2 mA IOH = - 7.0 mA VSS VIN VCC (5) VSS VIN VREF IOL = 15 A (6, 7) VOL2 = 1.0 V VOL2 = 2.5 V VOL2 = 4.0 V
VOH ILI ILI1 VOL2
1 110 185 215 65 K 0.3 0.5 0.8 1
V A A A V V V V
IOL2 RRST VOL3
IOL3 = 4 mA (7) IOL3 = 6 mA IOL3 = 10 mA IOL4 = 500 A
VOL4
NOTES:
1. Device is static and should operate below 1 Hz, but is tested only down to 4 MHz with the PLL enabled. With the PLL bypassed, the device is tested only down to 8 MHz. 2. Typicals are based on a limited number of samples and are not guaranteed. The values listed are at room temperature and VREF = VCC = 5.25 V. 3. VIH max for port 0 is VREF + 0.5 V. 4. All bidirectional pins when configured as complementary outputs. 5. Standard input pins include XTAL1, EA#, RESET#, and ports 1-6 when configured as inputs. 6. All bidirectional pins except P2.7/CLKOUT, which is excluded because it is not weakly pulled low in reset. Bidirectional pins include ports 1-6. 7. This specification is not tested in production and is based upon theoretical estimates and/or product characterization.
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87C196LA-20 MHz CHMOS 16-bit Microcontroller -- Automotive
Table 8. DC Characteristics at VCC = 4.75 V to 5.25 V (Sheet 2 of 2)
Symbol CS RWPD2 Parameter Pin capacitance (any pin to VSS) Weak pulldown resistance (all pins except P2.6) P2.6 only P2.6 only 0.4 1.0 1.2 3K ~100 K 2.0 3.5 4.0 Min Typical Max 10 Units pF mA mA mA Test Conditions (Note 1) FTEST = 1.0 MHz (Note 2) VOL4 = 1.0 V VOL4 = 2.5 V VOL4 = 4.0 V
IOL4 RWPD4
NOTES:
1. Device is static and should operate below 1 Hz, but is tested only down to 4 MHz with the PLL enabled. With the PLL bypassed, the device is tested only down to 8 MHz. 2. Typicals are based on a limited number of samples and are not guaranteed. The values listed are at room temperature and VREF = VCC = 5.25 V. 3. VIH max for port 0 is VREF + 0.5 V. 4. All bidirectional pins when configured as complementary outputs. 5. Standard input pins include XTAL1, EA#, RESET#, and ports 1-6 when configured as inputs. 6. All bidirectional pins except P2.7/CLKOUT, which is excluded because it is not weakly pulled low in reset. Bidirectional pins include ports 1-6. 7. This specification is not tested in production and is based upon theoretical estimates and/or product characterization.
6.2
6.2.1
AC Characteristics (Over Specified Operating Conditions)
Test Condition * Capacitive load on all pins = 100 pF * Rise and fall times = 10 ns * FXTAL1 = 8 MHz with PLL enabled in clock-doubler mode
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Advance Information Datasheet
Automotive -- 87C196LA-20 MHz CHMOS 16-bit Microcontroller
Table 9. AC Characteristics (Sheet 1 of 2)
Symbol Parameter Min Max Units
The 87C196LA meets these specifications Frequency on XTAL1, PLL bypassed FXTAL1 Frequency on XTAL1, PLL in 2x mode Operating frequency, f = FXTAL1; PLL in 1x mode f t TXHCH TCLCL TCHCL TCLLH TLLCH TLHLH TLHLL TAVLL TLLAX TLLRL TRLCL TRHLH TRLRH TRLAZ TLLWL TCLWL TQVWH TCHWH TWLWH TWHQX TWHLH TWHAX TRHAX Operating frequency, f = 2FXTAL1; PLL in 2x mode Period t = 1/f XTAL1 High to CLKOUT High or Low CLKOUT Cycle Time CLKOUT High Period CLKOUT Falling to ALE Rising ALE Falling to CLKOUT Rising ALE Cycle Time ALE High Period Address Setup to ALE Low Address Hold after ALE Low ALE Low to RD# Low RD# Low to CLKOUT Low RD# High to ALE Rising RD# Low to RD# High RD# Low to Address Float ALE Low to WR# Low CLKOUT Low to WR# Falling Edge Data Valid to WR# High CLKOUT High to WR# Rising Edge WR# Low to WR# High Data Hold after WR# High WR# High to ALE High AD15:8 Hold after WR# High AD15:8 Hold after RD# High t - 10 -5 t - 23 -5 t - 20 t - 25 t - 10 t - 30 t - 30 t + 15 30 25 t - 10 t - 15 t - 40 t -- 30 0 t-5 t t + 25 10 30 t - 10 - 10 - 35 4t t + 10 8 50 20 2t t + 20 30 15 20 125 110 MHz ns ns(2) ns ns ns ns ns ns ns ns ns ns ns ns(3) ns ns ns ns ns ns ns ns(3) ns(4) ns(4) 8 4 20 10 MHz(1)
NOTES: 1. Testing performed at 4.0 MHz with PLL enabled. With the PLL bypassed, the device is tested only down to 8 MHz. However, the device is static by design and typically operates below 1 Hz. 2. Typical specifications, not guaranteed. 3. Assuming back-to-back bus cycles. 4. 8-bit bus only.
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87C196LA-20 MHz CHMOS 16-bit Microcontroller -- Automotive
Table 9. AC Characteristics (Sheet 2 of 2)
Symbol Parameter Min Max Units
The system must meet these specifications to work with the 87C196LA TAVDV TRLDV TCLDV TRHDZ TRXDX Address Valid to Input Data Valid RD# Low to Input Data Valid CLKOUT Low to Input Data Valid RD# High to Input Data Float Data Hold after RD# Inactive 0 3t - 55 t - 22 t - 50 t ns ns ns ns ns
NOTES: 1. Testing performed at 4.0 MHz with PLL enabled. With the PLL bypassed, the device is tested only down to 8 MHz. However, the device is static by design and typically operates below 1 Hz. 2. Typical specifications, not guaranteed. 3. Assuming back-to-back bus cycles. 4. 8-bit bus only.
6.2.2
Explanation of AC Symbols
Each symbol is two pairs of letters prefixed by "t" for time. The characters in a pair indicate a signal and its condition, respectively. Symbols represent the time between the two signal/condition points.
Table 10. AC Timing Symbol Definitions
A C D L Q R W Character H L V X Z High Low Valid No Longer Valid Floating (low impedance) AD15:0 CLKOUT AD15:0, AD7:0 ALE AD15:0, AD7:0 RD# WR#, WRL# Condition
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Advance Information Datasheet
Automotive -- 87C196LA-20 MHz CHMOS 16-bit Microcontroller
Figure 4. System Bus Timing
TXTAL1 XTAL1 CLKOUT TCLLH ALE/ADV# TLHLL TLLRL RD# TAVLL AD15:0 (read) WR# AD15:0 (write) AD15:8 (8-bit data bus) TQVWH Address Out Data Out TWHQX Address Out TWHAX, TRHAX High Address Out
A4458-01
TCLCL
TXHCH
TCHCL
TLLCH TLHLH
TRLRH
TRHLH
TRLAZ TLLAX TRLDV Data In TLLWL TWLWH
TRHDZ
Address Out TAVDV
TWHLH
Table 11. External Clock Drive
Symbol 1/TXLXL TXLXL TXHXX TXLXX TXLXH TXHLX Parameter Frequency on XTAL1, PLL bypassed Frequency on XTAL1, PLL in 2x mode Oscillator Period (TOSC) High Time Low Time Rise Time Fall Time Min 8 4 50 0.35T 0.35T Max 20 10 250 0.65T 0.65T 10 10 ns ns ns ns ns Units MHz(1)
1. Testing performed at 4.0 MHz with PLL enabled. With the PLL bypassed, the device is tested only down to 8 MHz. However, the device is static by design and typically operates below 1 Hz.
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87C196LA-20 MHz CHMOS 16-bit Microcontroller -- Automotive
Figure 5. External Clock Drive Waveform
TXHXX 0.7 VCC + 0.5 V XTAL1
TXLXH TXLXX 0.3 VCC - 0.5 V 0.7 VCC + 0.5 V 0.3 VCC - 0.5 V TXLXL
TXHXL
A2119-03
Figure 6. AC Testing Input, Output Waveforms
3.5 V
2.0 V Test Points 0.8 V
2.0 V 0.8 V
0.45 V
Note: AC testing inputs are driven at 3.5 V for a logic " 1" and 0.45 V for a logic " 0" . Timing measurements are made at 2.0 V for a logic " 1" and 0.8 V for a logic " 0".
A2120-04
Figure 7. Float Waveform
VLOAD + 0.15 V VLOAD VLOAD - 0.15 V Timing Reference Points
VOH - 0.15 V
VOL + 0.15 V
Note: For timing purposes, a port pin is no longer floating when a 150 mV change from load voltage occurs and begins to float when a 150 mV change from the loading VOH/VOL level occurs with IOL/IOH 15 mA.
A2121-03
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Advance Information Datasheet
Automotive -- 87C196LA-20 MHz CHMOS 16-bit Microcontroller
7.0
7.1
EPROM Specifications
Operating Conditions
* Load Capacitance = 150 pF * TC = 25C 5C * VREF = 5.0 V 0.25 V * VSS * ANGND = 0.0 V * VPP = 12.5 V 0.25 V * EA# = 12.5 V 0.25 V * FOSC = 5.0 MHz
Table 12. AC EPROM Programming Characteristics
Symbol TAVLL TLLAX TDVPL TPLDX TLLLH TPLPH TLHPL TPHLL TPHDX TPHPL TLHPL TPLDV TSHLL TPHIL TILIH TILVH TILPL TPHVL Parameter Address Setup Time Address Hold Time Data Setup Time Data Hold Time PALE# Pulse Width PROG# Pulse Width
3
Min 0 100 0 400 50 50 220 220
Max
Units TOSC TOSC TOSC TOSC TOSC TOSC TOSC TOSC
PALE# High to PROG# Low PROG# High to Next PALE# Low Word Dump Hold Time PROG# High to Next PROG# Low PALE# High to PROG# Low PROG# Low to Word Dump Valid RESET# High to First PALE# Low PROG# High to AINC# Low AINC# Pulse Width PVER# Hold after AINC# Low AINC# Low to PROG# Low PROG# High to PVER# Valid
50 220 220 50 1100 0 240 50 170 220
TOSC TOSC TOSC TOSC TOSC TOSC TOSC TOSC TOSC TOSC
NOTES: 1. Run-time programming is done with FOSC = 6.0 MHz to 10.0 MHz, VCC, VPD, VREF = 5.0 V 0.25 V, TC = 25C 5C and VPP = 12.5 V 0.25 V. For run-time programming over a full operating range, contact factory. 2. Programming Specifications are not tested, but guaranteed by design. 3. This specification is for the word dump mode. For programming pulses use 300 TOSC + 100 s.
Table 13. DC EPROM Programming Characteristics
Symbol IPP Parameter VPP Programming Supply Current Min Max 100 Units mA
NOTE: VPP must be within 1 V of VCC while VCC <4.5 V. VPP must not have a low impedance path to ground or VSS while VCC >4.5 V.
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87C196LA-20 MHz CHMOS 16-bit Microcontroller -- Automotive
7.2
EPROM Programming Waveforms
Figure 8. Slave Programming Mode Data Program Mode with Single Program Pulse
RESET#
TAVLL TDVPL Data TLLAX TPLDX Address/Command
PORTS 3/4
Address/Command TSHLL
PALE# P2.1
TLLLH TLHPL TPLPH TPHLL
PROG# P2.2
TPHVL
PVER# P2.0
Valid TLLVH A4428-01
Figure 9. Slave Programming Mode in WORD Dump or Data Verify Mode with Auto Increment
RESET#
ADDR ADDR + 2 Ver Bits/WD Dump TPLDV TPHDX
PORTS 3/4
Address/Command TSHLL TPLDV
Ver Bits/WD Dump TPHDX
PALE# P2.1 PROG# P2.2
TILPL TPHPL
PVER# P2.0
A4429-01
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Advance Information Datasheet
Automotive -- 87C196LA-20 MHz CHMOS 16-bit Microcontroller
Figure 10. Slave Programming Mode Timing in Data Program Mode with Repeated Program Pulse and Auto Increment
RESET#
PORTS 3/4
Address/Command
Data
Data
PALE# P2.1 PROG# P2.2 PVER# P2.0 AINC# P2.4
TPHPL P1 P2
TILPL
TILVH Valid For P1 Valid For P2 TILIH
TPHIL A4430-01
8.0
A/D Converter Specifications
The speed of the A/D converter in the 10-bit or 8-bit modes can be adjusted by setting the AD_TIME special function register to the appropriate value. The AD_TIME register only programs the speed at which the conversions are performed, not the speed at which it can convert correctly. The converter is ratiometric, so absolute accuracy is dependent on the accuracy and stability of VREF. VREF must be within 0.5 V of VCC since it supplies both the resistor ladder and the digital portion of the converter and input port pins. For testing purposes, after a conversion is started, the device is placed in the IDLE mode until the conversion is complete. Testing is performed at VREF = 5.12 V and 20 MHz operating frequency. There is an AD_TEST register that allows for conversion on ANGND and VREF, as well as zero offset adjustment. The absolute error listed is without doing any adjustments.
Advance Information Datasheet
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87C196LA-20 MHz CHMOS 16-bit Microcontroller -- Automotive
Table 14. A/D Operating Conditions - Symbol Descriptions1
Symbol TA VCC VREF TSAM TCONV FOSC Description Automotive Ambient Temperature Digital Supply Voltage Analog Supply Voltage Sample Time Conversion Time Oscillator Frequency Min -40 4.75 4.75 2.0 15 4 18 20 Max +125 5.25 5.25
(2,3)
Units C V V s(4) s(4) MHz
NOTES: 1. ANGND and VSS should nominally be at the same potential. 2. VREF must not exceed VCC by more than +0.5 V. 3. Testing is performed at VREF = 5.12 V. 4. The value of AD_TIME must be selected to meet these specifications.
Table 15. A/D Operating Conditions - Parameter Descriptions
Parameter Resolution Absolute Error Full Scale Error Zero Offset Error Non-Linearity Differential Non-Linearity Channel-to-Channel Matching Repeatability Temperature Coefficients: Offset Fullscale Differential Non-Linearity Off Isolation Feedthrough VCC Power Supply Rejection Input Resistance DC Input Leakage NOTES: These values are expected for most parts at 25C, but are not tested or guaranteed. An "LSB", as used here, has a value of approximately 5 mV. (See Automotive Handbook for A/D glossary of terms). 1. These values are not tested in production and are based on theoretical estimates and/or laboratory test. 2. DC to 100 KHz. 3. Multiplexer Break-Make Guaranteed.

Typical,1
Min 1024 10 0
Max 1024 10 3
Units Level Bits LSBs LSBs LSBs
2 2 3 0.5 0 0.25 0 +0.5 1
LSBs LSBs LSBs LSBs(1) LSBs/C(1) dB(1,2,3) dB(1,2) dB(1,2)
0.009
- 60 - 60 - 60 750 0 1.2 K 2
(1) A
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Advance Information Datasheet
Automotive -- 87C196LA-20 MHz CHMOS 16-bit Microcontroller
9.0
AC Characteristics - Serial Port Shift Register Mode
Test Conditions
* TA = -40C to +125C * VCC = 5.0 V 5% * VSS = 0.0 V * Load Capacitance = 100 pF
9.1
Table 16. Serial Port Timing - Shift Register Mode
Symbol TXLXL TXLXH TQVXH TXHQX TXHQV TDVXH TXHDX1 TXHQZ1 Parameter Serial Port Clock Period Serial Port Clock Falling Edge to Rising Edge Output Data Setup to Clock Rising Edge Output Data Hold after Clock Rising Edge Next Output Data Valid after Clock Rising Edge Input Data Setup to Clock Rising Edge Input Data Hold after Clock Rising Edge Last Clock Rising to Output Float 2T + 200 0 5T Min 8T 4T - 50 3T 2T - 50 2T + 50 4T + 50 Max Units ns ns ns ns ns ns ns ns
1. Parameter not tested.
9.2
Waveform - Serial Port - Shift Register Mode0
Figure 11. Serial Port Waveform - Shift Register Mode
TXLXL
TXD
TQVXH TXLXH TXHQV TXHQX TXHQZ
RXD (out)
0
TDVXH
1
2
3
TXHDX
4
5
6
7
RXD (in)
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid A4427-01
Advance Information Datasheet
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87C196LA-20 MHz CHMOS 16-bit Microcontroller -- Automotive
10.0
Thermal Characteristics
All thermal impedance data is approximate for static air conditions at 1 watt of power dissipation. Values change depending on operating conditions and the application. The Intel Packaging Handbook (order number 240800) describes Intel's thermal impedance test methodology. The Components Quality and Reliability Handbook (order number 210997) provides quality and reliability information.
Table 17. Thermal Characteristics
Package Type AN87C196LA (52-pin PLCC) JA 42C/W JC 15C/W
NOTES: 1. JA = Thermal resistance between junction and the surrounding environment (ambient). Measurements are taken 1 foot away from case in static air flow environment. JC = Thermal resistance between junction and package surface (case). 2. All values of JA and JC may fluctuate depending on the environment (with or without airflow, and how much airflow) and device power dissipation at temperature of operation. Typical variations are 2C/W. 3. Values listed are at a maximum power dissipation of 0.5 W.
11.0
Design Considerations
To be supplied.
12.0
Device Errata
Contact your Intel sales representative for this product's specification update.
13.0
Datasheet Revision History
This is the (003) version of the 87C196LA-20 MHz CHMOS 16-bit Microcontroller datasheet.
Table 18. Revision History (Sheet 1 of 2)
Revision 002 002 002 002 002 Item All Cover Figure 3 Table 4 Section 6.0 Change Data sheet moved from Product Preview to Advance Information status. List of features changed to reflect 24 Kbytes of OTPROM and 768 bytes of register RAM. Modified to include PLLEN designation on pin 6. Signal descriptions modified for the PLLEN pin, to reflect the method for bypassing the on-chip PLL. Changed "PLL in 1x mode" to "PLL bypassed".
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Table 18. Revision History (Sheet 2 of 2)
Revision Item Change Changes to DC Characteristics as follows: * ICCMax from TBD to 95 mA * IREFMax from TBD to 5 mA * IIDLEMax from TBD to 42 mA *
PDDeleted
* IHDeleted * IOL2 (All pins except P2.6) Min, Max, @ VOL2 from TBD to: Min = 15 mAMax = 110 A@ VOL2 = 1.0 V Min = 30 mAMax = 185 A@ VOL2 = 2.5 V Min = 35 mAMax = 215 A@ VOL2 = 4.0 V * RWPU replaced with RWPD2 to accurately reflect the weak pulldown device. Typical set to 100 K for all pins except P2.6. * IOL2 (Added for P2.6 only) Min = 0.4 mAMax = 2.0 A@ VOL4 = 1.0 V Min = 1.0 mAMax = 3.5 A@ VOL4 = 2.5 V Min = 1.2 mAMax = 4.0 A@ VOL4 = 4.0 V * RWPD4 (Added for P2.6 only) To accurately reflect the weak pulldown device for P2.6. Typical set to 3 K. Changes to AC Characteristics as follows: * TCHCLMax from T+15 to T+20 ns * TCLLHMax from 15 to 30 ns 002 Table 9 * TLLCHMin from -20 to -35 ns * TRLCLMin from 4 to 0 * TRLAZMax from 5 to 10 ns * TCHWHMin from -10 to -5 ns Max from 15 to 30 ns 002 002 002 002 002 002 003 Table 11 and Figure 5 Figure 6 Figure 7 Section 7.2 Section 8.0 Section 9.0 All Added External clock drive specifications and waveform. Added AC testing input/output waveform. Added Float Waveform. Added EPROM specifications for programming characteristics. Added A/D converter specifications. Added AC characteristics for the serial port. Changed VCC and VREF operating spec conditions.
002
Section 6.1
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