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| 2002*February Inverter-type air conditioners The V850 SeriesTM of embedded microcontrollers answers diversified needs in all kinds of application systems. It realizes lower power consumption and noise while achieving higher performance and multiple functions. Consisting of a rich lineup, the V850 Series offers optimum solutions for nextgeneration embedded systems. Digital video cameras Automotive electronics DVD players Digital still cameras Cellular phones 2 Storage devices Pamphlet U15412EJ1V0PF Fax machines Single-lens reflex cameras Network modems Microwave ranges PDA Washing machines Digital video recorders Printers Home audio Vending machines Electronic music instruments Car audio Pamphlet U15412EJ1V0PF Car AV centers 3 V850 Performance POSITION NEC Microcontroller Lineup VR SeriesTM 64-bit MIPS RISC Microprocessors VR4x00 / 5x00 VR1x000 V850E/Mxx high-end lineup V850, V850ES, V850E ASSP lineup V850ES, V850/Sxx low-end lineup Da ta c pro ess ing V850 Series 32-bit RISC microcontrollers 78K Series 8/16-bit microcontrollers 78K4 78K0 78K0S Low-End High-End 8-bit microcontrollers Mid-range 16-bit microcontrollers Sys tem t con rol 75X/XL 17K 8-bit 16-bit 32-bit Price V850 ROADMAP V850E2/xxx External 32-bit bus 80 to 100 MHz SDRAM compatible 40 to 50 MHz V850E2 core 200 to 266 MHz @ 0.13 m or lower Instruction set upward compatible High-end lineup V850E1 core 124 MIPS /100 MHz @ 0.35 m or lower 33 MHz with on-chip flash memory Enhanced MEMC 33 to 40 MHz V850E/Mxx V850E/MAx V850E/MSx V853TM V850 ASSP lineup V850E ASSP lineup V850 core 38 MIPS /33 MHz @ 0.8 m or lower V850/Sxx low-power lineup V850ES low-power lineup Low-end lineup : Under development 4 Pamphlet U15412EJ1V0PF Low-end applications High-end applications INDEX 5KEYS V850 06 18 27 32 36 38 42 53 61 Architecture Variety of Peripheral Functions Low Power & Low Noise Middleware Flash Memory Microcontrollers Functional Outline Comfortable Development Environment Information Pamphlet U15412EJ1V0PF 5 5KEYS V850 Processor products Data processing V850E2 High Performance Scalable coverage of 20 MHz to over 100 MHz 3 to 4 times higher performance at same frequency compared to 16-bit microcontrollers V850, V850ES, and V850E1 cores are upward compatible at object level. V850 Series covers a broad range from middle to high-end market with a single instruction set 32-bit microcontrollers of other companies Applicable down to middle-range models 100MHz V850E1 50MHz 33MHz V850 16-bit microcontrollers of other companies 3-4 times higher performance Applicable up to high-end models System control V850ES V850 20MHz : Under development V850E/Mxx Automotive Extensive Product Lineup From low-end/high-end general-purpose products all the way to ASSP lineup Low-end lineup designed for 8/16-bit market (V850ES, V850/Sxx) High-end lineup with on-chip MEMC, DMA, that pursues high performance (V850E) ASSP lineup with on-chip dedicated hardware optimized for various fields (V850E, V850ES, V850/Sxx) High-end lineup Sophisticated memory I/F OA V850E/xxx V850ES/xxx V850E1 core V850ES core V850 core On-chip dedicated hardware Industrial V850/xxx ASSP lineup Communications Low power, low noise, expanded internal memory V850ES/xxx V850/Sxx Information appliances Consumer electronics Low-end lineup Amusement machines FAX Additional Functions Toys Portable terminals Handwriting recognition ADPCM TTS Electronic dictionaries DSC JBIG MH/MR/MMR Enriched middleware lineup Rich lineup of middleware related to video, audio, networks, etc., optimized for the V850 Realization of peripheral functions through V850 + middleware combination Shorter development time, lower system cost AV equipment Phones Video processing JPEG Human interface Car audio Middleware Browser Speech recognition Home appliances Network Java TCP/IP 6 Pamphlet U15412EJ1V0PF System System Integration High-performance CPU cores By meeting the five conditions consisting of leading-edge process technology, high-performance CPU cores, a rich lineup of IP cores, a top-down design environment, and a flexible application environment, the V850 Series offers optimum system-on-chip solutions. Process Analog IP Design environment PCI/F CPU DSP Memory Flash Logic DRAM middleware IP cores Middleware CPU Core Lineup 700 500 0.1m process V850E3 Nx85E3 350MHz V850E3/xxx V850E3/xxx xxx 300 V850E2 0.13m process Nx85E2 260MHz Nx85E2 200MHz Nx85E 100MHz Nx85E 66MHz [MIPS] 200 V850E1 V850E2/xxx V850E2/xxx V850E/MAx xxx 100 0.25m process 66 0.35m process 33 V850E/MA1TM V850E/IA1 TM MA2TM IA2TM V850 2000 2005 Utilization of existing functions Improved operability Accessible Development Enviroment Rich lineup and high operability Inherits operability of 78K Series. Shorter software development TAT through superior operability and sophisticated development environment Easy C-language support through high-performance CPUs and real-time OS embedding possible 78K Development Environment PM Project Manager V850 Development Environment PM Project Manager Higher versatility CC (Compiler) RX (Real-time OS) CA (Compiler) RX (Real-time OS) + RD (Task debugger) + AZ (Analyzer) V850 products Realize a sophisticated and powerful development environment through: *High performance *General-purpose registers *Large-capacity memory Higher performance Debugging support SM (Simulator) ID (Debugger) Debugging support SM (Simulator) ID (Debugger) Improved operability IE (In-circuit emulator) Support of high speed IE (In-circuit emulator) Pamphlet U15412EJ1V0PF 7 V850E Product Development Concept Pursuit of high performance High-performance CPU using V850E core 10% higher performance than V850 CPU at same frequency 10% to 20% higher code efficiency than V850 CPU through addition of C-compatible instructions Upward compatibility at object level with V850 CPU cores Enhanced external bus performance On-chip direct interface for various memories SRAM, page ROM, EDO DRAM, synchronous DRAM, etc. On-chip DMA controller Realization of voluminous data processing and high-performance control on one chip In mass production Under development In planning [Low Voltage] External 32-bit bus 144-pin LQFP/161-pin FBGA Higher performance V850E/Mxx 80 to 100MHz V850E/MA1 On-chip SDRAM controller ROMless/4 KB to 256 KB/10 KB On-chip 256 KB flash memory 50 MHz @ 3.0 to 3.6 V (5 V tolerance) More compact 100-pin LQFP Higher performance V850E/MA2 On-chip SDRAM controller ROMless/4 KB 40 MHz @ 3.0 to 3.6 V 144-pin LQFP/157-pin FBGA (3.3 V only) V850E/MS1TM(3.3V) V850E/MS1(5V) On-chip DRAM controller ROMless/4 KB to 128 KB/4 KB On-chip 128 KB flash memory 33 MHz @ 3.0 to 3.6 V 33 MHz @ 3.0 to 3.6 V/ 4.5 to 5.5 V (external) 144-pin LQFP More compact Higher performance Enhanced peripheral functions 100-pin LQFP [5 V ] 100-pin LQFP V850E/IA1 On-chip inverter and timer 256 KB/10 KB On-chip 256 KB flash memory 50 MHz @ 3.0 to 3.6 V/ 4.5 to 5.5 V (external) V850E/IA2 On-chip inverter and timer 128KB/6KB On-chip 128 KB flash memory 40 MHz @4.5 to 5.5V V850E/MS2TM Higher performance ROMless/4 KB 33 MHz @ 3.0 to 3.6 V/ 4.5 to 5.5 V (external) 100-pin LQFP Higher performance Enhanced peripheral functions V853 96KB/4KB to 256KB/8KB On-chip 128 KB, 256 KB flash memory 33 MHz @4.5 to 5.5V Higher performance 16-bit V SeriesTM 78K/III 8 Pamphlet U15412EJ1V0PF V850E Product Features V850E/MS1 Performance of 43 MIPS @ 33 MHz On-chip memory controllers for EDO DRAM, etc. Lineup of products for 5 V systems and 3.3 V systems V850E/MS2 Support of 5 V interface enables connection of existing external I/Os Contributes to higher cost performance of sets through use of V850E CPU architecture V850E/MA1 High performance of 62 MIPS @ 50 MHz On-chip memory controllers for SDRAM, etc. Various peripheral functions such as timer, serial interface, and A/D converter V850E/MA2 On-chip SDRAM controller Contributes to smaller applications, lighter weight, and higher cost performance through use of 14 x 14 mm, 100-pin package V850E/IA1 On-chip 3-phase sine wave PWM timer, 2-phase encoder input up/down counter, A/D converter, 2-system motor driving enabled through inverter control 6-system serial I/F including FCAN for automotive LAN (Ver. 2.0 Part B compliant) V850E/IA2 2-system motor driving enabled through on-chip peripheral functions almost the same as those of V850E/IA1 System can be configured with single 5 V power supply thanks to on-chip regulator Pamphlet U15412EJ1V0PF 9 V850E Product Application Examples System bus Image processing Shading Compensation/ binarization Optical system Document S/H CCD A/D V850E/MS1 ROM: 128 KB MH/MR/MMR JBIG RPU RAM 4 KB PORT INTC Motor Operation panel Motor driver Memory SDRM CPU DMA SIO ROM FAX Application example using V850E/MS1 RAM For storing image data Communication system AFE NCU Telephone network Paper Printing system Watch Real-time clock Image processing Printer engine Program ROM Font ROM DRAM SRAM ASIC CR motor ASIC IEEE1284 Printer Application example using V850E/MA1 PF motor Engine controller V850E/MA1 Interface controller IEEE1394 Color head USB Black head LAN Operation panel Pick up RF-Amp ADC DRAM AC-3 decoder 2ch DAC Speech output Driver DRAM NTSC/PAL Servo processor DVDPlayer Application example using V850E/MA2 Error correction Stream management A/V separation MPEG2 decoder CPUI/F Video encoder 3ch DAC Image output GUI Mechanical control microcontroller System control microcontroller V850E/MA2 Display Key input 10 Pamphlet U15412EJ1V0PF V850ES, V850/Sxx Product Development Concept High Performance 3 to 4 times higher performance compared to 16-bit CISC microcontrollers Middleware support (JPEG, speech recognition, etc.) Low noise & low power Optimum design for maximum operating frequency of 20 MHz Thorough EMI noise countermeasures Low-voltage support Realization of 2.2 V low voltage operation (V850ES/SA2, SA3) Variation in memory and I/O Various memory capacities (ROM: 64 KB to 512 KB, RAM: 4 KB to 24 KB) Various ASSPs (automotive bus support (IEBusTM, CAN), servo timer, etc.) Various packages (100-pin to 180-pin) Peripheral functions inherited from 78K Series Standard peripheral functions of 78K Series (timer, serial interface, etc.) Pursuit of high cost performance Designed for 8/16-bit application market [Low Voltage] In mass production Under development Enhanced peripheral functions 100-pin LQFP/121-pin FBGA 176-pin LQFP/180-pin FBGA [5 V] 144-pin LQFP V850/SV1TM On-chip servo timer 192 KB/8 KB to 384 KB/16 KB On-chip 256 KB, 384 KB flash memory 16 MHz @2.7 to 3.6 V 20 MHz @3.1 to 3.6 V V850/SC1,2,3TM On-chip IEBus (SC2), on-chip FCAN (SC3) 256 KB/20 KB to 512 KB/24 KB On-chip 512 KB flash memory 20 MHz@4.5 to 5.5V Enhanced peripheral functions 100-pin QFP/LQFP V850/SA1TM 64 KB/4 KB to 256 KB/8 KB On-chip 128 KB, 256 KB flash memory 17 MHz @2.7 to 3.6 V 20 MHz @3.0 to 3.6 V V850/SB1,2TM Support of low voltage 100-pin LQFP/121-pin FBGA On-chip IEBus (SB2) 128 KB/12 KB to 512 KB/24 KB On-chip 256 KB, 512 KB flash memory 20 MHz@4.5 to 5.5V Enhanced peripheral functions 100-pin LQFP V850ES/SA2,3TM 256 KB/16 KB On-chip 256 KB flash memory 13.5 MHz @2.2 to 2.7 V 17 MHz @2.3 to 2.7 V V850/SF1TM On-chip FCAN 256 KB/16 KB On-chip 256 KB flash memory 16 MHz@4.5 to 5.5V Higher 3 V performance 78K/IV 78K/0 5 V higher performance Pamphlet U15412EJ1V0PF 11 V850ES, V850/Sxx Product Features V850ES/SA2, SA3 Ultra-low power consumption/high-speed operation (30 mW @ 2.5 V, 17 MHz) Low-voltage operation of 2.2 V Min. (1.8 V under planning) On-chip single power supply flash memory On-chip V850ES core V850/SA1 Ultra-low power consumption (66 mW (20 MHz @ 3.3 V, mask ROM version, Typ.)) Rich memory lineup (ROM 64 KB to 256 KB/RAM 4 KB to 8 KB) Support of CSP package (121-pin FBGA) V850/SV1 Various on-chip peripheral functions including servo timer Rich memory lineup (ROM 192 KB to 384 KB/RAM 8 KB to 16 KB) Support of high-pin-count CSP package (180-pin FBGA) ASSP lineup for DVC V850/SB1, SB2 Low EMI noise On-chip large-capacity memory (512 KB/24 KB Max.) Rich memory lineup (ROM 128 KB to 512 KB/RAM 12 KB to 24 KB) Automotive bus support (V850/SB2 only) V850/SF1 Low EMI noise On-chip FCAN controller (2 ch Max.) ASSP lineup for car audio V850/SC1, SC2, SC3 Low EMI noise Enhanced peripheral functions for V850/SB1, SB2 (100-pin Automotive bus support (IEBus, FCAN) 144-pin) 12 Pamphlet U15412EJ1V0PF V850ES, V850/Sxx Product Features V850ES, V850/Sxx Series power performance mA/MIPS 10 Current consumption/performance 8-bit CISC 9.2mA/MIPS Low current consumption: 1/5th that of 16-bit CISC with equivalent performance 16-bit CISC 5 7.3mA/MIPS 1.1mA/MIPS 1.1mA/MIPS V850/SV1 V850/SB1 0.9mA/MIPS V850/SA1 0.7mA/MIPS V850ES/SA2, 3* :Under development 0 Smooth transition from CISC to RISC CISC-like use enabled * Bit manipulation instructions (SET1, CLR1, NOT1, TST1) * Multi-status flags * 32-bit barrel shifter On-chip standard peripheral functions of 78K Series * Timers (8-bit, 16-bit) * Serial interface (3-wire CSI, UART) * Watchdog timer, etc. High code efficiency * Equals CISC code efficiency (1.0 to 1.2) * High-level language (C language) programming supported Comparison of peripheral functions of 78K Series and V850/Sxx products 78K/0 Series 78K/IV Series V850 Series V850/SA1 V850/SB1,2 V850/SV1 V850/SF1 V850/SC1,2,3 PD78003x 16-bit timer 8-bit timer Serial interface (CSI) Serial interface (UART) I2C interface AD converter Real-time output Watchdog timer Watch timer Key return function WDT WT TM0 TM5 SIO3 UART0 IIC0 ADCTL0 PD78421x UART3 RT00 Separate specifications WDT WTN0 Separate specifications KR0 :Listed on left :Not provided Pamphlet U15412EJ1V0PF 13 V850 ASSP Lineup Inverter Control V850E/IA1 High performance V850E/IA2 For general use DVC V850/SAx For camera control V850/SV1 For servo control Car Audio V850/Sxx Standard product V850/SB2, SC2 IEBus V850/SF1, SC3 CAN bus Automotive Electronics V850/xxx ABS V850/xxx Air bag V850/xxx Dashboard V850E/IA2 inverter air conditioner application example Power supply block V850/SV1 System Block Diagram (DVC) Indoor unit Sensors 3CCD CDS +AGC 10-bit ADC Field memory DRAM LCD signal processing Error correction (modem) Finder V850E/IA2 Camera signal control Memory control Video compression/ decompression Head amp Head Vertical drive Drive SG Sync SG OSD Power module Power module Motor drive V850/SV1 Motor drive Display key operation Microphone Mic/amp ADC Error correction Compressor motor Fan motor V850/SB2 System Block Diagram (Car Audio) FM/AM tuner block MD deck block CD deck block Changer connector IEBus AUX connector PLL Audio switch DSP AMP Display block VFD Power supply block V850/SB2 FLT driver Front panel block FCAN driver Key microcontroller Key matrix Remote control receiver 14 Pamphlet U15412EJ1V0PF Memory Lineup Mask products Flash memory products V850/SC3 V850/SC3 V850/SC2 V850/SC2 V850/SC1 512K ROM Size (Bytes) V850/SC1 V850/SB2 V850/SB2 V850/SB1 V850/SB1 384K V850/SV1 V850/SV1 V850/SB2* V850/SB1* V850/SB2* V850/SB1* V850ES/SA3* V850ES/SA3* V850ES/SA2* V850ES/SA2* V850/SV1 256K V850/SV1 V850/SF1 V853 V853 V850/SV1 V850/SA1 V850/SA1 V850E/IA1 V850E/IA1 V850E/MA1 V850E/MA1 V850/SF1 V850/SB2 V850/SB2 V850/SB1 V850/SB1 192K V850/SV1 V853 V853 V850/SA1 128K V850/SA1 V850E/MA1 V850E/MS1 V850E/MS1 V850E/IA2 V850E/IA2 V850/SB2* V850/SB1* V850E/MA1 V850/SB2* V850/SB1* V853 96K V850E/MS1 64K V850/SA1 V850E/MS1 ROMless V850E/MS2 V850E/MA1 V850E/MA2 4K 6K 8K 10K 12K 16K 20K 24K *: Under development RAM Size (Bytes) Pamphlet U15412EJ1V0PF 15 Package Lineup Package Name 100-pin plastic QFP (14 x 20 mm) 100-pin plastic LQFP (14 x 14 mm) 144-pin plastic LQFP (20 x 20 mm) 176-pin plastic LQFP (24 x 24 mm) 121-pin plastic FBGA (12 x 12 mm) 157-pin plastic FBGA (14 x 14 mm) 161-pin plastic FBGA (13 x 13 mm) 180-pin plastic FBGA (13 x 13 mm) V850/SB1, SB2, SF1 V850E/MA2, MS2, IA2, V850ES/SA2, V850/SA1, SB1, SB2, SF1, V853 V850E/MA1, IA1, MS1, V850/SC1, SC2, SC3 V850/SV1 V850ES/SA3, V850/SA1 V850E/MS1 V850E/MA1 V850/SV1 Applicable Products QFP package photos 100-pin plastic QFP 0.65 mm pitch, 14 x 20 mm, 3.0 mm thick 100-pin plastic LQFP 0.5 mm pitch, 14 x 14 mm, 1.4 mm thick 144-pin plastic LQFP 0.5 mm pitch, 20 x 20 mm, 1.4 mm thick 176-pin plastic LQFP 0.5 mm pitch, 24 x 24 mm, 1.4 mm thick FBGA package photos 121-pin plastic FBGA 0.8 mm pitch, 12 x 12 mm, 1.48 mm thick 157-pin plastic FBGA 0.8 mm pitch, 14 x 14 mm, 1.31 mm thick 161-pin plastic FBGA 0.8 mm pitch, 13 x 13 mm, 1.48 mm thick 180-pin plastic FBGA 0.8 mm pitch, 13 x 13 mm, 1.48 mm thick The Eco Symbol mark is applied to products that comply with NEC's environmental standard, which is one of the world's toughest. Such products are antimony-free and use smaller amounts of halogen, and are subject to product assessment and green procurement. 16 Pamphlet U15412EJ1V0PF Pamphlet U15412EJ1V0PF 17 Architecture V850 Common Architecture The V850 Series, which consists of single-chip RISC microcontrollers that use an architecture optimized for embedding, has the following features. 5-stage pipeline processing Support of CISC-like instructions Harvard architecture Multi-status flags 32 general-purpose registers DSP function Simple addressing 32-bit barrel shifter 2-byte basic instruction set 5-stage pipeline processing The V850 Series uses a 5-stage pipeline structure (5 stages from instruction fetch to writeback) that supports simultaneous processing of 5 instructions, thus enabling the execution of almost all instructions in just one clock. Internal system clock Instruction 1 Instruction 2 Instruction 3 Instruction 4 Instruction 5 Instruction 6 IF ID EX MEM WB IF ID IF EX ID IF MEM EX ID IF WB MEM EX ID IF WB MEM EX ID IF Instruction 1 end Instruction 2 end WB MEM EX ID Instruction 3 end WB MEM EX Instruction 4 end WB MEM Instruction 5 end WB Instruction 6 end : Instruction fetch : Instruction decode : Instruction execution : Memory access to target address : Write execution result to register An instruction is executed each clock Harvard architecture The V850 Series uses the Harvard architecture, which is designed so that the instruction bus and data bus can operate completely independently from each other, thereby preventing pipeline operation problems and ensuring efficient instruction execution. In the case of an architecture other than the Harvard architecture, the MEM stage of CPU Instruction fetch Instruction bus BCU instruction 1 and the IF stage of instruction 4, and the MEM stage of instruction 2 and the IF stage of instruction 5 conflict, causing bus waits. This in turn causes the pipeline operation to become disordered and lowers the instruction execution speed. Pipeline Operation of Non-Harvard Architecture Internal ROM External memory Operand data access Data bus On-chip peripheral I/O Instruction1 Instruction2 Instruction 3 Instruction 4 Instruction 5 : Idles inserted due to bus wait IF ID IF EX ID IF MEM WB EX ID IF MEM WB EX ID IF MEM EX ID WB MEM EX WB MEM WB Internal RAM 18 Pamphlet U15412EJ1V0PF 32 general-purpose registers The V850 Series provides 32 general-purpose registers. Along with a hardware environment that is ideal for program execution, the development environment, including compilers, exploits these 32 registers to achieve program generation with superior code efficiency and execution performance. Comparison of Performance/Object Efficiency According to Number of Registers Byte count (bytes) 4000 Execution time (s) 12 For example, looking at the program execution time and code size changes when the number of registers used by the compiler is changed using the servo control module, we can see that the larger the number of registers, the better the program execution speed and the smaller the code size. However, from about 26 registers, the improvement in terms of execution speed and code size becomes smaller, and in the neighborhood of 32 registers, there are no more changes. This is why the V850 Series has been provided with 32 registers as the strict minimum requirement. 3000 9 2000 6 1000 3 0 16 18 20 22 24 Byte count 26 28 30 32 0 Used C program: Servo control module Execution time Number of registers Software register bank The number of registers can be selected from among 22, 26, and 32 as a compiler option to efficiently execute application programs. Unused registers can be used as a software register bank for which save and restore processing is not required during interrupt servicing or task switching, which increases the processing speed. Register bank interrupt Program execution Interrupt servicing instruction execution Actual interrupt servicing time Program execution Save the program counter, etc., to a save register. Execute the interrupt restore instruction. Restore the program counter value, etc., from the save register. Save general-purpose registers to stacks. Restore general-purpose registers from stacks. Normal interrupt Program execution Interrupt servicing instruction execution Actual interrupt servicing time User interrupt servicing routine execution time Total interrupt servicing time Program execution General-purpose register configuration 31 r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 r14 r15 r16 r17 r18 r19 r20 r21 r22 r23 r24 r25 r26 r27 r28 r29 r30 r31 31 PC 0 Zero Register Reserved for Address Generation Stack Pointer(SP) Global Pointer(GP) Text Pointer(TP) Name Application Operation System register configuration Operand Specification LDSR STSR Register for saving status during interrupt Register for saving status during NMI x Interrupt source register Program status word Register for saving status during CALLT execution Register for saving status during exception/debug trap CALLT base pointer x x r0 r1 Zero register Assembler reservation Always holds "0" Used as working register for address generation No. 0 1 2 3 System Register Name EIPC EIPSW FEPC FEPSW ECR PSW CTPC CTPSW DBPC DBPSW CTBP Reserved Application r2 Address/data variable register (If real-time OS being used does not use r2) r3 Stack pointer Global pointer Text pointer Used for stack frame generation during function call Used when accessing global variables in the data area Used as register for specifying the beginning of the text area (program code allocation) Only supported by V850E1 CPU core products supported 4 5 16 17 18 19 20 r4 r5 r6-r29 Element Pointer(EP) Link Pointer(LP) 0 Program Counter Address/data variable register Element pointer Used as base pointer for address generation during memory access Used during function call by compiler r30 6-15, 21-31 x : Access prohibited : Access enabled LDSR: Instruction to load general-purpose register contents to system register STSR: Instruction to store system register contents to general-purpose register r31 PC Link pointer Program counter Holds instruction addresses during program execution Pamphlet U15412EJ1V0PF 19 Simple addressing The increased amount of address calculations in the CPU in the case of complex addressing causes disturbances in the pipeline operation. As a result, address calculation becomes a bottleneck for pipeline processing and raising the frequency to increase the performance becomes difficult. The V850 Series avoids this problem by supporting only simple addressing. Pipeline Processing Time and CPU Operating Frequency In case of excessive addressing In case of simple addressing Pipeline processing sequence Instruction fetch Address calculation Operating frequency held back by slow processing Execution Memory access Writeback All processing is standardized and efficient Processing time Processing time Addressing mode Instruction addresses *Relative addressing (PC dependent) Add 9 signed bits or 22 signed bits of data of the instruction code to the program counter. Example: 22-bit data 31 0 26 25 PC 0 Operand addresses *Register addressing Addressing that accesses the general-purpose register specified by the general-purpose specification field or a system register as an operand. *Immediate addressing Addressing of 5-bit data or 16-bit data for manipulation in the instruction code. 0 disp22 31 Signed extension 22 21 *Based addressing 0 31 reg1 31 Signed extension 16 15 disp16 0 31 0 26 25 PC Addressing that accesses memory, with the sum of the contents of the generalpurpose register (reg1) and 16-bit displacement (disp16) as the operand address. 0 Memory subject to manipulation Memory subject to manipulation *Register addressing (register indirect) Transfer the contents of the general-purpose register specified by the instruction (reg1) to the program counter (PC). 31 26 25 reg1 0 *Bit addressing Addressing that accesses 1 bit of 1 byte of the memory space, with the sum of the contents of the generalpurpose register (reg1) and 16-bit displacement (disp16) that has been sign extended to word length as the operand address. 31 reg1 0 31 Signed extension 16 15 disp16 0 Memory subject to manipulation 31 0 26 25 PC 0 Memory subject to manipulation 2-byte basic instruction set The V850 Series employs a 2-byte instruction code to perform basic processing to enable compact program development equivalent to 16-bit CISC microcontrollers. *Improved object efficiency through ROMization programming Application of 2-byte instructions to all basic processing, consisting of load, store, arithmetic/ logic operations, and branching. Object Code Size Comparison (Dhrystone 1.1/Large model) 16-bitV(CISC) 78K/IV(CISC) V850(RISC) VR/MIPS32(RISC) 1.00 *To realize ease of use, restrictions on 16-bit fixed-length instructions are partially removed through incorporation of 32-bit instructions. *Bit manipulation instructions, etc. 1.03 1.02 1.48 20 Pamphlet U15412EJ1V0PF CISC-like instructions for embedding (bit manipulation instructions) The V850 Series supports bit manipulation instructions suitable for flag manipulation on I/O registers, which play a large role in embedding control. * Improvement of operability of memory mapped I/ Os for control purposes * Manipulation of any 1 bit of byte data in the memory space * Provision of test (tst1)/set (set1)/clear (clr1)/invert (not1) * Effective for reducing object size and execution time since flags can be manipulated in 1-bit units with 1 instruction Object size Execution time 4 bytes 4 clocks 12 bytes 4 clocks Item Coding example Bit Manipulation Instruction set1 Example: Setting (1) bit 6 of ASIM00 register When Used 6, ASIM00[r0] ld.b ori st.b ASIM00[r0], r20 0x0040, r20, r20 r20, ASIM00[r0] When Used add st.w ld.b ori st.b ld.w add -4, sp Save r20 r20, 0[sp] ASIM00[r0], r20 0x0040, r20, r20 r20, ASIM00[r0] 0[sp], r20 Restore r20 4, sp 24 bytes 8 clocks Multi-status flags In the V850 Series, calculation results are reflected in registers as status flags. As a result, delay branching such as can be seen in the RISC microcontrollers of other manufacturers does not occur and programs can be coded with the same feel as CISC microcontrollers. * Easy recording with assembler * Improved object efficiency and execution speed Example: Program that branches to positive/negative/zero according to register contents CISC Microcontroller cmp jz jgt jmp ax, 0 ZERO PLUS MINUS cmp bz bgt br V850 0, r10 ZERO PLUS MINUS Other Manufacturer's RISC Microcontroller cmp/eq bt cmp/pl bt bra nop #0, r10 ZERO r10 PLUS MINUS ;For delay branching ZERO : Zero processing PLUS : Positive processing MINUS : Negative processing DSP function The V850 Series provides a DSP function for executing high-speed calculations and product-sum operations indispensable for digital signal processing such as image and speech processing. * Direct data handling via general-purpose registers * Realization of digital signal processing through generalpurpose CPU * High-speed 16-bit (V850 CPU), 32-bit (V850E1 CPU) multiply/sum-of-products (Multiply: 1 to 2 clocks, sum-of-products: 3 clocks) * Effective for filter operations and matrix operations for feedback calculations in speed, position, and other servo control. Memory V850 CPU SAT flag MUL ALU INT General-purpose register CPU MUL ALU CPU+DSP DSP 32-bit barrel shifter V850 Series can realize bit manipulations frequently used during signed data and image data processing in 1 instruction per clock. * Shifting of any number of bits (0 to 31) executable in 1 instruction per clock Improved execution speed/object efficiency Effective for extracting arbitrary bit lengths of image data and signed data (extracting code during MH/MR/MMR encoding, etc.) Example: 27-bit logical right shift Other manufacturer's V850 RISC microcontroller Processing sequence SHR16 SHR8 SHR2 SHR 4 4 Rn Rn Rn Rn Number of instructions 1 SHR 27, Rn Number of execution clocks 1 Pamphlet U15412EJ1V0PF 21 Strengths of V850E1 and V850ES Cores The V850E1 and V850ES cores are CPU cores that enhance the functions of the V850 core. V850E1 core Higher performance and improved operating frequency of 50 to 100 MHz Improved external memory access function Improved code efficiency (10 to 15% higher than V850 core) *Addition of C language compatible instructions (Switch instruction, CALLT instruction, etc.) High performance high-end lineup (V850E products), system-on-chip core lineup V850ES core Next-generation CPU core of low-end lineup Support of lower voltage for V850/Sxx products Improved code efficiency through use of same architecture as V850E1 (10 to 15% higher than V850 core) CPU Core Function Maximum operating frequency Maximum program memory space Maximum data memory space Higher performance 20/33 MHz 16 MB 16 MB V850 20 MHz 16 MB 16 MB V850ES 50 V850E1 100MHz 64 MB 256 MB Use of 5-stage pipeline Use of Harvard architecture Improvement of pipeline * Non-blocking load/store Parallel execution of instructions (during instruction execution in internal ROM) * Addition of branch/load pipes * Shift to 3-operand manipulations in 1 slot Higher code efficiency Use of 2-byte instructions Use of CISC instructions Addition of C language compatible instructions (Addition of Switch instruction, Callt instruction, data conversion instruction, Prepare/Dispose instruction) Multiplier 16 x 16 bit 32 bit 16 x 16 bit 32 bit (32-bit multiply instruction support) 4 to 10 clocks 32 x 32 bit 64 bit Interrupt responsiveness 11 to 18 clocks 22 Pamphlet U15412EJ1V0PF Employment as ASIC CPU Cores Smooth transition to ASIC microcontroller development using V850E1 CPU cores 1. Introduction to market with short TAT through use of standard V850E1 products 2. Optimization of system through switch to ASIC Easy securing of compatibility from traditional systems made into ASICs through use of same device development methods for both standard products and ASIC microcontrollers Development of CPU cores bearing in mind shift to ASIC Software debugging support Release of CPU core that supports on-chip debugging through full-function in-circuit emulator, JTAG method (N-Wire ICE) and on-chip debugging with trace function Internal system bus configuration Independent high-speed 32-bit synchronous system bus and 16-bit asynchronous bus for low-speed peripheral function macro connection, realizing both high-speed processing, low-power consumption and easy design Provision of large assortment of peripheral function macros Cache memory, memory controller, ROM/RAM, USB, etc. Covering required performance and power consumption through support of a large variety of processes Process 0.35m 0.25m 0.13m Cell-based IC family CB-9VX CB-10VX CB-12 V850E1 core Realization of excellent performance/power ratio of 827 MIPS/W for 100 MHz Max. (at 2.5 V operation) Improved object efficiency A flexible and high-performance bus system can be configured through independent buses such as a high-speed system bus that enables 400 MB/s data transfer and a low-speed peripheral macro connection bus. Support of on-chip debugging function V850E1 core DBG I/F V850E/MA1 block configuration V850E1Core RCU INTC iROM I/F (32bit/1clk) iRAM I/F (32bit/1clk) DMA BCU TEST Ctrl CPU BBR INT(64ch) Peripheral Bus (16bit/asynchronous) ROM (256KB) RCU INTC CPU BBR INT Timer UART CSI 32x32 MUL Peripheral Bus 32 x 32 MUL System Bus PWM System Bus (32bit/1clk) RAM (10KB) DMA BCU TEST Ctrl PORT A/D iCACHE I/F dCACHE I/F Test Bus Test Bus MEMC Pamphlet U15412EJ1V0PF 23 V850E1, V850ES architecture The V850E1 and V850ES cores achieve high performance and higher code efficiency through the implementation of the following improvements to the V850 CPU core. Non-blocking load/store * Improved bus use efficiency * Shorter interrupt insensitivity period Addition of branch/load pipes * 2-clock branching * Parallel execution of instructions Shift to 3-operand manipulations in 1 slot * Improved absolute performance * Example: Synchronous processing of mov + add Addition of high-level language-compatible instructions * Improved code efficiency * 10 to 15% improvement in object efficiency mainly when C compiler used Pipeline configuration Master Pipeline (V850 CPU compatible) ID IF br/sld Pipeline ID Address calculation stage EX DF WB Non-blocking load/store Conventional (V850 CPU) Pipeline is stopped until MEM stage complete Load instruction ADD instruction Next instruction V850E1 CPU Load instruction ADD instruction Next instruction IF ID IF EX ID IF MEM (external memory) T1 T2 T3 EX ID WB (MEM) EX WB MEM WB Async WB Pipeline MEM WB Load, store buffer (1 stage each) Effective pipeline processing that uses the Async WB Pipeline when appropriate, according to the instruction. IF ID IF EX ID IF MEM (external memory) T1 T2 EX ID DF EX WB WB MEM WB IF (instruction fetch) ID (Instruction decode) EX (ALU, multiplier, barrel shifter execution) MEM (Memory access) WB (Writeback) DF (data fetch) : Fetches instructions and increments the fetch pointer. : Decodes instructions, creates immediate data, and reads registers. : Executes decoded instructions. : Accesses memory of corresponding addresses. : Writes execution results to registers. : Transfers execution data to WB stage. Addition of branch/load pipes *Pipeline operation with branch instruction Conventional (V850 CPU) Branch instruction Branch destination determined in EX stage *Parallel instruction execution (when executed by internal ROM) Conventional (V850 CPU) ADD instruction (16-bit length) Branch instruction (16-bit length) IF ID EX ID (MEM) EX WB MEM IF WB ID EX MEM IF ID EX MEM WB Branch destination instruction IF ID EX MEM WB Next instruction Branch destination determined in ID stage V850E1 CPU 1-clock reduction Branch instruction IF ID MEM WB V850E1 CPU ADD instruction Branch instruction IF ID ID EX MEM IF DF WB ID 2-clock reduction WB Branch destination instruction IF ID EX MEM WB Next instruction EX MEM WB * The next branch instruction code is also fetched due to the internal 32-bit bus. Shift to 3-operand manipulations in 1 slot Conventional (V850 CPU) mov add r20(src2), r22(src2), r21(dst) r21(dst) * Sequence from mov to arithmetic instruction is detected in the ID stage, and if dst is the same, the next manipulation is performed. src1 src2 dst : Replace with src2 of mov : src2 of arithmetic instruction : As is * mov + add instructions executable in 1 clock V850E1 CPU add r22(src2), r20(src1), r21(dst) 24 Pamphlet U15412EJ1V0PF Addition of high-level language compatible instructions The V850E1 and V850ES cores have enhanced the instruction set of the V850 core as follows. switch (2 bytes) unsigned Load * Reduction of unsigned manipulation code mov imm32, reg (6 bytes/2 clocks) * Reduction of address setting code mul/mulu (4 bytes) * Reduction of array address calculation * Improvement of sum-of-products performance Other * Bit manipulation (register indirect bit specification) * cmov (Conditional Move), divide (div/divu/divhu) * sasf, endian conversion * C language switch statement processing converted into instruction callt (2 bytes)/ctret (4 bytes) * Table-reference branching * Reducing size of call code that frequently appears Data conversion instructions (2 bytes) * char, short type cast executed with 1 instruction * sxh, sxb, zxb, and zxh instructions prepare/dispose (4 bytes) * Function start/end processing executed in 1 instruction switch R (table-reference branching) <1> Adds the table start address and double the register value. <2> Sign extends halfword entry data indicated by the address generated in <1> to word length, doubles it, and adds the table start address to generate a 32-bit address. <3> Branches to target address generated in <2>. callt N (Table-reference subroutine calling) 15 0 PC PC+2 switch R entry 0 entry 1 entry 2 *** <2> CTBP+2N <1> PC+2+2n CPU Item Coding example V850E1 switch r10 movhi movea shl add ld.h add jmp 22 bytes 9 clocks V850 hi (L267), zero, r9 lo (L267), r9, r9 1, r10 r9, r10 0[r10], r10 r9, r10 [r10] entry N PC CTPC CTBP+(unsigned(entry data)) <4> *** PC+2+2y <3> *** <2> entry n <1> <1> <3> Target Target PSW CTPSW : Program counter : Program status word : Register to save status during CALLT execution CTPSW : Register to save status during CALLT execution CTBP : CALLT base pointer N : 0 to 63 PC PSW CTPC Object size Execution time 2 bytes 5 clocks PC : Program counter R : General-purpose register n : General-purpose register (R) value y : signed(entry data) Bytes 600 V850E1 Core and V850ES Core vs. V850 Core Code Size Comparison Internal system clock Interrupt request Instruction 1 IF ID IFx Interrupt Response Time 500 EX IDx MEM WB 400 Instruction 2 300 Interrupt acknowledgement operation Interrupt servicing routine INT1 4 system clocks INT2 INT3 IF INT4 ID EX MEM WB 200 100 0 A B C D E F G H I J K System registers for saving the PC and PSW are provided and high-speed branching to the interrupt program is performed, except under the following conditions. * In IDLE/STOP mode * In case of consecutive interrupt request non-sample instructions * During external bus access * During access to the interrupt control register Remark INT1 to INT4 : Interrupt acknowledgement processing IFx : Invalid instruction fetch IDx : Invalid instruction decode V850 core V850E1 core, V850ES core Measurement program Pamphlet U15412EJ1V0PF *** 2n <1> Transfers the restored PC and PSW values to CTPC and CTPSW. <2> Adds the CTBP value and 2N to generate a 32-bit table entry address. <3> Loads the halfword of the address generated in <2> and adds the CTBP value to the value 0 extended to word length to generate the 32-bit target address. <4> Branches to the address generated in <3>. CTBP 15 0 entry 0 2N entry 1 entry 2 25 Middleware Performance Measurement conditions Common CPU Bus width : V850 core (33 MHz) Measurement results are frequency-converted values (50 MHz). : 16 bits Number of waits : 1 (The basic bus cycle is 3 clocks, so 1 bus cycle = 4 clocks.) Compiler Tool : CA850 : V850 in-circuit emulator (IE) (product of NEC) MH/MR/MMR * Internal ROM : Program stacks (including I/O parameters) * External memory (SRAM) : Encoding/decoding table, change point table, JBIG * Internal ROM : Program (including probability assumption table (1 KB)) * External memory (SRAM) : Learning table, stacks (including I/O parameters) V850 MH Method -- A4 100 dpi Compression Decompression V850 MR (K = 4) Method -- A4 100 dpi chart7 0.15s 0.11s chart8 0.10s 0.07s Compression Decompression Seconds chart1 0.06s 0.06s chart2 0.06s 0.05s chart3 0.09s 0.08s chart4 0.14s 0.12s chart5 0.09s 0.08s chart6 0.08s 0.07s chart1 0.07s 0.07s chart2 0.06s 0.06s chart3 0.10s 0.10s chart4 0.17s 0.16s chart5 0.11s 0.10s Seconds 0.20 0.18 0.16 0.14 0.12 0.10 0.08 0.06 0.04 0.02 0.00 chart6 0.09s 0.08s chart7 0.18s 0.15s chart8 0.11s 0.08s Compression Decompression Compression Seconds 0.16 0.14 0.12 0.10 0.08 0.06 0.04 0.02 0.00 1 2 3 4 5 6 7 8 chart Decompression Seconds 0.16 0.14 0.12 0.10 0.08 0.06 0.04 0.02 0.00 1 2 3 4 5 6 7 8 chart 0.20 0.18 0.16 0.14 0.12 0.10 0.08 0.06 0.04 0.02 0.00 1 2 3 4 5 6 7 8 chart 1 2 3 4 5 6 7 8 chart V850 MMR Method -- A4 100 dpi V850 JBIG Method -- A4 100 dpi (Layer=Lowest, TPBON=ON, AT=default) chart7 0.18s 0.16s chart8 0.11s 0.08s Compression LRLTWO=OFF LRLTWO=ON Decompression LRLTWO=OFF LRLTWO=ON Seconds 1.00 Compression Decompression chart1 0.07s 0.07s chart2 0.06s 0.05s chart3 0.11s 0.10s chart4 0.18s 0.17s chart5 0.11s 0.10s chart6 0.09s 0.07s chart1 0.41s 0.38s 0.46s 0.43s chart2 0.52s 0.48s 0.59s 0.57s chart3 0.63s 0.58s 0.73s 0.68s chart4 0.84s 0.76s 0.96s 0.89s Seconds 1.00 chart5 0.62s 0.57s 0.72s 0.68s chart6 0.57s 0.52s 0.67s 0.63s chart7 0.85s 0.78s 1.02s 0.93s chart8 0.90s 0.83s 1.04s 0.97s Seconds 0.20 0.18 0.16 0.14 0.12 0.10 0.08 0.06 0.04 0.02 0.00 1 2 Compression Seconds 0.20 0.18 0.16 0.14 0.12 0.10 0.08 0.06 0.04 0.02 0.00 Decompression Compression Decompression 0.80 0.80 0.60 0.60 0.40 0.40 0.20 0.20 0.00 1 2 3 4 5 6 7 8 chart 1 2 3 4 5 6 7 8 chart 0.00 1 2 3 4 5 6 LRLTWO=ON 7 8 chart 3 4 5 6 7 8 chart LRLTWO=OFF LRLTWO=ON LRLTWO=OFF JPEG Internal ROM Internal RAM Data I/O : Program : Stack, work area (one part) Sample ratio 4:1:1 (Quality75) 4:2:2 (Quality75) V850 JPEG Method Processing Time QVGA(320x240x24) VGA(640x480x24) Compression Decompression Compression Decompression 0.27s 0.33s 0.21s 0.26s 1.09s 1.33s 0.85s 1.04s External memory (SRAM) : Data and remaining work area : RGB 26 Pamphlet U15412EJ1V0PF Variety of Peripheral Functions Memory Access Functions SDRAM controller Products: V850E/MA1, MA2 SDRAM connectable without external circuit CAS latency: 2, 3 supported CBR refresh, CBR self refresh supported DRAM controller Products: V850E/MS1, MS2, MA1 EDO DRAM directly connectable without external circuit 2CAS type DRAM supported CBR refresh, CBR self refresh supported A1 to A12 A21, A22Note D0 to D15 SDCLK SDCKE CSn SDRAS SDCAS LDQM UDQM WE V850E/MA1 A0 to A11 A12, A13 DQ0 to DQ15 CLK CKE CS RAS CAS LDQM UDQM WE 64 Mb SDRAM (1 Mword x 16 bits x 4 banks) A1 to A12 D0 to D15 RASn LCAS UCAS WE OE V850E/MA1 A0 to A11 I/O1 to I/O16 RAS LCAS UCAS WE OE 64 Mb DRAM (4 Mword x 16 bits) Note The address signal used differs depending on the SDRAM product. DMA controller (provided in V850E products) Products: V850E/MA1, MA2, MS1, MS2, IA1, IA2 Transfer targets: Memory-peripheral I/O, memory-memory Single, single step, block transfer 8-/16-bit data units Transfer type: 1-cycle transfer, 2-cycle transfer Number of transfers: 65,536 Max. DMA controller (provided in V850/Sxx products) Products: V850/SA1, SB1, SB2, SV1, SF1, SC1, SC2, SC3 Transfer targets: Internal RAM-on-chip peripheral I/O Single transfer 8-/16-bit data units Transfer clock: 4 clocks Min. Number of transfers: 256 Max. On-chip peripheral bus CPU core External I/O DMA Bus interface On-chip peripheral I/O CPU core Internal bus Internal RAM Data control Address control Count control Channel control On-chip peripheral I/O Internal RAM 8/16bit-data External RAM 8-/16-bit bus External ROM DMA Transfer source address Transfer destination address Number of transfers Pamphlet U15412EJ1V0PF 27 A/D Converters Multi-stage buffer type Products: V853, V850/SV1, V850E/MA1, IA1, IA2, MS1 Conversion can be started by both software and hardware Eight conversion result registers are incorporated Select/scan modes can be switched ANI0 *********** Scan mode ANI0 (Input) ANI1 (Input) Tap selector Resistor string Selector AVREF ANI2 (Input) AVSS ANIn Successive approximation register ANI3 (Input) INTAD ADTRG Conversion controller A/D conversion Conversion result register 0 Conversion result register 1 Conversion result register 2 Conversion result register 3 Conversion result register 4 Conversion result register 5 Conversion result register 6 Conversion result register 7 Conversion result registers Select mode operation ANI1 (Input) A/D conversion Conversion result registers INTAD interrupt Analog input ANI0 ANI1 ANI2 ANI3 ANI4 ANI5 ANI6 ANI7 ;;;;; ; ;;;;; ;;;; ;;;;; ; ;;; Data 4 Data 1 Data 2 Data 3 Data 5 Data 6 Data 7 Data 1 (ANI1) Data 2 (ANI1) Data 3 (ANI1) Data 4 (ANI1) Data 5 (ANI1) Data 6 (ANI1) Data 7 (ANI1) Data 1 (ANI1) Data 2 (ANI1) Data 3 (ANI1) Data 4 (ANI1) Data 6 (ANI1) Conversion start Control bit Control bit Control bit Control bit Conversion start Control bit (Conversion result set set set set (Conversion result set register setting) register setting) Conversion result registers Conversion result register 0 Conversion result register 1 Conversion result register 2 A/D converter Conversion result register 3 Conversion result register 4 Conversion result register 5 Conversion result register 6 Conversion result register 7 INTAD interrupt ;;;;; ;;;; ;; ;;;;; ;;; ; ;;; Data 1 Data 5 Data 6 Data 2 Data 7 Data 3 Data 4 Data 1 (ANI0) Data 2 (ANI1) Data 3 (ANI2) Data 4 (ANI3) Data 5 (ANI0) Data 6 (ANI0) Data 7 (ANI1) Data 1 (ANI0) Data 2 (ANI1) Data 3 (ANI2) Data 4 (ANI3) Data 6 (ANI0) Conversion Conversion Conversion result result result register 0 register 1 register 2 Conversion result register 3 Conversion result register 0 Conversion start (Control register setting) Conversion start (Control register setting) Analog input Conversion result registers ANI0 ANI1 ANI2 ANI3 ANI4 ANI5 ANI6 ANI7 A/D converter Conversion result register 0 Conversion result register 1 Conversion result register 2 Conversion result register 3 Conversion result register 4 Conversion result register 5 Conversion result register 6 Conversion result register 7 28 Pamphlet U15412EJ1V0PF Timer/Counter Functions 24-bit servo timer Product: V850/SV1 24-bit timer unit for servo control Capture registers: 4 Compare registers: 2 External input detector with 1-64/1-128 divider PWM Product: V850/SV1 12- to 16-bit PWM output Main pulse + additional pulse configuration Main pulse: 4/5/6/7/8 bits Additional pulse: 8 bits Active level of PWM output pulse selectable Clear count control Tim Count clock INTCPn0 Selector 24-bit timer Selector INTOVm INTTIm PWM module register PWM module register (higher 8 bits) (lower 8 bits) Reload controller Selector OVFn Capture register 0 Selector INTCPn1 Vsync INTCPn2 1-64 division Capture register 1 Count clock m bit down counter (m = 4 to 8) m PWM pulse generator 8-bit counter 1-64 division Capture register 2 Capture register 3 Compare register 1 Compare register 2 INTCMm0 RTP INTCMm1 INTCPm0-9 1/2 Output controller PWMn Selector 1-128 division INTCPn3 3-phase inverter control timer Products: V850E/IA1, IA2 3-phase PWM output function Symmetric triangular wave, asymmetric triangular wave, sawtooth wave Interrupt culling function Culling rate: 1/1, 1/2, 1/3, 1/4, 1/8, 1/16 3-phase PWM forcible output stop function Real-time output function Count clock Compare buffer register Compare register 3 Output controller Up/down counter Products: V850E/IA1, IA2 16-bit 2-phase encoder input supported Compare registers: 2 Capture/compare registers: 2 Compare capture register INTCC0 16-bit timer Deadtime timer Compare capture register TCLR INTCC1 Edge detector Compare buffer register Compare register 0 Deadtime generator TO0 TCUD TO1 Selector 16-bit up/down counter timer CLR circuit Output control Compare register TO Compare buffer register Compare register 1 Deadtime generator TO2 TO3 TIUD Compare register INTCM0 Compare buffer register Compare register 2 INTCM1 Deadtime generator TO4 TO5 Pamphlet U15412EJ1V0PF 29 Serial Interface Variable-length serial interface Products: V850/SB1, SB2, SV1, SF1, SC1, SC2, SC3 3-wire serial I/O Data length switchable between 8 bits and 16 bits Start bit switchable between MSB and LSB 8-/16-bit serial interface Products: V850/SC1, SC2, SC3, V850E/IA1, IA2 3-wire serial I/O Data length switchable between 8 bits and 16 bits Start bit switchable between MSB and LSB MSB/LSB controller SIn 8-/16-bit variable-length shift register Counter clock SCKn Selector BRG SCKn Serial clock controller Interrupt controller INTCSIn SOn Serial clock counter (8/16 counting switchable) SCKn Interrupt controller SIn INTCSIn 8-bit shift register L 8-bit shift register H SOn Serial clock controller Selector BRG IEBus controller Products: V850/SB2, SC2 Supports communication mode 1 Maximum number of transfer bytes: 32 bytes/frame Maximum transfer speed: Approx. 17 Kbps CAN Products: V850E/IA1, V850/SF1, SC3 CAN protocol Ver. 2.0 Part B (Transmission/reception of standard and extended frames) Maximum transfer rate: 1 Mbps 32 message buffers Register block Transmission block Reception block Bit controller Field controller CANTX1 CAN receiver 1 CANRX1 CANTX2 CAN receiver 2 CANRX2 CAN module 2 CAN module 1 MAC (Memory Access Controller) Controller Interrupt request IETX IERX CAN RAM Message buffer 0 Message buffer 31 Control block Interrupt request Note The number of channels differs depending on the product. 30 Pamphlet U15412EJ1V0PF Distinctive Peripheral Functions of V850 Watch timer Products: V850/SB1, SB2, SV1, SC1, SC2, SC3 0.5-second interrupt generation using watch timer function Interval timer supported Hsync/Vsync separator Product: V850/SV1 Separation of Vsync (vertical) signal and Hsync (horizontal) signal from decoding sync signal of VCR Odd/even field discrimination Hsync mask signal HSOUT0 (Detected Hsync) Hsync separator HSOUT1 (Compensated Hsync) Selector Selector Selector fxx (main clock) fxt (subclock) 5-bit counter INTWTN CSYNCIN Edge switching Vsync separator IHsync detection 11-bit prescaler Odd/even field discrimination flag Count clock Selector Selector INTWTNI VSOUT(Vsync) Division by 2 ROM correction function Products: V850/SB1, SB2, SV1, SF1, SC1, SC2, SC3 Substitutes JMP r0 instruction for instruction of address to be corrected and branches to 0000H Program can be modified following creation of mask ROM Correction addresses: 4 points ROM correction operation RESET Internal ROM Normal flow ROM correction request flag = 0? no Clear ROM correction request flag ROM correction flow Instruction address bus ROM correction address register Yes Initialization Download correction program Jump to correction program Internal RAM Correction program execution Internal ROM (Max. 1 MB space) Comparator JMP r0 instruction generator Download correction program External ROM EEPROMTM, etc. Correction address enable setting information Write correction program to RAM Setting correction address and enabling ROM correction Correction address = XXXX ROM correction enable flag = 1 Return to internal ROM Output trigger controller Instruction replacement block Replace with JMP[r0] instruction Correction point Instruction data bus Next processing... Main routine Pamphlet U15412EJ1V0PF 31 Low Power & Low Noise Low Power Consumption Measures Low-power-consuming, high-speed microcontrollers are required for portable devices and battery-operated devices such as DVCs and cellular phones. The V850 Series incorporates various functions to lower the power consumption. Superior power performance The V850ES and V850/Sxx products feature a thorough power-saving design that realizes a superb power/performance ratio of 1.1 to 0.7 mA/MIPS. As a result, these products realize a low consumption current only one fifth that of a 16-bit CISC microcontroller of comparable performance. By featuring such extremely high power performance, these products enable the simultaneous realization of lower power consumption and more sophisticated functions in various systems. mA/MIPS 10 8-bit CISC 9.2mA/MIPS 7.3mA/MIPS Low power consumption 1/5 that of 16-bit CISC of comparable performance 16-bit CISC 5 1.1mA/MIPS 1.1mA/MIPS V850/SV1 V850/SB1 0.9mA/MIPS V850/SA1 0 Clock gear function The V850/Sxx products come with two oscillators: a main clock and a subclock. 1/1/, 1/2, 1/4, or 1/8 of the main clock or the subclockNote can be selected as the CPU operating clock, making it possible to minimize the power consumption according to the system's operating status. Note Not selectable in V850/SV1 Current consumption Approx. 70% reduction through clock gear Standby mode An efficient low-power-consumption system can be realized by using the three standby modes, STOP, IDLE, and HALT, according to the usage purpose. ;; ;; 0.7mA/MIPS Consumption current/performance V850ES/SA2, 3* *: Under development Operation modes Operation status of each mode CPU Peripheral Watch functions timer Oscillator Main Sub clock clock Normal operation mode HALT mode IDLE mode STOP mode Approx. 1/2 Approx. 1/10 Approx. 1/100 Current consumption reduced to 1/100 or lower! Further reduction to 1/20 through subclock operation Operating clock fxx (20MHz) fxx/8 fxt (32.768kHz) Current consumption Operating Stopped Function to cut voltage between A/D converter VREF and resistor string Voltage application to the A/D converter's resistor string can be switched on and off. The power consumption can be minimized by switching off voltage application to the resistor string when the A/D converter is not used. * Main products: V850/SB1, SB2, SC1, SC2, SC3, SF1 ON/OFF AVDD ANI0 *********** Tap selector Resistor string Successive approximation register Conversion controller Conversion result register ANIn Selector AVREF AVSS ADTRG INTAD 32 Pamphlet U15412EJ1V0PF EMI Countermeasures Minimizing the influence of electromagnetic interference (EMI) from the microcontroller in AV equipment such as car audio systems is a major requirement, making the reduction of EMI one of the highest technological priorities for microcontroller manufacturers. Various EMI countermeasures are implemented in the V850 Series. EMI countermeasures for individual chip Noise reduction measures focussing on the following three points are implemented as noise countermeasures in individual V850 Series chips. Reduction of noise generation * Use of low-voltage internal logic power supply * Optimization of oscillator Reduction of noise propagation * Separation of internal logic sound source and power supply of pins * Reduction of cross talk between different power supply wires Confining of noise inside * On-chip decoupling capacitor between power supply Example for V850/SB1, 2, SF1, SC1, 2, 3 Phase 1 V850/SB1 1st Ver. Phase 2 V850/SB1 A products Phase 3 V850/SB2 A products Phase4 V850/SF1 Phase5 V850/SBx B products V850/SCx Decoupling capacitor Increased on-chip capacitance 600pF 6000pF Separation of power supply and GND for port controller 10 dBm reduction 5 dBm reduction Separation of power supply and GND for oscillator Elimination of VDD protection element Optimization of output buffer Change of regulator voltage 10 dBm reduction (3.3V 3.0V) Insertion of bypass capacitor Optimization of operating frequency Internal regulator operation Separation of power supply circuit Noise (dBm) and GND inside microcontroller * Separation of power supply and GND for oscillator Standardization of evaluation methods (1/2) There are no rules regarding the EMI measurement testing method for individual microcontrollers. NEC aims to standardize evaluation circuit constants through the use of a standalone EMI evaluation board and evaluate products in a measuring environment that uses a shielded room and power supply filters. This approach enables the evaluation of different products (8-bit and 16-bit NEC CISC microcontrollers, etc.) in the same environment. Standalone EMI evaluation board Standalone EMI evaluation board measurement environment Spectrum analyzer Shielded room Probe Evaluation points Power supply +- Evaluation board Filter +- + - Pamphlet U15412EJ1V0PF 33 Standardization of evaluation methods (2/2) EMI evaluation results A comparison of the EMI evaluation results for Phase 2 products (V850/SB1 A products) and Phase 4 products (V850/SF1) is shown below. Product Name Measurement Point Phase 2 (V850/SB1 A Products) Phase 4 (V850/SF1) VDD 10dB 10dB Noise [dBm] 70 75 80 85 90 95 100 105 110 115 120 Noise [dBm] 70 75 80 85 90 95 100 105 110 115 120 Frequency [MHz] Frequency [MHz] Port 10dB 10dB Noise [dBm] 70 75 80 85 90 95 100 105 110 115 120 Noise [dBm] 70 75 80 85 90 95 100 105 110 115 120 Frequency [MHz] Frequency [MHz] Remark Oscillation frequency = 16 MHz Evaluation of characteristics using radio system board (1/2) In addition to EMI measurement using a standalone EMI evaluation board, NEC has also established an evaluation method employing set evaluation criteria using a radio system board. Since the evaluation results obtained with the radio evaluation board match the evaluation method established by the customer, the influence of EMI can be judged directly. Radio system board Radio system board measurement environment Tuner pack Audio output Electronic volume Audio amp Antenna Audio analyzer Power supply Signal generator - + 12 V power supply CPU board Coaxial cable Output Dummy load (4) Antenna Frequency to be modulated : 400 Hz Frequency deviation : 30% (22.5 kHz) RF signal output level : 60 dB V Output impedance : 75 LCD & key panel Audio output level : 0.5 W Radio system board 34 Pamphlet U15412EJ1V0PF Evaluation of characteristics using radio system board (2/2) Radio system board block diagram Audio amp + ---+ ---+ ---+ ---Analog 12 V Analog GND 0.1 Fx 4 Electronic volume LF RF LR RR Tuner pack L output R output Tuner 9V Tuner GND Analog 9V I2C bus Analog GND 0.027Fx2 3-wire SIO PLL CE Mute Digital 5V Microcontroller Digital GND LCD & keyboard LCD panel LCD driver Key matrix 3-wire SIO Strobe KEY REQ Digital 5V Digital GND CPU board Tuner Pack Electrical Specifications Parameter Audio S/N ratio Operational sensitivity MIN. 51 TYP. 58 6 MAX. 10 Unit dB dB V CPU board block diagram Noise-reduction element insertion location DIP switches Digital 5V AVDD AVSS BVDD BVSS EVDD EVSS VDD VSS REGC Digital GND 1F 0.33 H X1 V850/SBx SIO4 P37(CE) SIO3 P31 (Strobe) P01 (KEY REQ) P35 (Mute) RESET X2 PLL IC Digital 5V 1 kx2 SCL0 SDA0 Electronic volume IC P40-47 P50-57 LCD driver IC Audio amp IC Reset signal V850/SBx CPU board Results of characteristics evaluation using radio system board The EMI reduction efficiency can be ascertained with a radio system board in the same way as standalone microcontroller evaluation. Product Name Operational Sensivity [dBuV] Phase 5 (V850/SB1 B Products) Operational Sensivity [dBuV] Phase 3 (V850/SB2 A Products) 30 25 20 15 10 5 0 -5 85 90 95 100 Frequency [MHz] 105 110 16-Bit Microcontroller from Other Company Operational Sensivity [dBuV] fXX=12MHz 30 25 20 15 10 5 0 -5 85 90 95 100 Frequency [MHz] 105 110 30 25 20 15 10 5 0 -5 85 90 95 100 Frequency [MHz] 105 110 Product Name fXX=16MHz Operational Sensivity [dBuV] Phase 4 (V850/SF1) 25 20 15 10 5 0 -5 85 90 95 100 105 110 Operational Sensivity [dBuV] Phase 2 (V850/SB1 A Products) 30 25 20 15 10 5 0 -5 85 90 95 100 105 110 16-Bit Microcontroller from Other Company Operational Sensivity [dBuV] 30 30 25 20 15 10 5 0 -5 85 90 95 Frequency [MHz] 100 105 110 Frequency [MHz] Frequency [MHz] Remark fxx : Oscillation frequency Pamphlet U15412EJ1V0PF 35 Middleware Middleware Development System NEC is developing a range of middleware products suitable to processors for various systems. NEC middleware is realized by original NEC technology, superior thirdparty technology, and established standards. Standard specifications Original NEC technology Cooperation with third parties Middleware Development Communications MPEG7 MPEG-4 Video JPEG2000 Multimedia Development support system Planning System proposal Demonstration Performance evaluation 2001 USB WMA ATRAC3 Security Internet V.90 MP3 IrDA Echo canceller AAC Creation of middleware Accumulation of solutions Processor lineup Music source for incoming-call melody AMR XML MPEG-4 CELP TrueSpeechTM 8.5 Browser G.723/729 MH/MR/MMR POP/SMTP ADPCM HTTP JBIG JPEG PPP Speech recognition (Japanese) JAVA TM Information search WAP Image recognition Feasibility study V850 Series RISC Separation of hardware/software Next-generation processor Development Assembly support Customization Development completed Human interface TCP/IP Handwriting recognition (Japanese) Speech recognition (English (US)) Agent system Mass production Text To Speech (Japanese) Development completed 2001 JPEG Conforms to JPEG international standard Conforms to DCT baseline process (non-reverse coding) V850 Series Speech Recognition The V850 Series uses internal memory and peripheral I/Os to realize speech recognition on one chip. This makes this series ideal for applications that require speech recognition in sets with large constraints, such as games and home appliances. Speech recognition realized using just the internal memory and peripheral I/Os of V850 Series Increased number of recognized words Number of recognized words: 30 (for V850/SA1, 20 MHz) V850 Series Speech recognition system configuration example Versatile compression and decompression processing JPEG Performance Processing Time CPU V850E/MS1 (33MHz)Note Sample Ratio 4:1:1 (Quality75) QVGA (320x240x24) Compression Decompression 0.32s 0.24s VGA (640x480x24) Compression Decompression 1.3s 0.97s V850/SA1 (internal 20 MHz) Internal ROM Internal RAM LPF Mic/amp A/D(1ch) Increased number of recognized words Parent dictionary Child dictionary 1 Memory Capacity ROM/RAM ROM Table RAM Description Program Capacity Approx. 25 KB Approx. 62 KB Note Programs are placed in internal ROM, and stack and work areas (one part) are placed in internal RAM. Data and the remaining work area are placed in external RAM. Thomas, Richard, Harriet... Memory ROM Compression Decompression 10KB 7.5KB RAM Compression Decompression 5KB 10KB Friends Company Reservations * * * Child dictionary 2 Ms. Smith, Ms. Jones, Mr. Wang... Child dictionary 3 Recognition dictionary (in case of 20 words) Approx. 0.8 KB Note1 Work area (in case of 20 words) Approx. 4.0 KB Note2 Stack area Approx. 0.4 KB ANA, JAL, ticket... Notes 1. Figure using average of 5 letters per word to calculate standard dictionary size. 2. The variable work area is proportional to the number of recognized words. Speech recognition evaluation system In introducing speech recognition, NEC has provided an environment that allows easy evaluation. For details about this system or how to purchase it, contact NEC. 36 Pamphlet U15412EJ1V0PF Handwriting Recognition (Japanese Only) Easy to use because of flexibility regarding stroke order and count Pattern matching method based on "non-linear normalization matching method" Conversion of pen-drawn lines into image Text to Speech (TTS) (For Japanese Text) Speech synthesized from Japanese Kana and Kanji texts (SJIS code) Versatile speech synthesis Synthesis of male and female voices (2 types) Various parameters such as intonation and reading speed can be adjusted. High recognition rate, high-speed recognition Recognition of 95% or higher in 0.1 s (V85x: 25 MHz) Support of up to JIS No. 2 standard JIS No. 1 Standard: Approx. 3,400 characters, JIS No. 2 Standard: Approx. 800 characters TTS rhythm data (pitch, phoneme duration) can be designed (Support of Speech Designer) TTS using natural rhythm possible (synthesis of more natural sounding speech) New characters can be added (pictographs, etc., can be freely added) A dictionary can be created from character data using a dictionary compilation tool. Support of characters with special readings (character readings can be set using the user dictionary) Synthesis speed (V853: 25 MHz) Speech: Between 1.9 sNote and 3 s; Text analysis: 163 ms; speech generation: 1,709 ms Note Varies depending on the input character string. ROM/RAM ROM Description Program Dictionary data (approx. 4,200 characters) Data Capacity Approx. 60 KB Approx. 450 KB Approx. 60 KB Approx. 32 KB Approx. 2 KB ROM/RAM ROM Description Program data Dictionary data (approx. 80,000 words) Phoneme data Capacity Approx. 103 KB Approx. 1.2 MB Approx. 670 KB to 1.4 MB Approx. 160 KB Approx. 256 KB Approx. 8 KB x n blocks RAM Work area Stack area RAM Work area Stack area Speech output buffer Middleware Product List Middleware list Category Image Middleware MH/MR/MMR JBIG JPEG Text To Speech Japanese Speech CODEC G.726 (ADPCM) Speech recognition Japanese (small vocabulary) Speech recognition English (US) (small vocabulary) Handwriting recognition Japanese (input frame required) Browser TCP/IP IrDA protocol stack USB IEEE1394 PCMCIA/CF card PC-compatible file system Font V850 Series Speech Recognition Internet Drivers Other Remarks 1. 2. 3. : Development completed; : Under development; : In planning Third-party products included. For details about middleware products, refer to the following http://www.ic.nec.co.jp/apsoft/english/middle_top.html Middleware performance Middleware MH/MR/MMR JBIG JPEG G.726(ADPCM) Speech recognition (small vocabulary) Handwriting recognition (Japanese, input frame required) IrDA protocol stack Performance MH Chart1 : Enc0.12s/Dec0.08s Chart1 : Enc0.73s/Dec0.83s QVGA x 24 : Enc0.32s/Dec0.24s 32Kbps, 16Kbps 0.4s 0.1s/character ---Power(MIPS) ---------Enc8/Dec8.2 19 (20 words) 63 (100 words) 14 ---ROM 64 KB 21 KB 17.5 KB 9 KB 82 KB 570 KB 60 KB RAM 200 bytes 2.6 KB 15 KB 80 bytes 3.5 KB (15 words) 34 KB 16 KB Pamphlet U15412EJ1V0PF 37 Flash Memory Microcontrollers Features To answer the need for shorter development time and maintenance after shipping, NEC offers microcontrollers with on-chip flash memory available in a large range of capacities from 128 KB to 512 KB as part of the V850 Series. NEC's flash memory microcontrollers offer the following features. Support of batch rewrite of entire memory and rewrite in area units Flash memory programming with self-rewrite in area units Support of on-board programming through serial communication using a flash memory programmer Erase/write voltage: 2.5 V, 7.8 V, 10.3 V Flash Memory Size (Bytes) RAM Size (Bytes) V850E/MA1 V850E/IA1 V850E/IA2 V850E/MS1 V853 V850/SA1 V850/SV1 V850/SB1 V850/SB2 V850/SF1 V850/SC1 V850/SC2 V850/SC3 V850ES/SA2 V850ES/SA3 4K 128K 6K 8K 256K 10K 16K 384K 16K 512K 24K : Under development Rewrite Mode The V850 Series supports a programmer rewrite mode that uses serial communication supporting on-board programming, as well as a self-programming mode that rewrites flash memory with user programs, to enable continuous use from development to maintenance. Programmer rewrite mode CSI communication mode VPP VDD GND RESET Dedicated flash programmer (PG-FP3, etc.) SO SI SCK VPP VDD VSS RESET SI0 SO0 SCK0 Example: V850/SA1 Handshake-compatible CSI communication mode VPP VDD GND RESET Dedicated flash programmer (PG-FP3, etc.) SO SI SCK HS VPP VDD VSS RESET SI0 SO0 SCK0 P15 Example: V850/SA1 UART communication mode VPP VDD GND RESET Dedicated flash programmer (PG-FP3, etc.) TXD RXD VPP VDD VSS RESET RXD0 TXD0 Example: V850/SA1 Self-Programming Mode Flash memory can be erased and rewritten by calling a selfprogramming function (device-internal processing) using a selfprogramming interface, from a program placed in an area other than the flash memory. The self-programming function is called by switching from the normal operation mode to the selfprogramming mode using the flash programming mode control register (FLPMC). Normal operation mode Flash memory 3FFFFH 3FFFFH Self programming mode Flash memory FLPMC 02H Self-programming function (on-chip erase/ write routine) Erase areaNote (128 KB) 256 KB FLPMC 00H Erase areaNote (128 KB) 00000H 00000H Note Erasure is performed in area units (128 KB). 38 Pamphlet U15412EJ1V0PF Specifications Part No. Flash Memory Capacity 256 KB Power Supply Voltage 3.0 to 3.6 V Max. Operating Frequency 50 MHz Package Rewrite Voltage VDD 144-pin LQFP (20 x 20mm) 161-pin FBGA (13 x 13mm) 144-pin LQFP (20 x 20mm) 3.3 V VPP 7.8 V CSI, HS-compatible CSI 100 Rewrite Mode W/E Count V850E/MA1 V850E/IA1 256 KB 3.0 to 3.6 V (Internal unit) 4.5 to 5.5 V (External pin) 50 MHz 3.3 V 7.8 V CSI, UART, HS-compatible CSI 100 V850E/MS1 128 KB 3.0 to 3.6 V 33 MHz 144-pin LQFP (20 x 20mm) 157-pin FBGA (14 x 14mm) 144-pin LQFP (20 x 20mm) 3.3 V 7.8 V CSI, UART, HS-compatible CSI 100 128 KB 3.0 to 3.6 V (Internal unit) 4.5 to 5.5 V (External pin) V853 128 KB 4.5 to 5.5 V 33 MHz 100-pin LQFP (14 x 14mm) 100-pin LQFP (14 x 14mm) 5V 10.3 V CSI, UART, HS-compatible CSI 20 256 KB V850/SA1 128 KB 3.0 to 3.6 V 20 MHz 100-pin LQFP (14 x 14mm) 100-pin LQFP (14 x 14mm) 121-pin FBGA (12 x 12mm) 3.3 V 7.8 V CSI, UART, HS-compatible CSI 100 256 KB V850/SV1 256 KB 3.1 to 3.6 V 20 MHz 176-pin LQFP (24 x 24mm) 180-pin FBGA (13 x 13mm) 180-pin FBGA (13 x 13mm) 3.3 V 7.8 V CSI, UART, HS-compatible CSI 100 384 KB V850/SB1 256 KB 4.0 to 5.5 V 20 MHz 100-pin LQFP (14 x 14mm) 100-pin QFP (14 x 20mm) 100-pin QFP (14 x 20mm) 3.3 V 7.8 V CSI, UART, HS-compatible CSI 100 512 KB V850/SB2 256 KB 4.0 to 5.5 V 13 MHz 100-pin LQFP (14 x 14mm) 100-pin QFP (14 x 20mm) 100-pin QFP (14 x 20mm) 3.3 V 7.8 V CSI, UART, HS-compatible CSI 100 512 KB V850/SF1 256 KB 4.0 to 5.5 V 16 MHz 100-pin LQFP (14 x 14mm) 100-pin QFP (14 x 20mm) 3.3 V 7.8 V CSI, UART, HS-compatible CSI 100 V850/SC1, SC2, SC3 512 KB 4.0 to 5.5 V 20 MHz 144-pin LQFP (20 x 20mm) 100-pin LQFP (14 x 14mm) 3.3 V 7.8 V CSI, UART, HS-compatible CSI CSI, UART 100 V850ES/SA2* 256 KB 2.3 to 2.7 V 17 MHz 2.5 V 2.5 V 100 V850ES/SA3* 256 KB 2.3 to 2.7 V 17 MHz 121-pin FBGA (12 x 12mm) 2.5 V 2.5 V CSI, UART 100 * : Under Development Pamphlet U15412EJ1V0PF 39 Flash Memory Programmers NEC flash memory programmer (PG-FP3) [Features] Supports write to all NEC microcontrollers with dual-power supply flash memory Device-specific information required for writing can be automatically set with parameter files. Supports both on-board writing and program adapter writing. Easy-to-carry A5 size Simple operation either on standalone basis or with a dedicated application (Flashpro III) on WindowsTM 95, 98, 2000, or Windows NTTM Ver. 4.0 Third-party flash memory programmers (1/2) Programming system Y1000-8 [Manufacturer/Marketing] Wave Technology Co., Ltd. [Target Devices] V850E/MA1, V850/SV1 [Features] Gang programmer enabling simultaneous programming and verification of up to 8 devices Enables reading of master data directly from floppy disk to internal memory. Data dump display and editing functions Master data storable on internal hard disk Emphasizes simple and comfortable operation via touch panel and workability via PASS/FAIL display, check-sum display, and task count display supporting sockets [Additional information] TEL: +81-3-5304-1885 FAX: +81-3-5304-1886 E-mail: sales@y1000.com Website: http://www.y1000.com/en/index.html Flashpro III FL-PR3 [Manufacturer/Marketing] Naito Densei Machida Mfg. Co., Ltd. [Target Devices] V850 Series [Features] Supports writing to all NEC microcontrollers with dual-power supply flash memory Device-specific information required for writing can be automatically set with parameter files. Supports both on-board writing and program adapter writing. Easy-to-carry A5 size Simple operation either on standalone basis or with a dedicated application (Flashpro III) on Windows 95, 98, 2000, or Windows NT Ver. 4.0 [Additional Information] FAX: +81-45-475-4091 E-mail: info@ndk-m.co.jp Website: http://www.ndk-m.co.jp/eng/index.html 40 Pamphlet U15412EJ1V0PF Third-party flash memory programmers (2/2) NET IMPRESS [Manufacturer/Marketing] Yokogawa Digital Computer Corporation [Target Devices] V850E/IA1, V850/SB1 (PD70F3033A) [Features] This in-circuit programmer for flash memory microcontrollers (NET IMPRESS) is used to program the microcontrollers with on-chip flash memory of each company, which have various writing specifications, while solder mounted on the user system board. This programmer comes in four models (AF220, AF210, AF120, AF110) to be used according to the intended application field. One control module is the key to this product's versatility. Microcontrollers of the same family are supported by changing parameters, and microcontrollers of different families are supported by purchasing the license for the descriptor part. Can be used on standalone basis as well as via a host machine. Rich lineup of freeware [Additional Information] TEL : Japan +81-42-333-6224 U.S.A +408-244-1932 Europe +44-1256-811998 FAX : Japan +81-42-352-6109 U.S.A +408-244-1881 Europe +44-1256-811761 E-mail : info@advice.ydc.co.jp Website : http://www.ydc.co.jp/micom/index_E.htm Flash Memory Programmers NEC's flash memory programmer (PG-FP3) supports all NEC microcontrollers with dual-power-supply on-chip flash memory. The PG-FP3 stores the device-specific information required for rewriting in a parameter file and the rewriting environment for each microcontroller can be automatically set by downloading this file. After the parameter file is downloaded, the PG-FP3 can be used on a standalone basis. Combined with a program adapter (FA series (manufactured by Naito Densei Machida Mfg. Co., Ltd.)), this programmer can be used to write single microcontrollers. On-board writing is also possible using a target cable. An example of the rewriting environment when using the program adapter is described below. Example of rewriting environment Flash memory programmer (PG-FP3) Target system Power supply unit Host machine interface (RS-232-C) To host machine Cautions 1. Install the control software of the PG-FP3 and the parameter file of the target device in the host machine. * PG-FP3 control software: Provided with PG-FP3 * Parameter files: Distributed via online delivery 2. In addition to using the program adapter, rewriting can also be done on-board on the target system. Pamphlet U15412EJ1V0PF 41 Functional Outline (1/11) V850E/MA1 Item PD703103A PD703105A PD703106A PD703107A PD70F3107A V850E/MA2 PD703108 CPU core CPU performance (Dhrystone) Internal ROM V850E1 ---None 62MIPS (@ 50 MHz) 128 KB (Mask ROM) 256 KB (mask ROM) 256 KB (flash memory) V850E1 ---None Internal RAM External bus interface Address bus Data bus Programmable waits Interrupt sources 4 KB 26 bits 16 bits 0 to 7 10 KB 4 KB 25 bits 16 bits 0 to 7 External: 25 (17)Note Internal: 33 32x32 64 0.02 to 0.04s (@ 50 MHz) External: 8 (4) Internal: 23 Note DSP function 0.025 to 0.05s (@ 40 MHz) 0.075s (@ 40 MHz) 32x32+32 32 0.06s (@ 50 MHz) 16x16 32 32 ------16-bit timer/event counter x 4 ch 16-bit interval timer x 4 ch ------16-bit timer/event counter x 2 ch 16-bit interval timer x 4 ch ------2 ch ---2 ch 4 ch (10-bit resolution) 4 ch 16x16+32 Timer/counter (RPU) Serial interface (SIO) CSI CSI/I2C CSI/UART UART Dedicated BRG 1 ch ---2 ch 1 ch 3 ch 8 ch (10-bit resolution) 4 ch A/D converter DMA controller Real-time output port Ports I/O Input Other peripheral I/O functions ---106 9 Memory access control function (SDRAM, SRAM, EDO DRAM, page ROM, etc., directly connectable) PWM: 2 ch (8/9/10/12-bit resolution) HALT, IDLE, STOP 4 to 50 MHz ---74 5 Memory access control function (SDRAM, SRAM, page ROM, etc., directly connectable) HALT, IDLE, STOP 4 to 40 MHz Power save function Operating frequency Power supply voltage 3.0 to 3.6 V 3.0 to 3.6 V Power consumption (Typ.) 540mW (@ 3.3 V, 50 MHz) 376mW (@ 3.3 V, 40 MHz) Package 144-pin plastic LQFP (20 x 20 mm) 144-pin plastic LQFP (20 x 20 mm) 161-pin plastic FGBA (13 x 13 mm) 100-pin plastic LQFP (14 x 14 mm) Note Number of external interrupts that can be used to release STOP mode 42 Pamphlet U15412EJ1V0PF (2/11) V850E/IA1 Item V850E1 62MIPS (@ 50 MHz) 256 KB (mask ROM) 256 KB (flash memory) PD703116 PD70F3116 PD703114 V850E/IA2 PD70F3114 CPU core CPU performance (Dhrystone) Internal ROM V850E1 50MIPS (@ 40 MHz) 128 KB (mask ROM) 128 KB (flash memory) Internal RAM External bus interface Address bus Data bus Programmable waits Interrupt sources 10 KB 24 bits 16 bits 0 to 7 6 KB 22 bits 16 bits 0 to 7 External: 20 (14)Note Internal: 46 32x32 64 0.02 to 0.04s (@ 50 MHz) External: 16 (12) External: 42 0.025 to 0.05s (@ 40 MHz) Note DSP function 32x32+32 32 0.06s (@ 50 MHz) 0.075s (@ 40 MHz) 16x16 32 32 ------16-bit 3-phase sine wave PWM timer x 2 ch 16-bit encoder counter/timer x 2 ch 16-bit timer/counter x 2 ch 16-bit timer/event counter x 1 ch 16-bit interval timer x 1 ch ------16-bit 3-phase sine wave PWM timer x 2 ch 16-bit encoder counter/timer x 1 ch 16-bit timer/counter x 2 ch 16-bit timer/event counter x 1 ch 16-bit interval timer x 1 ch 1 ch ---1 ch 1 ch 3 ch 6 ch (10-bit resolution): A/D converter 0, 8 ch (10-bit resolution): A/D converter 1 4 ch 16x16+32 Timer/counter (RPU) Serial interface (SIO) CSI CSI/I2C CSI/UART UART Dedicated BRG 2 ch ------3 ch 4 ch 8 ch (10-bit resolution), 2 units 4 ch A/D converter DMA controller Real-time output port Ports I/O Input Other peripheral I/O functions ---75 8 Memory access control function (SRAM, ROM connectable) ---47 6 Memory access control function (SRAM, ROM connectable) Power save function Operating frequency HALT, IDLE, STOP 4 to 50 MHz HALT, IDLE, STOP 4 to 40 MHz Power supply voltage Internal unit: 3.3 V, A/D converter: 5 V, external pin: 5 V 5 V (Internal unit: 3.3 V, A/D converter: 5 V, external pin: 5 V) (On-chip regulator) 440mW Power consumption (Typ.) 630 mW (For internal unit: 3.3 V, external pin: 5 V, 50 MHz) Package 144-pin plastic LQFP (20 x 20 mm) 100-pin plastic LQFP (14 x 14 mm) Note Number of external interrupts that can be used to release STOP mode Pamphlet U15412EJ1V0PF 43 (3/11) V850E/MS1 Item V850E ---None 43 MIPS (@ 33 MHz) 96 KB (mask ROM) 128 KB (mask ROM) 128 KB (flash memory) PD703100-40 PD703100-33 PD703101-33 PD703102-33 PD70F3102-33 CPU core CPU performance (Dhrystone) Internal ROM Internal RAM External bus interface Address bus Data bus Programmable waits Interrupt sources 4 KB 24 bits 16 bits 0 to 7 External: 25 (1) Internal: 47 32x32 64 Note DSP function 0.025 to 0.05s (@ 40 MHz) 32 0.075s (@ 40 MHz) ---32 ---16-bit timer/event counter x 6 ch 16-bit interval timer x 2 ch 0.03 to 0.06s (@ 33 MHz) 32x32+32 0.09s (@ 33 MHz) 16x16 32 16x16+32 Timer/counter (RPU) Serial interface (SIO) CSI CSI/I2C CSI/UART UART Dedicated BRG 2 ch ---2 ch ---3 ch 8 ch (10-bit resolution) 4 ch A/D converter DMA controller Real-time output port Ports I/O Input Other peripheral I/O functions ---114 9 Memory access control function (EDO DRAM, SRAM, page ROM, etc., directly connectable) Power save function Operating frequency HALT, IDLE, STOP 2 to 40 MHz 2 to 33 MHz Power supply voltage Internal unit: 3.3 V, A/D converter: 5 V External pin: 5 V 540mW (@ 40 MHz) 430mW (@ 33 MHz) Power consumption (Typ.) Package 144-pin plastic LQFP (20 x 20 mm) Note Number of external interrupts that can be used to release STOP mode 44 Pamphlet U15412EJ1V0PF (4/11) V850E/MS1 Item PD703100A-40 PD703100A-33 PD703101A-33 PD703102A-33 PD70F3102A-33 V850E/MS2 PD703130 CPU core CPU performance (Dhrystone) Internal ROM V850E ---None 43MIPS (@ 33 MHz) 96 KB (mask ROM) 128 KB (mask ROM) 128 KB (flash memory) V850E ---None Internal RAM External bus interface Address bus Data bus Programmable waits Interrupt sources 4 KB 24 bits 16 bits 0 to 7 4 KB 24 bits 16 bits 0 to 7 External: 25 (1) Internal: 47 32x32 64 Note External: 10 (1)Note Internal: 35 0.03 to 0.06s (@ 33 MHz) 0.03 to 0.06s (@ 33 MHz) 0.09s (@ 33 MHz) ------16-bit timer/ event counter x 4 ch 16-bit interval timer x 2 ch ------2 ch ---2 ch 4 ch (10-bit resolution) 4 ch DSP function 0.025 to 0.05s (@ 40 MHz) 32 0.075s (@ 40 MHz) ---32 ---- 32x32+32 0.09s (@ 33 MHz) 16x16 32 16x16+32 Timer/counter (RPU) 16-bit timer/event counter x 6 ch 16-bit interval timer x 2 ch Serial interface (SIO) CSI CSI/I2C CSI/UART UART Dedicated BRG 2 ch ---2 ch ---3 ch 8 ch (10-bit resolution) 4 ch A/D converter DMA controller Real-time output port Ports I/O Input Other peripheral I/O functions ---114 9 Memory access control function (EDO DRAM, SRAM, page ROM, etc., directly connectable) ---76 5 Memory access control function (EDO DRAM, SRAM, page ROM, etc., directly connectable) HALT, IDLE, STOP 2 to 33MHz 10 to 33MHz Power save function Operating frequency HALT, IDLE, STOP 2 to 40MHz Power supply voltage Internal unit: 3.3 V, A/D converter: 3.3 V External pin: 3.3 V 330mW (@ 40 MHz) 270mW (@ 33 MHz) Internal unit: 3.3 V, A/D converter: 5 V External pin: 5 V 381mW (@ 33 MHz) Power consumption (Typ.) Package 144-pin plastic LQFP (20 x 20 mm) 144-pin plastic LQFP (20 x 20 mm) 157-pin plastic FBGA (14 x 14 mm) 100-pin plastic LQFP (14 x 14 mm) Note Number of external interrupts that can be used to release STOP mode Pamphlet U15412EJ1V0PF 45 (5/11) V850ES/SA2 Item PD703201/ PD703201Y PD70F3201/ PD70F3201Y PD703204/ PD703204Y V850ES/SA3 PD70F3204/ PD70F3204Y CPU core CPU performance (Dhrystone) Internal ROM V850ES 21 MIPS (@ 17 MHz)/16 MIPS (@ 13.5 MHz) 256 KB (mask ROM) 16 KB Address bus Data bus Programmable waits 22 bits 8/16 bits 0 to 7 24 bits 256 KB (flash memory) 256 KB (mask ROM) 256 KB (flash memory) Internal RAM External bus interface Interrupt sources External: 8 (8) Internal 30 (Y products: 31) 32x32 64 0.24 to 0.29s (@ 17 MHz) Note 1 External: 8 (8)Note 1 Internal: 31 (Y products: 32) DSP function 32x32+32 32 0.35s (@ 17 MHz) 16x16 32 32 0.06 to 0.12s (@ 17 MHz) 0.18s (@ 17 MHz) 16-bit timer/event counter x 2 ch 8-bit timer/event counter x 4 ch (usable as 16-bit timer/event counter x 2 ch) 16x16+32 Timer/counter (RPU) Serial interface (SIO) CSI CSI/I2C Note 2 2 ch 1 ch 1 ch 1 ch 2 ch (UART-dedicated) 12 ch (10-bit resolution) 4 ch 3 ch 1 ch 1 ch 1 ch 2 ch 16 ch (10-bit resolution) CSI/UART UART Dedicated BRG A/D converter DMA controller Real-time output port Ports I/O Input Other peripheral I/O functions ---68 14 Real-time counter (for watch): 1 ch Watchdog timer: 1 ch 84 18 Power save function Operating frequency HALT, IDLE, STOP When using main clock: 2 to 17 MHz (@ 2.4 V)/2 to 13.5 MHz (@ 2.3 V) When using subclock: 32.768 kHz (only real-time counter operating) Power supply voltage 2.3 to 2.7 V (@ 17 MHz)/2.2 to 2.7 V (@ 13.5 MHz) Power consumption (Typ.) When using main clock: 30 mW* (@ 2.5 V, 17 MHz) Package 100-pin plastic LQFP (14 x 14 mm) 121-pin plastic FBGA (12 x 12 mm) Notes1. Number of external interrupts that can be used to release STOP mode 2. Only Y products have an on-chip I2C bus interface. CSI/I2C : PD703201Y, 703204Y, 70F3201Y, 70F3204Y CSI : PD703201, 703204, 70F3201, 70F3204 Remark Values with * are target values. 46 Pamphlet U15412EJ1V0PF (6/11) V850/SA1 Item PD703014A/ PD703014AY PD703014B/ PD703014BY PD703015A/ PD703015AY PD703015B/ PD703015BY PD70F3015B/ PD70F3015BY PD703017A/ PD703017AY PD70F3017A/ PD70F3017AY CPU core CPU performance (Dhrystone) Internal ROM V850 23MIPS (@ 20 MHz)/19MIPS (@ 17 MHz) 64 KB (mask ROM) 128 KB (mask ROM) 128 KB (flash memory) 256 KB (mask ROM) 256 KB (flash memory) Internal RAM External bus interface Address bus Data bus Programmable waits Interrupt sources 4 KB 22 bits 16 bits 0 to 3 External: 9 (6)Note 1 Internal: 22 32x32 64 ---- 8 KB DSP function 32x32+32 32 ---- 16x16 32 32 0.05 to 0.10s (@ 20 MHz) 0.15s (@ 20 MHz) 16-bit timer/event counter x 2 ch 8-bit timer/event counter x 4 ch (usable as 16-bit timer/event counter x 2 ch) 16x16+32 Timer/counter (RPU) Serial interface (SIO) CSI CSI/I2C Note 2 1 ch 1 ch 1 ch 1 ch 2 ch (UART-dedicated) 12 ch (10-bit resolution) 3 ch (only for internal RAM 8-bit x 1 ch or 4-bit x 2 ch on-chip peripheral I/O) CSI/UART UART Dedicated BRG A/D converter DMA controller Real-time output port Ports I/O Input Other peripheral I/O functions 72 13 Watch timer: 1 ch Watchdog timer: 1 ch Power save function Operating frequency HALT, IDLE, STOP Using main clock: 2 to 20 MHz (@ 3.3 V)/2 to 17 MHz (@ 3 V) Using subclock: 32.768 kHz Power supply voltage 3.0 to 3.6 V (@ 20 MHz)/2.7 to 3.6 V (@ 17 MHz) Using main clock: 66 mW (@ 3.3 V, 20 MHz)/56 mW (@ 3.3 V, 17 MHz) Power consumption (Typ.) Using main clock: 105 mW(@ 3.3 V, 20 MHz)/ 99 mW (@ 3.3 V, 17 MHz) Using main clock: Using main clock: 66 mW (@ 3.3 V, 20 MHz)/ 105 mW (@ 3.3 V, 20 MHz)/ 56 mW (@ 3.3 V, 17 MHz) 99 mW (@ 3.3 V, 17 MHz) Package 100-pin plastic LQFP (14 x 14 mm) 121-pin plastic FBGA (12 x 12 mm)Note 4 Note 3 Notes1. Number of external interrupts that can be used to release STOP mode 2. Only Y products have an on-chip I2C bus interface. CSI/I2C : PD703014AY, 703014BY, 703015AY, 703015BY, 703017AY, 70F3015BY, 70F3017AY CSI : PD703014A, 703014B, 703015A, 703015B, 703017A, 70F3015B, 70F3017A 3. PD703014B, 703014BY, 703015B, 703015BY, 703017A, 703017AY, 70F3015B, 70F3015BY, 70F3017A, 70F3017AY 4. PD703014A, 703014AY, 703015A, 703015AY, 703017A, 703017AY, 70F3017A, 70F3017AY Caution The maximum operating frequency of the I2C bus interface is 17 MHz. Pamphlet U15412EJ1V0PF 47 (7/11) V850/SV1 Item PD703041/ PD703041Y PD703039/ PD703039Y PD703040/ PD703040Y PD70F3040/ PD70F3040Y PD703038/ PD703038Y PD70F3038/ PD70F3038Y CPU core CPU performance (Dhrystone) Internal ROM V850 23 MIPS (@ 20 MHz)/18 MIPS (@ 16 MHz) 192 KB (mask ROM) 8 KB Address bus Data bus Programmable waits 22 bits 16 bits 0 to 3 External: 9 (6)Note 1 Internal: 43 (Y products: 44) 32x32 64 ---32 ---256 KB (mask ROM) 16 KB 256 KB (flash memory) 384 KB (mask ROM) 384 KB (flash memory) Internal RAM External bus interface Interrupt sources DSP function 32x32+32 16x16 32 32 0.05 to 0.10s (@ 20 MHz) 0.15s (@ 20 MHz) 24-bit timer/event counter x 2 ch 16-bit timer/event counter x 2 ch 8-bit timer/event counter x 8 ch (usable as 16-bit timer/event counter x 4 ch) 16x16+32 Timer/counter (RPU) Serial interface (SIO) CSI CSI/I2CNote 2 CSI/UART UART Dedicated BRG 1 ch 2 ch 2 ch ---3 ch 16 ch (10-bit resolution ) 6 ch (only for internal RAM on-chip peripheral I/O) A/D converter DMA controller Real-time output port Ports I/O Input Other peripheral I/O functions 8-bit x 2 ch or 4-bit x 4 ch 135 16 Vsync/Hsync separator Watch timer: 1 ch Watchdog timer: 1 ch PWM: 4 ch (12 to 16-bit resolution) Power save function Operating frequency HALT, IDLE, STOP 4 to 20 MHz (@ 3.3 V)/4 to 16 MHz (@ 3 V) Power supply voltage 3.1 to 3.6 V (@ 20 MHz)/2.7 to 3.6 V (@ 16 MHz) Power consumption (Typ.) 82 mW (@ 3.3 V, 20 MHz)/72 mW (@ 3.3 V, 16 MHz) 148 mW (@ 3.3 V, 20 MHz)/ 132 mW (@ 3.3 V, 16 MHz) 82 mW (@ 3.3 V, 20 MHz) 72 mW (@ 3.3 V. 16 MHz) 148 mW (@ 3.3 V, 20 MHz) 132 mW (@ 3.3 V, 16 MHz) Package 176-pin plastic LQFP (24 x 24 mm) 176-pin plastic LQFP (24 x 24 mm) 180-pin plastic FBGA (13 x 13 mm) 180-pin plastic FBGA (13 x 13 mm) Notes1. Number of external interrupts that can be used to release STOP mode 2. Only Y products have an on-chip I2C bus interface. CSI/I2C : PD703038Y, 703039Y, 703040Y, 703041Y, 70F3038Y, 70F3040Y CSI : PD703038, 703039, 703040, 703041, 70F3038, 70F3040 Caution The maximum operating frequency of the I2C bus interface is 17 MHz. 48 Pamphlet U15412EJ1V0PF (8/11) V850/SC1 Item V850 23MIPS (@ 20 MHz) 512 KB (mask ROM) 24 KB Address bus Data bus Programmable waits Interrupt sources 22 bits 16 bits 0 to 3 PD703068Y V850/SC2 PD703069Y PD703088Y V850/SC3 PD703089Y V850/SC1, V850/SC2, V850/SC3 PD70F3089Y CPU core CPU performance (Dhrystone) Internal ROM V850 21MIPS (@ 19 MHz) 512 KB (mask ROM) 24 KB 22 bits 16 bits 0 to 3 V850 18MIPS (@ 16 MHz) 512 KB (mask ROM) 24 KB 22 bits 16 bits 0 to 3 V850 23MIPS (@ 20 MHz) 512 KB (flash memory) 24 KB 22 bits 16 bits 0 to 3 Internal RAM External bus interface External: 12 (9)Note Internal: 39 32x32 64 ---- External: 12 (9)Note Internal: 41 ---- External: 12 (9) Internal: 43 ---- Note External: 12 (9) Internal: 46 Note External: 12 (9) Internal: 46 ---- Note DSP function 32x32+32 32 ---- ---- ---- ---- 16x16 32 32 0.05 to 0.10s (@ 20 MHz) 0.15s (@ 20 MHz) 16-bit timer/ event counter x 10 ch 0.053 to 0.106s (@ 19 MHz) 0.159s (@ 19 MHz) 16-bit timer/ event counter x 10 ch 0.06 to 0.12s (@ 16 MHz) 0.18s (@ 16 MHz) 16-bit timer/event counter x 10 ch 0.05 to 0.10s (@ 20 MHz) 0.15s (@ 20 MHz) 16-bit timer/ event counter x 10 ch 16x16+32 Timer/counter (RPU) Serial interface (SIO) CSI CSI/I2C CSI/UART UART Dedicated BRG 2 ch 2 ch 2 ch 2 ch 5 ch 12 ch (10-bit resolution) 6 ch (only for internal RAM on-chip peripheral I/O) ---- 2 ch 2 ch 2 ch 2 ch 5 ch 12 ch (10-bit resolution) 6 ch (only for internal RAM on-chip peripheral I/O) ---112 12 IEBus (simple version): 1 ch Watch timer: 1 ch Watchdog timer: 1 ch HALT, IDLE, STOP Using main clock: 4 to 19 MHz (@ 5 V) Using subclock: 32.768 kHz 3.5 to 5.5 V (A/D converter: 4.5 to 5.5 V) Using main clock: 120 mW* (@ 5 V, 19 MHz) 2 ch 2 ch 2 ch 2 ch 5 ch 12 ch (10-bit resolution) 6 ch (only for internal RAM on-chip peripheral I/O) 2 ch 2 ch 2 ch 2 ch 5 ch 12 ch (10-bit resolution) 6 ch (only for internal RAM on-chip peripheral I/O) ---112 12 FCAN : 2 ch IEBus (simple version): 1 ch/FCAN: 2 ch Watch timer: 1 ch Watchdog timer: 1 ch HALT, IDLE, STOP Using main clock: 4 to 20 MHz (@ 5 V) Using subclock: 32.768 kHz 4.0 to 5.5 V (A/D converter: 4.5 to 5.5 V) Using main clock: 150 mW* (@ 5 V, 20 MHz) A/D converter DMA controller Real-time output port Ports I/O Input Other peripheral I/O functions ---112 12 FCAN : 1 ch Watch timer: 1 ch Watchdog timer: 1 ch HALT, IDLE, STOP Using main clock: 4 to 16 MHz (@ 5 V) Using subclock: 32.768 kHz 3.5 to 5.5 V (A/D converter: 4.5 to 5.5 V) 112 12 ---Watch timer: 1 ch Watchdog timer: 1 ch Power save function Operating frequency HALT, IDLE, STOP Using main clock: 4 to 20 MHz (@ 5 V) Using subclock: 32.768 kHz 3.5 to 5.5 V (A/D converter: 4.5 to 5.5 V) Using main clock: 125 mW* (@ 5 V, 20 MHz) Power supply voltage Power consumption (Typ.) Using main clock: 110 mW* (@ 5 V, 16 MHz) Package 144-pin plastic LQFP (20 x 20 mm) 144-pin plastic LQFP (20 x 20 mm) 144-pin plastic LQFP (20 x 20 mm) 144-pin plastic LQFP (20 x 20 mm) Note Number of external interrupts that can be used to release STOP mode Remark Values with * are target values. Pamphlet U15412EJ1V0PF 49 (9/11) V850/SF1 Item PD703078Y PD703079Y PD70F3079Y PD703031A/ PD703031AY V850/SB1 PD703033A/ PD70F3033A/ PD703030A/ PD703033AY PD70F3033AY PD703030AY PD703032A/ PD70F3032A/ PD703032AY PD70F3032AY CPU core CPU performance (Dhrystone) Internal ROM V850 18MIPS (@ 16 MHz) 256 KB (mask ROM) 16 KB Address bus Data bus Programmable waits 22 bits 16 bits 0 to 3 256 KB (flash memory) V850 23MIPS (@ 20 MHz) 128 KB (mask ROM) 12 KB 22 bits 16 bits 0 to 3 256 KB (mask ROM) 16 KB 256 KB (flash memory) 384 KB (mask ROM) 20 KB 512 KB (mask ROM) 24 KB 512 KB (flash memory) Internal RAM External bus interface Interrupt sources External: 9 (6)Note 1 Internal: 32 32x32 64 ---- External: 9 (6)Note 1 Internal: 35 External: 9 (6) Internal: 30 (Y products: 31) ---- Note 1 DSP function 32x32+32 32 ---- ---- 16x16 32 32 0.06 to 0.12s (@ 16 MHz) 0.18s (@ 16 MHz) 16-bit timer/event counter x 8 ch 0.05 to 0.10s (@ 20 MHz) 0.15s (@ 20 MHz) 16-bit timer/event counter x 2 ch 8-bit timer/event counter x 4 ch (usable as 16-bit timer/event counter x 2 ch) 8-bit timer x 2 ch (usable as 16-bit timer x 1 ch) 1 ch 2 ch 2 ch ---3 ch 12 ch (10-bit resolution) on-chip peripheral I/O) 6 ch (only for internal RAM on-chip peripheral I/O) 16x16+32 Timer/counter (RPU) Serial interface (SIO) CSI CSI/I2CNote 2 CSI/UART UART Dedicated BRG 1 ch 1 ch 2 ch ---3 ch 12 ch (10-bit resolution) 6 ch (only for internal RAM A/D converter DMA controller Real-time output port Ports I/O Input Other peripheral I/O functions ---72 12 FCAN : 1 ch FCAN : 2 ch 8 bits x 1 or 4 bits x 2 71 12 ---Watch timer: 1 ch Watchdog timer: 1 ch HALT, IDLE, STOP Using main clock: 2 to 20 MHz (@ 5 V) Using subclock: 32.768 kHz Watch timer : 1 ch Watchdog timer : 1 ch Power save function Operating frequency HALT, IDLE, STOP Using main clock: 4 to 16 MHz (@ 5 V) Using subclock: 32.768 kHz Power supply voltage 4.0 to 5.5 V (A/D converter: 4.5 to 5.5 V) (@ 16 MHz) Using main clock: 75 mW (mask ROM)/ 125 mW (flash memory)(@ 5 V, 16 MHz) 4.0 to 5.5 V (A/D converter: 4.5 to 5.5 V) Power consumption (Typ.) Using main clock: 125 mW (@ 5 V, 20 MHz) Using main clock: 165 mW (@ 5 V, 20 MHz) Using main clock: 125 mW (@ 5 V, 20 MHz) Using main clock: 165 mW (@ 5 V, 20 MHz) Package 100-pin plastic LQFP (14 x 14 mm) 100-pin plastic QFP (14 x 20 mm) 100-pin plastic LQFP (14 x 14 mm) 100-pin plastic QFP (14 x 20 mm) 100-pin plastic QFP (14 x 20 mm) Notes1. Number of external interrupts that can be used to release STOP mode 2. Only Y products have an on-chip I2C bus interface. CSI/I2C : PD703030AY, 703031AY, 703032AY, 703033AY, 703078Y, 703079Y, 70F3032AY, 70F3033AY, 70F3079Y CSI : PD703030A, 703031A, 703032A, 703033A, 70F3032A, 70F3033A 50 Pamphlet U15412EJ1V0PF (10/11) V850/SB2 Item PD703034A/ PD703034AY PD703035A/ PD703035AY PD70F3035A/ PD70F3035AY PD703036A/ PD703036AY PD703037A/ PD703037AY PD70F3037A/ PD70F3037AY CPU core CPU performance (Dhrystone) Internal ROM V850 15MIPS (@ 13 MHz) 128 KB (mask ROM) 12 KB Address bus Data bus Programmable waits 22 bits 16 bits 0 to 3 External: 9 (6)Note 1 Internal: 32 (Y products: 33) 32x32 64 ---32 ---256 KB (mask ROM) 16 KB 256 KB (flash memory) 384 KB (mask ROM) 20 KB 512 KB (mask ROM) 24 KB 512 KB (flash memory) Internal RAM External bus interface Interrupt sources DSP function 32x32+32 16x16 32 32 0.077 to 0.154s (@ 13 MHz) 0.231s (@ 13 MHz) 16-bit timer/event counter x 2 ch 8-bit timer/event counter x 4 ch (usable as 16-bit timer/event counter x 2 ch) 8-bit timer x 2 ch (usable as 16-bit timer x 1 ch) 16x16+32 Timer/counter (RPU) Serial interface (SIO) CSI CSI/I2CNote 2 CSI/UART UART Dedicated BRG 1 ch 2 ch 2 ch ---3 ch 12 ch (10-bit resolution) 6 ch (only for internal RAM on-chip peripheral I/O) A/D converter DMA controller Real-time output port Ports I/O Input Other peripheral I/O functions 8 bits x 1 or 4 bits x 2 71 12 IEBus (simple version) Watch timer: 1 ch Watchdog timer: 1 ch Power save function Operating frequency HALT, IDLE, STOP Using main clock: 2 to 13 MHz (@ 5 V) Using subclock: 32.768 kHz Power supply voltage 4.0 to 5.5 V (A/D converter: 4.5 to 5.5 V) Power consumption (Typ.) Using main clock: 75 mW (@ 5 V, 13 MHz) Using main clock: 125 mW (@ 5 V, 13 MHz) Using main clock: 75 mW (@ 5 V, 13 MHz) Using main clock: 125 mW (@ 5 V, 13 MHz) Package 100-pin plastic LQFP (14 x 14 mm) 100-pin plastic QFP (14 x 20 mm) 100-pin plastic QFP (14 x 20 mm) Notes1. Number of external interrupts that can be used to release STOP mode 2. Only Y products have an on-chip I2C bus interface. CSI/I2C : PD703034AY, 703035AY, 703036AY, 703037AY, 70F3035AY, 70F3037AY CSI : PD703034A, 703035A, 703036A, 703037A, 70F3035A, 70F3037A Pamphlet U15412EJ1V0PF 51 (11/11) V853 Item PD703003A PD703004A PD703025A PD70F3003A PD70F3025A CPU core CPU performance (Dhrystone) Internal ROM V850 38MIPS (@ 33 MHz) 128 KB (mask ROM) 96 KB (mask ROM) 256 KB (mask ROM) 128 KB (flash memory) 256 KB (flash memory) Internal RAM External bus interface Address bus Data bus Programmable waits Interrupt sources 4 KB 20 bits 16 bits 0 to 3 Note 8 KB 4 KB 8 KB External: 17 (1) Internal: 32 32x32 64 ---- DSP function 32x32+32 32 ---- 16x16 32 32 0.03 to 0.06s (@ 33 MHz) 0.09s (@ 33 MHz) 16-bit timer/event counter x 4 ch 16-bit timer x 1 ch 16x16+32 Timer/counter (RPU) Serial interface (SIO) CSI CSI/I2C CSI/UART UART Dedicated BRG 2 ch ---2 ch ---3 ch 8 ch (10-bit resolution) ---- A/D converter DMA controller Real-time output port Ports I/O Input Other peripheral I/O functions ---67 8 PWM: 2 ch (8/9/10/12-bit resolution) D/A converter: 2 ch Power save function Operating frequency HALT, IDLE, STOP 5 to 33 MHz (@ 5 V) Power supply voltage 4.5 to 5.5V 365 mW (@ 5 V, 33 MHz) 450 mW (@ 5V, 33 MHz) 425 mW (@ 5 V, 33 MHz) 480 mW (@ 5 V, 33 MHz) Power consumption (Typ.) Package 100-pin plastic LQFP (14 x 14 mm) Note Number of external interrupts that can be used to release STOP mode 52 Pamphlet U15412EJ1V0PF Comfortable Development Environment Development Flow Product planning System design PM Hardware design Software design RX850, RX850 Pro Coding Fabrication Compiling/ assembly Standalone testing Debugging CA850 SM850 +RD850, +RD850 Pro +AZ850 System debugging ID850 IE Hardware tools DF703xxx System evaluation Commercialization Software tools Development Tools (1/3) Software tools Product Name Software package C compiler Device file Project Manager Integrated debugger System simulator Real-time OS Task debugger System performance analyzer Middleware Notes 1. Packaged in SP850 2. Included with CA850 3. Included with RX850, RX850 Pro Remark For details, refer to the V800 SeriesTM Development Environment Pamphlet (U10782E). SP850 CA850Note 1 DF703xxxNote 1 PMNotes 1, 2 ID850Note 1 SM850Note 1 RX850, RX850 Pro RD850, RD850 ProNote 3 AZ850Note 1 AP703000-Bxxx, AP703100-Bxxx Pamphlet U15412EJ1V0PF 53 Development Tools (2/3) Hardware tools Target Device Device Name V850E/MA1 Package 144-pin plastic LQFP (20 x 20 mm) 161-pin plastic FBGA (13 x 13 mm) IE-V850E-MC-A Main Unit In-Circuit Emulator Emulation Board IE-703107-MC-EM1 IE-703107-MC-EM1 + CSSOCKET161A1413N01S1 (under development)Note 1 Note 1 LSPACK161A1413N01 (under development) Note 1 CSICE161A1413N02 (under development) IE-703107-MC-EM1 + VP-V850E/MA1-MA2 (under development)Note 2 IE-V850E-MC IE-703116-MC-EM1 IE-703114-MC-EM1 IE-703102-MC IE-703102-MC-EM1 IE-703102-MC-EM1-A IE-703102-MC-EM1-A + CSPACK157A1614N01Note 1 CSICE157A1614N01Note 1 IE-703102-MC-EM1 + VP-V850E/MS1-MS2Note 2 IE-703002-MC IE-703017-MC-EM1 IE-703017-MC-EM1 + CSPACK121A1312N02Note 1 CSICE121A1312N02Note 1 IE-703037-MC-EM1 IE-703037-MC-EM1 + NEXB-100SD/RBNote 1 IE-703040-MC-EM1 IE-703040-MC-EM1 + CSSOCKET180A1513N01NNote 1 CSSOCKET180A1513N01S01Note 1 EXC-180A/SV1Note 1 IE-703079-MC-EM1 IE-703079-MC-EM1 + SWEX100SD/GF-N17DNote 1 NQPACK100RBNote 1 YQPACK100RBNote 1 HQPACK100RBNote 1 YQSOCKET100RBNNote 1 YQGUIDENote 1 IE-703089-MC-EM1 IE-703003-MC-EM1 V850E/MA2 100-pin plastic LQFP (14 x 14 mm) V850E/IA1 V850E/IA2 V850E/MS1 (5V) V850E/MS1 (3.3V) 144-pin plastic LQFP (20 x 20 mm) 100-pin plastic LQFP (14 x 14 mm) 144-pin plastic LQFP (20 x 20 mm) 144-pin plastic LQFP (20 x 20 mm) 157-pin plastic FBGA (14 x 14 mm) V850E/MS2 (5V) 100-pin plastic LQFP (14 x 14 mm) V850/SA1 100-pin plastic LQFP (14 x 14 mm) 121-pin plastic FBGA (12 x 12 mm) V850/SB1, V850/SB2 100-pin plastic LQFP (14 x 14 mm) 100-pin plastic QFP (14 x 20 mm) V850/SV1 176-pin plastic LQFP (24 x 24 mm) 180-pin plastic FBGA (13 x 13 mm) V850/SF1 100-pin plastic LQFP (14 x 14 mm) 100-pin plastic QFP (14 x 20 mm) V850/SC1, V850/SC2, V850/SC3 V853 144-pin plastic LQFP (20 x 20 mm) 100-pin plastic LQFP (14 x 14 mm) Notes 1. Tokyo Eletech Corp. 2. Naito Densei Machida Mfg. Co., Ltd. Remarks 1. The following parts are required as common products. * PC interface board : IE-70000-PCI-IF-A or IE-70000-CD-IF-A * Power supply : IE-70000-MC-PS-B 2. For details, refer to the V800 SeriesTM Development Environment Pamphlet (U10782E). 54 Pamphlet U15412EJ1V0PF Development Tools (3/3) V850E/MA1, V850E/MA2, V850E/IA1, V850E/IA2 hardware tool configuration example In-circuit emulator (main unit) Emulation board Power supply unit Conversion adapter/conversion socket To common interface block V850E/MS1, V850E/MS2 hardware tool configuration example In-circuit emulator (main unit) Emulation board Power supply unit Conversion adapter/conversion socket To common interface block V850/SA1, V850/SB1, V850/SB2, V850/SV1, V850/SF1, V850/SC1 ,V850/SC2, V850/SC3, V853 hardware tool configuration example In-circuit emulator (main unit) Emulation board Power supply unit Conversion adapter/conversion socket To common interface block Pamphlet U15412EJ1V0PF 55 Development Environment (1/2) Development environment using in-circuit emulator Real-time OS Task debugger Compiler Debugger Analyzer Integrated development environment In-circuit emulator NEC NEC NEC ID850 AZ850 NEC Note RX850 RX850 Pro RD850 Note RD850 Pro Note ATI CA850 GHS NEC Note The RD850, RD850 Pro, and AZ850 can be used with ID850, MULTI, PARTNER, and WATCHPOINT. Remarks 1. ATI CATS : Accelerated Technology, Inc. : Communication And Technology Systems, Inc. : Gaio Technology Co., Ltd. : Green Hills SoftwareTM, Inc. V850 IE Series CATS CCV850 CCV850E Metrowerks ID850 ZIPC850 GHS Nucleus Plus Mispo CodeWarrior(R) Red Hat MULTI TM Midas Lab AZ850 NORTi(R)3 GAIO RTE-V85x-IE Series GAIO GHS GNU KMC PARTNER AZ850 Sophia Systems Sophia Systems G-OS exeGCC GAIO WATCHPOINT TM AZ850 YDC UniSTAC Series YDC XCC-V XASS-V advice Series micro VIEW-G GAIO XDDI-V KMC : Kyoto Microcomputer Corporation Metrowerks : Metrowerks Corporation Midas Lab : Midas Lab Co., Ltd. Mispo : MiSPO, Inc. Red Hat : Red Hat Corporation Sophia Systems : Sophia Systems Co., Ltd. YDC : Yokogawa Digital Computer Corporation 2. For details, refer to the V800 Series Development Environment Pamphlet (U10782E). Development environment using ROM emulator and evaluation board Real-time OS Task debugger Compiler Debugger Analyzer ROM emulator Evaluation board Low-cost evaluation board (limited functions) Evaluation board NEC NEC CA850 Cosmo KMC RX850 RX850 Pro RD850 Note RD850 Pro Note CEB-V85x Series PARTNER AZ850 Note exeGCC GHS Note The RD850, RD850 Pro, and AZ850 can be used with ID850, MULTI, and PARTNER. Remarks 1. ATI : Accelerated Technology, Inc. Cosmo : Cosmo Co., Ltd. GAIO : Gaio Technology Co., Ltd. GHS : Green Hills SoftwareTM, Inc. KMC : Kyoto Microcomputer Corporation Lightwell : Lightwell Co., Ltd. Metrowerks : Metrowerks Corporation Midas Lab : Midas Lab Co., Ltd. Midoriya : Midoriya Electric Co., Ltd. Mispo : MiSPO, Inc. Red Hat : Red Hat Corporation WRS : Wind River Systems, Inc. 2. For details, refer to the V800 Series Development Environment Pamphlet (U10782E). CCV850 CCV850E ATI KMC Metrowerks GHS Nucleus Plus PARTNER-ET II Midas Lab Code Warrior MULTI AZ850 Midoriya RTE-V85x-PC/CB Series EMUSE Mispo Red Hat Lightwell NORTi3 GNU MDX700 WRS TornadoTM GNU CrossWind 56 Pamphlet U15412EJ1V0PF Development Environment (2/2) Development environment using simulator Real-time OS Task debugger Compiler Debugger Simulator Analyzer Integrated development environment Co-simulation tool NEC NEC NEC RX850 RX850 Pro RD850 RD850 Pro CA850 SM850 AZ850 NEC SM850 ZIPC850 GHS CATS YOKOGAWA MULTI Virtual ICE (R) Synopsys GHS ATI Synopsys Eaglei(R) CCV850 Remarks 1. ATI CATS Nucleus Plus Mispo NORTi3 GAIO GAIO XCCV/XASS-V GAIO XDEB G-OS : Accelerated Technology, Inc. : Communication And Technology Systems, Inc. GAIO : Gaio Technology Co., Ltd. GHS : Green Hills Software, Inc. Mispo : MiSPO, Inc. YOKOGAWA : Yokogawa Electric Corporation Synopsys : Nihon Synopsys, Inc. 2. For details, refer to the V800 Series Development Environment Pamphlet (U10782E). Pamphlet U15412EJ1V0PF 57 Software Package (SP850) Product configuration The SP850 software package consists of the following software development tools. *C compiler (CA850) *Project Manager (PM) *Integrated debugger (ID850) *System simulator (SM850) *System performance analyzer (AZ850) *Device file (DF703xxx) C Compiler (CA850) Features *Complies with ANSI-C, a C language standard. *Supports libraries for embedded systems *Compact code size and faster execution speed can be realized through powerful optimization *Utilities useful for embedded systems (ROMization processor, etc.) *Description of embedded systems in C language (specification of memory allocation and I/O register access) is possible. System Simulator (SM850) Features *Same operability as debugger *Target-less evaluation prior to target completion possible *In addition to the operation of the CPU itself, target system operation including on-chip peripheral unit and interrupt servicing can also be simulated. *Pseudo-target system construction and I/O operation are possible through external parts. *Data generated by 0/1 logic and timing charts can be input to the program being simulated. *Larger number of events than in-circuit emulator *Execution speed estimates can be done on the host machine to accurately simulate pipeline operationNote. *Construction by user target system users is possible through user open interface. *A peripheral I/O register status can be specified and when this status occurs, the system can be made to output an interrupt at the desired timing or transfer data to memory (peripheral I/O register event & action function). Note The pipeline mode is supported by the V853. Project Manager (PM) Features *Project management (management of target chip, source, and environment during debugging is possible.) *Automation of series of operations consisting of edit, build, and debug *Integration of Help function *Included with C compiler package Target devices V853, V850/SA1, V850/SB1, V850/SB2, V850/SF1, V850E/MS1, V850E/ MA1, V850E/IA1 58 Pamphlet U15412EJ1V0PF Integrated Debugger (ID850) Features *Supports object files *Debugging at source level *Debugging using target resources *Real-time execution on target *Event setting according to complex software operation *Online help function In-Circuit Emulator Features *Realization of high transparency with emulator functions concentrated in a dedicated chip *V850 core IE enabling easy product expansion *V850E1 core IE enabling high-speed operation *Connectable to various personal computers Real-Time OSs (RX850, RX850 Pro) Features *Comply with global standard (ITRON 3.0 specifications). *Support power management function. *Enable embedding of required functions only (selection of system calls to be used). *Support sophisticated task development through task debugger (RD). *Support application operation analysis through system performance analyzer (AZ) *Inherit attributes of real-time OS of 16-bit V Series and 78K Series Task Debuggers (RD850, RD850 Pro) Features *Display detailed information on OS resources such as tasks. *Issue system calls. *Display source of referenced tasks. *Included with real-time OS (RX850, RX850 Pro) System Performance Analyzer (AZ850) Features *Detection of bugs through system timing errors *Detection of bugs due to simultaneous operation of complex tasks *Detection/analysis of real-time system execution performance *Operation linked to various debuggers TCP/IP Software Library (RX-NET) for V850E Products Product configuration *TCP/IP protocol stack *Applications *LAN control driver Features *RFC-compliant *Multiprotocol stack *Support of numerous socket interfaces/libraries *Support of applications as option products *Simplified device driver *Support of NEC real-time OS (RX850 Pro) Target devices V850E products Pamphlet U15412EJ1V0PF 59 OSEK/VDX Specification-Compliant OS (RX-OSEK850) Features * Kernel OSEK/VDX OS Ver. 2.0 specification-compliant Supports four conformance classes (BCC1, BCC2, ECC1, ECC2). * Communications OSEK/VDX COM Ver. 2.1 Rev. 1 specification-compliant Supports three conformance classes (CCC1, CCC2, CCC3). * Configurator Configurator simplifying construction of system information (OIL850) OIL Ver. 2.0-compliant format supported for configuration files * Task debugger (RD-OSEK850) Task debugger effective for debugging applications that use the RX-OSEK850 included as standard. RISC Microcontroller Reference Platform (SolutionGearTM) Features * General-purpose evaluation boards available as development platforms for RISC microcontroller software * Supported CPU: V850E/MA1 * Global and PC-compatible interfaces provided, including PCI, ISA, PCMCIA, E-IDE, EthernetTM, Serial, Parallel, PS/2, and USB * Used combined with CPU-independent motherboard (usable in common with VR Series) and any of various CPU boards * Real-time OS, middleware, and sample drivers are included. * Development environment of Green Hills Software (evaluation version) provided * MULTI/PARTNER remote monitor version can be used. * Reference design information provided It's actually testable Circuit diagrams are provided This board usable for comparison purposes It does not work properly. Is this a hardware or software problem? I want to measure the CPU performance Can such a performance be realized? This is my first device so I want sample circuits H/W Device selection Board design/development Debugging Software design/development S/W Time I want to use OS /middleware I want to start software development ahead of board development The OS and middleware look difficult to start up and use The OS and middleware are bundled. Since various peripheral devices are mounted,debugging can be started from device-independent parts. A user-own coding part matching this board is provided as sample. At such times, RISC microcontroller reference platform is ideal Cooperation with Third Parties By strengthening its cooperation with third-party companies and creating tool groups that combine the best characteristics of NEC tools and third-party tools, NEC provides a development environment that answers diversified user needs. 60 Pamphlet U15412EJ1V0PF Information V850 Series Website Introduction For information about the V850 Series and the V850 Series development environment, check out the NEC Microcomputer website. http://www.ic.nec.co.jp/micro/index_e.html Product Information Product information on the V850 Series, development environments for the V850 Series, and the middleware reference platform can be referenced. Downloading Development Tools Development tools for the V850 Series can be downloaded. Upgrade information is provided. Downloading Documents Documents about the V850 Series and V850 Series development environment can be downloaded. FAQ Answer to questions about the V850 Series development environment are introduced. Pamphlet U15412EJ1V0PF 61 IEBus, EEPROM, Solution Gear, V Series, V800 Series, V850 Series, V830 Family, V853, V850/SA1, V850/SB1, V850/SB2, V850/SC1, V850/SC2, V850/SC3, V850/SF1, V850/SV1, V850E/IA1, V850E/IA2, V850E/MA1, V850E/MA2, V850E/MS1, V850E/MS2, V850ES/SA2, V850ES/SA3, and VR Series are trademarks of NEC Corporation. TrueSpeech is a trademark of DSP Group, Inc. JAVA and all trademarks and logos related to JAVA are trademarks of Sun Microsystems, Inc. Windows and Windows NT are either registered trademarks or trademarks of Microsoft Corporation in the United States and/or other countries. NORTi is a trademark of MiSPO, Inc. CodeWarrior is a trademark of Metrowerks Corporation. Green Hills Software and MULTI are trademarks of Green Hills Software, Inc. WATCHPOINT is a trademark of Sophia Systems Co., Ltd. Tornado is a trademark of Wind River Systems, Inc. Virtual ICE is a trademark of Yokogawa Electric Corporation. Synopsys Eaglei is a trademark of Synopsys, Inc. TRON stands for The Realtime Operating system Nucleus. ITRON is an abbreviation of Industrial TRON. Ethernet is a trademark of Xerox Corporation. Caution: The I2C bus interface circuit is incorporated in the PD703014AY, 703014BY, 703015AY, 703015BY, 70F3015BY, 703017AY, 70F3017AY, 703030AY, 703031AY, 703032AY, 70F3032AY, 703033AY, 70F3033AY, 703034AY, 703035AY, 70F3035AY, 703036AY, 703037AY, 70F3037AY, 703038Y, 70F3038Y, 703039Y, 703040Y, 70F3040Y, 703041Y, 703068Y, 703069Y, 703078Y, 703079Y, 70F3079Y, 703088Y, 703089Y, 70F3089Y, 703201Y, 70F3201Y, 703204Y, 70F3204Y. Those who use the I2 C bus interface can be granted the license below by giving prior notification before ordering the custom code. Purchase of NEC I2 C components conveys a license under the Philips I2C Patent Rights to use these components in an I2 C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. 62 Pamphlet U15412EJ1V0PF The export of these products from Japan is regulated by the Japanese government. The export of some or all of these products may be prohibited without governmental license. To export or re-export some or all of these products from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales representative. * The information in this document is current as of August, 2001. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC's data sheets or data books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all products and/or types are available in every country. Please check with an NEC sales representative for availability and additional information. * No part of this document may be copied or reproduced in any form or by any means without prior written consent of NEC. NEC assumes no responsibility for any errors that may appear in this document. * NEC does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC semiconductor products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC or others. * Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of customer's equipment shall be done under the full responsibility of customer. NEC assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. * While NEC endeavours to enhance the quality, reliability and safety of NEC semiconductor products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize risks of damage to property or injury (including death) to persons arising from defects in NEC semiconductor products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment, and anti-failure features. * NEC semiconductor products are classified into the following three quality grades: "Standard", "Special" and "Specific". The "Specific" quality grade applies only to semiconductor products developed based on a customer-designated "quality assurance program" for a specific application. The recommended applications of a semiconductor product depend on its quality grade, as indicated below. Customers must check the quality grade of each semiconductor product before using it in a particular application. "Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots "Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) "Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. The quality grade of NEC semiconductor products is "Standard" unless otherwise expressly specified in NEC's data sheets or data books, etc. If customers wish to use NEC semiconductor products in applications not intended by NEC, they must contact an NEC sales representative in advance to determine NEC's willingness to support a given application. (Note) (1) "NEC" as used in this statement means NEC Corporation and also includes its majority-owned subsidiaries. (2) "NEC semiconductor products" means any semiconductor product developed or manufactured by or for NEC (as defined above). M8E 00. 4 Pamphlet U15412EJ1V0PF 63 For further information, please contact: NEC Corporation NEC Building 7-1, Shiba 5-chome, Minato-ku Tokyo 108-8001, Japan Tel: 03-3454-1111 http://www.ic.nec.co.jp/ [North & South America] NEC Electronics Inc. 2880 Scott Blvd. Santa Clara, CA 95050-2554, U.S.A. Tel: 408-588-6000 800-366-9782 Fax: 408-588-6130 800-729-9288 http://www.necel.com/ NEC do Brasil S.A. Electron Devices Division Rodovia Presidente Dutra, Km 214 07210-902-Guarulhos-SP Brasil Tel: 011-6462-6810 Fax: 011-6462-6829 [Europe] NEC Electronics (Europe) GmbH Oberrather Str. 4 40472 Dusseldorf, Germany Tel: 0211-6503-01 Fax: 0211-6503-327 http://www.ee.nec.de/ Branch The Netherlands Boschdijk 187a 5612 HB Eindhoven, The Netherlands Tel: 040-2445845 Fax: 040-2444580 Branch Sweden P.O. Box 134 18322 Taeby, Sweden Tel: 08-6380820 Fax: 08-6380388 NEC Electronics (UK) Limited Cygnus House, Sunrise Parkway, Linford Wood, Milton Keynes, MK14 6NP, U.K. Tel: 01908-691-133 Fax: 01908-670-290 NEC Electronics (France) S.A. 9, rue Paul Dautier-B.P. 52 78142 Velizy-Villacoublay Cedex France Tel: 01-3067-5800 Fax: 01-3067-5899 Madrid Office Juan Esplandiu, 15 28007 Madrid, Spain Tel: 091-504-2787 Fax: 091-504-2860 NEC Electronics Italiana s.r.l. Via Fabio Filzi, 25/A, 20124 Milano, Italy Tel: 02-667541 Fax: 02-66754299 [Asia & Oceania] NEC Electronics Hong Kong Limited 12/F., Cityplaza 4, 12 Taikoo Wan Road, Hong Kong Tel: 2886-9318 Fax: 2886-9022/9044 Seoul Branch 10F, ILSONG Bldg., 157-37, Samsung-Dong, Kangnam-Ku Seoul, the Republic of Korea Tel: 02-528-0303 Fax: 02-528-4411 NEC Electronics Taiwan Ltd. 7F, No. 363 Fu Shing North Road Taipei, Taiwan, R. O. C. Tel: 02-2719-2377 Fax: 02-2719-5951 NEC Electronics Singapore Pte. Ltd. 238A Thomson Road #12-01/10 Novena Square Singapore 307684 Tel: 253-8311 Fax: 250-3583 G02. 1 Document No. U15412EJ1V0PF00 (1st edition) Date Published February 2002 N CP(K) Printed in Japan (c) NEC Corporation 2002 |
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