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FUJITSU SEMICONDUCTOR DATA SHEET
DS05-10144-5E
MEMORY
CMOS 1 M x 4 BIT FAST PAGE MODE DRAM MB814400A-60/-70/-80
CMOS 1,048,576 x 4 bit Fast Page Mode Dynamic RAM s DESCRIPTION
The Fujitsu MB814400A is a fully decoded CMOS Dynamic RAM (DRAM) that contains a total of 4,194,304 memory cells accessible in 4-bit increments. The MB814400A features a "fast page" mode of operation whereby high-speed random access of up to 1,024-bits of data within the same row can be selected. The MB814400A DRAM is ideally suited for mainframe, buffers, hand-held computers video imaging equipment, and other memory applications where very low power dissipation and high bandwidth are basic requirements of the design. Since the standby current of the MB814400A is very small, the device can be used as a non-volatile memory in equipment that uses batteries for primary and/or auxiliary power. The MB814400A is fabricated using silicon gate CMOS and Fujitsu's advanced four-layer polysilicon process. This process, coupled with three-dimensional stacked capacitor memory cells, reduces the possibility of soft errors and extends the time interval between memory refreshes. Clock timing requirements for the MB814400A are not critical and all inputs are TTL compatible.
s PRODUCT LINE & FEATURES
Parameter RAS Access Time CAS Access Time Address Access Time Randam Cycle Time Fast Page Mode Cycle Time Low power Dissipation * * * * Operating current Standby current MB814400A-60 60 ns max. 15 ns max. 30 ns max. 110 ns min. 40 ns min. 605 mW max. MB814400A-70 70 ns max. 20 ns max. 35 ns max. 125 ns min. 45 ns min. 550 mW max. MB814400A-80 80 ns max. 20 ns max. 40 ns max. 140 ns min. 45 ns min. 495 mW max.
11 mW max. (TTL level)/5.5 mW max. (CMOS level) * * * * Early write or OE controlled write capability RAS only CAS-before-RAS, or Hidden Refresh Fast page Mode, Read-Modify-Write capability On chip substrate bias generator for high performance
1,048,576 words x 4 bit organization Silicon gate, CMOS, 3D-Stacked Capacitor Cell All input and output areTTL compatible 1024 refresh cycles every16.4 ms
This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields. However, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this high impedance circuit.
1
MB814400A-60/MB814400A-70/MB814400A-80
s ABSOLUTE MAXIMUM RATINGS (See WARNING)
Parameter Voltage at any pin relative to VSS Voltage of VCC supply relative to VSS Power Dissipation Short Circuit Output Current Storage Temperature Symbol VIN, VOUT VCC PD -- TSTG Value -1 to +7 -1 to +7 1.0 50 -55 to +125 Unit V V W mA C
WARNING: Permanent device damage may occur if the above Absolute Maximum Ratings are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
s PACKAGE
Marking side
LCC-26P-M04
ZIP-20P-M02
(Normal Bend)
Marking side (Reverse Bend)
FPT-26P-M01
FPT-26P-M02
Package and Ordering Information
- 26-pin plastic (300 mil) SOJ, order as MB814400A-xxPJN - 20-pin plastic ZIP, order as MB814400A-xxPZ - 26-pin plastic (300 mil) TSOP-ll, with normal bend leads, order as MB814400A-xxPFTN - 26-pin plastic (300 mil) TSOP-ll, with reverse bend leads, order as MB814400A-xxPFTR
2
MB814400A-60/MB814400A-70/MB814400A-80
Fig. 1 - MB814400A DYNAMIC RAM - BLOCK DIAGRAM
RAS CAS
Clock Gen #1 Write Clock Gen Mode Control
WE
Clock Gen #2
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10
Refresh Address Counter Substrate Bias Gen Address Buffer & PreDecoder Row Decoder Column Decoder Sense Ampl & I/O Gate
Data In Buffer
DIN
* *
*
*
Data Out Buffer
4,194,304 Bit Storage Cell
DOUT
*
*
OE VCC VSS
s CAPACITANCE
(TA = 25C, f = 1 MHz)
Parameter Input Capacitance, A0 toA9, DIN Input Capacitance, RAS, CAS, WE, OE Input/Output Capacitance, DQ1 to DQ4
Symbol CIN1 CIN2 CDQ
Typ. -- -- --
Max. 5 7 7
Unit pF pF pF 3
MB814400A-60/MB814400A-70/MB814400A-80
s PIN ASSIGNMENTS AND DESCRIPTIONS
26-Pin SOJ: (Top View) 26-Pin FPT: (Top View) DQ1 DQ2 WE RAS A9 1 2 3 4 5 26 25 24 23 22 VSS DQ4 DQ3 CAS OE DQ1 DQ2 WE RAS A9 1 2 3 4 5 26 25 24 23 22 VSS DQ4 DQ3 CAS OE
A0 A1 A2 A3 VCC
9 10 11 12 13
18 17 16 15 14
A8 A7 A6 A5 A4
A0 A1 A2 A3 VCC
9 10 11 12 13
18 17 16 15 14
A8 A7 A6 A5 A4
20-Pin ZIP: (Top View) CAS DQ4 DQ1 WE 2 4 6 8 A9 10 A1 12 14 A3 16 A4 18 A6 20 A8 VSS DQ4 DQ3 CAS OE 26 25 24 23 22 1 2 3 4 5 DQ1 DQ2 WE RAS A9
1 3 5 7 9 11 13 15 17 19 OE DQ3 VSS DQ2 RAS A0 A2 VCC A5 A7
Designator
Function
DQ1 to DQ4 DOUT WE RAS A0 to A9 VCC OE CAS VSS
Data Input/Output Data Output. Write Enable. Row Address Strobe. No Connection. Address Inputs. +5 volt Power Supply. Column Address Strobe. Circuit Ground.
A8 A7 A6 A5 A4
18 17 16 15 14
9 10 11 12 13
A0 A1 A2 A3 VCC
4
MB814400A-60/MB814400A-70/MB814400A-80
s RECOMMENDED OPERATING CONDITIONS
Parameter Supply Voltage Input High Voltage, all inputs Input Low Voltage, all inputs Input Low Voltage, DQ(*) Notes 1 1 1 1 Symbol VCC VSS VIH VIL VILD Min. 4.5 0 2.4 -2.0 -1.0 Typ. 5.0 0 -- -- -- Max. 5.5 0 6.5 0.8 0.8 Unit V V V V 0C to +70C Ambient Operating Temp.
* : Undershoots of up to -2.0 volts with a pulse width not exceeding 20 ns are acceptable.
s FUNCTIONAL OPERATION
ADDRESS INPUTS
Twenty input bits are required to decode any four of 4,194,304 cell addresses in the memory matrix. Since only ten address bits are available, the column and row inputs are separately strobed by CAS and RAS as shown in Figure 5. First, ten row address bits are input on pins A0-through-A9 and latched with the row address strobe (RAS) then, ten column address bits are input and latched with the column address strobe (CAS). Both row and column addresses must be stable on or before the falling edge of CAS and RAS, respectively. The address latches are of the flow-through type; thus, address information appearing after tRAH (min.)+ tT is automatically treated as the column address.
WRITE ENABLE
The read or write mode is determined by the logic state of WE. When WE is active Low, a write cycle is initiated; when WE is High, a read cycle is selected. During the read mode, input data is ignored.
DATA INPUT
Input data is written into memory in either of three basic ways--an early write cycle, an OE (delayed) write cycle, and a read-modify-write cycle. The falling edge of WE or CAS, whichever is later, serves as the input data-latch strobe. In an early write cycle, the input data (DQ1 to DQ4) is strobed by CAS and the setup/hold times are referenced to CAS because WE goes Low before CAS. In a delayed write or a read-modify-write cycle, WE goes Low after CAS; thus, input data is strobed by WE and all setup/hold times are referenced to the write-enable signal.
DATA OUTPUT
The three-state buffers are TTL compatible with a fanout of two TTL loads. Polarity of the output data is identical to that of the input; the output buffers remain in the high-impedance state until the column address strobe goes Low. When a read or read-modify-write cycle is executed, valid outputs are obtained under the following conditions: tRAC : tCAC : tAA : tOEA : from the falling edge of RAS when tRCD (max.) is satisfied. from the falling edge of CAS when tRCD is greater than tRCD (max.). from column address input when tRAD is greater than tRAD (max.). from the falling edge of OE when OE is brought Low after tRAC, tCAC, or tAA.
The data remains valid until either CAS or OE returns to a High logic level. When an early write is executed, the output buffers remain in a high-impedance state during the entire cycle.
FAST PAGE MODE OF OPERATION
The fast page mode of operation provides faster memory access and lower power dissipation. The fast page mode is implemented by keeping the same row address and strobing in successive column addresses. To satisfy these conditions, RAS is held Low for all contiguous memory cycles in which row addresses are common. For each fast page of memory, any of 1,024-bits can be accessed and, when multiple MB 814400s are used, CAS is decoded to select the desired memory fast page. Fast page mode operations need not be addressed sequentially and combinations of read, write, and/or ready-modify-write cycles are permitted. 5
MB814400A-60/MB814400A-70/MB814400A-80
s DC CHARACTERISTICS
(Recommended operating conditions unless otherwise noted.)
Parameter Output High Voltage Output Low Voltage Notes 1 1 Symbol VOH VOL Conditions IOH = -5 mA IOL = 4.2 mA 0 V VIN 5.5 V; 4.5 V VCC 5.5 V; VSS = 0 V; All other pins not under test = 0 V 0 V VOUT 5.5 V; Data out disabled RAS & CAS cycling; tRC = min. RAS = CAS = VIH ICC2 RAS = CAS VCC -0.2 V CAS = VIH, RAS cycling; tRC = min. -- --
Note 3
Values Min. 2.4 -- Typ. -- -- Max. -- V 0.4 Unit
Input Leakage Current (Any Input)
II(L)
-10
--
10 A
Output Leakage Current Operating Current (Average Power 2 Supply Current) Standby Current (Power Supply Current) Refresh Current#1 (Average Power 2 Supply Current) Fast Page Mode Current MB814400A-60 MB814400A-70 MB814400A-80 TTL level CMOS level MB814400A-60 MB814400A-70 MB814400A-80 MB814400A-60 2 MB814400A-70 MB814400A-80 Refresh Current#2 (Average Power 2 Supply Current) MB814400A-60 MB814400A-70 MB814400A-80
IDO(L)
-10
--
10 110
ICC1
--
--
100 90 2.0 1.0 110
mA
mA
ICC3
--
--
100 90 55
mA
ICC4
RAS = VIL, CAS cycling; tRC = min.
--
--
50 45 90
mA
ICC5
RAS cycling; CAS-before-RAS; tRC = min.
--
--
80 70
mA
6
MB814400A-60/MB814400A-70/MB814400A-80
s AC CHARACTERISTICS
(At recommended operating conditions unless otherwise noted.)
No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Parameter Notes Symbol tREF tRC tRWC tRAC tCAC tAA tOH tON tOFF tT tRP tRAS tRSH tCRP tRCD tCAS tCSH tCPN tASR tRAH tASC tCAH tRAD tRAL tCAL tRCS tRRH tRCH tWCS tWCH
Notes 3, 4, 5
Time Between Refresh Random Read/Write Cycle Time Read-Modify-Write Cycle Time Access Time from RAS Access Time from CAS 6, 9 7, 9
MB814400A-60 MB814400A-70 MB814400A-80 Unit Min. Max. Min. Max. Min. Max. -- 16.4 -- 16.4 -- 16.4 ms 110 -- 125 -- 140 -- ns 155 -- 175 -- 195 -- ns -- -- -- 0 0 -- 2 40 60 15 5 20 15 60 10 0 10 0 12 15 30 30 0 0 0 0 10 60 15 30 -- -- 15 50 -- 10000 -- -- 45 -- -- -- -- -- -- -- 30 -- -- -- -- -- -- -- -- -- -- 0 0 -- 2 45 70 20 5 20 20 70 10 0 10 0 12 15 35 35 0 0 0 0 10 70 20 35 -- -- 15 50 -- 10000 -- -- 50 -- -- -- -- -- -- -- 35 -- -- -- -- -- -- -- -- -- -- 0 0 -- 2 50 80 20 5 20 20 80 10 0 10 0 15 15 40 40 0 0 0 0 12 80 20 40 -- -- 20 50 -- 10000 -- -- 60 -- -- -- -- -- -- -- 40 -- -- -- -- -- -- -- ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Column Address Access 8, 9 Time Output Hold Time Output Buffer Turn On Delay Time Output Buffer Turn off Delay 10 Time Transition Time RAS Precharge Time RAS Pulse Width RAS Hold Time CAS to RAS Precharge Time 11, 12
15 RAS to CAS Delay Time
16 CAS Pulse Width 17 CAS Hold Time CAS Precharge Time 18 19 (Normal) 19 Row Address Set Up Time 20 Row Address Hold Time 21 Column Address Set Up Time 22 Column Address Hold Time RAS to Column Address 23 13 Delay Time 24 Column Address to RAS Lead Time 25 Column Address to CAS Lead Time 26 Read Command Set Up Time Read Command Hold Time 27 14 Referenced to RAS Read Command Hold Time 28 14 Referenced to CAS Write Command Set Up 29 15 Time 30 Write Command Hold Time
7
MB814400A-60/MB814400A-70/MB814400A-80
s AC CHARACTERISTICS (Continued)
(At recommended operating conditions unless otherwise noted.)
No. 31 32 33 34 35 Parameter Notes Symbol tWP tRWL tCWL tDS tDH tRWD tCWD tAWD tRPC tCSR tCHR tWSR tWHR tOEA tOEZ tOEL tOEH tOED tDZC tDZO tPC tPRWC tCPA tCP tRASP tRHCP tCPWD
Notes 3, 4, 5
WE Pulse Width Write Command to RAS Lead Time Write Command to CAS Lead Time DIN set Up Time DIN Hold Time 15 15
MB814400A-60 MB814400A-70 MB814400A-80 Unit Min. Max. Min. Max. Min. Max. 10 -- 10 -- 12 -- ns 15 -- 20 -- 20 -- ns 15 -- 18 -- 20 -- ns 0 -- 0 -- 0 -- ns 10 -- 10 -- 12 -- ns 85 40 55 0 0 10 0 10 -- -- 10 0 15 0 0 40 85 -- 10 -- 35 60 -- -- -- -- -- -- -- -- 15 15 -- -- -- -- -- -- -- 35 -- 200000 -- -- 95 45 60 0 0 10 0 10 -- -- 10 0 15 0 0 45 93 -- 10 -- 40 65 -- -- -- -- -- -- -- -- 20 15 -- -- -- -- -- -- -- 40 -- 200000 -- -- 110 50 70 0 0 12 0 10 -- -- 10 0 20 0 0 45 100 -- 10 -- 40 70 -- -- -- -- -- -- -- -- 20 20 -- -- -- -- -- -- -- 40 -- 200000 -- -- ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
36 RAS to WE Delay Time 37 CAS to WE Delay Time 38
Column Address to WE 15 Delay Time RAS Precharge Time to CAS Active 39 Time (Refresh Cycles) CAS Set Up Time for CAS-before40 RAS Refresh CAS Hold Time for CAS-before-RAS 41 Refresh 42 WE SetUp Time from RAS 43 WE Hold Time from RAS 44 Access time from OE 20 20 9
Output Buffer Turn Off 45 Delay 10 from OE 46 OE to RAS Lead Time for Valid Data OE Hold Time Referenced 47 16 to WE 48 OE to Data In Delay Time 49 DIN to CAS Delay Time 50 DIN to OE Delay Time 51 52 53 54 55 56 57 17 17
Fast Page Mode Read/Write Cycle Time Fast Page Mode Read-ModifyWriteCycle Time Access Time from CAS 9, 18 Precharge Fast Page Mode CAS Precharge Time Fast Page Mode RAS Pulse width Fast Page Mode RAS Hold Time from CAS Precharge Fast Page Mode CAS Precharge to WE Delay Time
8
MB814400A-60/MB814400A-70/MB814400A-80
Notes: 1. Referenced to VSS. 2. ICC depends on the output load conditions and cycle rates; The specified values are obtained with the output open. ICC depends on the number of address change as RAS = VIL and CAS = VIH, VIL > -0.5 V. ICC1, ICC3 and ICC5 are specified at one time of address change during RAS = VIL and CAS = VIH. ICC4 is specified at one time of address change during one Page cycle. 3. An Initial pause (RAS = CAS = VIH) of 200 s is required after power-up followed by any eight RASonly cycles before proper device operation is achieved. In case of using internal refresh counter, a minimum of eight CAS-before-RAS initialization cycles instead of 8 RAS cycles are required. 4. AC characteristics assume tT = 5 ns. 5. VIH (min.) and VIL (max.) are reference levels for measuring timing of input signals. Also transition times are measured between VIH (min.) and VIL (max.). 6. Assumes that tRCD tRCD (max.), tRAD tRAD (max.). If tRCD is greater than the maximum recommended value shown in this table, tRAC will be increased by the amount that tRCD exceeds the value shown. Refer to Fig. 2 and 3. 7. If tRCD tRCD (max.), tRAD tRAD (max.), and tASC tAA - tCAC - tT, access time is tCAC. 8. If tRAD tRAD (max.) and tASC tAA - tCAC - tT, access time is tAA. 9. Measured with a load equivalent to two TTL loads and 100 pF. 10. tOFF and tOEZ is specified that output buffer change to high impedance state. 11. Operation within the tRCD (max.) limit ensures that tRAC (max.) can be met. tRCD (max.) is specified as a reference point only; if tRCD is greater than the specified tRCD (max.) limit, access time is controlled exclusively by tCAC or tAA. 12. tRCD (min.) = tRAH (min.)+ 2tT + tASC (min.). 13. Operation within the tRAD (max.) limit ensures that tRAC (max.) can be met. tRAD (max.) is specified as a reference point only; if tRAD is greater than the specified tRAD (max.) limit, access time is controlled exclusively by tCAC or tAA. 14. Either tRRH or tRCH must be satisfied for a read cycle. 15. tWCS is specified as a reference point only. If tWCS tWCS (min.) the data output pin will remain High-Z state through entire cycle. 16. Assumes that tWCS < tWCS (min.) 17. Either tDZC or tDZO must be satisfied. 18. tCPA is access time from the selection of a new column address (that is caused by changing CAS from "L" to "H"). Therefore, if tCP is long, tCPA is longer than tCPA (max.). 19. Assumes that CAS-before-RAS refresh. 20. Assumes that Test mode function.
9
MB814400A-60/MB814400A-70/MB814400A-80
Fig. 2 - tRAC vs. tRCD
tRAC (ns) tRAC (ns)
Fig. 3 - tRAC vs. tRAD
tCPA (ns) 80
Fig. 4 - tCPA vs. tCP
140 120 100 80 60 40 80 ns Version 70 ns Version 60 ns Version
100 70 90 80 ns Version 80 70 60 30 50 70 ns Version 60 ns Version 50 40 60 ns Version 60 70 ns/80 ns Version
20
40
60
80
100 120
10
20
30
40
50
60
10
20
30
40
50
60
tRCD (ns)
tRAD (ns)
tCP (ns)
s FUNCTIONAL TRUTH TABLE
Operation Mode Standby Read Cycle Write Cycle (Early Write) Read-ModifyWrite Cycle RAS-only Refresh Cycle CAS-before-RAS Refresh Cycle Hidden Refresh Cycle Test mode set Cycle (CBR) Test Mode Set Cycle (Hidden) Clock Input RAS H L L L L L HL L HL CAS H L L L H L L L L WE X H L OE X L X Address Row -- Valid Valid Valid Valid -- -- -- -- Column -- Valid Valid Valid -- -- -- -- -- Input Data Input -- -- Valid Valid -- -- -- -- -- Output High-Z Valid High-Z Valid High-Z High-Z Valid High-Z Valid Refresh -- Yes* Yes* Yes* Yes Yes Yes Yes Yes tCSR tCSR (min.) Previous data is kept. tCSR tCSR (min.) tWSR tWSR (min.) tCSR tCSR (min.) tWSR tWSR (min.) tRCS tRCS (min.) tWCS tWCS (min.) tCWD tCWD (min.) Note
HL LH X H H L L X X L X X
Note: X : "H" or "L" *1: It is impossible in Fast Page Mode.
10
MB814400A-60/MB814400A-70/MB814400A-80
Fig. 5 - READ CYCLE
tRC tRAS RAS VIH VIL tCRP tRCD CAS VIH VIL tASR VIH VIL tRAH tRAD tRAL tASC tCAL tCAH COLUMN ADD tRCS VIH VIL tRAC VOH DQ (Output) VOL DQ (Input) VIH VIL tDZO VIH OE VIL "H" or "L" Invalid Data
DESCRIPTION To implement a read operation,a valid address is latched in by the RAS and CAS address strobes and with WE set to a High level and OE set to a low level, the output is valid once the memory access time has elapsed. The access time is determined by RAS (tRAC) CAS (tCAC), OE (tOEA) or column addresses (tAA) under the following conditions: If tRCD> tRCD (max.), access time = tCAC. If tRAD> tRAD (max.), access time = tAA. If OE is brought Low after tRAC,tCAC, or tAA (which ever occurs later), access time = tOEA. However, if either CAS or OE goes High, the output returns to a high-impedance state after tOH is satisfied.
tCSH tRSH tCAS
tRP
tOEL
A0 to A9
ROW ADD
tRRH tRCH tAA tCAC tOH tOFF VALID DATA tON HIGH-Z tOED tOEA tOEZ HIGH-Z
WE
HIGH-Z tDZC
11
MB814400A-60/MB814400A-70/MB814400A-80
Fig. 6 - EARLY WRITE CYCLE (OE = "H" or "L")
tRC tRAS RAS VIH VIL tCSH tCRP tRCD CAS VIH VIL tASR tRAD tRAH tASC COLUMN ADD tRAL tCAL tCAH tRSH tCAS tRP
A0 to A9
VIH VIL
ROW ADD
tWCS WE VIH VIL
tWCH
tDS VIH DQ (Input) VIL
tDH VALID DATA IN
DQ VOH (Output) VOL
HIGH-Z
"H" or "L"
DESCRIPTION A write cycle is similar to a read cycle except WE is set to a Low state and OE is a "H" or "L" signal. A write cycle can be implemented in either or three ways - early write, OE write (delayed write), or read-modify-write. During all write cycles, timing parameters tRWL, tCWL and tRAL must be satisfied. In the early write cycle shown above tWCS satisfied, data on the DQ pin is latched with the falling edge of CAS and written into memory.
12
MB814400A-60/MB814400A-70/MB814400A-80
Fig. 7 - OE (DELAYED WRITE CYCLE)
tRC tRAS RAS VIH VIL tCSH tCRP VIH VIL tASR tRAH tASC A0 to A10 VIH VIL ROW ADD COL ADD tCWL tWCH tRWL tWP VIH WE VIL tDZC DQ (Input) VIH VIL HIGH-Z tAA tRAC HIGH-Z tDZO VIH OE VIL tOED tCAC tDS tDH VALID DATA IN tCAH tRAD tCAL tRAL tRCD tCAS tRSH CAS tRP
VOH DQ (Output) VOL
HIGH-Z tOEA tOEZ tOEH
"H" or "L" Invalid Data
DESCRIPTION In the OE (delayed write) cycle, tWCS is not satisfied; thus, the data on the DQ pins is latched with the falling edge of WE and written into memory. The Output Enable (OE) signal must be changed from Low to High before WE goes Low (tOED + tT + tDS).
13
MB814400A-60/MB814400A-70/MB814400A-80
Fig. 8 - READ-MODIFY-WRITE-CYCLE
tRWC tRAS RAS VIH VIL tCRP CAS VIH VIL tASR tRAH tCSH tRCD tCAS tRSH tRP
tRAD tASC tCAH tRAL COL ADD tRWD tRCS tCWL tRWL
A0 to A9
VIH VIL
ROW ADD
WE
VIH VIL
tCWD tAWD tDS tDZC tWP tDH HIGH-Z tOED tCAC tRAC HIGH-Z tON tOEA tDZO tON tOEZ
VALID
DQ (Input)
VIH VIL
VALID DATA IN tOEH
tAA DQ VOH (Output) VOL
HIGH-Z
OE
VIH VIL
"H" or "L"
DESCRIPTION The read-modify-write cycle is executed by changing WE from High to Low after the data appears on the DQ pins. In the read-modifywrite cycle, OE must be changed from Low to High after the memory access time.
14
MB814400A-60/MB814400A-70/MB814400A-80
Fig. 9 - FAST PAGE MODE READ CYCLE (Early Write)
tRASP RAS VIH VIL tRAD tCRP CAS VIH VIL tASR tRAH A0 to A9 VIH VIL
ROW ADD
tRCD
tRHCP tRP
tPC tCSH tCAS tASC
COL ADD
tCP
tRSH tCAS tCAS tCAH tASC
COL ADD
tCAH
tASC
tCAH
tRRH
tRAL
COL ADD
tRCS VIH VIL tDZC VIH DQ (Input) VIL
tRCH
tRCS tRCH
tRCS
tRCH
WE
tOEL tCPA tDZC tDZC
HIGH-Z
HIGH-Z
HIGH-Z
tDZO tRAC tON
tOH tCAC tOFF
tDZO tCAC ton
tOH tOFF
tDZO
DQ VOH (Output) VOL
HIGH-Z tAA tOEA tOEZ tAA tOEA tOEZ
OE
VIH VIL tOED tOED "H" or "L"
Valid Data
DESCRIPTION The fast page mode of operation permits faster successive memory operations at multiple column locations of the same row address. This operation is performed by strobing in the row address and maintaining RAS at a Low level and WE at a High level during all successive memory cycles in which the row address is latched. The access time is determined by tCAC, tAA, tCPA, or tOEA, whichever one is the latest in occurring.
15
MB814400A-60/MB814400A-70/MB814400A-80
Fig. 10 - FAST PAGE MODE WRITE CYCLE (OE = "H" or "L")
tRASP RAS VIH VIL tCSH tCRP tRCD CAS VIH VIL tRAH tASR A0 to A9 VIH VIL ROW ADD tWCS VIH VIL tWP tDS VIH DQ (Input) VIL VALID DATA tDH tDS VALID DATA tWP tDH tDS tWP tASC COL ADD tWCH tWCS tCWL WE tCWL tRAD tCAH tASC tCAH tCAL COL ADD tWCH tWCS tWCH tCWL tASC COL ADD tCAH tRAL tCAS tPC tCP tCAS tCAS tRHCP tRSH tRP
tDH VALID DATA
DQ VOH (Output) VOL
HIGH-Z
"H" or " L"
DESCRIPTION The fast page mode write cycle is executed in the same manner as the fast page mode read cycle except for the states of WE and OE are reversed. Data appearing on the DQ pins is latched on the falling edge of CAS and written into memory. During the fast page mode write cycle, including the delayed (OE) write and read-modify-write cycles, tCWL must be satisfied.
16
MB814400A-60/MB814400A-70/MB814400A-80
Fig. 11 - FAST PAGE MODE OE WRITE CYCLE
tRAD RAS VIH VIL tCRP CAS VIH VIL tRAH tASR A0 to A9 VIH VIL
ROW ADD.
tRASP tPC tRCD tCSH tCAS tRP tCP tRSH tCAS tCAS tASC tCAH
COL ADD COL ADD
tASC
COL ADD
tCAH
tASC
tCAH
tRAL
tCWL WE VIH VIL tDZC tDS tDH VIH DQ (Input) VIL
VALID
tRCS tWP tWP tDS
tCWL
tRWL tCWL tWP
tDH
VALID
tDH tDS
VALID
tAA tCAC tRAC
HIGH-Z
tOED tOED tOEH tAA tCAC tOEH tAA tCAC tOED
DQ VOH (Output) VOL
tDZO tOEA tOEZ tOEA tOEZ
tOEA tOEZ
tOEH
OE
VIH VIL
"H" or "L" Invalid Data
DESCRIPTION The fast page mode OE (delayed) write cycle is executed in the same manner as the fast page mode write cycle except for the states of WE and OE. Input data on the DQ pins are latched on the falling edge of WE and written into memory. In the fast page mode delayed write cycle, OE must be changed from Low to High before WE goes Low (tOED + tT + tDS).
17
MB814400A-60/MB814400A-70/MB814400A-80
Fig. 12 - FAST PAGE MODE READ-MODIFY-WRITE CYCLE
tRAD VIH RAS VIL tCRP CAS VIH VIL tRAH tASR A0 to A9 VIH VIL ROW ADD tRCS VIH VIL tDZC DQ (Input) VIL VIH tOED tCAC tCAH tASC COL ADD tCWL tCWD tAWD tDS VALID tAA DQ VOH (Output) VOL tAA tWP COL ADD tCPWD tRCS tCWD tDS tDH VALID tOED tCAC tDH VALID tDS tDH tWP tCWL tPRWC tRCD tCSH tCAS tRSH tCP tCAS tASC tCAH COL ADD tRCS tCWL tWP tRWL tASC tCAH tCAS tRAL tRASP tRP
WE
HIGH-Z tON tDZO
tON tOEZ tOEH tOEZ
OE
VIH VIL tOEA tCPA tOEA
"H" or "L" Valid Data
DESCRIPTION During fast page mode of operation, the read-modify-write cycle can be executed by switching WE from High to Low after input date appears at the DQ pins during a normal cycle.
18
MB814400A-60/MB814400A-70/MB814400A-80
Fig. 13 - RAS-ONLY REFRESH (WE = OE = "H" or "L")
tRC tRAS RAS VIH VIL tASR A0 to A9 VIH VIL tCRP CAS VIH VIL tOH DOUT VOH VOL HIGH-Z "H" or "L"
DESCRIPTION Refresh of RAM memory cells is accomplished by performing a read, a write, or a read-modify-write cycle at each of 1024 row addresses every 16.4-milliseconds. Three refresh modes are available: RAS-only refresh, CAS-before-RAS refresh, and hidden refresh. RAS-only refresh is performed by keeping RAS Low and CAS High throughout the cycle; the row address to be refreshed is latched on the falling edge of RAS. During RAS-only refresh, DQ pin is kept in a high-impedance state.
tRP tRAH ROW ADDRESS tRPC
tOFF
Fig. 14 - CAS-BEFORE-RAS REFRESH (ADDRESSES = OE = "H" or "L")
tRC RAS VIH VIL tCPN CAS VIH VIL tWSR WE VIH VIL tOFF tOH DQ VOH (Output) VOL
DESCRIPTION
tRAS tCSR
tRP
tCHR
tRPC
tWHR
HIGH-Z "H" or "L"
CAS-before-RAS refresh is an on-chip refresh capability that eliminates the need for external refresh addresses. If CAS is held Low for the specified setup time (tCSR) before RAS goes Low, the on-chip refresh control clock generators and refresh address counter are enabled. An internal refresh operation automatically occurs and the refresh address counter is internally incremented in preparation for the next CAS-before-RAS refresh operation. WE must be held High for the specified set up time (tWSR) before RAS goes low in order not to enter "test mode".
19
MB814400A-60/MB814400A-70/MB814400A-80
Fig. 15 - HIDDEN REFRESH CYCLE
tRC tRAS RAS VIH VIL tRCD tRAD CAS VIH VIL tASR A0 to A9 VIH VIL tRAH tASC ROW ADDRESS tRCS tAA tRAC tDZC DQ (Input) DQ (Output) VIH VIL tON VOH VOL VIH VIL tRCS [Test Mode] WE VIH VIL tRAC tDZC DQ (Input) DQ (Output) VIH VIL tON VOH VOL VIH VIL HIGH-Z tDZO OE tOEA tCAC tAA tRRH HIGH-Z tDZO OE tOEA tCAC tRAL tCAH COLUMN ADDRESS tRRH tRSH tOEL
tRP
tRC tRAS tRP tCRP tCHR
[Normal Mode] WE VIH VIL
tWSR
tWHR
HIGH-Z tOFF tOH VALID DATA OUT tOEZ tOED
tWSR
tWHR
HIGH-Z tOH VALID DATA OUT tOEZ
tOFF
tOED
"H" or "L"
DESCRIPTION A hidden refresh cycle may be performed while maintaining the latest valid data at the output by extending the active time of CAS and cycling RAS. The refresh row address is provided by the on-chip refresh address counter. This eliminates the need for the external row address that is required by DRAMs that do not have CAS-before-RAS refresh capability. WE must be held High for the specified set up time (tWSR) before RAS goes Low in order not to enter "test mode" .
20
MB814400A-60/MB814400A-70/MB814400A-80
Fig. 16 - TEST MODE SET CYCLE (A0 to A9, OE = "H" or "L")
tRC VIH VIL tRAS tRP
RAS
tCPN tCSR CAS VIH VIL tCHR
tRPC
tWSR WE VIH VIL tOFF tOH DOUT VOH VOL
tWHR
HIGH-Z
"H" or "L"
DESCRIPTION Test Mode ; The purpose of this test mode is to reduce device test time to one eighth of that required to test the device conventionally. The test mode function is entered by performing a WE and CAS-before-RAS (WCBR) refresh for the entry cycle. In the test mode, read and write operations are executed in units of eights bits which are selected by the address combination of RA10, CA0 and CA10. In the write mode, data at DIN is written into eight cells simultaneously. But the data must be input from DQ2 only. In the read mode, the data of eight cells at the selected addresses are read back out from DQ and checked in the following manner. When the eight bits are all "L" or all "H", a "H" level is output. When the eight bits show a combination of "L" and "H", a "L" level is output. The test mode function is exited by performing a RAS-only refresh or a CAS-before-RAS refresh for the exit cycle. In test mode operation, the following parameters are delayed approximately 5 ns from the specified value in the data sheet. tRC, tRWC, tRAC, tAA, tRAS, tCSH, tRAL, tRWD, tAWD, tPC, tPRWC, tCPA, tRHCP , tCPWD
21
MB814400A-60/MB814400A-70/MB814400A-80
Fig. 17 - CAS-BEFORE-RAS REFRESH COUNTER TEST CYCLE
VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL tWSR tCSR
RAS
tCHR
tCP
tFRSH tFCAS tFCAH tRAL
tRP
CAS
tASC tWHR tRCS tDZC
A0 to A9
COLUMN ADDRESS tCWL tFCWD
tRWL tWP tDH
WE DQ (Input)
tDS
DQ VOH (Output) VOL OE VIH VIL
HIGH-Z tOED tFCAC HIGH-Z tDZO tON tOEA tOEZ
VALID DATA IN
HIGH-Z tOEH
"H" or "L" Valid Data
DESCRIPTION A special timing sequence using the CAS-before-RAS refresh counter test cycle provides a convenient method to verify the functionality of CAS-before-RAS refresh circuitry. If, after a CAS-before-RAS refresh cycle. CAS makes a transition from High to Low while RAS is held Low, read and write operations are enabled as shown above. Row and column addresses are defined as follows: Row Address: Bits A0 through A9 are defined by the on-chip refresh counter. Column Address: Bits A0 through A9 are defined by latching levels on A0-A9 at the second falling edge of CAS. The CAS-before-RAS Counter Test procedure is as follows ; 1) Initialize the internal refresh address counter by using 8 RAS only refresh cycles. 2) Use the same column address throughout the test. 3) Write "0" to all 1024 row addresses at the same column address by using normal write cycles. 4) Read "0" written in procedure 3) and check; simultaneously write "1" to the same addresses by using CAS-before-RAS refresh counter test (read-modify-write cycles). Repeat this procedure 1024 times with addresses generated by the internal refresh address counter. 5) Read and check data written in procedure 4) by using normal read cycle for all 1024 memory locations. 6) Reverse test data and repeat procedures 3), 4), and 5).
(At recommended operating conditions unless otherwise noted.) No. 90 91 92 93 94 Parameter Access Time from CAS Column Address Hold Time CAS to WE Delay Time CAS Pulse Width RAS Hold Time Symbol tFCAC tFCAH tFCWD tFCAS tFRSH MB814400A-60 MB814400A-70 MB814400A-80 Unit Min. Max. Min. Max. Min. Max. -- ns 50 -- -- 60 55 -- -- -- 30 ns 30 35 75 50 50 -- -- -- 80 55 55 -- -- -- 90 60 60 -- -- -- ns ns ns
Note . Assumes that CAS-before-RAS refresh counter test cycle only.
22
MB814400A-60/MB814400A-70/MB814400A-80
s PACKAGE DIMENSIONS
(Suffix: -PJN)
26 pin, Plastic SOJ (LCC-26P-M04)
3.40 -0.20 .134 -.008 * 17.150.13(.675.005)
22 26 18 14
+0.35 +.014
2.25(.089)NOM 0.64(.025)MIN R0.81(.032)TYP
INDEX
7.62 (.300) 8.430.13 (.332.005) NOM
6.810.51 (.268.020)
LEAD No
1 5 9 13
0.20 -0.02 .008 -.001
+0.05
+.002
1.27(.050)TYP
2.54(.100)TYP 15.24(.600)REF 2.50(.098)NOM
Details of "A" part 0.81(.032)MAX
0.10(.004)
"A"
0.430.10(.017.004)
C
1995 FUJITSU LIMITED C26054S-3C-1
Dimensions in mm(inches).
23
MB814400A-60/MB814400A-70/MB814400A-80
s PACKAGE DIMENSIONS (Continued)
(Suffix: -PZ)
20 pin, Plastic ZIP (ZIP-20P-M02)
25.88 -0.30 1.019 -.012
+0.20 +.008
2.850.20 (.112.008)
INDEX
8.500.25 (.335.010)
9.830.33 (.387.013)
0.250.05 (.010.002)
3.00(.118)MIN
1.27(.050)TYP LEAD No.
1
0.500.10(.020.004)
2.54(.100)TYP
(BOTTOM VIEW)
20
C
1994 FUJITSU LIMITED Z20002S-4C-2
Dimensions in mm(inches).
24
MB814400A-60/MB814400A-70/MB814400A-80
s PACKAGE DIMENSIONS (Continued)
(Suffix: -PFTN)
26 pin, Plastic TSOP(II) (FPT-26P-M01)
Details of "A" part
26 22 18 14
0.15(.006)
0.25(.010) INDEX "A" 0.15(.006)MAX 0.50(.020)MAX LEAD No.
1 5 9 13
* 17.140.10
(.675.004) 0.400.10 (.016.004) 0.21(.008)
M
1.10 -0.05 +.004 .043 -.002
+0.10
9.220.20 (.363.008) 7.620.10 (.300.004)
0.150.05 (.006.002)
1.27(.050)TYP
0.10(.004) 15.24(.600)REF
0(0)MIN (STAND OFF)
0.500.10 (.020.004)
8.220.20 (.324.008)
C
1994 FUJITSU LIMITED F26001S-3C-3
Dimensions in mm(inches).
25
MB814400A-60/MB814400A-70/MB814400A-80
s PACKAGE DIMENSIONS (Continued)
(Suffix: -PFTR)
26 pin, Plastic TSOP(II) (FPT-26P-M02)
Details of "A" part
26 22 18 14
0.15(.006)
0.25(.010) INDEX "A" 0.15(.006)MAX 0.50(.020)MAX LEAD No.
1 5 9 13
15.24(.600)REF 1.27(.050)TYP 0.10(.004) 0(0)MIN (STAND OFF) 0.500.10 (.020.004) 8.220.20 (.324.008) 0.150.05 (.006.002)
0.400.10 (.016.004)
0.21(.008)
M
1.10 -0.05 +.004 .043 -.002
+0.10
* 17.140.10
(.675.004)
7.620.10 (.300.004) 9.220.20 (.363.008)
Dimensions in mm(inches).
C
1994 FUJITSU LIMITED F26002S-3C-3
26
FUJITSU LIMITED
For further information please contact:
Japan FUJITSU LIMITED Corporate Global Business Support Division Electronic Devices KAWASAKI PLANT, 4-1-1, Kamikodanaka Nakahara-ku, Kawasaki-shi Kanagawa 211-88, Japan Tel: (044) 754-3763 Fax: (044) 754-3329 North and South America FUJITSU MICROELECTRONICS, INC. Semiconductor Division 3545 North First Street San Jose, CA 95134-1804, U.S.A. Tel: (408) 922-9000 Fax: (408) 432-9044/9045 Europe FUJITSU MIKROELEKTRONIK GmbH Am Siebenstein 6-10 63303 Dreieich-Buchschlag Germany Tel: (06103) 690-0 Fax: (06103) 690-122 Asia Pacific FUJITSU MICROELECTRONICS ASIA PTE. LIMITED #05-08, 151 Lorong Chuan New Tech Park Singapore 556741 Tel: (65) 281-0770 Fax: (65) 281-0220
All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information and circuit diagrams in this document presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. Also, FUJITSU is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. FUJITSU semiconductor devices are intended for use in standard applications (computers, office automation and other office equipment, industrial, communications, and measurement equipment, personal or household devices, etc.). CAUTION: Customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with FUJITSU sales representatives before such use. The company will not be responsible for damages arising from such use without prior approval. Any semiconductor devices have inherently a certain rate of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Control Law of Japan, the prior authorization by Japanese government should be required for export of those products from Japan.
F9703 (c) FUJITSU LIMITED Printed in Japan
24

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