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| CobraNetTM EV-2 Digital Audio Networking Processor CobraNet TM EV-2 Development System Manual (c)Copyright 2005 Cirrus Logic, Inc. http://www.cirrus.com SEP 2005 EV-2MAN21 CobraNetTM EV-2 Contacting Cirrus Logic Support For all product questions and inquiries contact a Cirrus Logic Sales Representative. To find the one nearest to you go to www.cirrus.com IMPORTANT NOTICE Cirrus Logic, Inc. and its subsidiaries ("Cirrus") believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided "AS IS" without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liability. No responsibility is assumed by Cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights associated with the information contained herein and gives consent for copies to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other products of Cirrus. This consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR W ARRANTED FOR USE IN AIRCRAFT SYSTEMS, MILITARY APPLICATIONS, PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, AUTOMOTIVE SAFETY OR SECURITY DEVICES, LIFE SUPPORT PRODUCTS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK AND CIRRUS DISCLAIMS AND MAKES NO W ARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE IMPLIED W ARRANTIES OF MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE, W ITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED IN SUCH A MANNER. IF THE CUSTOMER OR CUSTOMER'S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICATIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER AGENTS FROM ANY AND ALL LIABILITY, INCLUDING ATTORNEYS' FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION W ITH THESE USES. Cirrus Logic, Cirrus, the Cirrus Logic logo designs, CobraNet, and DSP Conductor are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks or service marks of their respective owners. SPI is a registered trademark of Motorola, Inc. 2 Rev. 2.1 CobraNetTM EV-2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Getting Started . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Required Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 Included: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 Not Supplied: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 Setup Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 Switch and Connector Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 J300 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 J401 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 J700 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 P450 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 P501 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 P504 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 SW200 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 SW201-SW204 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 SW500 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 Detailed Description of EV-2 Components . . . . . . . . . . . . . . . . . . . . . . . . . . 11 The Microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Microcontroller Memory Space: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Microcontroller Port Connections: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Interfacing the Microcontroller to the CM . . . . . . . . . . . . . . . . . . . . . . . . .13 Programming the Microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 Interfacing Serial Audio to the CM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 FPGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 Configuring the FPGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 Functional Discussion of FPGA Operation . . . . . . . . . . . . . . . . . . . . . . . .18 Hex Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 EV-2 Schematics, Page-by-Page Description . . . . . . . . . . . . . . . . . . . . . . . .22 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 Microcontroller and Hex Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 A/D Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 D/A Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 Connectors and Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 Optional VCXO and clock buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 AES3 Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 Power Supply Conditioning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 FPGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 Appendix A: Definition of Terms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Appendix B: EV-2 Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Appendix C: Other Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Appendix D: EV-2 Schematic Drawings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Appendix E: EV-2 Command Line Interface. . . . . . . . . . . . . . . . . . . . . . . . . . 38 Rev. 2.1 3 CobraNetTM EV-2 Introduction The EV-2 provides a means of evaluating the CM-1 or CM-2 CobraNetTM Modules and the Cirrus Logic CobraNet Silicon Series of devices. In addition to evaluating the CM-1 or CM-2 (hereafter collectively referred to as the CM except where differences between the CM-1 and CM-2 exist), the user may also use the EV-2 as a development platform and as an example interface for CMs, the Cobranet Silicon Series, and other CobraNet related projects. The EV-2 connects to the CM via the module's host interface. An 8051-type microcontroller interfaces to the CM's host port, and a simple audio router on the EV-2 allows multiple audio inputs and outputs to connect to the CM's serial audio interface. The EV-2 software provides a simple interface for audio routing on the EV-2, as well as development support. C M M O D U L E I N T E R F A C E VCXO ADC DAC FPGA Analog Input Analog Output AES Output Input LEDs 8051 SRAM Hex Switches RS232 Interfaces Figure 1. EV-2 Block Diagram Features*: * Analog audio I/O: Two channels of analog audio input converted to high quality, 24-bit, 48 kHz or 96 kHz digital audio. Two channels of 24-bit, 48 kHz or 96 kHz digital audio converted to high quality, analog audio output. Refer to Appendix B for audio I/O specifications. Digital audio I/O: One stream of AES3 input and one stream of AES3 output. An AES3 stream is two channels of digital audio. The AES3 input stream is sample rate converted. 8051-type microcontroller: 64kB on-chip Flash Program Memory, 1kB internal SRAM, 32kB external SRAM and in-system programmability. Field programmability: The supplied EV-2 software provides a means to reprogram EV-2 microcontroller firmware for field upgrades or user development. RS232 Interfaces: Two RS232 interfaces, one direct to the CM and another to the microcontroller. * * * * Rev. 2.1 4 CobraNetTM EV-2 * Routing flexibility: Route from any audio source to any audio sink using the supplied EV-2 software. Route to and from the CM as well as within the EV-2. Sine wave generation: A sine wave test tone may be used as an alternate audio source. Minimal frequency and gain control is provided. Hex switches: Four hex formatted switches may be used for network identification of the CobraNet module and/or user development. Command line interface: The 8051, via its RS232 serial interface, can be used to configure the CM using a command line interface.Cobranet HMI variables can be viewed and modified using this interface. Refer to Appendix E for a description of the Command line interface. LED display: Three LED indicators are provided and may be used for user development. Power supply: Uses standard computer ATX power supply (not included). * * * * * *The EV-2 has gone through a hardware revision to incorporate state-of-the-art A/D and D/A converters from Cirrus logic. The new revision board is identified by a "Rev. E" designator. Most of the changes in this document relate to the new converters and their functionality. Any other changes which differ from the Rev. D board will be identified as such. 5 Rev. 2.1 CobraNetTM EV-2 Getting Started Required Materials Included: The CobraNet EV-2 Development Package ships with the following materials: * * * EV-2 module w/ CM CobraNet PCB 3' CAT5 crossover cable 6 - Pin Phoenix-style audio connectors Qty. (2) Qty. (1) Qty. (6) NOTE: In order to provide you with the latest versions of our firmware and software development kit (SDK), we use web-based distribution for our updates. To obtain the latest versions of documentation and software, please go to www.cirrus.com/cobranetsoftware. Not Supplied: * Two (2) ATX computer power supplies with cables are required, one for each EV-2 module. These devices are commonly available at computer retail stores. Audio cables. RS232 cables. (Not required to pass audio.) * * Setup Procedure * Using the supplied Phoenix connectors, build audio input and output cables and two AES3 cables (if desired). These will be used to connect your audio input and output devices to the EV-2 modules. For analog audio pin assignments, see Figure 2 or Figure 3 below. For AES3 pin assignments, see Figure 4 below. Connect a power supply to the ATX Power Connector at P450 on each EV-2 module. Connect the CAT5 crossover cable between the Ethernet jacks at J5 on each CM board. Connect a stereo audio source to the analog inputs at J300. Connect a stereo audio monitor to the analog outputs at J401. Apply power to both EV-2 modules. Verify that you have established a proper connection. See Table 1 on page 7 for Ethernet connector LED status The LED CR710, if on, indicates that the AES3 receiver does not detect a valid AES3 data input stream. If AES3 I/O is not being used, this can be disregarded. Otherwise, connect a proper AES3 signal to J700. Note that there must be a valid AES3 input for the AES3 output to work. * * * * * * Rev. 2.1 6 CobraNetTM EV-2 * * CR300, when on, indicates an overflow condition detected on the A/D converter. The units are now ready to pass audio. The audio input at J300 on one board should now appear at J401 on the other board and vice versa. gnd - + gnd - + Input Output P450 Hex Switches SW201-4 SW508 J700 AES I/O Power StatuAs ATX Power Connector P504 Serial Bridging Connector CR710 AES LED System Reset Switch Programming Switch P501 SW200 CobraNet module CM-1 or CM-2 Serial MCU Connector CR300 Ethernet Jacks J5 J6 J401 Audio Outputs (+-gnd) (+-gnd) J300 Audio Inputs (+-gnd) (+-gnd) Figure 2. Connector, Switch and Jack Locations Module CM-1 Condition Conductor Performer Fault CM-2 Left LED Flashing Orange Solid Orange Flashing Orange Left LED Flashing Green Flashing Green Flashing Red Right LED Solid Orange Solid Green Flashing Red Right LED Flashing Green Flashing Green Flashing Orange Table 1: Ethernet Jack Indicator Legend. 7 Rev. 2.1 CobraNetTM EV-2 Switch and Connector Functionality J300 Audio Input Connector: Phoenix-style connector for two-channel balanced audio input, +14.4 dBu maximum (0 dBFS). Refer to Figure 3 for the signal connection. J401 Audio Output Connector: Phoenix-style connector for two-channel balanced audio output, +8.3 dBu maximum (0 dBFS). Refer to Figure 3 for the signal connection. + Left gnd + Right gnd Figure 3. Analog Audio Input and Output Phoenix-style Connectors J700 AES3 I/O Connector: Phoenix-style connector for an AES3 stream. Refer to Figure 4 for the signal connection. For the AES3 tranceiver to operate properly a vailid AES3 signal must be provided at the AES3 input. + gnd Output + gnd Input Figure 4. AES3 I/O Phoenix-style Connector P450 ATX power supply connector: ATX power supply is not included with this kit. P501 9-Pin, D-Type Connector: RS232 connection for communicating with the EV-2 microcontroller using the supplied routing software or a command line interface ( see Appendix E ). Data format is 19200, e, 8, 1. P504 9-Pin, D-Type Connector: RS232 connection to the CM for serial bridging. The default data format is 19200 baud, 9-bit format for the CM-1. 9-bit format supports any 8 bit format with parity such as 19200, e, 8, 1. The default data format for the CM-2 is 19200 baud, 8-bit format. Rev. 2.1 8 CobraNetTM EV-2 SW200 Programming switch: The EV-2 microcontroller can be programmed via its serial port, connector P501. The supplied software can be used to perform field updates to the board's code and firmware. This programming capability is initially disabled, but can be enabled by setting the hex switches to FFF8H and then clicking on the "Hex Switches" display (see Figure 6 ). For more information about the programming mode, please refer to the Programming the Microcontroller section. SW201-SW204 Hex switches: SW201-SW204 may be used to uniquely identify the unit on a network. Valid settings fall within the range 0000-FFEF (values FFF0-FFFF are reserved). Changing these values updates the value of the CobraNet module's SNMP variable, sysName, to the current hex switch value. Through SNMP, the user may query this variable. The SNMP response is of the form "PEAK_AUDIO_EVAL-SWwxyz", where the wxyz represents the hex values of the switches in ASCII format. SW500 System reset switch: This momentary switch resets the EV-2 and attached CM, and initiates calibration operations for the analog-to-digital converter (ADC) and digital-to-analog converter (DAC). Software The EV-2 is supplied with the CNEval.exe application, which may be used to setup audio routes on the EV-2 (this should not be confused with routing audio over the CobraNet network). The EV-2 has seven sources of audio input, with each source consisting of a stereo pair of audio channels. The sources are: * * * * Four Synchronous Serial Interface (SSI) audio streams from the CM An AES3 audio input stream. One audio stream from the ADC (Rev. D boards had two audio streams from the ADC) A sine wave generator, a stream of two identical 24-bit resolution sine waves. Using CNEval.exe, the user can route any of these seven source streams to any of the six output streams. The available output streams are: * * * The four SSI audio streams going to the CM One going to the DAC One to the AES3 transmitter. CNEval.exe communicates with the EV-2 via an RS-232 serial connection. CNEval.exe can communicate using either COM1 or COM2 of the PC on which it is running. The connection from computer to EV-2 must be made as follows: * Connect a straight-through, male-to-female, 9-pin RS232 cable to EV-2 connector P501. 9 Rev. 2.1 CobraNetTM EV-2 * Select the appropriate PC serial port. The software will attempt to make contact with the EV-2. Once communication is established, the routing can then be configured. (See Figure 5 below for an example of a routing scheme.) * Figure 5. Screen Shot of EV-2 Software - Audio Routing Interface The default on power up state of the EV-2 is for the ADC and DAC to be the source and sink respectively, using the CM's SSI #0 I/O stream. The audio is then transmitted/received via a CobraNet Bundle to/from the other CM. This allows evaluation of the CobraNet module in the analog domain without any configuration. The EV-2 software also has a programming mode that may be used to perform field updates of the EV-2 microcontroller code. For more information about the programming mode, please refer to the section Programming the Microcontroller below. Besides the Route panel, the HMI panel under the Panels menu allows the user to configure some HMI variables for evaluation purposes. From the HMI panel the user can set receiver and transmitter bundle assignments as well as changes latency, data format, and sample rate. The Peek menu provides a means to view HMI variables. In the various panels under Peek, items that are in an indented text field are ones which are read/write. These can not be changed from the Peek panels but are there to alert the user that these are variables that could be changed via SNMP or the Host port. Rev. 2.1 10 CobraNetTM EV-2 Detailed Description of EV-2 Components The Microcontroller The microcontroller on the EV-2 is a Philips Semiconductor P89C51RD2. This microcontroller has 64 kByte of internal Flash Program Memory and 1 kByte of Static RAM. The microcontroller is field programmable using the provided CNEval.exe software. The microcontroller's clock rate is 33Mhz. Philips P89C51RD2 preliminary specification for programming information and part usage may be found on the Philips Semiconductor website: http://www.semiconductors.philips.com. Microcontroller Memory Space: Besides the internal program and data memory space the microcontroller also has an external 64k data memory space. The microcontroller is hard-wired to execute from internal Flash Program Memory only. The Flash Program Memory has been segmented to store both Program and FPGA configuration data. The Program Memory map is shown in Table 2 on page 11 and the data memory map is shown in Table 3 on page 11: Memory Location 0x0000-0xBFFF 0xC000-0xFFFF Description Program Memory FPGA Configuration Data Table 2: Flash Program Memory Map Memory Location 0x0000- 0x02FF 0x0300-0x7FFF 0x8000-0x87FF 0x8800 0x8801-0xFFFF Description Internal Static RAM External Static RAM Unused FPGA express mode configuration* Unused Table 3: Microcontroller Data Memory Map After Reset but Before FPGA Configuration *After reset, the FPGA is the only device in the upper 32k of the data memory space. The microcontroller is then able to configure the FPGA and once configured the FPGA performs more sophisticated address decoding of the upper data memory space. Refer to the FPGA section of this document for a detailed description of the configuration process and a listing of the current EV-2 FPGA firmware memory map. 11 Rev. 2.1 CobraNetTM EV-2 Microcontroller Port Connections: Port 0: used for the address/data (AD) bus. Once configured, the FPGA latches the lower address byte from the AD lines. Port 1: used for several purposes as shown in Table 4 on page 12. Bit # 0 Name of Signal INIT_IO# I/O I Description Used when configuring the FPGA. Refer to Xilinx Spartan datasheet for more detail. Used to initiate the FPGA configuration. Refer to Xilinx Spartan datasheet for more detail. Mute signal from the CM module Not used. May be used to concatenate settings from other hex switches. Used to latch the hex switch values into a serial shift register. Used to shift the hex switch values from the serial shift register. The hex switch value from the serial shift register appears at this input. This is used for communication between the FPGA and MCU. 1 PROGRAM# O 2 3 MUTE# HEX_DATA_IN I O 4 5 6 HEX_CLOCK HEX_SHIFT HEX_DATA_OUT O O O 7 MCU_P17 O Table 4: Port 1 Signal Descriptions Port 2: upper address bus. Port 2 is output only. Rev. 2.1 12 CobraNetTM EV-2 Port 3: See Table 5 on page 13. Bit # 0 1 2 RXD TXD HREQ# Name of Signal I/O I O O Description RS232 serial port receive signal. RS232 serial port transmit signal Connected to the CM module host request signal. See CobraNet Technical Datasheet for a complete description of this signal. Connected to the CM module host acknowledge signal. See CobraNet Technical Datasheet for a complete description of this signal. May be used as an interrupt request on the microcontroller. Watchdog signal from the CM Connected to SCI_CLK via the FPGA. Also used to detect sample rate. Microcontroller write signal. Microcontroller read signal. 3 HACK# I 4 5 Watchdog MCU_P35 I I/O 6 7 WR# RD# O O Table 5: Port 3 Signal Descriptions Interfacing the Microcontroller to the CM Please refer to the EV-2 schematic, found in Appendix D for information regarding interfacing to the CM. The CM has a host interface that allows a host processor (such as an 8051 microcontroller) to interface to the DSP on the CM. From a hardware perspective the interface to the CM-1 and CM-2 is almost the same,. The host interface signals are a data strobe signal, HDS#; a read/write line, HRW, an 8-bit bi-directional data bus, HD0-HD7, and three address lines, HA0-HA2 on the CM-1 and four address lines, HA0-HA3 on the CM-2. The HEN# line has been configured by the CobraNet software to be ignored or seen as a logic low. Given this host configuration, the interface of the microcontroller to the CM host port is straightforward. In addition to the above signals there are two more, HACK# and HREQ# which can be used as flags to indicate a state change on the CM. With regard to the CM-1 which uses a Motorola DSP56303, care must be taken with the timing of HDS# and HWR. Motorola's timing specifications for the DSP56303 host port in a non-multiplexed, single data strobe mode requires a set up time from the falling edge of HWR# to the falling edge of HDS# of 4.7ns and the hold time from the rising edge of HDS# to the rising edge of HWR# of 3.3ns. The pulse of the HDS# signal must be wholly within the pulse of the HWR# signal with the constraints stated above. Please refer to Motorola's DSP56303 Technical Data sheet for complete information regarding timing and interface issues. This is available for download from the Motorola web site at http://www.freescale.com. 13 Rev. 2.1 CobraNetTM EV-2 In the EV-2 application, the host address lines are generated by the address latch in the FPGA (see Table 6 on page 16) and the host data bus is connected directly to the data bus of the microcontroller. The HREQ# and HACK# signals are connected to the two interrupt inputs of the microcontroller. These signals may be used for data handshaking and asynchronus notification respectively. The final host signal, HRESET#, resets the CM when asserted low. Setting a bit in the host reset register (see Table 6 on page 16) controls this signal. See the discussion of the FPGA below for more information about this signal. Supplemental information regarding the CM Host interface may by found in the section titled "Host Management Interface" in the CS1810xx data sheet available on the Cirrus Logic website: www. cirrus.com. Programming the Microcontroller The EV-2 is designed so that field updates of both the microcontroller firmware and the FPGA firmware are possible. If only the efficacy and performance of the CobraNet paradigm is being evaluated, reprogramming of the microcontroller is not required. However, use of the field program capability may aid in the design of a CobraNet based product. Modifying the Flash Program Memory of the microcontroller constitutes the update. The programming instructions that follow pertain to the supplied EV-2 routing/programming software, CNEval.exe. Programming the microcontroller is a multi-stage process: 1. 2. 3. 4. Install the EV-2 CNEval.exe software on your Windows-based computer. Install an RS232 cable from port 1 or 2 on your PC to P501, the 9-pin D-type connector closest to the center of the board. Run CNEval.exe Change the hex switches (SW201-SW204) to FFF8 (as viewed when looking at the hex switches). You may, as an alternative, click in the narrow recessed panel on the left of the upper status bar. Select "Program" from the Utility menu in CNEval.exe. From the "Serial" drop-down menu select a serial connection, either port COM1 or COM2 based on which is connected. Located near the two serial RS232 connectors is a switch, SW200. This switch must be set to the program mode position. The program position is indicated by silk screen on the EV-2 board. Push switch SW508, the momentary reset switch. SW508 is located just behind the hex switches. Select which firmware to update, either the FPGA or the 8051. Wait for programming to complete. Do not interrupt the programming process! Once programming has completed for the microcontroller or the FPGA firmware, return the programming switch, SW200, to the normal operation position and press the reset switch, SW508. Click OK to return to the main window in CNEval.exe. 5. 6. 7. 8. 9. 10. 11. 12. Rev. 2.1 14 CobraNetTM EV-2 Interfacing Serial Audio to the CM In general, interfacing to most off-the-shelf A/D and D/A converters is straightforward and the CM is no exception. Most signals for a direct connection to these as well as other audio ICs such as the CS8420 AES3 transceiver, are available on the CM module interface connector. Most converters provide for a choice of bit clock and sample (frame) clock polarity, as well as audio data formats such as SPITM or I2S. The A/D converter, a Cirrus Logic CS5381 is configured for slave operation, which means that it requires a bit clock and a sample (frame) clock input. The master, bit and sample clocks are direct connections from FS512, SCK and FS1 respectively, as is the data stream which comes from one of the SSI ports. The CM can be configured to clock data from either edge of the bit clock, as well as allowing for specifying the polarity of the sample clock. (See the CobraNet website and the CobraNet Technology Datasheet for more information.) This is important since the CS5396 works with sample pairs which need to be phase aligned. The polarity of the sample clock specifies this alignment. For the EV-2 application, the SSI ports of the CM have been programmed to send two channels per port. This allows a straightforward connection without any demultiplexing. The connection to the Cirrus Logic CS4398 D/A converter is similarly straightforward. Like the SCS5381, it uses the FS512, bit clock and sample clock directly from the CM. Data to the DAC and from the ADC are also direct except that they pass through a selector circuit in the FPGA. If a particular design does not include multiple sources of audio, then the connection can be direct to the CM interface connector. FPGA The Field Programmable Logic Array is a Xilinx Spartan(tm) XCS10XLVQ100-4. It is mapped into the microcontroller's memory space. The microcontroller must configure the FPGA after power on or reset. Express mode configuration is used for this part. Refer to the Xilinx Spartan(tm) XL family data sheet for more information on the Express mode configuration operation. This data sheet can be found at the Xilinx web site, http://www.xilinx.com/. The address for configuration is 0x8800. Once configured, the FPGA's two main functions are to decode the microcontroller's address signals and to route audio from a user selected source to a user selected destination. Secondary functions are to generate a sine wave signal and implement registers whose function are mostly of a control nature. A discussion of the memory decoding, routing, sine wave generation and other functions follow. The memory map of the upper 32k of the microcontroller space after configuration, is shown in Table 6 on page 16. Most bit-defined locations use the least significant microcontroller data bus signal AD0 as the controlling bit. Other data bits are ignored on these registers. Power on and reset default for all registers is 0 unless specified otherwise. 15 Rev. 2.1 CobraNetTM EV-2 Memory Location 0x8000 R/W W Description Bit register for green LED, CR903. 0=LED on, 1=LED off. Refer to Table 10 on page 20 for this and other LED registers. Bit register for red LED, CR904. 0=LED on, 1=LED off. Bit register for yellow LED, CR905. 0=LED on, 1=LED off. Bit register for green LED blink control. 0=blink off, 1=blink on. Bit register for green LED blink control. 0=blink off, 1=blink on. Bit register for green LED blink control. 0=blink off, 1=blink on. DAC audio routing address (see Table 7 on page 18). Bit register for DAC mute signal. 0=mute on, 1=mute off. Bit register for sample rate mode. 0=48k, 1=96k. Note: use AD1 instead of AD0 Bit register for DAC reset signal. 0=reset on, 1=reset off. Audio Calibration Status. 1=Calibrating, 0=Ready. See the Calibrating Audio section for details. Manual ADC Calibration. 0=Normal, 1=Calibrate. See the Calibrating the ADC section for details. (Rev. D applicable only) Bit register for ADC slave/master control. 0=Slave, 1=Master. (Rev. D applicable only) ADC high pass filter (HPF) select. 0=Enabled, 1=Disabled. AES3 audio routing address (see Table 7 on page 18). Bit register for AES3 mute signal. 0=AES output muted, 1=Unmuted. SSI 0 audio routing address (see Table 7 on page 18). Bit register for SSI 0 mute signal. 0=Muted, 1=Unmuted. SSI 1 audio routing address (see Table 7 on page 18). Bit register for SSI 1 mute signal. 0=Muted, 1=Unmuted. 0x8001 0x8002 0x8004 0x8005 0x8006 0x8008 0x8009 0x800A 0x800B 0x8010 0x8010 W W W W W W W W W R W 0x8011 0x8012 0x8018 0x8019 0x8020 0x8021 0x8028 0x8029 W W W W W W W W Table 6: Microcontroller Memory Map of Upper 32k After FPGA Configuration Rev. 2.1 16 CobraNetTM EV-2 Memory Location 0x8030 0x8031 0x8038 0x8039 0x8040 0x8041 0x8042 0x8043 0x8044 0x8045 0x8046 0x8047 0x8048 0x8049 0x8051 0x8052 0x8054 0x8058 0x8060 0x8061 0x8062 0x8070 0x8078 R/W W W W W Note 1 Note 1 Note 1 Note 1 Note 1 Note 1 Note 1 Note 1 Note 1 Note1 W W W R/W R R R R/W R/W Description SSI 2 audio routing address (Table 7 on page 18). Bit register for SSI 2 mute signal. 0=Muted, 1=Unmuted. SSI 3 audio routing address (Table 7 on page 18). Bit register for SSI 3 mute signal. 0=Muted, 1=Unmuted. CM-1 Host Port ICR register. CM-2 Message-A register. CM-1 Host Port CVR register. CM-2 Message-B register. CM-1 Host Port ISR register. CM-2 Message-C register. CM-1 Host Port IVR register. CM-2 Message-D register. CM-1: Unused. CM-2 Data-A register. CM-1 Host Port Data register high. CM-2 Data-B register. CM-1 Host Port Data register middle. CM-2 Data-C register. CM-1 Host Port Data register low. CM-2 Data-D register. CM-2 Host Control Register. CM-2 Host Status Register. Bit register for Host reset signal. 0=Asserted, 1=Deasserted. Bit register for Host interface mode. 0=Motorola, 1=Intel Signal MCU_P35 is either SCI_CLK from the CM or FS1 from the CM. 0=SCI_CLK, 1=FS1. Auxiliary lines. Not used, for test purposes only. FPGA configuration major version. FPGA configuration minor version. FPGA configuration revision number. Sinewave Gain register. See Table 9 on page 19. Sinewave Frequency register. See Table 8 on page 19. Table 6: Microcontroller Memory Map of Upper 32k After FPGA Configuration Note 1: The FPGA only decodes this address. The actual register is located on the CM. See the Motorola DSP56303 users manual or the CS18101 manual for a discussion of each of these host port registers. 17 Rev. 2.1 CobraNetTM EV-2 Configuring the FPGA The FPGA is configured from data that is stored in the upper 16kbytes (0xC000-0xFFFF) of the microcontroller's Flash Program Memory. The microncontroller code for configuring the FPGA uses express mode which writes byte-wide data to the FPGA. Refer to the Xilinx Spartan XL family data sheet for more information on the express mode configuration operation. The address used for writing configuration data is 0x8800. Functional Discussion of FPGA Operation Routing of Audio Data The routing of audio data is achieved by a simple 8 to 1 multiplexing operation; for each audio destination three data bits in an a register in the FPGA select the source. For example, the three data bits in the D/A audio routing register determine which audio source is selected to appear at the analog outputs (J401). Table 7 on page 18 shows the definition of the data bits and the respective audio source. microcontroller data bit AD2 AD1 AD0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 CM SSI 0 CM SSI 1 CM SSI 2 CM SSI 3 ADC Audio Source AES3 Input ADC (low latency, Rev D only) Otherwise same as ADC above. Sine wave Table 7: Definition of Audio Routing Register Bits Rev. 2.1 18 CobraNetTM EV-2 Sine Wave Generator The FPGA contains a 32-sample, 24-bit, sine table. The table is stepped through at the sample clock rate so the resulting fundamental frequency is 48kHz / 32 samples = 1500Hz and 3000Hz at 96kHz. Limited control over frequency and gain is provided. Listed below are the values to write to the frequency and gain registers in the FPGA. Frequency register data bits AD3 0 0 0 0 0 0 0 1 AD2 0 0 0 1 1 1 1 0 AD1 0 1 1 0 0 1 1 0 AD0 1 0 1 0 1 0 1 0 Frequency 48kHz sample rate (96kHz sample rate) 1.5 kHz (3.0 kHz) 3.0 kHz (6.0 kHz) 4.5 kHz (9.0 kHz) 6.0 kHz (12.0 kHz) 7.5 kHz (15.0 kHz) 9.0 kHz (18.0 kHz) 10.5 kHz (21.0 kHz) 12.0 kHz (24.0 kHz) Table 8: Sine Wave Frequency Register Bit Definitions Gain register data bits AD1 AD0 0 0 1 1 0 1 0 1 Gain 0dB -6dB -12dB -18dB Table 9: Sine Wave Gain Register Bit Definitions 19 Rev. 2.1 CobraNetTM EV-2 LED Control There are two bit registers to control the state of each of three LEDs. The mapping of control bits to LED behavior is described in Table 10 on page 20. The data bit is always AD0. Note that blink overrides on/off but when blink is turned off the LED will go to the state designated by the On/Off bit. On/Off 0 1 0 1 Blink 0 0 1 1 Status off on blink blink Table 10: LED Status Calibrating the ADC There is a ten-second warm-up time to allow both the ADC and DAC to settle. All audio is muted during this 10-second warm-up. This warm-up cycle only takes place on system reset which is initiated by either power-up or a user pushing the reset button (SW508). Version Control The FPGA contains three hardwired eight-bit registers that contain an ASCII version number of the FPGA configuration file. The microcontroller reads these registers for version control and reporting purposes. Mute Control Muting comes from three different sources 1) the microcontroller can mute or unmute audio by writing to a bit control register. There is one mute bit control register for each output audio path, 2) the CM asserts its mute signal, and 3) all audio is unconditionally muted during a power on/reset warm-up cycle. Rev. 2.1 20 CobraNetTM EV-2 Hex Switches Four pins on the 8051 allow the hex switches to be read. The EV-2 circuitry associated with the hex switches serves as an example implementing this common CobraNet feature (see Recommended User Interface Practices section in the CobraNet Programmer's Manual for a discussion of use of this scheme). Requirements include a physical (hardware) mapping of the hex switches to a code (software) within the CM. Some of the requirements to achieve this are listed below: 1. Two of the four signals will be control signals: a Shift/Load# signal where Shift is high and Load is Low. The Load allows for parallel, asynchronous loading of the hex switch data into a shift register and the Shift allows for serial shifting of data out of that register. A clock signal to perform the shifting operation where data changes on the rising end of the clock. The 74HC165 IC is an example of a part that supports this protocol. The other two signals are the shifted data output and an input that will be shifted serially into the shift register concatenating it with the hex data. The intent of this latter signal is to allow for the possibility of concatenating other data, additonal hex switches or otherwise, for application specific enhancements. The software will convert the serial hex data stream to a four-byte ASCII value that represents the switch settings. 2. 3. Figure 6. Example Switch Setting As shown in Figure 6, viewing hex switches from the front, the given switch positions would read as "CA30" in a software query of the hex switch setting. On the EV-2, the microcontoller is responsible for reading the switches through the hardware serial interface and converting those readings to an ASCII representation. This representation is then written to the CM through the host port. Specifically, the EV-2 microcontroller updates the CM's HMI variable, sysName. Using SNMP, the user may query this variable. The SNMP response is of the form "PEAK_AUDIO_EVAL-SWwxyz", where the wxyz represents the hex values of the switches in ASCII format. In the example shown in Figure 6, a query of sysName would return "PEAK_AUDIO_EVAL_SWCA30". 21 Rev. 2.1 CobraNetTM EV-2 EV-2 Schematics, Page-by-Page Description The following sections provide detailed descriptions of the EV-2 schematic drawings contained in Appendix D. Block Diagram This page is a hierarchical block diagram showing an overview of all schematic pages and interconnects between pages. Microcontroller and Hex Switches This page shows an 8051-type microcontroller, its connections, and peripherals. Peripherals include 32kbytes of SRAM, hex switch interface, clock oscillator and programming switch. A/D Converter This circuit is based on the Cirrus Logic CS5381 reference design. See the Cirrus Logic website, http://www.cirrus.com, for a detailed description of the CS5381, its development system, the CDB5381, and reference design, the CRD5381. D/A Converter This circuit is based on the Cirrus Logic CS4398 reference design. See the Cirrus Logic website, http://www.cirrus.com, for a detailed description of the CS4398 and its development system, CDB4398. The CS4398 in the EV-2 design runs in stand-alone mode. Connectors and Interfaces This page shows the CM interface connectors, P510 and P511, as well as the RS232 interface. The reset switch circuit, SW508 and associated components are also included on this page. Optional VCXO and clock buffers Although the CM produces a high quality master clock, in some applications, the master clock my be compromised by long or noisy signal paths (i.e. ribbon cable connection). An optional VCXO circuit is included as an example of re-clocking the master clock (FS512) to attenuate jitter. The VCXO is not installed on the current EV-2 board. Clock buffers are used to recondition the clock from the CM. AES3 Transceiver This circuit uses the Cirrus Logic CS8420 AES3 Transceiver. See the Cirrus Logic website, http://www.cirrus.com, for a detailed description of the CS8420 as well as the evaluation board, the CDB8420. The CS8420 runs in AES3 transceiver mode with input sample rate conversion. For the AES3 tranceiver to operate properly, a valid AES3 signal must be provided at the AES3 input. Power Supply Conditioning The main power connector is a standard ATX connector. The voltage mains are conditioned, as well as protected with transient voltage suppressor diodes. Numerous voltage regulators are used to filter and condition the power supplied to the analog audio section. FPGA This page shows the connections to the FPGA, which is a Xilinx XCS10XL-4VQ100 IC. See the FPGA discussion above for a detailed description of its functionality. Rev. 2.1 22 CobraNetTM EV-2 Appendix A: Definition of Terms This Appendix contains brief definitions of many of the terms used in the discussion of CobraNet and CobraNet networks. Audio Channel A single audio signal. Audio channels on CobraNet have a 48KHz sampling rate and may be 16, 20 or 24 bit resolution. Multiple audio channels may be carried in a Bundle. Audio Stream Two audio signals, i..e. a stereo pair. Audio on the EV-2 is routed in streams. This is equivalent to the SSI data of the CM when in 16 channel mode, i.e. two channels per SSI. Broadcast Addressing Broadcasting is a special case of Multicasting (see multicast below). Whereas it is possible, in some cases, to indicate intended recipients of multicast data, broadcast data is unconditionally received by all DTEs within a network domain. Bundle The basic network transmission unit under CobraNet. Up to 8 audio channels may be carried in a Bundle. Category 5 Cable (CAT5) CAT5 is inexpensive unshielded twisted pair (UTP) data grade cable. It is very similar to ubiquitous telephone cable but the pairs are more tightly twisted. CAT5 cable runs for Ethernet are limited to 100 meters due to signal radiation and attenuation considerations. A CAT5 run in excess of 100 meters may be overly sensitive to electromagnetic interference (EMI). It should be noted that not all CAT5 cable is UTP. Shielded CAT5 also exists but is rare due to its greater cost and a much shorter distance limitations than UTP CAT5. CobraNet CobraNet is a combination of hardware, software and protocol allowing distribution of many channels of digital audio over Fast Ethernet. CobraNet supports switched and repeater Ethernet networks. On a repeater network, CobraNet eliminates collisions and allows full bandwidth utilization of the network. CobraNet uses standard Ethernet packet structure and network infrastructure. CobraNet Device A device in compliance with the CobraNet specification for transmission and/or reception of digital audio and associated sample clock. Conductor CobraNet Device on the network supplying master clock. A conductor arbitration procedure insures that, at any time, there is one and only one conductor per network. Crossover Cable A crossover cable can be used to directly connect two network devices. DTE Short for Data Terminal Equipment, a DTE is any network device that produces or consumes data. A CobraNet Device is a DTE. 23 Rev. 2.1 CobraNetTM EV-2 Ethernet A Local Area Network (LAN) technology that allows transmission of information between computers. Ethernet is, by far, the most widely deployed LAN standard worldwide. Fast Ethernet A newer version of Ethernet, also known as 100BASE-T. It supports data transfer rates of 100Mbps. CobraNet operates on a Fast Ethernet network. Full Duplex Data can be transmitted and received simultaneously. Half Duplex Data can only be transmitted in one direction at a time. Hub Hub is not a technically concise term. The term can be used to refer to either a Repeater Hub or a Switching Hub. Mbps Short for megabits per second, it is a measure of data transfer speed. Multicast Addressing Data which is Multicast is addressed to a group of, or all DTEs on a network. All DTEs receive multicast addressed data and decide individually whether the data is relevant to them. A Switched Hub is typically not able to determine appropriate destination port or ports for multicast data and thus must send the data out all ports simultaneously just as a Repeater Hub does. Multicast addressing is to be avoided when possible since it uses bandwidth network wide and since all DTEs are burdened with having to decide whether multicast data is relevant to them. Multicast Bundle A multicast Bundle supports a one-to-many routing of audio on the network. Ethernet multicast addressing is used to deliver a multicast Bundle. Because a multicast bundle consumes bandwidth network-wide, use of this delivery service must be rationed on a switched network. Network Topology The physical and logical relationship of nodes in a network; i.e., a star, ring, tree, bus, etc. Node A processing location. A node can be a computer, a switch, a CobraNet device, or any other device that has a unique network address. Repeater Hub An Ethernet multi-port repeater. A data signal arriving in any port is electrically regenerated and reproduced out all other ports on the hub. An Ethernet network is typically wired in a star configuration and the hub is at the center. The use of hubs requires that all devices on the network run in half duplex mode. Run Length Each type of media has a limitation in the length of a point-to-point run between two devices. When maximum run length guidelines are exceeded it may not be possible to establish a Rev. 2.1 24 CobraNetTM EV-2 valid network connection or data may be corrupted. Longer distances can be achieved by upgrading the media or using multiple runs in series. Switch/Switching Hub A Switch examines addressing fields on data arriving at each port and attempts to direct the data out the port or ports to which the data is addressed. Data may be buffered within the Switching Hub to avoid the collision condition that may be experienced within a Repeater Hub. A network utilizing Switching Hubs realizes higher overall bandwidth capacity as data may be received through multiple ports simultaneously without conflict. Switches are full-duplex devices. A network utilizing switches to connect network segments is referred to as a switched network. Unicast Addressing Data which is unicast is addressed to a specific DTE. A Switching Hub may examine the unicast address field of the data and determine on which port the addressed DTE resides and direct the data only to that port. Delivery of an e-mail message is an example of unicast data addressing. Unicast Bundle A unicast Bundle supports a one-to-one routing of audio on the network. Ethernet unicast addressing is used to deliver a Unicast Bundle. Because unicast addressing is friendly to Ethernet switches, unicast Bundles should be used for audio delivery whenever possible. Unregulated Traffic Refers to any data transmitted onto a network by non-CobraNet devices. Unregulated traffic is particularly offensive on a repeater network as it interferes with CobraNet's collision avoidance mechanism and can result in audio dropouts. On a switched network, unregulated traffic is only a problem if it appears in such copious quantity as to overload the network. 25 Rev. 2.1 CobraNetTM EV-2 Appendix B: EV-2 Specifications A/D: Cirrus Logic CS5381 AUDIO SPECIFICATIONS: * * Two input channels. Frequency Response (-1 dB from a full-scale 1 kHz sine wave input): 20 Hz to 20 kHz, +-0.1 dB, 48kHz sample rate 20 Hz to 40 kHz, +0.1, -4 dB, 96kHz sample rate * Total Harmonic Distortion plus noise ( full-scale 1k Hz sine wave input ): < -114 dB, 48kHz sample rate < -110 dB, 96kHz sample rate * Dynamic Range (-60 dB from a full-scale 1kHz sine wave input, unweighted): > 115 dB, 48kHz sample rate > 110 dB, 96kHz sample rate * * Maximum Input Level: +8.3dBu, balanced differential. Input Impedance: 20 k Ohms balanced. DIGITAL SPECIFICATIONS * * A/D quantization: 24-bit resolution. Audio Sampling Rate: 48kHz or 96kHz CONNECTOR: 6-Pin Phoenix-type connector. Digital I/O: Cirrus Logic CS8420-CS * AES3 input and output. Input is sample rate converted. CONNECTOR: 6-Pin Phoenix-type connector. OTHER SPECIFICATIONS * * * Power Consumption: <10 W (includes CM) Power Connector: Uses standard ATX power supply connector (ATX power supply not included). RS232 Connection: Non-standard (RX/TX only) EIA-RS232C connection with auto loop back. Connectors are 9-pin D-types. Rev. 2.1 26 CobraNetTM EV-2 D/A: Cirrus Logic CS4398 AUDIO SPECIFICATIONS: * * Two output channels. Frequency Response (-1 dB from a full-scale 1 kHz sine wave input): 20 Hz to 20 kHz, +-0.1 dB, 48kHz sample rate 20 Hz to 40 kHz, +0.1dB, -10 dB, 96k sample rate * Total Harmonic Distortion plus noise ( full-scale 1k Hz sine wave input ): < -106 dB, 48kHz and 96k sample rates * Dynamic Range (-60 dB from a full-scale 1kHz sine wave input, unweighted): > 112 dB, 48kHz and 96k sample rates * * Maximum Output Level: +9.75 dBu balanced differential. Output Impedance: 200 Ohms DIGITAL SPECIFICATIONS * * D/A quantization: 24-bit resolution Audio Sampling Rate: 48kHz and 96kHz CONNECTOR: 6-Pin Phoenix-type connector. 27 Rev. 2.1 CobraNetTM EV-2 Appendix C: Other Resources A comprehensive array of CobraNet information can be accessed at the Cirrus Logic public website. Among the resources available are: FAQs, white papers, datasheets, programmer's guides, network design guidelines, common network terminology, a listing of recommended and tested Ethernet equipment and set-up information for selected Ethernet switches. The main URL for this site is: http://www.cirrus.com. A developer's website containing more in-depth technical information is also maintained which targets primarily CobraNet manufacturers and those considering integrating CobraNet into their products. Access to the developer's website is granted subject to execution of a Non-disclosure Agreement (NDA). Please contact your local Cirrus Logic sales office or distributor for further details. The public CobraNet website can be found at: http://www.cirrus.com/en/products/pro/areas/netaudio.html. The latest documentation and software for CobraNet products can be found at: http://www.cirrus.com/cobranetsoftware. Rev. 2.1 28 1 4 2 3 29 CNEV_FPGA EV2_FPGA.Sch PROGRAM# INIT_IO# A[0..7] A[0..7] D PROGRAM# INIT_IO# HACK# RD# WR# ALE AD[0..7] MCU_CLK A[8..15] TXD PROGRAM# MCU_P35 MCU_P17 HPF# DA_DATA SSI_DIN[0..3] AES_DOUT ADDR3 AD_RESET# DA_CS# DA_CCLK MCU_P35 MCU_P17 MCU_P17 MCU_P35 AD_DATA1 MCU_CLK A[8..15] TXD PROGRAM# SCI_CLK AUX_POWER[0..3] RSVD[1..4] MUTE# AD[0..7] HWR# HRESET# HEN# HCS# EN_96K EN_96K# DA_RESET# HACK# RD# WR# ALE AD[0..7] WR# ALE A[8..15] RD# AD[0..7] WR# ALE A[8..15] RD# DA_CDOUT DA_CDOUT DA_CDOUT SSI_DOUT[0..3] AES_DIN AES_BCLK FS512_CLK FS1_OUT MCU_CLK HWR# SCI_CLK HRESET# AUX_POWER[0..3] HEN# RSVD[1..4] HCS# MUTE# EN_96K EN_96K# MCU_P17 DA_RESET# MCU_P35 AD_DATA1 HPF# DA_DATA SSI_DOUT[0..3] SSI_DIN[0..3] AES_DIN AES_DOUT AES_BCLK FS512_CLK ADDR3 FS1_OUT AD_RESET# MCU_CLK DA_CS# DA_CDOUT DA_CCLK C Auxiliary VXCO EV2_VCXO.sch EV2_com.sch HREQ# HEN# MRESET MRESET# WATCHDOG MUTE# RXD RXD AES I/O EV2_AES.Sch AES_DIN AES_DIN WATCHDOG MUTE# B HREQ# HEN# MRESET MRESET# FS512_IN SSI_CLK_IN FS1_IN FS512_IN SSI_CLK_IN FS1_IN FS512_OUT SSI_CLK FS1_OUT AES_BCLK AES_FS1 FS512_CLK MCLK FS512_OUT SSI_CLK FS1_OUT AES_BCLK AES_FS1 FS512_CLK MCLK FS1_IN SSI_CLK_IN SSI_DOUT0 SSI_DOUT1 SSI_DOUT2 SSI_DOUT3 FS512_OUT SCI_CLK FS1_IN SSI_CLK_IN SSI_DOUT0 SSI_DOUT1 SSI_DOUT2 SSI_DOUT3 MRESET# AES_DOUT AES_BCLK AES_FS1 EN_96K# EN_96K FS512_OUT RESET# AES_DOUT AES_BCLK AES_WCLK EN_96K# EN_96K FS512_OUT UPC and logic EV2_8051.sch HREQ# HREQ# MRESET MRESET D CobraNetTM EV-2 WATCHDOG MUTE# A[0..7] RXD INIT_IO# WATCHDOG MUTE# A[0..7] RXD INIT_IO# D/A Converter EV2_DA.sch C DA_RESET# DA_DATA MCLK SSI_CLK FS1_OUT EN_96K DA_CCLK DA_CS# DA_RESET# DA_DATA MCLK SSI_CLK FS1_OUT EN_96K DA_CCLK DA_CS# Common components HACK# HCS# HWR# HRESET# A[0..2] AD[0..7] ADDR3 RSVD[1..4] HACK# HCS# HRW HRESET# A[0..2] AD[0..7] ADDR3 RSVD[1..4] TXD B TXD SSI_DIN0 SSI_DIN1 SSI_DIN2 SSI_DIN3 SSI_DIN0 SSI_DIN1 SSI_DIN2 SSI_DIN3 FS512_IN FS512_IN Appendix D: EV-2 Schematic Drawings AUX_POWER[0..3] FS512_OUT SCI_CLK AUX_POWER[0..3] A/D Converter EV2_AD.sch AD_DATA1 AD_DATA1 Power EV2_pwr.sch Cirrus Logic, Inc. www.peakaudio.com www.cirrus.com Title: CobraNet (TM) Evaluation Board Size: A Number: File: EV2_Main.Sch Date: 19-Oct-2004 Sheet 1 of 9 A MCLK SSI_CLK FS1_OUT HPF# AD_RESET# EN_96K MCLK SSI_CLK FS1_OUT HPF# AD_RESET# EN_96K 2500 55th Street Suite 210 Boulder, CO 80301 A Revision: Engineer: Bill Lowe 2 3 4 Rev. 2.1 E 1 1 4 +5V +5V U210 4 VCC OUT GND 33MHZ OSC SOCKET40 51.1P1S R202 D B200 .1S SKT200 3 MCU_CLK MCU_CLK C221 10A20S B210 .1S 2 GND +5V +5V 2 3 C 1 2 3 4 5 6 7 8 9 10 GND U201 R201 10KP1S QH QH 7 9 1 5 C 1 2 4 8 1 2 3 4 10 9 8 7 6 5 4 3 2 Rev. 2.1 R204 10KP1S SW200 PSEN# 1 2 4 3 GND = ON DIPSW1_SPDT D Select programming mode. GND R206 10KSIP +5V R203 10KP1S TPS U202 1 15 2 SH/LD CLK INH CLK QH QH +5V B201 .1S GND +5V 7 9 A[0..7] A[0..7] TP200 MCU8051 GND GND U200 MRESET 9 MRESET RST XTAL2 19 XTAL1 ALE 31 EA PSEN AD0 39 P0.0(AD0) RD/P3.7 AD1 38 P0.1(AD1) TIMER 1/P3.5 AD2 37 P0.2(AD2) WR/P3.6 AD3 36 P0.3(AD3) TIMER 0/P3.4 AD4 35 P0.4(AD4) INTR1/P3.3 AD5 34 P0.5(AD5) INTR0/P3.2 AD6 AD[0..7] 33 AD[0..7] P0.6(AD6) TXD/P3.1 AD7 32 P0.7(AD7) RXD/P3.0 INIT_IO# 1 INIT_IO# P1.0 P2.7(A15) PROGRAM# 2 PROGRAM# P1.1 P2.6(A14) MUTE# 3 MUTE# P1.2 P2.5(A13) HEX_DATA_IN 4 P1.3 P2.4(A12) HEX_CLOCK 5 P1.4 P2.3(A11) HEX_SHIFT 6 P1.5 P2.2(A10) HEX_DATA_OUT 7 P1.6 P2.1(A9) MCU_P17 8 MCU_P17 P1.7 P2.0(A8) 18 30 29 17 15 16 14 13 12 11 10 28 27 26 25 24 23 22 21 ALE ALE PSEN# RD# RD# MCU_P35 MCU_P35 WR# WR# WATCHDOG WATCHDOG HACK# HACK# HREQ# HREQ# TXD TXD RXD RXD A15 A14 A13 A12 A11 A10 A9 A8 A[8..15] A[8..15] C +5V SW204 U204 5 C 1 2 4 8 1 2 3 4 BCH SW3 SW203 A0 A1 A2 A3 A4 A5 A6 A7 B D0 D1 D2 D3 D4 D5 D6 D7 11 12 13 15 16 17 18 19 AD5 AD6 AD7 AD0 AD1 AD2 AD3 AD4 B +5V B204 .1S A15 +5V R200 10KP1S 20 RD# 22 WR# 27 CE OE WE 7C199-12 GND 5 74HC165 C 1 2 4 8 1 2 3 4 10 11 12 13 14 3 4 5 6 SER A B C D E F G H BCH SW3 R205 10KSIP 1 15 2 SH/LD CLK INH CLK A14 A13 A12 A11 A10 A9 A8 21 23 24 25 26 1 2 3 4 5 6 7 8 9 10 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 SW202 Cirrus Logic, Inc. TP201 TPG +5V B202 .1S GND GND 2 Size: A Number: File: EV2_8051.Sch Date: 19-Oct-2004 3 Sheet 2 of 9 A BCH SW3 SW201 74HC165 GND 10 11 12 13 14 3 4 5 6 SER A B C D E F G H 2500 55th Street Suite 210 Boulder, CO 80301 www.peakaudio.com www.cirrus.com Title: CobraNet (TM) Evaluation Board - MPC, SRAM and Hex Switches Revision: E Engineer: Bill Lowe 4 A 5 C 1 2 4 8 1 2 3 4 CobraNetTM EV-2 30 BCH SW3 1 1 4 C301 470PFS8 +9VA B300 2 3 D 2 R300 +5VA R361 5.11P1S B351 .1S GND C353 .01S8 + C305 10A6S + C352 10A6S 90.9P1S OPA627 B301 B352 .1S 3 R302 10KP.1S GND VCC_+3 .1S GND U300 6 7 4 1 5 19 R301 -9VA C311 U350 .1SGND GND 100KS VA VQ 470PFS8 +9VA B310 24 FILT+ REF_GND VQ MCLK SCLK LRCK SDOUT VCC_+3 5 4 3 9 R313 634P1S VQ 21 AINR+ + R310 90.9P1S OPA627 B311 .1SGND AINRC308 10A6S C350 GND .01S8 22 C307 .01S8 23 7 VD C351 47A16AES VL GND .01S8 6 8 -9VA C331 17 R333 634P1S R330 90.9P1S OPA627 B331 .1SGND TP300 TPG C326 2700PFS8 16 4 1 5 7 AGND AGND 4 1 5 7 R321 -9VA C321 470PFS8 +9VA B320 C332 GND GND 100KS GND .01S8 GND R323 634P1S R320 90.9P1S OPA627 B321 .1SGND 2 VQ R322 10KP.1S 2 3 7 C320 .1S GND U320 6 Cirrus Logic, Inc. www.peakaudio.com www.cirrus.com Title: CobraNet (TM) Evaluation Board - ADC Size: A Number: File: EV2_AD.Sch Date: 19-Oct-2004 3 Sheet 3 of 9 18 4 1 5 31 R303 634P1S D R312 10KP.1S 2 3 .1S GND U310 6 MCLK SSI_CLK FS1_OUT AD_DATA1 CR300 MCLK SSI_CLK FS1_OUT AD_DATA1 LED0603R R352 10KP1S AD_RESET# HPF# EN_96K R305 90.9P1S C C306 2700PFS8 20 AD_RESET# HPF# EN_96K AINL470PFS8 +9VA B330 OVFL RST I2S/LJ M/S HPF M0 M1 MDIV AINL+ GND CS5381 GND 15 1 12 2 11 13 14 10 2 3 R332 10KP.1S R360 1KP1S B .1S GND U330 6 C300 CobraNetTM EV-2 10A20S C302 C C310 10A20S J300 6 5 4 3 2 1 R311 100KS 1X6PHNX GND B C330 10A20S R331 100KS A 2500 55th Street Suite 210 Boulder, CO 80301 A 10A20S Revision: Engineer: Bill Lowe 4 E Rev. 2.1 -9VA 1 1 4 2 3 7 22 VD VA 4 C VQ 8 26 + DGND AGND CS4398 8 21 4 8 Rev. 2.1 +5VB VCC_+3 6 R410 5 196P1S 4560 C414 0.015UF -9VB U410A 3 1 2 196P1S 4560 +9VB R425 C424 0.015UF GND C422 47A16AES R416 100KS GND 196P1S C410 0.015UF C420 0.015UF GND R422 464P1S C423 0.018UF R420 C404 681P1S 196P1S GND R421 C421 2200PFS C411 2200PFS 681P1S 464P1S U400 AOUTL+ AMUTEC AOUTL24 25 23 R411 C413 0.018UFR412 7 R415 C412 B401 .1S + C401 10A6S U410B D R426 100KS 47A16AES J401 C 10A6S FILT+ +5VB VREF 16 GND 20 18 19 C440 0.015UF GND R440 196P1S 681P1S R441 C430 0.015UF 196P1S 681P1S 464P1S C431 2200PFS C441 2200PFS R442 464P1S C443 0.018UF R430 R431 C433 0.018UFR432 6 7 5 4560 B402 .1S C402 47A16AES B403 .1S GND U430B R435 196P1S C434 0.015UF -9VB U430A 3 1 2 4560 +9VB C432 17 + C403 100AE6R3S 15 1 2 3 4 5 6 1X6PHNX BMUTEC AOUTR47A16AES R436 100KS B C444 0.015UF R445 196P1S GND C442 R446 100KS GND 47A16AES DA_CCLK DA_CDOUT DA_CS# TP400 TPG R404 1KP1S R405 1KP1S EN_96K R406 1KP1S R407 1KP1S D B400 .1S + C400 10A6S GND B404 .1S 27 VLS 14 VLC MCLK SSI_CLK FS1_OUT DA_DATA MCLK SSI_CLK FS1_OUT DA_DATA 6 4 5 3 MCLK SCLK LRCK SDIN 2 28 1 DSD_SCLK DSD_A DSD_B EN_96K DA_CCLK DA_CDOUT DA_CS# GND EN_96K 9 DA_CCLK 10 DA_CDOUT 11 DA_CS# 12 REF_GND M3 (AD1/CDIN) M2 (SCL/CCLK) M1 (SDA/CDOUT) M0 (AD0/CS) AOUTR+ DA_RESET# DA_RESET# 13 RST B R403 1KP1S GND +9VB B410 .1S B412 .1S Cirrus Logic, Inc. GND GND A GND GND GND B411 .1S B413 .1S GND 2500 55th Street Suite 210 Boulder, CO 80301 www.peakaudio.com www.cirrus.com Title: CobraNet (TM) Evaluation Board - DAC Size: A Number: File: EV2_DA.Sch Date: 19-Oct-2004 Sheet 4 of 9 Engineer: Bill Lowe Revision: A -9VB E 2 3 4 CobraNetTM EV-2 32 1 1 4 VCC_+3 2 3 ADDR3 GND VCC_+3 GND VCC_+3 VCC_+3 GND VCC_+3 GND B511 B510 + C510 VCC_+3 .1S .1S 10A6S GND VCC_+3 GND GND VCC_+3 GND VCC_+3 GND VCC_+3 J500 RSVD1 3SRHDR GND VCC_+3 74LVX14S 74LVX14S U508C 5 6 74LVX14S U508D VCC_+3 14 B508 .1S MMS_CONN40 FS1_IN REF_CLK_IN GND 1 2 3 33 Reset Circuit MRESET# CobraNet Module Connectors + U508F U508E 12 11 10 13 MRESET# TP500 TPS P510 D MRESET SCI_TXD C508 10A6S SW508 SW2349 D SCI_CLK CobraNetTM EV-2 A[0..2] + C511 10A6S GND A[0..2] HACK# HRW HCS# HREQ# HEN# CR508 1N4148S R508 10KP1S AD[0..7] AD[0..7] 9 U508G VCC GND 74LVX14S 74LVX14S 8 HRESET# GND 7 U508A 1 GND 74LVX14S C SCI_RXD SCI_CLK HACK# HRW HCS# HREQ# HEN# A0 A1 A2 AD0 AD1 AD2 AD3 AD4 AD5 AD6 HRESET# AD7 ADDR3 2 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 C Serial Interface +5V RSVD[1..4] RSVD[1..4] 8051 com P501 C502 U507 .1S C501 .1S TXD TXD P511 VS+ C1+ C1C2+ C211 13 10 8 T1IN R1IN T2IN R2IN MAX232A 2 C503 .1S C504 MUTE# FS1_IN FS512_OUT FS512_IN 1 3 4 5 VST1OUT R1OUT 6 .1SGND 14 12 RXD RXD GND 1 6 2 7 3 8 4 9 5 DB9FRA SCI_TXD B SSI_CLK_IN SSI_DOUT0 SSI_DOUT1 SSI_DOUT2 SSI_DOUT3 SSI_DIN0 SSI_DIN1 SSI_DIN2 SSI_DIN3 T2OUT R2OUT 7 9 SCI_RXD B P504 WATCHDOG RSVD2 MUTE# FS1_IN FS512_OUT FS512_IN REF_CLK_IN SSI_CLK_IN SSI_DOUT0 SSI_DOUT1 SSI_DOUT2 SSI_DOUT3 SSI_DIN0 SSI_DIN1 SSI_DIN2 SSI_DIN3 RSVD3 WATCHDOG RSVD4 AUX_POWER2 AUX_POWER0 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 GND VCC_+3 GND VCC_+3 VCC_+3 GND VCC_+3 B513 B512 + C512 GND .1S .1S 10A6S VCC_+3 GND VCC_+3 GND +5V GND VCC_+3 GND B514 + C513 VCC_+3 .1S 10A6S GND GND +5V GND +5V AUX_POWER3 AUX_POWER1 1 6 2 7 3 8 4 9 5 MMS_CONN40 AUX_POWER[0..3] CM com GND DB9FRA AUX_POWER[0..3] Cirrus Logic, Inc. Size: A Number: File: EV2_com.Sch Date: 19-Oct-2004 2 3 Sheet 5 of 9 A TP501 TPG A www.peakaudio.com www.cirrus.com Title: CobraNet (TM) Evaluation Board - CM & serial I/O, and reset circuit. Revision: Engineer: Bill Lowe 4 2500 55th Street Suite 210 Boulder, CO 80301 Rev. 2.1 GND E 1 1 4 2 3 VCC_+3 VCC_+3 GND 10 GND B R502 51.1P1S GND VCC_+3 U501E 14 R515 FS1_OUT 51.1P1S FS1_OUT B501 .1S GND 7 VCC GND 74LVX125A FS512_CLK FS512_CLK U501D 74LVX125A 12 11 AES_BCLK AES_BCLK U510E 14 5 51.1P1S GND U510B 74LVX125A 6 R512 B B500 .1S VCC 7 GND GND 74LVX125A FS1_IN FS1_IN U510D 74LVX125A 12 11 GND 13 4 Cirrus Logic, Inc. R514 51.1P1S AES_FS1 AES_FS1 Size: A Number: File: EV2_VCXO.Sch Date: 19-Oct-2004 Sheet 6 of 9 2 3 A 2 U510A 74LVX125A 3 13 1 1 Rev. 2.1 D 4 U601B 6 D 5 74LVX86S 9 U601C 8 10 The VCXO circuit provides an example of a circuit that will reduce jitter on the master clock. In the EV-2 application jitter is low enough where this circuit does not improve the jitter performance significantly. The end user, because of long trace lengths or running the master clock through other components such as gates or FPGAs, may want to consider implementing a jitter attenuation circuit such as this one. R501 51.1P1S FS512_EV 1 U600 1 VC GND 24.576MHZ VCXO VCC_+3 B600 .1S GND 51.1P1S OUT 3 R602 FS512_OUT FS512_OUT VCC C606 .1S 2 GND GND GND FS512_IN R606 10KP1S 74LVX86S 2 3 R603 464P1S U601A VCC_+3 4 74LVX86S 12 U601D 11 13 74LVX86S Without VCXO populate R501 and not R602. With VCXO populate R602 and not R501. 14 U601E VCC 7 FS512_IN C GND GND 74LVX86S C VCC_+3 B601 .1S Optional VCXO GND Clock buffers 9 51.1P1S SSI_CLK U510C 74LVX125A 8 R511 SSI_CLK 2 Clock buffers U501A 74LVX125A 3 R503 51.1P1S MCLK MCLK SSI_CLK_IN SSI_CLK_IN A www.peakaudio.com www.cirrus.com Title: CobraNet (TM) Evaluation Board - Optional VCXO and clock buffers. Revision: E Engineer: Bill Lowe 4 2500 55th Street Suite 210 Boulder, CO 80301 GND CobraNetTM EV-2 34 1 1 4 2 3 6 AES_RXP R672 249P1S U700 4 VA+ VD+ 3 R701 110P1S RXP RXN OMCK TXP AES_DOUT AES_BCLK AES_WCLK 14 13 12 SDIN ISCLK ILRCK +5V TXN 25 110P1S 2 PE65612 4 26 R708 R673 1 90.9P1S L702 3 5 AES_MCLK 21 SDOUT OSCLK OLRCK 18 16 17 AES_DIN AES_DIN AES_BCLK AES_WCLK L701 1 23 AGND RST FILT CS8420 7 22 DGND 74LVX74S GND EN_96K# EN_96K# VCC_+3 5 Q Q EN_96K 9 8 4 10 35 BD700 D FBS1 B700 .1S GND C672 GND 22PFS J700 GND B701 .1S +5V AES_RXP AES_RXN 1 2 3 4 5 6 1X6PHNX R707 10KP1S R710 464P1S GND CR710 LED0603R R706 10KP1S C 2 27 24 DFC0 DFC1 H/S RESET# 9 8 R703 10KP1S R704 10KP1S R705 10KP1S R709 249P1S GNDGND R711 1.54KP1S GND GND C700 8200PFS B C701 .47S GND GND GND GND RERR RMCK PRO/C COPY ORIG EMPH/U AUDIO/V TCBL 11 10 20 1 28 3 19 15 PRE CLK D CLR FS512_OUT 9 VCC Q Q GND VCC_+3 14 5 6 7 U501C 74LVX125A 8 CobraNetTM EV-2 D AES_RXN 4 2 PE65612 C673 22PFS GND B672 .1S C GND AES_DOUT AES_BCLK AES_WCLK +5V R702 +5V R700 10KP1S 10KP1S RESET# B VCC_+3 U506A FS512_OUT FS512_OUT 4 3 2 1 U506B Cirrus Logic, Inc. U501B 74LVX125A 6 R507 51.1P1S AES_MCLK Size: A Number: File: EV2_AES.Sch Date: 19-Oct-2004 Sheet 7 of 9 A B506 .1S PRE CLK D CLR 2500 55th Street Suite 210 Boulder, CO 80301 EN_96K GND 10 11 12 13 www.peakaudio.com www.cirrus.com Title: CobraNet (TM) Evaluation Board - AES Transceiver Revision: Engineer: Bill Lowe 2 3 4 A Rev. 2.1 74LVX74S E 1 1 4 2 3 +12V GND VR461 78M05S +12V 1 B460 .1S + C461 10A6S D 2 VR460 78M05S +5VB OUT 3 C460 .01S8 GND 2 Rev. 2.1 OUT + C463 10A6S GND GND GND VCC_+3 GND + C450 220AE10S P450 GND +5V -12V TVS450 SMAJ5V0A + C452 470AE16S B453 .1S B454 .1S TVS452 P4SMB13A GND GND +5VA 3 IN +12V TVS451 P4SMB13A ATX_POWER GND GND GND +12V 1 4 +5V +9VA R470 249P1S C471 10A20S R471 1.54KP1S GND R481 1.54KP1S 4 R480 249P1S 1 -9VA C481 10A20S GND -12V CR504 LEDPCGRN R513 464P1S B481 .1S C482 .01S8 VR481 2 3 6 7 ADJ OUT LM337L -9VB ADJ OUT 4 R482 249P1S 1 IN IN IN IN R483 1.54KP1S GND C483 10A20S B471 .1S C472 .01S8 VR471 IN OUT OUT OUT ADJ OUT LM317L R472 1.54KP1S B 2 3 6 7 R473 249P1S C473 10A20S +9VB + C453 220AE10S B455 .1S TVS453 P4SMB6V8A 1 2 3 4 5 6 7 8 9 10 +3.3VDC +3.3VDC COM +5VDC COM +5VDC COM PWR_OK +5VSB +12VDC GND + C454 220AE10S +5V B456 .1S +3.3VDC -12VDC COM PS_ON# COM COM COM -5VDC +5VDC +5VDC 11 12 13 14 15 16 17 18 19 20 C + C451 470AE16S 2 3 6 7 1 IN D B461 .1S C462 .01S8 GND B450 .1S C B451 .1S B452 .1S +12V VR470 1 B IN 4 OUT OUT OUT ADJ OUT LM317L B470 .1S C470 .01S8 B480 .1S C480 .01S8 VR480 A 2 3 6 7 IN IN IN IN Cirrus Logic, Inc. www.peakaudio.com www.cirrus.com Title: CobraNet (TM) Evaluation Board - Power Size: A Number: File: EV2_pwr.sch Date: 19-Oct-2004 Sheet 8 of 9 2500 55th Street Suite 210 Boulder, CO 80301 A -12V LM337L Revision: Engineer: Bill Lowe 2 3 4 E CobraNetTM EV-2 36 1 1 4 U508B EN_96K 3 EN_96K# 74LVX14S 4 EN_96K# 2 AUX_POWER[0..3] AUX_POWER[0..3] 3 VCC_+3 B902 .1S GND A[8..15] A[8..15] A11 VCC_+3 GND LED0 A8 A15 A9 A0 A10 A1 RSVD4 AUX_POWER3 AUX_POWER1 AUX_POWER0 AUX_POWER2 AES_DOUT AES_DOUT AES_DIN AES_DIN LED2 LED1 B901 .1S 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 VCC3 GCK8, I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCC3 GND I/O I/O I/O I/O I/O I/O I/O (CS1) I/O GCK7, I/O I/O GND TDO, O VCC_+3 B907 .1S GND PWRDWN I/O, GCK3 I/O (HDC) I/O I/O (LDC) I/O I/O I/O I/O I/O I/O (INIT) VCC3 GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O, GCK4 GND DONE 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 NC DA_CS# EN_96K INIT_IO# 464P1S LEDPCGRN CR904 FS512_CLK MCU_P17 HWR# NC NC NC DA_CDOUT NC FS512_CLK MCU_P17 HWR# DA_CCLK DA_CCLK AD_RESET# AD_RESET# HPF# HPF# DA_RESET# DA_RESET# AD_DATA1 AD_DATA1 LEDPCRED DA_DATA DA_CDOUT A DA_CS# EN_96K INIT_IO# 37 D AES_BCLK D AES_BCLK CobraNetTM EV-2 RD# MCU_CLK GND RD# MCU_CLK VCC_+3 U901 A[0..7] GND A[0..7] GND B903 .1S WR# MCU_P35 AD[0..7] AD[0..7] FS1_OUT GND MCU_P35 AD0 A2 C AD1 A3 C AD2 A4 A12 AD3 GND VCC_+3 A13 AD4 A14 B904 .1S A7 A6 GND AD5 A5 AD6 WR# PROGRAM# WR# PROGRAM# AD7 B 1 FS1_OUT 2 3 RSVD3 SSI_DIN3 4 SSI_DIN2 5 SSI_DIN[0..3] SSI_DIN1 6 SSI_DIN[0..3] SSI_DOUT[0..3] SSI_DIN0 7 SSI_DOUT[0..3] SSI_DOUT3 8 SSI_DOUT2 9 SSI_DOUT1 10 11 VCC_+3 GND 12 SSI_DOUT0 13 B908 MUTE# 14 MUTE# .1S 15 RSVD2 16 RSVD[1..4] ADDR3 ADDR3 RSVD[1..4] GND 17 RSVD1 HRESET# 18 HRESET# HEN# 19 HEN# R902 HCS# 20 HCS# 1KP1S SCI_CLK 21 SCI_CLK 22 23 24 GND 25 GND GND I/O, GCK1 I/O I/O, TDI I/O, TCK I/O, TMS I/O I/O I/O I/O GND VCC3 I/O I/O I/O I/O I/O I/O I/O I/O I/O, GCK2 M1 GND M0 VCC3 VCC3 CCLK (DOUT) GCK6, I/O (D0, DIN) I/O I/O (D1) I/O I/O (D2) I/O I/O I/O (D3) I/O GND VCC3 I/O (D4) I/O I/O I/O I/O (D5) I/O I/O (D6) I/O GCK5, I/O (D7) I/O PROGRAM VCC3 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 B VCC_+3 XCS10XL-4VQ100 NC B905 .1S GND GND GND ALE ALE CR903 LED0 R903 +5V LED1 R904 Cirrus Logic, Inc. B906 GND 464P1S 2500 55th Street Suite 210 Boulder, CO 80301 www.peakaudio.com www.cirrus.com Title: CobraNet (TM) Evaluation Board - FPGA VCC_+3 .1S A CR905 LED2 R905 DA_DATA R901 51.1P1S 464P1S Size: A Number: File: EV2_FPGA.Sch Date: 19-Oct-2004 2 3 Sheet 9 of 9 Engineer: Bill Lowe 4 Revision: E Rev. 2.1 LEDPCYLW 1 CobraNetTM EV-2 Appendix E: EV-2 Command Line Interface. The EV-2 supports a simple command line interface (CLI). This interface allows the user to evaluate the CobraNet module (CM) and monitor and control Host Management Interface (HMI) variables. A list and description of commands follow. Please reference the CobraNet Programmer's Manual for more information about the HMI variables. Please note that there is a significant difference between the CM-1 and CM-2 HMI variable format, i.e. how the raw data is stored in the CM's memory. Refer to the CobraNet Programmer's Manual regarding the HMI variable formats. Command line Syntax The CLI is case insensitive, either upper or lower case in any combination may be used. Parameters enclosed within < > are mandatory with a few exceptions. At least one white space is required between command and parameters. Leading, lagging and multiple white spaces are ignored. A "ctrl-C" or "esc" will abort a command. With exceptions where noted, all numeric values are to be entered or will be displayed in hexadecimal format with a leading "0x". This command line interface allows the user to write scripts (i.e Python scripts) that monitor and control HMI variables. Two commands are supported that allow the user to perform these tasks: Peek Rev. 2.1 38 CobraNetTM EV-2 Poke - command - what is returned - command - what is returned - command - what is returned - command - what is returned This difference here is that the "peek 0x40104" command returns the raw value as it is stored in memory, the "peek rxPriority" command returns the value as it should be represented. In this example the CM-1 returned a different value than the CM-2 for the "peek 0x40104" command but the same value for the "peek rxPriority" command; this is because the storage format of the variable in memory is different between the CM-1 and CM-2. The main memory architecture difference between the CM-1 and CM-2 is that the CM-1 has a 24-bit wide memory bus whereas the CM-2 has a 32-bit wide memory bus. In the above example the rxPriority HMI variable is an Integer16 data type. On the CM-1 this type of data uses the middle and upper byte of the 24-bit memory location to store the data whereas the CM-2 stores the data in the lower two bytes of the 32-bit wide memory location. In summary, using the HMI variable name will return data in the proper format. Using the address will return the raw data at the address location. This also applies to the Poke command. When using the "poke 39 Rev. 2.1 CobraNetTM EV-2 There are a number of commands that control the state of the EV-2 board. Some of these commands should prove useful to the user when evaluating the CM. These commands are: Route |
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