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FUJITSU SEMICONDUCTOR DATA SHEET
DS07-12545-1E
8-bit Proprietary Microcontroller
CMOS
F2MC-8L MB89960 Series
MB89965/P965A/F969A/ MB89PV960
s DESCRIPTION
The MB89960 series is a single-chip microcontroller that utilizes the F2MC-8L core for low voltage and high speed performance. The microcontroller contains a range of peripheral functions including timers, a serial interface, I2C interface, A/D converter, and external interrupts. The internal I2C interface complies with the SM bus standard and supports an SM bus battery controller.
s FEATURES
* Range of package options * QFP and MQFP packages (0.8 mm pitch) * LQFP package (0.5 mm and 0.65 mm pitch) * High speed operation at low voltage Minimum instruction execution time = 0.4 s (for a 10 MHz oscillation) * F2MC-8L CPU core Instruction set optimized for controller applications * Multiplication and division instructions * 16-bit arithmetic operations * Bit test branch instructions * Bit manipulation instructions, etc. * Dual-clock control system * Main clock : 10 MHz max. (Four speed settings available, oscillation halts in sub-clock mode) * Sub-clock : 32.768 kHz (Operation clock for sub-clock mode) * * * * Four channels 8/16-bit timer/counter (8-bit x 2 channels or 16-bit x 1 channel) 21-bit timebase timer Clock prescaler (15-bit)
* Serial I/O Selectable transfer format (MSB-first or LSB-first) supports communications with a wide range of devices. * A/D converter 10-bit x 4 channels
MB89960 Series
* External interrupts * External interrupt 1 (3 channels) Three independent interrupt inputs can be used to recover from low-power consumption modes (with edgedetection function) * External interrupt 2 (1 channel with 8 inputs) Eight inputs can be used to recover from low-power consumption modes (with "L" level detection function) * * * * Low-power consumption modes (standby modes) Stop mode (As all oscillations halt in sub-clock mode, current consumption falls to almost zero.) Sleep mode (The CPU stops to reduce the current consumption to approximately 1/3 of normal.) Clock mode (All operation halts other than the clock prescaler resulting in very low power consumption.)
* I2C interface* * Supports Intel SM bus and Philips I2C bus standards. * Uses a two-wire data transfer protocol. * * * * Max. 35 I/O ports Output-only ports (N-ch open drain) General-purpose I/O ports (CMOS) Output-only ports (CMOS)
:6 : 21 :8
* : I2C license The customer is licensed to use the Philips I2C patent when using this product in an I2C system that complies with the Philips I2C standard specifications.
s PACKAGE
Plastic LQFP, 48-pin Plastic QFP, 48-pin Plastic QFP, 48-pin
(FPT-48P-M05)
(FPT-48P-M13)
(FPT-48P-M16)
Ceramic MQFP, 48-pin
Plastic LQFP, 64-pin
(MQP-48C-P01) 2
(FPT-64P-M09)
MB89960 Series
s PRODUCT LINEUP
Part No. Prameter Classification MB89965 Mass-produced products (mask ROM products) MB89P965A MB89F969A MB89PV960 Piggyback/ evaluation product for testing and development 32 K x 8-bit (External ROM) *
One-time product
Flash product
ROM size RAM size
16 K x 8-bit (Internal mask ROM) 512 x 8-bit Number of instructions Instruction bit length Instruction length Data bit length Minimum execution time Interrupt processing time Output-only ports (N-ch open drain)
60 K x 8-bit
1024 x 8-bit : 136 : 8-bit : 1 to 3 bytes : 1-, 8-, 16bits : 0.4 s (at 10 MHz) : 3.6 s (at 10 MHz) : 6 (4 pins are shared with analog inputs) (2 pins are shared with resource I/O) :8 : 21 (shared with resource I/O) 35 (max.)
CPU functions
Ports
Output-only ports (CMOS) General-purpose I/O ports (CMOS) Total
21-bit Timebase timer Four interrupt intervals selectable 0.82 ms, 3.3 ms, 26.2 ms, or 419.4 ms (approx.) (for main clock) Watchdog timer Reset trigger period : 419.4 ms (10 MHz main clock) 500 ms (32.768 MHz sub-clock) One channel. Supports Intel SM bus (version 1.0) and Philips I2C bus standards. Uses a 2-wire protocol for communications with other devices. Peripheral functions I2C interface Included/Not included (Specified when ordering. See "Ordering Information" for details.) Included
8/16-bit timer/ counter Timer
2 channel 8-bit timer/counter operation (independent operation clocks for timer 1 and timer 2) or 16-bit timer/counter operation (operation clock period : 0.8 s to 204.8 s) can execute an event counter operation and output a square wave using an external Clock. 1 or 16-bit timer/counter operation mode 8 bits LSB-first or MSB-first selectable Transfer clocks : External or three internal clocks (0.8 s, 3.2 s, 12.8 s) Selectable edge detection (rising, falling, or either edge) 3 independent channels These can also be used to recover from standby modes (edge detection is still available in stop mode) . 1 channel with 8 inputs ("L" level interrupts, independent input enable) This can also be used to recover from standby modes (level detection is still available in stop mode) .
Serial I/O External interrupt 1 (edge) External interrupt 2 (level)
(Continued)
3
MB89960 Series
(Continued)
Part No. Prameter MB89965 MB89P965A MB89F969A MB89PV960
Periph- A/D converter eral functions 15-bit Clock prescaler Interrupt interval : 31.25 ms, 0.25 s, 0.50 s, 1.00 s (for a 32.768 kHz sub-clock) Low power consumption (standby modes) Process Operating voltage Sleep mode, stop mode, and clock mode CMOS 3.5 V to 5.5 V
4 channel x 10-bit resolution A/D conversion time : 15.2 s (MB89965, MB89P965A, MB89F969A) 13.2 s (MB89PV960) Continuous activation is available using the output from the 8/16-bit timer/counter or timebase timer. Reference voltage input (AVR)
* : Use the MBM27C256A-20TVM as the external ROM (Operating voltage : 4.5 V to 5.5 V) Note : Unless otherwise stated, clock periods and conversion times are for 10 MHz operation with the main clock operating at maximum speed.
s PACKAGES AND CORRESPONDING PRODUCTS
Part No. Package FPT-48P-M05 FPT-48P-M13 FPT-48P-M16 FPT-64P-M09 MQP-48C-P01 : Available x : Not available x x x x x MB89965 MB89P965A MB89F969A x x x MB89PV960 x x x x
4
MB89960 Series
s DIFFERENCES AMONG PRODUCTS
1. Memory Space
Please take note of the differences among products before testing and developing software for the MB89960 series. * The RAM and ROM configurations differ among products. * If the bottom stack address is set at the top RAM address, this will need to be relocated if changing to a different product.
2. Current Consumption
* In the case of the MB89PV960, add the current consumed by the EPROM which is connected to the top socket. * When operated at low speed, one-time PROM and EPROM products will consume more current than mask ROM products. However, the current consumption in sleep/stop modes is the same.
3. Functional Differences Between MB89960 Series
MB89965/P965A/F969A Power-on reset delay time External reset delay time in stop/ sub-clock mode or external interrupt delay time in main stop mode Port pin pull-up resistors A/D conversion time I2C noise elimination circuit Regulator stabilization delay time, regulator recovery time, oscillation stabilization delay time Regulator recovery time, oscillation stabilization delay time Software-selectable 38 instruction cycles Always present regardless of ICCR : DMPB bit setting MB89PV960 Oscillation stabilization delay time
Oscillation stabilization delay time
Not available 33 instruction cycles Disabled if ICCR : DMPB bit = "1"
4. Mask Options
Functions that can be selected as options and the methods used to specify these options vary by the product. Before using mask options, check section " Mask Options".
5
MB89960 Series
s PIN ASSIGNMENT
(TOP VIEW)
AVCC RST MOD0 MOD1 X0 X1 VCC X0A X1A P27 P26 P25
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
P40/AN0 P41/AN1 P42/AN2 P43/AN3 AVR AVSS P44/SDA P45/SCL P30/SCK P31/SO P32/SI P33/EC
P34/TO/CLK C P00/INT20 P01/INT21 P02/INT22 P03/INT23 P04/INT24 P05/INT25 P06/INT26 P07/INT27 P10/INT10 P11/INT11
P24 P23 P22 P21 P20 P17 VSS P16 P15 P14 P13 P12/INT12
(FPT-48P-M05) (FPT-48P-M13) (FPT-48P-M16)
(Continued)
6
MB89960 Series
(Continued)
(TOP VIEW)
AVCC RST MOD0 MOD1 X0 X1 VCC X0A X1A P27 P26 P25
1 2 3 4 5 6 7 8 9 10 11 12
68 67 66 65 64 63 62 61
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
P40/AN0 P41/AN1 P42/AN2 P43/AN3 AVR AVSS P44/SDA P45/SCL P30/SCK P31/SO P32/SI P33/EC
69 70 71 72 73 74 75 76
60 59 58 57 56 55 54 53
P34/TO/CLK N.C. P00/INT20 P01/INT21 P02/INT22 P03/INT23 P04/INT24 P05/INT25 P06/INT26 P07/INT27 P10/INT10 P11/INT11
* : Pin assignment on package top (MB89PV960) Pin Pin Pin No. Pin No. Pin No. Name Name 49 50 51 52 53 54 55 56 VPP A12 A7 A6 A5 A4 A3 N.C. 57 58 59 60 61 62 63 64 N.C. A2 A1 A0 O1 O2 O3 VSS 65 66 67 68 69 70 71 72
P24 P23 P22 P21 P20 P17 VSS P16 P15 P14 P13 P12/INT12
13 14 15 16 17 18 19 20 21 22 23 24
77 78 79 80 49 50 51 52
(MQP-48C-P01)
Pin Name O4 O5 O6 O7 O8 CE A10 N.C.
Pin No. 73 74 75 76 77 78 79 80
Pin Name OE N.C. A11 A9 A8 A13 A14 VCC
N.C. : Internally connected. Do not use.
(Continued)
7
MB89960 Series
(Continued)
(TOP VIEW)
8
N.C. N.C. P24 P23 P22 P21 P20 P17 VSS P16 P15 P14 P13 P12/INT12 N.C. N.C.
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
TEST MOD2 AVCC RST MOD0 MOD1 X0 X1 VCC X0A X1A P27 P26 P25 N.C. N.C.
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
N.C. N.C. P40/AN0 P41/AN1 P42/AN2 P43/AN3 AVR AVSS P44/SDA P45/SCL P30/SCK P31/SO P32/SI P33/EC N.C. N.C.
N.C. N.C. P34/TO/CLK C P00/INT20 P01/INT21 P02/INT22 P03/INT23 P04/INT24 P05/INT25 P06/INT26 P07/INT27 P10/INT10 P11/INT11 N.C. N.C.
(FPT-64P-M09)
MB89960 Series
s PIN DESCRIPTIONS
Pin No. MQFP-48* 5 6 8 9 3 4
3
LQFP-48*1 QFP-48*2 5 6 8 9 3 4
LQFP-64* 7 8 10 11 5 6
4
Pin Name X0 X1 X0A X1A MOD0 MOD1
Circuit Type
Function Oscillator connection pins for the main clock oscillator (crystal oscillator or similar) . When using an external clock, input the clock signal to X0 and leave X1 open. Oscillator connection pins for the sub-clock oscillator (crystal oscillator or similar) . When using an external clock (low speed : 32.768 kHz) , input the clock signal to X0A and leave X1A open. Input pins for setting the memory access mode. Connect directly to VSS. Reset I/O pin This is an N-ch open-drain output type with pullup resistor and a hysteresis input type. The pin outputs "L" when an internal reset is present. Similarly, inputting "L" initializes the internal circuits. General-purpose I/O ports Also serves as the external interrupt 2 inputs (wakeup inputs) . The external interrupt 2 inputs are hysteresis inputs. General-purpose I/O ports Also serves as the external interrupt 1 inputs (wakeup inputs) . The external interrupt 1 inputs are hysteresis inputs. General-purpose I/O ports
A
B
C
2
2
4
RST
D
27 to 34
27 to 34
37 to 44
P00/INT20 to P07/INT27 P10/INT10 to P12/INT12 P13 to P17 P20 to P27 P30/SCK
E
24 to 26
24 to 26
30, 35, 36 24, 26 to 29 12 to 14 19 to 23
E
18, 20 to 23
18, 20 to 23
E
10 to 17
10 to 17
G
General-purpose outoput-only ports General-purpose I/O port Also serves as the serial clock I/O. A hysteresis input. General-purpose I/O port Also serves as the serial I/O data output. A hysteresis input.
40
40
54
F
39 *1 : FPT-48P-M05
39
53
P31/SO
F
(Continued)
*2 : FPT-48P-M16, FPT-48P-M13 *3 : MQP-48C-P01 *4 : FPT-64P-M09
9
MB89960 Series
(Continued)
Pin No. MQFP-48*
3
LQFP-48*1 QFP-48*2 38
LQFP-64*
4
Pin Name
Circuit Type
Function General-purpose I/O port Also serves as the serial I/O data input. A hysteresis input. General-purpose I/O port Also serves as the external clock input for the 8/ 16-bit timer/counter. A hysteresis input. General-purpose I/O port Also serves as the overflow output for the 8/16bit timer/counter and the CLK clock output. A hysteresis input. Connect a 0.1 F capacitor on the MB89965, MB89P965A, and MB89F969A. General-purpose Nch open-drain outputs. Also serves as the A/D converter analog inputs. General-purpose Nch open-drain output. Also serves as the I2C interface data output. General-purpose Nch open-drain output. Also serves as the I2C interface clock I/O. Power supply pin Power supply (GND) pin A/D converter power supply pin Use this pin at the same voltage as VCC. A/D converter reference voltage input pin A/D converter power supply pin Use this pin at the same voltage as VSS. These pins are not connected. Do not connect these on the MB89PV960. TEST pin. Connect directly to VSS. Only used on the MB89F969A. Treat as an N.C. pin on the MB89965. Memory access mode setting pin. Connect directly to VSS. Only used on the MB89F969A. Treat as an N.C. pin on the MB89965.
38
52
P32/SI
F
37
37
51
P33/EC
F
36
36
46
P34/TO/ CLK
F
45 to 48
35
45
C P40/AN0 to P43/AN3 P44/SDA P45/SCL VCC VSS AVCC AVR AVSS
H
45 to 48
59 to 62
42 41 7 19 1 44 43
42 41 7 19 1 44 43
56 55 9 25 3 58 57 15 to 18 31 to 34 47 to 50 63, 64 1
I I
35
N.C.
TEST
C
2
MOD2
C
*1 : FPT-48P-M05 *2 : FPT-48P-M16, FPT-48P-M13 *3 : MQP-48C-P01 *4 : FPT-64P-M09 10
MB89960 Series
* Pin Descriptions for External EPROM (MB89PV960 only) Pin No. Pin Name I/O 49 50 51 52 53 54 55 58 59 60 61 62 63 64 65 66 67 68 69 70 71 73 75 76 77 78 79 80 56 57 72 74 Vpp A12 A7 A6 A5 A4 A3 A2 A1 A0 O1 O2 O3 VSS O4 O5 O6 O7 O8 CE A10 OE A11 A9 A8 A13 A14 VCC O "H" level output pin
Function
O
Address output pins
O
Address output pins
I
Data input pins Power supply (GND) pin
I
Data input pins
O O O
ROM chip enable pin Outputs "H" during standby mode. Address output pin ROM output enable pin Always outputs "L".
O
Address output pins

EPROM power supply pin Internally connected pins Always leave open circuit.
N.C.
11
MB89960 Series
s I/O CIRCUIT TYPE
Type
X1 Nch X0 Pch Pch Nch
Circuit
Remarks
A
High speed clock (main clock oscillation) * Oscillation feedback resistor
Main clock control signal
X1A Nch X0A Pch Pch Nch Nch
B
Low speed clock (sub-clock oscillation) * Oscillation feedback resistor
Sub-clock control signal
C
* CMOS input
R Pch
D
Nch
* Output pull-up resistor (Pch) approx. 50 k (at 5 V) * Hysteresis input
R
Pch Pch
Pull-up
E
Nch Port Resource
* CMOS output * CMOS input * Selectable pull-up resistor approx. 50 k (at 5 V)
(Continued)
12
MB89960 Series
(Continued) Type
Circuit
Remarks
R
Pch Pch
Pull-up
F
Nch Resource
* CMOS output * Hysteresis input * Selectable pull-up resistor approx. 50 k (at 5 V)
Pch
G
Nch
* CMOS output
R
Pch
Pull-up
H
Nch Analog input
* * * *
Nch-open drain output Analog input (A/D converter) Selectable pull-up resistor (The pull-up resistor cannot be used when used as an analog input.) approx. 50 k (at 5 V)
Nch
I
SMB buffer SMB input I2C buffer I2C input
* Nch open drain output * Selectable SMB or I2C input buffer
13
MB89960 Series
s HANDLING DEVICES
1. Do not exceed maximum rated voltage (to prevent latch-up)
Latch-up may occur on CMOS ICs if voltage higher than VCC or lower than VSS is applied to input or output pins other than medium- and high voltage pins or if the voltage applied between VCC and VSS higher the rating. If latch-up occurs, the power supply current increases rapidly resulting in thermal damage to circuit elements. Therefore, ensure that maximum ratings are not exceeded in circuit operation. Similarly, when turning the analog power supply on or off, ensure the analog power supply voltages (AVCC and AVR) and analog input voltages do not exceed the digital power supply (VCC) .
2. Power supply voltage fluctuations
Rapid fluctuation of the voltage may cause the device to misoperate, even if the voltage remains within the allowed operating range. The standard for power supply voltage stability is a peak-to-peak VCC ripple voltage at the mains supply frequency (50 to 60 Hz) of 10% or less of VCC and a transient voltage change rate of 0.1 V/ms or less such as when turning the power supply on or off.
3.
Treatment of unused input pins
Leaving unused input pins unconnected can cause misoperation or permanent damage to the device due to latchup. Always pull-up or pull-down unused input pins using a 2 k or larger resistor. If some I/O pins are unused, either set as outputs and leave open circuit or set as inputs and treat in the same way as input pins.
4.
Treatment of N.C. pins
Always leave N.C. (internally connected) pins open.
5. Treatment of power supply pins on microcontrollers with an A/D converter
Even if not using the A/D converter, connect to be AVCC = VCC and AVSS = AVR = VSS.
6. Precautions on using an external clock
An oscillation stabilization delay occurs after a power-on reset or when recovering from sub-clock or stop mode, even if an external clock is used.
14
MB89960 Series
s PROGRAMMING SPECIFICATIONS FOR ONE-TIME PROM PRODUCTS
The MB89P965A has a "PROM mode" that enables the microcontroller to be programmed using a generalpurpose ROM programmer via a special adaptor. Note, however, that electronic signature mode is not available.
1. ROM Programmer Adaptor and Recommended ROM Writers
Package Name FPT-48P-M05 FPT-48P-M13 Adaptor Part No. Sun Hayato Co. Ltd. ROM2-48LQF-32DP-8LA ROM2-48QF2-32DP-8LA AF9708 (ver 1.44 or later) AF9709 (ver 1.44 or later) Recommended Programmer Manufacturer and Model Ando Denki Co. Ltd.
FPT-48P-M16 ROM2-48QF-32DP-8LA * Enquiries Sun Hayato Co. Ltd. : TEL 03-3986-0403 Ando Denki Co. Ltd. : TEL 044-549-7300
2. PROM Mode Memory Map
Normal operating mode 0000H I/O 0080H RAM 0100H Generalpurpose 0200H registers 0280H
Not available PROM mode (addresses on ROM programmer) C000H Program area (PROM) FFFFH 3FFFH 0000H Program area (PROM)
3. PROM Programming Procedure (When using an Ando EPROM programmer)
1) Set the EPROM programmer type code to 17209. 2) Load the program data into addresses 0000H to 3FFFH in the EPROM programmer. 3) Use the EPROM programmer to program to addresses C000H to FFFFH.
4. Programming Yield
Due to the nature of OTPROM memory, a program test to all bits on a blank OTPROM microcontroller cannot be performed at Fujitsu. For this reason, a programming yield of 100% cannot be assured at all times. 15
MB89960 Series
s PROGRAMMING AND ERASING FLASH MEMORY ON THE MB89F969A
1. Flash Memory
The flash memory is located between 1000H and FFFFH in the CPU memory map and incorporates a flash memory interface circuit that allows read access and program access from the CPU to be performed in the same way as mask ROM. Programming and erasing flash memory is also performed via the flash memory interface circuit by executing instructions in the CPU. This enables the flash memory to be updated in place under the control of the CPU, providing an efficient method of updating program and data.
2. Flash Memory Features
* * * * * * * *
60 K byte x 8-bit configuration (16 K + 8 K + 8 K + 28 K sectors) Automatic programming algorithm (Embedded algorithm* : Equivalent to MBM29LV200) Includes an erase pause and restart function Data polling and toggle bit for detection of program/erase completion Detection of program/erase completion via CPU interrupt Compatible with JEDEC-standard commands Sector Protection (sectors can be combined in any combination) No. of program/erase cycles : 10,000 (min.)
Embedded Algorithm is a trademark of Advanced Micro Devices.
3. Procedure for Programming and Erasing Flash Memory
Programming and reading flash memory cannot be performed at the same time. Accordingly, to program or erase flash memory, the program must first be copied from flash memory to RAM so that programming can be performed without program access from flash memory.
4. Flash Memory Register
* Control status register (FMCS)
Address 002EH
bit7 bit6 bit5 WE R/W bit4 RDY R bit3 bit2 bit1 bit0
Reserved
Initial value 000X00-0B
INTE RDYINT R/W R/W
Reserved Reserved
R/W
R/W
R/W
5. Sector Configuration
The table below shows the sector configuration of flash memory and lists the addresses of each sector for both during CPU access a flash memory programming. * Sector configuration of flash memory Flash Memory 16 K bytes 8 K bytes 8 K bytes 28 K bytes
CPU Address FFFFH to C000H BFFFH to A000H 9FFFH to 8000H 7FFFH to 1000H
Programmer Address 1FFFFH to 1C000H 1BFFFH to 1A000H 19FFFH to 18000H 17FFFH to 11000H
* : Programmer address The programmer address is the address to be used instead of the CPU address when programming data from a parallel flash memory programmer. Use the programmer address on programming or erasing using a generalpurpose parallel programmer. 16
MB89960 Series
6. ROM Programmer Adaptor and Recommended ROM Programmers
Package Name FPT-64P-M09 Adaptor Part No. Sun Hayato Co. Ltd. FLASH-64QF2-32DP-8LF Recommended Programmer Manufacturer and Model Ando Denki Co. Ltd. AF9708 (ver 1.60 or later) AF9709 (ver 1.60 or later)
* Enquiries Sun Hayato Co. Ltd. : TEL 03-3986-0403 Ando Denki Co. Ltd. : TEL 044-549-7300
17
MB89960 Series
s PROGRAMMING A PIGGYBACK/EVALUATION EPROM
1. EPROM Type
MBM27C256A-20TVM
2. Programming Adaptor
Use the following programming adaptor (made by Sun Hayato Co. Ltd.) to program the EPROM using a ROM programmer. * Programming adaptor Package LCC-32 (Square) Enquiries Sun Hayato Co. Ltd. : TEL03-3986-0403
Adaptor Socket Part No. ROM-32LC-28DP-S
3. Memory Space
Normal operating mode
0000H 0080H
I/O RAM
0280H
Not available EPROM mode (addresses on ROM programmer)
8000H
0000H
Program area (PROM)
Program area (PROM)
FFFFH
7FFFH
4. EPROM Programming Procedure
(1) Setup the EPROM programmer to the MBM27C256A. (2) Load the program data into addresses 0000H to 7FFFH in the EPROM programmer. (3) Use the ROM programmer to program to addresses 0000H to 7FFFH.
18
MB89960 Series
s BLOCK DIAGRAM
Main clock X0 X1 High speed oscillator circuit (Max. 10 MHz) Clock control Sub-clock X0A X1A Timebase timer
Reset circuit (watchdog timer)
RST
Low speed oscillator circuit (32.768 kHz) Clock prescaler CMOS I/O port
16-bit timer/counter 8-bit timer/counter 2 P34/TO/CLK
Internal data bus
P00/INT20 to P07/INT27
Port 0
8
8-bit timer/counter 1
Port 3
P33/EC
8
External interrupt 2 (Level)
8-bit serial I/O
P32/SI P31/SO P30/SCK
Port 1
P10/INT10 to P12/INT12 P13 to P17
3 5
3 External interrupt 1 (edge)
CMOS I/O port AVR AVCC AVSS
CMOS I/O port
P20 to P27
Port 2
8
CMOS output port 10-bit A/D converter RAM 4 Port 4 4 P40/AN0 P43/AN3
F2MC-8L CPU
I2C interface
P44/SDA P45/SCL
ROM
Nch open drain output port
Other pins MOD0, MOD1, Vcc, Vss, C
19
MB89960 Series
s CPU CORE
1. Memory Space
(1) Structure of memory space * I/O area (address : 0000H to 007FH) * Assign the control registers, data registers, and similar of the internal peripheral functions. * As the I/O area is allocated as part of the memory space, it can be accessed in the same way as memory. Direct addressing also provides high speed access. * * * * * * * * * * RAM area Static RAM is provided as an internal data area. The size of internal RAM differs between products. Addresses 80H to FFH provide high speed access using direct addressing. Addresses 100H to 1FFH are used as the general-purpose register area. The initial value of RAM after a reset is undefined. ROM area ROM memory is provided as the internal program area. The size of internal ROM differs between products. Addresses FFC0H to FFFFH are used for the vector table and similar.
(2) Memory map
MB89965 MB89P965A 0000H I/O 0080H RAM 0100H Registers 0200H 0280H 0200H 0480H 1000H Not available 0100H 0080H 0000H
MB89F969A 0000H I/O 0080H RAM 0100H Registers 0200H 0480H
MB89PV960
I/O
RAM
Registers
Not available
Not available 8000H
C000H ROM ROM FFC0H FFFFH FFC0H FFFFH FFC0H FFFFH Vector table (Reset, interrupt, vector call instruction) ROM
20
MB89960 Series
2. Registers
The MB89960 series provides two types of registers: dedicated registers in the CPU and general-purpose registers. The dedicated registers are as follows. Program counter (PC) Accumulator (A) : A 16-bit register for indicating the instruction storage positions. : A 16-bit register that provides temporary storage for arithmetic operations and similar. Instructions that operate on 8-bit data use the lower byte. Temporary accumulator (T) : A 16-bit register used for arithmetic operations with the accumulator. Instructions that operate on 8-bit data use the lower byte. Index register (IX) : A 16-bit register used for index modification. Extra pointer (EP) : A 16-bit pointer used for indicating a memory address . Stack pointer (SP) : A 16-bit register used for indicating a stack area. Program status (PS) : A 16-bit register used to store a register pointer and condition code.
16 bits Initial value PC A T IX EP SP RP PS CCR : Program counter : Accumulator : Temporary accumulator : Index register : Extra pointer : Stack pointer : Program status FFFDH Undefined Undefined Undefined Undefined Undefined I flag = 0, IL1, IL0 = 11 Other bits are undefined
The upper 8 bits of the PS contain the register bank pointer (RP) and the lower 8 bits contain the condition code register (CCR) . (See the diagram below.)
RP bit15 bit14 bit13 bit12 bit11 bit10 bit9 R4 R3 R2 R1 R0 - - Half carry flag Interrupt enable flag Interrupt level bits Negative flag Zero flag Overflow flag Carry flag X : Undefined bit8 - bit7 H bit6 I bit5 IL1 CCR bit4 IL0 bit3 N bit2 Z bit1 V bit0 C CCR Initial value X011XXXXB
PS
21
MB89960 Series
The RP contains the address of the currently used register bank. The conversion diagram below shows the relationship between the RP value and actual address. Rules for converting of actual addresses of the general-purpose register area
Upper (RP) "0" Actual address "0" "0" "0" "0" "0" "0" A9 "1" A8 R4 A7 R3 A6 R2 A5 R1 A4 R0 A3 Lower (op code) b2 A2 b1 A1 b0 A0
A15 A14 A13 A12 A11 A10
CCR contains bits that indicate the result of an arithmetic operation or information about transfer data and bits used to control CPU operation when an interrupt occurs. H-flag : Set to "1" when a carry from bit 3 to bit 4 or a borrow from bit 4 to bit 3 occurs as a result of an arithmetic operation. Cleared to "0" otherwise. This flag is for decimal adjustment instructions and should be ignored for operations other than addition and subtraction. : Interrupts are enabled when this flag is set to "1" and disabled when the flag is set to "0". Cleared to "0" by a reset. : Indicates the level of interrupts currently allowed. The CPU only processes interrupts with a request level higher than the value indicated by these bits. IL1 0 0 1 1 N-flag Z-flag V-flag C-flag IL0 0 1 0 1 Interrupt Level 1 2 3 Low = No interrupt Priority High
I-flag IL1, 0
: Set to "1" when the MSB of the result of an arithmetic operation is "1" and cleared to "0" when the MSB is "0". : Set to "1" when the result of an arithmetic operation is zero. Cleared to "0" otherwise : Set to "1" when a 2's complement overflow occurs as the result of an arithmetic operation. Cleared to "0" if no 2's complement overflow occurs. : Set to "1" when a carry from bit 7 or a borrow to bit 7 occurs as the result of an arithmetic operation. Cleared to "0" otherwise. Set to the shift-out value in the case of a shift instruction.
22
MB89960 Series
The following general-purpose registers are provided : General-purpose registers : 8-bit resisters for storing data The general-purpose registers are 8-bit registers and are allocated in the register banks of the memory. Each bank contains 8 registers and all 32 banks can be used on MB89960 series microcontrollers. The register bank pointer (RP) specifies the bank that is currently in use. Register bank structure
Address = 0100H + 8 x (RP) R0 R1 R2 R3 R4 R5 R6 R7 32 banks
Memory area
23
MB89960 Series
s I/O MAP
Address 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 20H 21H 22H ADC1 ADC2 ADDH T2CR T1CR T2DR T1DR SMR SDR Timer 2 control register Timer 1 control register Timer 2 data register Timer 1 data register Serial mode register Serial data register (Unused area) A/D control register 1 A/D control register 2 A/D data register H R/W R/W R/W 0 0 0 0 0 0 - 0B - 0 0 0 0 0 0 1B - - - - - - XXB R/W R/W R/W R/W R/W R/W X0 - - XXX0B X0 0 0XXX0B XXXXXXXXB XXXXXXXXB 0 0 0 0 0 0 0 0B XXXXXXXXB (Unused area) IBSR IBCR ICCR IADR IDAR SYCC STBC WDTC TBTC WPCR PDR3 DDR3 PDR4 Abbreviation PDR0 DDR0 PDR1 DDR1 PDR2 Register Name Port 0 data register Port 0 direction register Port 1 data register Port 1 direction register Port 2 data register (Unused area) System clock control register Standby control register Watchdog control register Timebase timer control register Clock prescaler control register Port 3 data register Port 3 direction register Port 4 data register (Unused area) I2C bus status register I2C bus control register I C clock control register I C address register I2C data register
2 2
Read/Write R/W W R/W W R/W
Initial Value XXXXXXXXB 0 0 0 0 0 0 0 0B XXXXXXXXB 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B
R/W R/W R/W R/W R/W R/W R/W R/W R R/W R/W R/W R/W
X - - MM1 0 0B 0 0 0 1 0 - - -B 0 - - - XXXXB 0 0 - - - 0 0 0B 0 0 - - - 0 0 0B - - -XXXXXB - - 0 0 0 0 0 0B - - 1 1 1 1 1 1B 0 0 0 0 0 0 0 0B 0 0 0 1 1 0 0 0B 0 0 0XXXXXB - XXXXXXXB XXXXXXXXB
(Continued)
24
MB89960 Series
(Continued) Address
23H 24H 25H 26H to 27H 28H 29H 2AH 2BH 2CH to 31H 32H 33H 34H to 7BH 7CH 7DH 7EH 7FH ILR1 ILR2 ILR3 ITR EIE2 EIF2 PURR1 PURR2 PURR3 PURR4
Abbreviation ADDL EIC1 EIC2
Register Name A/D data register L External interrupt 1 control register 1 External interrupt 1 control register 2 (Unused area) Pull-up resistor register 1 (MB89965, P965A, and F969A only) Pull-up resistor register 2 (MB89965, P965A, and F969A only) Pull-up resistor register 3 (MB89965, P965A, nd F969A only) Pull-up resistor register 4 (MB89965, P965A, and F969A only) (Unused area) External interrupt 2 control register External interrupt 2 flag register (Unused area) Interrupt level setting register 1 Interrupt level setting register 2 Interrupt level setting register 3 Interrupt test register
Read/Write R/W R/W R/W
Initial Value XXXXXXXXB 0 0 0 0 0 0 0 0B - - - - 0 0 0 0B
R/W R/W R/W R/W
1 1 1 1 1 1 1 1B 1 1 1 1 1 1 1 1B XXX1 1 1 1 1B XXXX1 1 1 1B
R/W R/W W W W Not available
0 0 0 0 0 0 0 0B - - - - - - - 0B 1 1 1 1 1 1 1 1B 1 1 1 1 1 1 1 1B 1 1 1 1 1 1 1 1B XXXXXX0 0B
* Read/write notation R/W : Reading and writing available R : Read-only W : Write-only * Initial value notation 0 : Initial value of bit is "0". 1 : Initial value of bit is "1". X : Initial value of bit is undefined. M : Initial value of bit is specified by mask option. : Bit is not used. Note : Do not use the "unused areas".
25
MB89960 Series
s ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
Rating Min. VSS - 0.3 VSS - 0.3 VSS - 0.3 VSS - 0.3 VSS - 0.3 VSS - 0.3 -40 -55 Max. VSS + 6.0 VSS + 6.0 VCC + 0.3 VSS + 6.0 VCC + 0.3 VSS + 6.0 15 4 100 40 -15 -4 -50 -20 300 450 +85 +150 V V mA mA mA mA mA mA mA mA mW C C Average value (operating current x operating ratio) MB89F969A only Average value (operating current x operating ratio) Average value (operating current x operating ratio) Average value (operating current x operating ratio) Pins other than P44 and P55 Pins P44 and P45 Pins other than P44 and P55 Pins P44 and P45 (AVSS = VSS = 0.0 V) Unit Remarks
Parameter
Symbol VCC AVCC AVR
Power supply voltage
V
*
Input voltage Output voltage "L" level maximum output current "L" level average output current "L" level total maximum output current "L" level total average output current "H" level maximum output current "H" level average output current "H" level total maximum output current "H" level total average output current Power consumption Operating temperature Storage temperature
VI VO IOL IOLAV IOL IOLAV IOH IOHAV IOH IOHAV PD TA Tstg
* : Set AVCC to the same potential as VCC. Also ensure that AVCC does not exceed VCC at power on. WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
26
MB89960 Series
2. Recommended Operating Conditions
Value Min. 3.5* 3.0 2.7* 1.5 AVR Operating temperature TA 3.5 -40 Max. 5.5* 5.5 5.5* 5.5 AVCC +85
(AVSS = VSS = 0.0 V) Unit V V V V V C Remarks Normal operation guaranteed range (MB89965/P965A/F969A) To maintain RAM state in stop mode (MB89965/P965A/F969A) Normal operation guaranteed range (MB89PV960) To maintain RAM state in stop mode (MB89PV960)
Parameter
Symbol
Power supply voltage
VCC AVCC
* : Differs depending on the operating frequency and analog guaranteed range. See the figure below and "5. Electrical Characteristics for the A/D Converter". Operating Voltage - Operating frequency
6 Analog accuracy guaranteed range : VCC = AVCC = 3.5 V to 5.5 V
5 Operating Voltage (V) Operation guaranteed range 4 3.5 3 2.7 2 : MB89PV960 : MB89965, MB89P965A, and MB89F969A 1 2 3 4 5 6 7 8 9 10
Operating Frequency (MHz)
The figure above shows the frequency of the external oscillator when the instruction cycle setting is 4/FC. As the operating voltage depends on the instruction cycle, change to the new instruction cycle value if using the gear function to change the operating speed. WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand. 27
MB89960 Series
3. DC Characteristics
Symbol VIH
(AVCC = VCC = 5.0 V, AVSS = VSS = 0.0 V, TA = -40 C to +85 C) Pin Name P00 to P07, P10 to P17, P30 to P34 RST, INT20 to INT27, INT10 to INT12, SI, SCK, EC, TEST MOD0/1/2 Condition Value Min. 0.7 VCC Typ. Max. VCC + 0.3 Unit Remarks
Parameter
V
VIHS "H" level input voltage VIHM VIHSMB
0.8 VCC
VCC + 0.3
V
VCC - 0.3 VSS + 1.4

VCC + 0.3 VSS + 5.5 VSS + 5.5 0.3 VCC
V V V
MOD pin input When SMB selected When I2C selected
SCL, SDA VIHI2C P00 to P07, P10 to P17, P30 to P34 RST, INT20 to INT27, INT10 to INT12, SI, SCK, EC, TEST MOD0/1/2
0.7 VCC VSS - 0.3
VIL
V
VILS "L" level input voltage VILM VILSMB
VSS - 0.3
0.2 VCC
V
VSS - 0.3 VSS - 0.3

VSS + 0.3 VSS + 0.6 0.3 VCC VCC + 0.3
V V V
MOD pin input When SMB selected When I2C selected
SCL, SDA VILI2C Voltage applied to open drain output pins "H" level output voltage
VSS - 0.3
VD
P40 to P45 P00 to P07, P10 to P17, P20 to P27, P30 to P34 P00 to P07, P10 to P17, P20 to P27, P30 to P34, P40 to P45, RST
VSS - 0.3
V
VOH
IOH = -2.0 mA
4.0
V
"L" level output voltage
VOL
IOL = 4.0 mA
0.4
V
(Continued)
28
MB89960 Series
(AVCC = VCC = 5.0 V, AVSS = VSS = 0.0 V, TA = -40 C to +85 C) Parameter Symbol Pin Name P00 to P07, P10 to P17, P20 to P27, P30 to P34, P40 to P45 MOD0/1/2, TEST Open-drain output leak current ILIOD P40 to P45 0 V < VI < VSS + 5.5 V Condition Value Min. Typ. Max. Unit Remarks
Input leak current
-5 0 V < VI < VCC -10
+5 A
ILI
Without pullup resistor option

+10 +5 A
Pull-up resistance
P00 to P07, P10 to P17, P20 to P27, RPULL P30 to P34, P40 to P45, RST
VI = 0.0 V
25
50
100
With pull-up resistor option MB89PV960
ICC1
FCH = 10.0 MHz tINST*2 = 0.4 s main run mode VCC (when using an external clock) FCH = 10.0 MHz tINST*2 = 6.4 s main run mode FCH = 10.0 MHz tINST*2 = 0.4 s main sleep mode

10 4 5 3 1 3 2
20 7 8 8 3 8 4 mA
MB89965 MB89P965A MB89F969A MB89PV960
Power supply current*1
ICC2
mA MB89965 MB89P965A MB89F969A MB89PV960 mA MB89965 MB89P965A MB89F969A
ICCS1
(Continued)
29
MB89960 Series
(Continued)
Parameter Symbol
ICCS2
(AVCC = VCC = 5.0 V, AVSS = VSS = 0.0 V, TA = -40 C to +85 C) Pin Name Condition FCH = 10.0 MHz tINST*2 = 6.4 s main sleep mode FCH = 32.768 kHz sub run mode VCC (when using an external clock) FCH = 32.768 kHz sub sleep mode FCH = 32.768 kHz * clock mode, main stop mode TA = +25 C * sub stop mode Except AVCC, AVSS, VCC, and AVSS Value Min.
ICCL
Typ. 1 70 20 0.3 10 5 1 5
Max. 3 150 100 1 50 15 10 10
Unit
Remarks
mA A mA A A MB89PV960 A MB89965 MB89P965A MB89F969A MB89PV960 MB89965 MB89P965A MB89F969A

Power supply current*1
ICCLS
ICCT
ICCH
Input capacitance
CIN
f = 1 MHz
10
pF
*1 : The power supply current values are for an external clock. *2 : See " (4) Instruction Cycle" in "4. AC Characteristics".
30
MB89960 Series
4. AC Characteristics
(1) Reset Timing (VCC = 5.0 V, AVSS = VSS = 0.0 V, TA = -40 C to +85 C) Symbol tZLZH Condition Value Min. 48 tHCYL* Max. Unit ns Remarks
Parameter RST "L" pulse width
* : tHCYL is the period (1/FC) of the oscillation input to X0.
tZLZH
RST
0.2 VCC 0.2 VCC
(2) Power-On Reset Value Min. 0.5 1
(AVSS = VSS = 0.0 V, TA = -40 C to +85 C) Symbol tR tOFF Condition Max. 50 Unit ms ns For repeated operation Remarks
Parameter Power supply rising time Power supply cutoff time
Note : Ensure that the power supply rising time is less than the selected oscillation stabilization delay time. For example, if the main clock frequency FC = 10 MHz and 214/FC is selected as the oscillation stabilization delay time, the resulting oscillation stabilization delay time is 1.6 ms. As rapid changes in the power supply voltage may cause a power-on reset, if you need to change the power supply voltage while the device is operating, ensure that the power supply voltage changes smoothly.
tR 2.0 V
tOFF
VCC
0.2 V
0.2 V
0.2 V
31
MB89960 Series
(3) Clock Timings
(AVSS = VSS = 0.0 V, TA = -40 C to +85 C) Symbol Pin Name FCH FCL tHCYL tLCYL PWH PWL PWHL PWLL tCR tCF X0, X1 X0A, X1A X0, X1 X0A, X1A X0 X0A X0 Value Min. 1 100 20 Typ. 32.768 30.5 15.2 Max. 10 1000 10 Unit MHz kHz ns s ns s ns Remarks Main clock Sub clock Main clock Sub clock External clock External clock External clock
Parameter Clock frequency Clock cycle time
Input clock pulse width
Input clock rising/falling time
* X0 and X1 clock timing and input conditions
tHCYL PWH tCR tCF 0.8 VCC 0.8 VCC 0.2 VCC 0.2 VCC 0.2 VCC PWL
X0
* Clock configurations
When using a crystal oscillator or ceramic oscillator
When using an external clock
X0
X1 FCH
X0
X1 Open circuit FCH
C1
C2
32
MB89960 Series
* X0A and X1A clock timing conditions
tLCYL PWHL tCR tCF 0.8 VCC 0.8 VCC 0.2 VCC 0.2 VCC 0.2 VCC PWLL
X0A
* Sub clock configuration
When using a crystal oscillator or ceramic oscillator
When using an external clock
X0A
X1A FCL
X0A
X1A Open circuit FCL
C1
C2
(4) Instruction Cycle Parameter Symbol Value 4/FCH, 8/FCH, 16/FCH, 64/FCH tINST 2/FCL
(AVSS = VSS = 0.0 V, TA = -40 C to +85 C) Unit Remarks FCH = 10 MHz (4/FCH) operation time tINST = 0.4 s FCL = 32.768 kHz operation time tINST = 61.036 s
Instruction cycle (Minimum instruction execution time)
s
33
MB89960 Series
(5) Serial I/O Timings Symbol tSCYC tSLOV tIVSH tSHIX tSHSL tSLSH tSLOV tIVSH tSHIX
(VCC = 5.0 V, AVSS = VSS = 0.0 V, TA = -40 C to +85 C) Pin Name SCK SCK, SO SCK, SI SCK, SI SCK SCK SCK, SO SCK, SI SCK, SI External clock operation Internal clock operation Condition Value Min. 2 tINST* -200 200 200 tINST* tINST* 0 200 200 Max. 200 200 Unit s ns ns ns s s ns s s Remarks
Parameter Serial clock cycle time SCK SO delay time Valid SI SCK SCK valid SI hold time Serial clock "H" pulse width Serial clock "L" pulse width SCK SO delay time Valid SI SCK SCK valid SI hold time * Internal shift clock mode
* : See " (4) Instruction cycle" for a definition of tINST.
tSCYC 0.8 VCC
SCK
0.2 VCC tSLOV
0.2 VCC
SO
0.8 VCC 0.2 VCC tIVSH tSHIX
SI
0.8 VCC 0.8 VCC 0.2 VCC 0.2 VCC
* External shift clock mode
tSLSH tSHSL 0.8 VCC 0.8 VCC
SCK
0.2 VCC
0.2 VCC tSLOV
SO
0.8 VCC 0.2 VCC tIVSH tSHIX
SI
0.8 VCC 0.8 VCC 0.2 VCC 0.2 VCC
34
MB89960 Series
(6) Peripheral Input Timings
(VCC = 5.0 V, AVSS = VSS = 0.0 V, TA = -40 C to +85 C) Symbol tILIH tIHIL Pin Name INT10 to INT12, INT20 to INT27, EC Value Min. 2 tINST* 2 tINST* Max. Unit s s Remarks
Parameter Peripheral input "H" pulse width Peripheral input "L" pulse width
* : See " (4) Instruction cycle" for a definition of tINST.
tILIH
tIHIL
INT10 INT12, INT20 INT27, EC
0.8 VCC 0.8 VCC 0.2 VCC 0.2 VCC
35
MB89960 Series
j
(7) I2C Timings Sym bol tSTA tSTO tSTA tSTO
(VCC = 5.0 V, AVSS = VSS = 0.0 V, TA = -40 C to +85 C) Pin SCL SDA Value Min. 1/4tINST*1 x m* x n*3 - 20 Max. 1/4tINST*1 x m*2 x n*3 + 20 1/4tINST*1 x (m*2 x n*3 + 8) + 20 1/4tINST*1 x (m*2 x n*3 + 8) + 20 1/4tINST*1 x m*2 x n*3 + 20 1/4tINST* x (m* x n* + 8) + 20
1 2 3
Parameter Start condition output Stop condition output Start condition detect Stop condition detect
Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Remarks Master mode Master mode
SCL 1/4tINST*1 x (m*2 x n*3 + 8) SDA - 20 SCL SDA SCL SDA 1/4tINST*1 x 6 + 40 1/4tINST*1 x 6 + 40
Restart condition outSCL 1/4tINST*1 x (m*2 x n*3 + 8) tSTASU put SDA - 20 Restart condition deSCL tSTASU tect SDA SCL output "L" width tLOW SCL SCL SDA 1/4tINST*1 x 4+40 1/4tINST*1 x m*2 x n*3 - 20 1/4tINST* x (m* x n* + 8) - 20
1 2 3
Master mode
Master mode Master mode
SCL output "H" width tHIGH SDA output delay SDA output setup time after interrupt SCL input "L" pulse width SCL input "H" pulse width SDA input setup time SDA hold time tDO
1/4tINST*1 x 4 - 20 1/4tINST*1 x 4 - 20 1/4tINST*1 x 6 + 40 1/4tINST*1 x 2 + 40 40 0
1/4tINST*1 x 4 + 20
tDOSU SDA tLOW tHIGH tSU tHO SCL SCL SDA SDA
*1: See " (4) Instruction cycle" for a definition of tINST. *2: m is the value set in the ICCR : CS4 and CS3 bits (bits 4 to 3) . *3: n is the value set in the ICCR : CS2 to CS0 bits (bits 2 to 0) . * Data transmit (master/slave)
tDO
tDO
tSU
ACK
tHO
tDOSU
SDA
tSTASU tSTA tLOW tHO 1
SCL
9
* Data receive (master/slave)
tSU tHO tHIGH tLOW 8
tDO
ACK
tDO
tDOSU
SDA SCL
tSTO 9
6
7
36
MB89960 Series
5. Electrical Characteristics for the A/D Converter
Sym Pin bol
(AVcc = 3.5 V to 5.5 V, AVSS = VSS = 0.0 V, TA = -40 C to +85 C) Value Min. -5.0 -2.5 -1.9 Typ. AVR + 0.5 LSB VCC - 1.5 LSB 60 tINST*1 38 tINST*1 16 tINST* 1.5 1 400
1
Parameter Resolution Total error Non-linearity error Differential linearity error
Condition
Max. 10 +5.0 +2.5 +1.9 AVR + 4.5 LSB VCC + 1.5 LSB 4 10 AVR 3 5 AVCC 5
Unit bit LSB LSB LSB mV mV LSB s s s A V mA A V A A
Remarks
Zero transition voltage VOT Full-scale transition voltage Variation between channels A/D mode conversion time*2 A/D sampling time Analog input current Analog input voltage range Power supply current Reference voltage Reference voltage supply current AN0 to VAIN AN3 IA IAH IR IRH IAIN VFST
AVR = AVCC
AVR - 3.5 LSB VCC - 6.5 LSB

MB89965 MB89P965A MB89F969A MB89PV960
AVSS AVSS + 3.5
A/D operation AVCC TA = + 25 C A/D stop AVR A/D operation A/D stop
*1 : See " (4) Instruction cycle" for a definition of tINST. *2 : Includes sampling time.
37
MB89960 Series
6. A/D Converter Glossary
* Resolution The change in analog voltage that can be recognized by the A/D converter. * Linearity error (unit : LSB) The deviation between the actual conversion characteristics and the line linking the zero transition point ("00 0000 0000B" "00 0000 0001B") and the full scale transition point ("11 1111 1110B" "11 1111 1111B") . * Differential linearity error (unit : LSB) The variation from the ideal input voltage required to change the output code by 1 LSB. * Total error (unit : LSB) The total error is the difference between the actual value and the theoretical value.
Theoretical I/O Characteristics
3FFH 3FEH VFST 3FFH 3FEH 1.5 LSB 3FDH Actual conversion characteristic {1 LSB x N + 0.5 LSB}
Total Error
Digital Output
Digital output
3FDH
004H 003H 002H 001H 0.5 LSB AVSS AVR VOT 1 LSB
004H 003H 002H 001H AVSS VNT Actual conversion characteristic Theoretical characteristic AVR
Analog Input
VFST - VOT 1022
Analog input
VNT - {1 LSB x N + 0.5 LSB} 1 LSB
1 LSB =
(V)
Total error for digital output N =
38
MB89960 Series
Zero Transition Error
004H Actual conversion characteristic 3FFH
Full Scale Transition Error
Theoretical characteristic Actual conversion characteristic
Digital Output
Digital Output
003H
3FEH VFST (Actual measured value) Actual conversion characteristic
002H Actual conversion characteristic 001H VOT (Actual measured value) AVSS
3FDH
3FCH
AVR
Analog Input
Analog Input
Linearity Error
3FFH 3FEH Actual conversion characteristic {1 LSB x N + VOT} VFST (Actual measured VNT value) 004H 003H 002H 001H AVSS Actual conversion characteristic Theoretical characteristic N-2 VOT (Actual measured value) AVR AVSS N+1
Differential Linearity Error
Theoretical characteristic Actual conversion characteristic
Digital output
3FDH
Digital output
V (N + 1) T
N
N-1
VNT Actual conversion characteristic
AVR
Analog input
VNT - {1 LSB x N + VOT} 1 LSB
Analog Input
V (N + 1) T - VNT 1 LSB
Linearity error of digital output N =
Differential linearity error of digital output N =
-1
39
MB89960 Series
7. Notes for A/D Conversion
* Analog input pins and input impedance The A/D converter incorporates a sample & hold circuit as shown below. When an A/D conversion starts, the voltage at the analog input pin is captured by the sample & hold capacitor for a period of 16 instruction cycles. Accordingly, if the output impedance of the external circuit connected to the analog input is high, the analog input voltage may not stabilize within the period of the analog input sampling time. Therefore, ensure that the output impedance of the external circuit is sufficiently low (10 k or less) . If it is not possible to reduce the output impedance of the external circuit, connecting an external capacitor of approximately 0.1 F is recommended. Equivalent circuit of analog input
MB89960 series
Sample & hold circuit R
AN0 to AN3
Comparator controller
C
Closed for approximately 16 instruction cycles after initiating A/D conversion.
MB89965 MB89P965A MB89F969A MB89PV960
R = 3.2 k, C = 30 pF approx R = 1.4 k, C = 64 pF approx.
Analog channel selector
* Error The relative error increases as |AVR - AVSS| becomes smaller.
40
MB89960 Series
8. Electrical Characteristics of Flash Memory
* Programming and erasing characteristics Parameter Power supply current*1 Fixed time per sector regardless of size Successful completion time Unsuccessful completion time Successful completion time Unsuccessful completion time Sym Pin bol Name IFWE VCC Condition VCC = 5.0 V Value Min. Typ. Max. *2 1 40 15 Unit Remarks mA s
Sector erasing time

8
3600
s
Programming time
per byte
650 3600
s
*1 : Automatic algorithm executing *2 : If a fault occurs during sector erasing, detection via DQ5 may not be available (DQ5 = 1 may not occur) . Accordingly, a fault must be assumed after 15 s, even if DQ5 does not go to "1".
41
MB89960 Series
s MASK OPTIONS
Part No. NO Specifying procedure Initial value* selection for main clock oscillation stabilization delay time (FCH = 10 MHz) * 01 : 212/FCH (0.4 ms approx.) * 10 : 216/FCH (6.6 ms approx.) * 11 : 218/FCH (26.2 ms approx.) MB89965 Specify when ordering mask MB89P965A/ MB89F969A Not available MB89PV960 Not available
1
Selectable
218/FCH (26.2 ms approx.)
218/FCH (26.2 ms approx.)
FCH : Frequency of main clock oscillation * : This specifies the initial value after a reset of the oscillation stabilization delay time setting bits in the system clock control register (SYCC : WT1, WT0)
s ORDERING INFOMATION
Part Number MB89965PFV1 MB89P965APFV1 MB89965CPFV1 MB89965PFM MB89P965APFM MB89965CPFM MB89965PF MB89P965APF MB89965CPF MB89F969APFM MB89PV960CF Package Plastic LQFP, 48-pin (FPT-48P-M05) Plastic QFP, 48-pin (FPT-48P-M13) Plastic QFP, 48-pin (FPT-48P-M16) Plastic LQFP, 64-pin (FPT-64P-M09) Ceramic MQFP, 48-pin (MQP-48C-P01) Remarks The MB89965PFV1 does not have an I2C function. The MB89965PFM does not have an I2C function. The MB89965PF does not have an I2C function.
42
MB89960 Series
s PACKAGE DIMENSIONS
(These package dimensions are provisional. Please obtain the actual dimensions of the final product separately.) Plastic LQFP, 48-pin Note : The pin width and thickness includes plating. (FPT-48P-M05)
9.000.20(.354.008)SQ 7.000.10(.276.004)SQ
36 25
0.1450.055 (.006.002)
37
24
0.08(.003) INDEX
Details of "A" part 1.50 -0.10 .059 -.004
+0.20 +.008
(Mounting height)
48
13
"A" 0~8 LEAD No. 0.50(.020)
1 12
0.100.10 (.004.004) (Stand off)
0.200.05 (.008.002)
0.08(.003)
M
0.500.20 (.020.008) 0.600.15 (.024.006)
0.25(.010)
C
2000 FUJITSU LIMITED F48013S-c-4-8
Dimensions in mm (inches).
43
MB89960 Series
Plastic QFP, 48-pin (FPT-48P-M13)
13.100.40 SQ (.516.016) 10.000.20 SQ (.394.008)
36 25
2.35(.093)MAX (Mounting height) 0(0)MIN (STAND OFF)
37
24
Details of "A" part 0.15(.006) 8.80 (.346) REF
11.500.30 (.453.012)
0.20(.008) 0.18(.007)MAX 0.53(.021)MAX
INDEX "A"
48 13
Details of "B" part LEAD No.
1 12
0.80(.0315)TYP
0.300.10 (.012.004) "B"
0.16(.006)
M
0.150.05 (.006.002) 0~10 0.800.30 (.031.012)
0.10(.004)
C
2000 FUJITSU LIMITED F48023S-1C-2
Dimensions in mm (inches).
44
MB89960 Series
Plastic QFP, 48-pin (FPT-48P-M16)
17.200.40 SQ (.677.016) +0.30 12.00 -0.10 SQ
36
.472 -.004
+.012
25
2.70(.106)MAX (Mounting height) 0.05(.002)MIN (STAND OFF)
37
24
Details of "A" part 0.15(.006) 8.80 (.346) REF
13.600.40 (.535.016)
0.20(.008) 0.15(.006)MAX 0.50(.020)MAX
INDEX
48
"A"
13
Details of "B" part
LEAD No.
1
12
0.15 -0.01 0.300.06 (.012.002) "B" 0.16(.006)
M
+0.05 +.002
0.80(.0315)TYP
.006 -.0004 1.800.30 (.071.012)
0~10
0.15(.006)
C
2000 FUJITSU LIMITED F48026S-1C-2
Dimensions in mm (inches).
45
MB89960 Series
Ceramic MQFP, 48-pin (MQP-48C-P01)
17.20(.677)TYP 15.000.25 (.591.010) 14.820.35 (.583.014) 1.50(.059)TYP 1.00(.040)TYP 8.80(.346)REF 0.800.22 (.0315.0087) PIN No.1 INDEX
PIN No.1 INDEX
1.020.13 (.040.005)
10.92 -0.0 +.005 .430 -0
+0.13
7.14(.281) 8.71(.343) TYP TYP
PAD No.1 INDEX 0.30(.012)TYP 4.50(.177)TYP 1.10 -0.25 +.018 .043 -.010
+0.45
0.400.08 (.016.003)
0.60(.024)TYP
8.50(.335)MAX
0.150.05 (.006.002)
C
1994 FUJITSU LIMITED M48001SC-4-2
Dimensions in mm (inches).
46
MB89960 Series
Plastic LQFP, 64-pin (FPT-64P-M09)
14.000.20(.551.008)SQ
48 33
+0.20 +.008
12.000.10(.472.004)SQ
1.50 -0.10 .059 -.004
(Mounting height)
49
32
9.75 (.384) REF 1 PIN INDEX
13.00 (.512) NOM
64
17
LEAD No.
1
16
Details of "A" part "A"
M
0.65(.0256)TYP
0.300.10 (.012.004)
0.13(.005)
0.127 -0.02 .005 -.001
+0.05 +.002
0.100.10 (STAND OFF) (.004.004)
0.10(.004) 0 10
0.500.20 (.020.008)
C
2000 FUJITSU LIMITED F64018S-1C-3
Dimensions in mm (inches).
47
MB89960 Series
FUJITSU LIMITED
All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information and circuit diagrams in this document are presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. Also, FUJITSU is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). Please note that Fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the prior authorization by Japanese government will be required for export of those products from Japan.
F0104 (c) FUJITSU LIMITED Printed in Japan

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