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NVMFS4841N Power MOSFET
Features
30V, 7 mW, 89A, Single N-Channel SO8FL
* * * * *
Small Footprint (5x6 mm) for Compact Design Low RDS(on) to Minimize Conduction Losses Low QG and Capacitance to Minimize Driver Losses AEC-Q101 Qualified These are Pb-Free Devices*
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V(BR)DSS 30 V Value 30 "20 89 63 Unit V V A
RDS(ON) MAX 7.0 mW @ 10 V 11.4 mW @ 4.5 V
ID MAX 89 A
MAXIMUM RATINGS (TJ = 25C unless otherwise noted)
Parameter Drain-to-Source Voltage Gate-to-Source Voltage Continuous Drain Current RYJ-mb (Notes 1, 2, 3, 4) Power Dissipation RYJ-mb (Notes 1, 2, 3) Continuous Drain Current RqJA (Notes 1 & 3, 4) Power Dissipation RqJA (Notes 1, 3) Pulsed Drain Current Tmb = 25C Steady State Tmb = 100C Tmb = 25C Tmb = 100C TA = 25C Steady State TA = 100C TA = 25C TA = 100C TA = 25C, tp = 10 ms TA = 25C IDM IDmaxPkg TJ, Tstg IS EAS PD ID PD Symbol VDSS VGS ID
D (5,6)
112 56 16 11 3.7 1.8 336 80 -55 to 175 51 180
W A
G (4) S (1,2,3) N-CHANNEL MOSFET
W A A
1
MARKING DIAGRAM
D S S S G V4841 AYWWG G D D
Current limited by package (Note 4)
Operating Junction and Storage Temperature Source Current (Body Diode) Single Pulse Drain-to-Source Avalanche Energy (TJ = 25C, VDD = 24 V, VGS = 10 V, IL(pk) = 19 A, L = 1.0 mH, RG = 25 W) Lead Temperature for Soldering Purposes (1/8 from case for 10 s)
C A mJ
SO-8 FLAT LEAD CASE 488AA STYLE 1
D
TL
260
C
A = Assembly Location Y = Year WW = Work Week G = Pb-Free Package (Note: Microdot may be in either location)
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.
ORDERING INFORMATION
Device NVMFS4841NT1G NVMFS4841NT3G Package SO-8FL (Pb-Free) SO-8FL (Pb-Free) Shipping 1500 / Tape & Reel 5000 / Tape & Reel
THERMAL RESISTANCE MAXIMUM RATINGS (Note 1)
Parameter Junction-to-Mounting Board (top) - Steady State (Note 2, 3) Junction-to-Ambient - Steady State (Note 3) Symbol RYJ-mb RqJA Value 1.3 41 Unit C/W
1. The entire application environment impacts the thermal resistance values shown, they are not constants and are only valid for the particular conditions noted. 2. Psi (Y) is used as required per JESD51-12 for packages in which substantially less than 100% of the heat flows to single case surface. 3. Surface-mounted on FR4 board using a 650 mm2, 2 oz. Cu pad. 4. Maximum current for pulses as long as 1 second is higher but is dependent on pulse duration and duty cycle.
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
(c) Semiconductor Components Industries, LLC, 2010
December, 2010 - Rev. 0
1
Publication Order Number: NVMFS4841N/D
NVMFS4841N
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise specified)
Parameter OFF CHARACTERISTICS Drain-to-Source Breakdown Voltage Drain-to-Source Breakdown Voltage Temperature Coefficient Zero Gate Voltage Drain Current V(BR)DSS V(BR)DSS/ TJ IDSS IGSS VGS(TH) VGS(TH)/TJ RDS(on) gFS CISS COSS CRSS QG(TOT) QG(TH) QGS QGD QG(TOT) VGS = 10 V, VDS = 15 V, ID = 30 A VGS = 4.5 V, VDS = 15 V; ID = 30 A VGS = 0 V, f = 1 MHz, VDS = 12 V VGS = 10 V VGS = 4.5 V Forward Transconductance CHARGES AND CAPACITANCES Input Capacitance Output Capacitance Reverse Transfer Capacitance Total Gate Charge Threshold Gate Charge Gate-to-Source Charge Gate-to-Drain Charge Total Gate Charge SWITCHING CHARACTERISTICS (Note 6) Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time DRAIN-SOURCE DIODE CHARACTERISTICS Forward Diode Voltage VSD tRR ta tb QRR VGS = 0 V, dIS/dt = 100 A/ms, IS = 30 A VGS = 0 V, IS = 30 A TJ = 25C TJ = 125C 0.9 0.8 20.5 11.6 8.9 10.7 nC ns 1.2 V td(ON) tr td(OFF) tf VGS = 4.5 V, VDS = 15 V, ID = 15 A, RG = 3.0 W 13.5 66.5 15.5 7.5 ns 1436 348 177 11.5 2.0 5.0 5.1 25.4 nC 17 nC pF ID = 30 A ID = 30 A VGS = 0 V, VDS = 30 V TJ = 25 C TJ = 125C VGS = 0 V, ID = 250 mA 30 25 1 10 100 V mV/C mA nA Symbol Test Condition Min Typ Max Unit
Gate-to-Source Leakage Current ON CHARACTERISTICS (Note 5) Gate Threshold Voltage Negative Threshold Temperature Coefficient Drain-to-Source On Resistance
VDS = 0 V, VGS = 20 V VGS = VDS, ID = 250 mA 1.5 5.6 4.7 9.2 16
2.5
V mV/C
7.0 11.4
mW S
VDS = 15 V, ID = 15 A
Reverse Recovery Time Charge Time Discharge Time Reverse Recovery Charge
5. Pulse Test: pulse width v 300 ms, duty cycle v 2%. 6. Switching characteristics are independent of operating junction temperatures.
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NVMFS4841N
TYPICAL PERFORMANCE CURVES
130 120 110 100 90 80 70 60 50 40 30 20 10 0 130 120 110 100 90 80 70 60 50 40 30 20 10 0
ID, DRAIN CURRENT (AMPS)
VGS = 5 V 4.5 V
4V 3.8 V 3.6 V 3.4 V 0 1 2 3 4 5
ID, DRAIN CURRENT (AMPS)
5.5 V to 10 V
TJ = 25C
VDS = 10 V
TJ = 125C TJ = 25C TJ = -55C 1 2 3 4 5 6 7 8
VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)
VGS, GATE-TO-SOURCE VOLTAGE (VOLTS)
Figure 1. On-Region Characteristics
RDS(on), DRAIN-TO-SOURCE RESISTANCE (W) RDS(on), DRAIN-TO-SOURCE RESISTANCE (W) 0.017
Figure 2. Transfer Characteristics
0.018 0.017 0.016 0.015 0.014 0.013 0.012 0.011 0.010 0.009 0.008 0.007 0.006 0.005
ID = 30 A TJ = 25C
TJ = 25C 0.014 VGS = 4.5 V 0.011 0.008 VGS = 10 V 0.005 0.002
3
4
5
6
7
8
9
10
11
10
15
20
25
30
35
40
45
50
55
60
VGS, GATE-TO-SOURCE VOLTAGE (VOLTS)
ID, DRAIN CURRENT (AMPS)
Figure 3. On-Resistance vs. Gate-to-Source Voltage
RDS(on), DRAIN-TO-SOURCE RESISTANCE (NORMALIZED) 1.9 1.8 1.7 1.6 1.5 1.4 1.3 1.2 1.1 1.0 0.9 0.8 0.7 0.6 -50 10000 ID = 30 A VGS = 10 V 1000 IDSS, LEAKAGE (nA) 100 10 1 0.1 -25 0 25 50 75 100 125 150 175 5
Figure 4. On-Resistance vs. Drain Current and Gate Voltage
VGS = 0 V TJ = 150C TJ = 125C
TJ = 25C
10
15
20
25
30
TJ, JUNCTION TEMPERATURE (C)
VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)
Figure 5. On-Resistance Variation with Temperature
Figure 6. Drain-to-Source Leakage Current vs. Voltage
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NVMFS4841N
TYPICAL PERFORMANCE CURVES
2200 2000 C, CAPACITANCE (pF) 1800 1600 1400 1200 1000 800 600 400 200 0 10 Crss 5 0 5 VGS VDS 10 15 20 25 30 Crss Coss Ciss TJ = 25C 12 11 10 9 8 7 6 5 4 3 2 1 0 0 2 4 QGS QGD VDD = 15 V VGS = 10 V ID = 30 A TJ = 25C 6 8 10 12 14 16 18 20 22 24 26 QG, TOTAL GATE CHARGE (nC)
VGS, GATE-TO-SOURCE VOLTAGE (VOLTS)
QT
Ciss
GATE-TO-SOURCE OR DRAIN-TO-SOURCE VOLTAGE (VOLTS)
Figure 7. Capacitance Variation
1000
Figure 8. Gate-To-Source and Drain-To-Source Voltage vs. Total Charge
30 IS, SOURCE CURRENT (AMPS) VGS = 0 V 25 20 15 10 5 0 0.5 TJ = 25C
VDD = 15 V ID = 15 A VGS = 10 V
t, TIME (ns)
100 tr td(off) 10 td(on) tf
1
1
10 RG, GATE RESISTANCE (W)
100
0.6
0.7
0.8
0.9
1.0
VSD, SOURCE-TO-DRAIN VOLTAGE (VOLTS)
Figure 9. Resistive Switching Time Variation vs. Gate Resistance
EAS, SINGLE PULSE DRAIN-TO-SOURCE AVALANCHE ENERGY (mJ) 1000 I D, DRAIN CURRENT (AMPS) 180 160 140 120 100 80 60 40 20 0 25
Figure 10. Diode Forward Voltage vs. Current
ID = 19 A
100
10 ms 100 ms 1 ms
10
VGS = 20 V SINGLE PULSE TC = 25C RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 0.1
10 ms dc 100
1
10 1 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)
50 75 100 125 150 175 TJ, STARTING JUNCTION TEMPERATURE (C)
Figure 11. Maximum Rated Forward Biased Safe Operating Area
Figure 12. Maximum Avalanche Energy vs. Starting Junction Temperature
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NVMFS4841N
TYPICAL PERFORMANCE CURVES
100 RqJ(t) (C/W) EFFECTIVE TRANSIENT THERMAL RESISTANCE Duty Cycle = 0.5 10 0.2 0.1 0.05 1 0.02 0.01 0.1
SINGLE PULSE 0.01 0.000001 0.00001
0.0001
0.001
0.01
0.1
1
10
100
1000
t, PULSE TIME (s)
Figure 13. FET Thermal Response
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NVMFS4841N
PACKAGE DIMENSIONS
DFN5 5x6, 1.27P (SO-8FL) CASE 488AA-01 ISSUE D
0.20 C D 2
6 NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION D1 AND E1 DO NOT INCLUDE MOLD FLASH PROTRUSIONS OR GATE BURRS.
2X
A B
5 2X
D1
0.20 C E1 2 E c
4X
q
A1
1
2
3
4
TOP VIEW
3X
C
SEATING PLANE
0.10 C A 0.10 C SIDE VIEW
8X
e
DETAIL A
DIM A A1 b c D D1 D2 E E1 E2 e G K L L1 M q
MILLIMETERS MIN NOM MAX 0.90 1.00 1.10 0.00 --- 0.05 0.33 0.41 0.51 0.23 0.28 0.33 5.15 BSC 4.50 4.90 5.10 3.50 --- 4.22 6.15 BSC 5.50 5.80 6.10 3.45 --- 4.30 1.27 BSC 0.51 0.61 0.71 0.51 --- --- 0.51 0.61 0.71 0.05 0.17 0.20 3.00 3.40 3.80 0_ --- 12 _
DETAIL A
SOLDERING FOOTPRINT*
1.270
STYLE 1: PIN 1. SOURCE 2. SOURCE 3. SOURCE 4. GATE 5. DRAIN 6. DRAIN 3X
b e/2
1 4
0.750
4X
0.10 0.05
CAB c L
1.000
4X
0.965 1.330 0.495 3.200 0.475
2X 2X
K E2 L1
6 5
0.905 4.530
2X
M
G
D2 BOTTOM VIEW
1.530 4.560 *For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
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NVMFS4841N/D

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