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W9451GBDA-6 512MB (64M x 64) DDR SDRAM DIMM
1. GENERAL DESCRIPTION
The W9451GBDA is a 512MB Double Data Rate Synchronous Dynamic RAM (DDR SDRAM) memory modules. It is organized in a 64M x 64 bit configuration using eight pieces of Winbond W942508AH (32M x 8 bits) DDR SDRAMs and assembled on a JEDEC standard 184-pin DIMM PCB. To provide high data bandwidth, W9451GBDA uses a double data rate architecture to transfer two data words per clock cycle and delivers a data bandwidth of up to 2.7G (DDR333) bytes per second. It is ideal for high performance systems that require fast data transfer memory modules. By reading the Serial Presence-Detect (SPD), the system can identify the module type, DDR SDRAM timing parameters and other necessary information to optimize system setting and maximize its performance.
2. FEATURES
* JEDEC standard 184-pin, Dual In-Line Memory Module (DIMM) * Comply to DDR333 specification * Two memory rows on this module * Differential clock inputs (CLK and CLK ) * Double Data Rate architecture, two data transfers per clock cycle * CAS Latency: 2.5 * Burst Lengths: 2, 4, 8 * Auto Refresh and Self Refresh * 8K refresh cycles / 64 mS * Serial Presence Detect with EEPROM * Interface: SSTL-2 * Power supply: 2.5V 0.1V * PCB height: 1.25 inches
3. AVAILABLE PART NUMBERS
MODULE PART NUMBER W9451GBDA-6 SPEED DDR333/CL2.5
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Publication Release Date: March 15, 2002 Revision A1
W9451GBDA-6
4. PIN ASSIGNMENT
PIN
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
FONT
VREF DQ0 VSS DQ1 DQS0 DQ2 VDD DQ3 NC NC VSS DQ8 DQ9 DQS1 VDDQ CKL1 CLK1 VSS DQ10 DQ11 CKE0 VDDQ DQ16 DQ17 DQS2 VSS A9 DQ18 A7 VDDQ DQ19
PIN
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52
FONT
A5 DQ24 VSS DQ25 DQS3 A4 VDD DQ26 DQ27 A2 VSS A1 *CB0 *CB1 VDD *DQS8 A0 *CB2 VSS *CB3 BA1 KEY
PIN
62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92
FONT
VDDQ WE DQ41 CAS VSS DQS5 DQ42 DQ43 VDD *S2 DQ48 DQ49 VSS CLK2 CLK2 VDDQ DQS6 DQ50 DQ51 VSS VDDID DQ56 DQ57 VDD DQS7 DQ58 DQ59 VSS WP SDA SCL
PIN
93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123
BACK
VSS DQ4 DQ5 VDDQ DQS9 DQ6 DQ7 VSS NC NC *A13 VDDQ DQ12 DQ13 DQS10 VDD DQ14 DQ15 CKE1 VDDQ *BA2 DQ20 A12 VSS DQ21 A11 DQS11 VDD DQ22 A8 DQ23
PIN
124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 KEY 145 146 147 148 149 150 151 152 153
BACK
VSS A6 DQ28 DQ29 VDDQ DQS12 A3 DQ30 VSS DQ31 *CB4 *CB5 VDDQ CLK0 CLK0 VSS *DQS17 A10 *CB6 VDDQ *CB7
PIN
154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175
BACK
RAS DQ45 VDDQ CS0 CS1 DQS14 VSS DQ46 DQ47 *S3 VDDQ DQ52 DQ53 NC VDD DQS15 DQ54 DQ55 VDDQ NC DQ60 DQ61 VSS DQS16 DQ62 DQ63 VDDQ SA0 SA1 SA2 VDDSPD
53 54 55 56 57 58 59 60 61
DQ32 VDDQ DQ33 DQS4 DQ34 VSS BA0 DQ35 DQ40
VSS DQ36 DQ37 VDD DQS13 DQ38 DQ39 VSS DQ44
176 177 178 179 180 181 182 183 184
*These pins are not used in this module.
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W9451GBDA-6
5. PIN DESCRIPTIONS
PIN CLKn, CLKn Clock Input NAME FUNCTION DESCRIPTION CLKn and CLKn are differential clock inputs. All input command signals are sampled at the positive edge of CLK(except for DQ, DM and CKE). Disable or enable the command decoder. When command decoder is disabled, new command is ignored and previous operation continues. CKE controls the clock activation and deactivation. When CKE is low, Power Down mode, Suspend mode, or Self-Refresh mode is entered. Multiplexed pins for row and column address. Row address: A0 - A12. Column address: A0 - A9. Selects bank to be activated during row address latch time. Selects bank for read/write during column address latch time. Command input. When sampled at the rising edge of the clock, RAS , CAS and WE define the operation to be executed. Referred to RAS Referred to RAS The output buffer is placed at Hi-Z when DM is sampled high in read cycle. In write cycle, sampling DM high will block the write data. Multiplexed pins for data output and input Output with read data, input with write data. DQS is edge-aligned with read data, centered in write data. Power supply (2.5V). Ground SSTL-2 Reference voltage Separated power supply for SPD EEPROM (2.3V - 3.6V) Clock for serial presence detection Data line for serial presence detection System assigned address (SA0 - SA2) to identify different memory module in a system board. No connection
CSn CKEn A0 - A12 BA0 - BA1
Chip select Clock Enable Address Bank Select Address Row Address Strobe Column Address Strobe Write Enable Input/Output Mask Data Input/Output Data Strobe Input/Output Power (+2.5V) Ground Reference Voltage SPD Power Serial Clock Serial Data I/O SPD Address Line No Connection
RAS
CAS WE DM0 - DM7 DQ0 - DQ63 DQS0 - DQS7 VDD VSS VREF VDDSPD SCL SDA SAn NC
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Publication Release Date: March 15, 2002 Revision A1
W9451GBDA-6
6. BLOCK DIAGRAM
CS1 CS0 DQS0 DM0/DQS9 DM
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2
DQS4 DM4/DQS13 CS DQS U0 DM
I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2
DQS CS DQS U8
DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39
DM
I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2
CS DQS U4
DM
I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2
CS DQS U12
DQS1 DM1/DQS10 DM
DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2
DQS5 DM5/DQS14 CS DQS U1 DM
I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2
CS DQS U9
DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47
DM
I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2
CS DQS U5
DM
I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2
CS DQS U13
DQS2 DM2/DQS11 DM
DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2
DQS6 DM6/DQS15 CS DQS U2 DM
I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2
CS DQS U10
DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55
DM
I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2
CS DQS U6
DM
I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2
CS DQS U14
DQS3 DM3/DQS12 DM
DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2
DQS7 DM7/DQS16 CS DQS U3 DM
I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2
CS DQS U11
DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63
DM
I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2
CS DQS U7
DM
I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2
CS DQS U15
A0 ~ A13, BA0 & 1 RAS SERIAL PD SCL U7 A0 A1 A2 SDA WP WE SA0 SA1 SA2 SDA CKE0 VDD SPD VDD/VDDQ CAS
SDRAMs U0 ~ U15 SDRAMs U0 ~ U15 SDRAMs U0 ~ U15 SDRAMs U0 ~ U15
CKE1
SDRAMs U8 ~ U15 SDRAMs U0 ~ U7 SPD D0~D15
VREF VSS
D0~D15 D0~D15
VDDID
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W9451GBDA-6
7. ABSOLUTE MAXIMUM RATINGS
PARAMETER Input, Output Voltage Power Supply Voltage Operating Temperature Storage Temperature Soldering Temperature (10s) Power Dissipation for Each Component Short Circuit Output Current SYMBOL VIN, VOUT VDD, VDDQ TOPR TSTG TSOLDER PD IOUT RATING -0.3 - VDDQ +0.3 -0.3 - 3.6 0 - 70 -55 - 150 260 16 50 UNIT V V C C C W mA NOTES 1 1 1 1 1 1 1
Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the device.
8. RECOMMENDED DC OPERATING CONDITIONS
(Ta = 0 to 70 C)
PARAMETER
Power Supply Voltage Power Supply Voltage (for I/O Buffer) Input reference Voltage Termination Voltage (System) Input High Voltage (DC) Input Low Voltage (DC) Differential Clock DC Input Voltage Input Differential Voltage. CLK and
CLK inputs (DC)
SYMBOL
VDD VDDQ VREF VTT VIH (DC) VIL (DC) VICK (DC) VID (DC) VIH (AC) VIL (AC) VID (AC) VX (AC) VISO (AC)
MIN.
2.4 2.4 0.49 x VDDQ VREF -0.04 VREF +0.15 -0.3 -0.1 0.36 VREF +0.31 0.7 VDDQ/2 -0.2 VDDQ/2 -0.2
TYP.
2.5 2.5 0.50 x VDDQ VREF -
MAX.
2.6 VDD 0.51 x VDDQ VREF +0.04 VDDQ +0.3 VREF -0.15 VDDQ +0.1 VDDQ +0.6 VREF -0.31 VDDQ +0.6 VDDQ/2 +0.2 VDDQ/2 +0.2
UNIT
V V V V V V V V V V V V V
NOTES
2 2 2, 3 2 2 2 16 14, 16 2 2 14, 16 13, 16 15, 16
Input High Voltage (AC) Input Low Voltage (AC) Input Differential Voltage. CLK and
CLK inputs (AC)
Differential AC input Cross Point Voltage Differential Clock AC Middle Point
Notes: Undershoot limit: VIL (min.) = -0.9V with a pulse width < 5 nS Overshoot limit: VIH (max.) = VDDQ +0.9V with a pulse width < 5 nS VIH (DC) and VIL (DC) are levels to maintain the current logic state, VIH (AC) and VIL (AC) are levels to change to the new logic state.
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Publication Release Date: March 15, 2002 Revision A1
W9451GBDA-6
9. CAPACITANCE
(VDD = VDDQ = 2.5V 0.2V, f = 1 MHz, TA = 25 C, VOUT (DC) = VDDQ/2, VOUT (Peak to Peak) = 0.2V) PARAMETER Address Input Capacitance (A0 - A12, BA0, BA1) Command Input Capacitance ( RAS , CAS , WE )
CS signals Input Capacitance ( CS0 , CS1 )
SYMBOL Cadd-IN CCMD-IN CCS-IN CCKE-IN CCLK-IN CI/O
MIN.
MAX. 24 24 12 12 12 5
UNIT pF pF pF pF pF pF
CKE signal Input Capacitance (CKE0, CKE1) CLK signals Input Capacitance (CLKn, CLKn ) DM/DQS/DQ Input capacitance (DM0 - DM7, DQS0 - 7, DQ0 - 63)
10. DC CHARACTERISTICS
PARAMETER OPERATING CURRENT: One Bank Active-Precharge; tRC = tRC min; tCK = tCK min; DQ, DM and DQS inputs changing twice per clock cycle; Address and control inputs changing once per clock cycle OPERATING CURRENT: One Bank Active-Read-Precharge; Burst = 2; tRC = tRC min; CL=2.5; tCK = tCK min; IOUT=0mA; Address and control inputs changing once per clock cycle. PRECHARGE-POWER-DOWN STANDBY CURRENT: All Banks Idle; Power down mode; CKE < VIL max; tCK = tCK min; Vin = VREF for DQ, DQS and DM IDLE FLOATING STANDBY CURRENT: CS > VIH min; All Banks Idle; CKE > VIH min; Address and other control inputs changing once per clock cycle; Vin = Vref for DQ, DQS and DM IDLE STANDBY CURRENT: CS > VIH min; All Banks Idle; CKE > VIH min; tCK = tCK min; Address and other control inputs changing once per clock cycle; Vin > VIH min or Vin < VIL max for DQ, DQS and DM IDLE QUIET STANDBY CURRENT: CS > VIH min; All Banks Idle; CKE > VIH min; tCK = tCK min; Address and other control inputs stable; Vin > VREF for DQ, DQS and DM ACTIVE POWER-DOWN STANDBY CURRENT: One Bank Active; Power down mode; CKE < VIL max; tCK = tCK min ACTIVE STANDBY CURRENT: CS > VIH min; CKE > VIH min; One Bank ActivePrecharge; tRC = tRAS max; tCK = tCK min; DQ, DM and DQS inputs changing twice per clock cycle; Address and other control inputs changing once per clock cycle OPERATING CURRENT: Burst = 2; Reads; Continuous burst; One Bank Active; Address and control inputs changing once per clock cycle; CL = 2.5; tCK = tCK min; IOUT = 0 mA OPERATING CURRENT: Burst = 2; Write; Continuous burst; One Bank Active; Address and control inputs changing once per clock cycle; CL=2.5; tCK = tCK min; DQ, DM and DQS inputs changing twice per clock cycle AUTO REFRESH CURRENT: tRC = tRFC min SELF REFRESH CURRENT: CKE < 0.2V RANDOM READ CURRENT: 4 Banks Active Read with activate every 20 nS, AutoPrecharge Read every 20ns; Burst = 4; tRCD = 3; IOUT= 0mA; DQ, DM and DQS inputs changing twice per clock cycle; Address changing once per clock cycle SYM. MAX. -6 IDD0 1240 7 UNIT NOTES
IDD1 IDD2P
1240 32
7, 9
IDD2F
720
7
IDD2N
720
7
IDD2Q IDD3P
640 320
mA
7
IDD3N
920
7
IDD4R
1710
7, 9
IDD4W IDD5 IDD6 IDD7
1710 1880 48 2520
7 7
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W9451GBDA-6
11. AC CHARACTERISTICS OF SDRAM COMPONENTS (Notes: 10, 12)
SYMBOL tRC tRFC tRAS tRCD tRAP tCCD tRP tRRD tWR tDAL tCK tAC tDQSCK tDQSQ tCH tCL tHP tQH tRPRE tRPST tDS tDH tDIPW tDQSH tDQSL tDSS tDSH tWPRES tWPRE tWPST tDQSS tDSSK tIS tIH tIPW tHZ tLZ tT(SS) tWTR tXSNR tXSRD tREF tMRD PARAMETER Active to Ref/Active Command Period Ref to Ref/Active Command Period Active to Precharge Command Period Active to Read/Write Command Delay Time Active to Read with Auto Precharge Enable Read/Write(a) to Read/Write(b) Command Period Precharge to Active Command Period Active(a) to Active(b) Command Period Write Recovery Time Auto Precharge Write Recovery + Precharge Time CLK Cycle Time CL = 2.5 Data Access Time from CLK, CLK DQS Output Access Time from CLK, CLK Data Strobe Edge to Output Data Edge Skew CLk High Level Width CLK Low Level Width CLK Half Period (minimum of actual tCH, tCL) DQ Output Data Hold Time from DQS DQS Read Preamble Time DQS Read Postamble Time DQ and DM Setup Time DQ and DM Hold Time DQ and DM Input Pulse Width (for each input) DQS Input High Pulse Width DQS Input Low Pulse Width DQS Falling Edge to CLK Setup Time DQS Falling Edge Hold Time from CLK Clock to DQS Write Preamble Set-up Time DQS Write Preamble Time DQS Write Postamble Time Write Command to First DQS Latching Transition UDQS - LDQS Skew (x 16) Input Setup Time Input Hold Time Control & Address Input Pulse Width (for each input) Data-out High-impedance Time from CLK, CLK Data-out Low-impedance Time from CLK, CLK SSTL Input Transition Internal Write to Read Command Delay Exit Self Refresh to Non-read Command Exit Self Refresh to Read command Refresh Time (8K) Mode Register Set Cycle Time MIN. 60 72 42 15 15 1 18 12 15 30 6 -0.7 -0.6 0.45 0.45 Min. (tCL, tCH) THP -0.55 0.9 0.4 0.45 0.45 1.75 0.35 0.35 0.2 0.2 0 0.25 0.4 0.75 -0.25 0.75 0.75 2.2 -0.7 -0.7 0.5 1 75 10 12 -6 MAX. UNITS NOTES
100000
nS
tCK
15 0.7
nS 16
0.6 0.45 0.55 0.55 tCK 11
nS
1.1 0.6
tCK nS
11
tCK
11
nS 11 0.6 1.25 0.25 tCK
nS
0.7 0.7 1.5 tCK nS tCK mS nS
64
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Publication Release Date: March 15, 2002 Revision A1
W9451GBDA-6
12. AC TEST CONDITION OF SDRAM COMPONENTS
PARAMETER Input High Voltage (AC) Input Low Voltage (AC) Input Reference Voltage Termination Voltage Input Signal Peak to Peak Swing Differential Clock Input Reference Voltage Input Difference Voltage. CLK and CLK Inputs (AC) Input Signal Minimum Slew Rate Output Timing Measurement Reference Voltage SYMBOL VIH VIL VREF VTT VSWING VR VID(AC) SLEW VOTR VALUE VREF +0.31 V REF -0.31 0.5 x VDDQ 0.5 x VDDQ 1.0 Vx (AC) 1.5 1.0 0.5 x VDDQ UNIT V V V V V V V V/nS V
VDDQ VIH min (AC) V SWING (MAX) VREF VIL max (AC) VSS
T T
VTT
RT= 50 ohms
output
Z = 50 ohms 30pF
SLEW = (VIH min (AC) - V ILmax (AC)) / T
A.C. TEST LOAD (A)
Notes: (1) (2) (3) (4) (5) (6) (7) Conditions outside the limits listed under "ABSOLUTE MAXIMUM RATINGS" may cause permanent damage to the device. All voltages are referenced to VSS, VSSQ. Peak to peak AC noise on VREF may not exceed 2% of VREF (DC). VOH = 1.95V,VOL = 0.35V VOH = 1.9V,VOL = 0.4V The values of IOH(DC) is based on VDDQ = 2.4V and VTT = 1.19V. The values of IOL(DC) is based on VDDQ = 2.4V and VTT = 1.11V. These parameters depend on the cycle rate and these values are measured at a cycle rate with the minimum values of tCK and tRC.
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W9451GBDA-6
(8) (9) VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF and must track variations in the DC level of VREF. These parameters depend on the output loading. Specified values are obtained with the output open.
(10) Transition times are measured between VIH min.(AC) and VIL max.(AC).Transition (rise and fall) of input signals have a fixed slope. (11) If the result of nominal calculation with regard to tCK contains more than one decimal place, the result is rounded up to the nearest decimal place. i.e., tDQSS = 0.75 x tCK, tCK = 7.5 nS, 0.75 x 7.5 nS = 5.625 nS is rounded up to 5.6 nS. (12) VX is the differential clock cross point voltage where input timing measurement is referenced. (13) VID is magnitude of the difference between CLK input level and CLK input level. (14) VISO means {VICK(CLK) + VICK( CLK )}/2. (15) Refer to the figure below. (16) tAC and tDQSCK depend on the clock jitter. These timing are measured at stable clock.
CLK VX CLK VICK VSS VID(AC) VICK VX VX VICK VX VICK VX
VID(AC)
0 V Differential
VISO VISO(min) VSS VISO(max)
(17) tAC and tDQSCK depend on the clock jitter. These timing are measured at stable clock.
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Publication Release Date: March 15, 2002 Revision A1
W9451GBDA-6
13. OPERATION MODES
The following Simplified Truth Table illustrates the operation modes of DDR SDRAM. For more detailed information please refer to the DDR SDRAM datasheet. Simplified Truth Table
COMMAND DEVICE STATE Idle Any Any Active Active
(3) (3)
CKEN-1
CKEN
DMN
BS0 BS1 V V X V V V V L, L H, L X X X X X X
A10
A12, A11, A9-A0 V X X V V V V C V X X X X X X
CS
RAS
CAS
WE
Bank Active Bank Precharge Precharge All Write Write with Autoprecharge Read Read with Autoprecharge Mode Register Set Extended Mode Register Set No Operation Burst Read Stop Device Deselect Auto Refresh Self Refresh Entry Self Refresh Exit
H H H H H H H H H H H H H H L
X X X X X X X X X X X X H L H
X X X X X X X X X X X X X X X
V L H L H L H C V X X X X X X
L L L L L L L L L L L H L L H L
L L L H H H H L L H H X L L X H X H X H X X
H H H L L L L L L H H X L L X H X H X H X X
H L L L L H H L L H L X H H X X X X X X X X
Active(3) Active(3) Idle Idle Any Active Any Idle Idle Idle (Self Refresh) Idle/ Active(5) Any (Power Down) Active Active
Power Down Mode Entry
H
L
X
X
X
X
H L
Power Down Mode Exit
L
H
X
X
X
X
H L
Data Write Enable Data Write Disable Notes: 1. 2. 3. 4. 5.
H H
X X
L H
X X
X X
X X
X X
V = Valid X = Don't Care L = Low level H = High level CKEn signal is input level when commands are issued. CKEn-1 signal is input level one clock cycle before the commands are issued. These are state designated by the BS0, BS1 signals. Power Down Mode can not entry in the burst cycle.
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W9451GBDA-6
14. SERIAL PRESENCE DETECT EEPROM
The Serial Presence Detect (SPD) function is implemented by using a 2,408-bit EEPROM component. This nonvolatile storage device contains those data for identifying the module type and various SDRAM organizations and timing parameters. System read operations to the EEPROM device occur using the DIMM SCL(clock) and SDA (data) signals, together with SA(2:0) which provide the EEPROM Device Address.
SPD EEPROM DC Operating Conditions
(Vcc = 2.3V - 3.6V)
PARAMETER/CONDITION Supply Voltage Input High (Logic 1) Voltage, all inputs Input Low (Logic 0) Voltage, all inputs Output Low Voltage, lOUT = 3 mA Input Leakage Current, VIN = GND to VCC Output Leakage Current, VOUT = GND to VCC Power Supply Current SCL Clock Frequency =100 KHz
SYM. VCC VIH VIL VOL ILI ILO ICC
MIN. 2.3 VCC x 0.7 -0.3
MAX. 3.6 VCC +0.5 VCC x 0.3 0.4 2 2 1
UNIT V V V V A A mA
NOTES
IOL = 3 mA
SPD AC Operating Conditions
(Vcc = 2.3V - 3.6V)
PARAMETER SCL Clock Frequency Noise Suppression Time Constant at SCL, SDA Inputs SCL Low to SDA Data Out Valid Time the bus must be free before a new transition can start Start Condition Hold Time Clock Low Period Clock High Period Start Condition Setup Time Data in Hold Time Data in Setup Time SDA and SCL Rise time SDA and SCL Fall Time Stop Condition Setup Time Data Out Hold Time Write Cycle Time
SYM. fSCL fI tAA tBUF tHD:STA tLOW tHIGH tSU:STA tHD:DAT tSU:DAT tR tF tSU:STO tDH tWR
MIN.
0.2 4.7 4.0 4.7 4.0 4.7 0 250
MAX. 100 100 3.5
UNIT KHz nS S S S S S S S nS S nS S nS mS
1 300 4 200 10
Note: The write cycle time (tWR) is the time from a valid stop condition of a write sequence to the end of the internal erase/program cycle. During the write cycle the EEPROM bus interface circuits are disabled, SDA is allowed to remain high the bus level pull-up resistor, and the device does not respond to its slave address.
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Publication Release Date: March 15, 2002 Revision A1
W9451GBDA-6
15. SPD DATA
Byte No. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 FUNCTION DESCRIBED Defines # Bytes Written into Serial Memory at Module Manufacturer Total # Bytes of SPD Memory Device Fundamental Memory Type (FPM, EDO, DRAM..) # Row Addresses on This Assembly # Column Addresses on This Assembly # Module Rows on This Assembly Data Width of This Assembly Data Width Continuation Voltage Interface Standard of This Assembly SDRAM Cycle Time @CAS Latency of 2.5 SDRAM Access Time @CAS Latency of 2.5 DIMM Configuration Type (Non-parity, Parity ECC) Refresh Rate/Type SDRAM Width, Primary DRAM Error Checking SDRAM Data Width Minimum Clock Delay, Back Random Column Addresses Burst Lengths Supported #Bank on Each SDRAM Device CAS# Latencies Supported CS# Latency Write Latency SDRAM Module Attributes FUNCTION SUPPORTED -6 128 bytes 256 bytes (2K-bit) DDR SDRAM 13 10 2 row 64 bits SSTL 2.5V 6 nS +/-0.7 nS Non parity 7.8 S, support self refresh X8 None TCCD = 1 CLK 2, 4, 8 4 banks 2.5 0 CLK 1 CLK Differential Clock, Non-buffered Non-registered & redundant addressing 2.5V+/-10% voltage tolerance, Burst Read, Write, precharge all, auto precharge 7.5 nS +/-0.7 nS 18 nS 12 nS 18 nS 42 nS Each row of 256MB 0.75 nS 0.75 nS 0.45 nS 0.45 nS Initial release revision HEX VALUE -6 80h 08h 07h 0Dh 0Ah 02h 40h 00h 04h 60h 70h 00h 82h 08h 00h 01h 0Eh 04h 08h 01h 02h 20h
22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 - 61 62 63 64 - 128
SDRAM Device Attributes: General SDRAM Cycle Time @ CAS Latency of 2 SDRAM Access Time @CAS Latency of 2 SDRAM Cycle Time @ CAS Latency of 1.5 SDRAM Access time @CAS Latency of 1.5 Precharge to Active Command Period (tRP) Active to Active Command Period (tRRD) Active to Read/Write Command Delay Time (tRCD) Minimum Active to Precharge Period (tRAS) Density of Each Row on Module Command and Address Signal Input Setup Time Command and Address Signal Input Hold Time Data Signal Input Setup Time Data Signal Input Hold Time Superset Information (may be used in future) SPD Data Specification Revision Checksum for Bytes 0 - 62 Unused Storage Locations
00h 75h 70h 00h 00h 48h 30h 48h 2Ah 40h 75h 75h 45h 45h 00h 00h 07h 00h
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W9451GBDA-6
16. LABELING INFORMATION
There is a product description sticker stuck on each module to fully describe the information of the module. The following are examples of the product description sticker. Examples: MODULE P/N W9451GBDA-6 (DDR333/CL2.5 DIMM) EXAMPLE OF STICKER W9451GBDA-6 512MB DDR333/CL2.5 DIMM TAIWAN 126K264896
The content of this product description sticker is described as below:
1.
MODULE PART NUMBER W9451GBDA-6
DIMM Module Part Number Informatoin W94 51 G Winbond Product Line W94: DDR SDRAM BDA -6/-7/-75/-8 Speed Grade -6: DDR333/CL2.5 -7: DDR266/CL2 -75: DDR266/CL2.5 -8: DDR200/CL2 Module Version A: A Version Module Type D: Unbuffered DIMM
Memory Size 51: 512Mbytes DDR SDRAM Type G: 32M x 8 DDR SDRAM Version B: B Version
2. 3. 4. 5. 6.
Total Memory Size: 512 Mbytes Compliant Industry Spec: DDR333/CL2.5,DDR266/CL2, DDR266/CL2.5 or DDR200/CL2 Module Type: DIMM Manufacturing Location: TAIWAN Tracking Number: 926K264896 (The number " 926K264896" is for reference only. It is changed according to assembly date, assembly site, and serial lot number.)
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Publication Release Date: March 15, 2002 Revision A1
W9451GBDA-6
17. PACKAGE DIMENSION
Units:Inches
Front View
5.25 0.157 0.394 1.250 0.098
Rear View
SPD
0.170 Max
SIDE VIEW
0.050 0.004
Tolerances: .005 unless othrerwise specified Component P/N: W942508BH-6/-7/-75/-8 (32M X 8 DDR-SDRAM,TSOP-66)
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0.70
W9451GBDA-6
Headquarters
No. 4, Creation Rd. III, Science-Based Industrial Park, Hsinchu, Taiwan TEL: 886-3-5770066 FAX: 886-3-5665577 http://www.winbond.com.tw/
Winbond Electronics Corporation America
2727 North First Street, San Jose, CA 95134, U.S.A. TEL: 1-408-9436666 FAX: 1-408-5441798
Winbond Electronics (Shanghai) Ltd.
27F, 2299 Yan An W. Rd. Shanghai, 200336 China TEL: 86-21-62365999 FAX: 86-21-62365998
Taipei Office
9F, No.480, Rueiguang Rd., Neihu Chiu, Taipei, 114, Taiwan, R.O.C. TEL: 886-2-8177-7168 FAX: 886-2-8751-3579
Winbond Electronics Corporation Japan
7F Daini-ueno BLDG, 3-7-18 Shinyokohama Kohoku-ku, Yokohama, 222-0033 TEL: 81-45-4781881 FAX: 81-45-4781800
Winbond Electronics (H.K.) Ltd.
Unit 9-15, 22F, Millennium City, No. 378 Kwun Tong Rd., Kowloon, Hong Kong TEL: 852-27513100 FAX: 852-27552064
Please note that all data and specifications are subject to change without notice. All the trade marks of products and companies mentioned in this data sheet belong to their respective owners.
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Publication Release Date: March 15, 2002 Revision A1

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