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Si5330
1 . 8 / 2 . 5 / 3 . 3 V LOW J I T T E R, LOW SKEW C L O C K BUFFER/ L E V E L TRANSLATOR
Features

18 17 16 15 14 13 7 8 9 10 11 12
Supports single-ended or differential input clock signals Generates four differential (LVPECL, LVDS, HCSL) or eight single-ended (CMOS, SSTL, HSTL) outputs Provides signal level translation Differential to single-ended Single-ended to differential Differential to differential Single-ended to single-ended Wide frequency range LVPECL, LVDS: 5 to 710 MHz HCSL: 5 to 250 MHz SSTL, HSTL: 5 to 350 MHz CMOS: 5 to 200 MHz Additive jitter: 150 fs RMS typ

RSVD_GND
CLK0A
CLK0B
VDDO0
20
Small size: 24-lead, 4 x 4 mm QFN
VDD
24
23
22
21
OEB
19
Output-output skew: 100 ps Propagation delay: 2.5 ns typ Single core supply with excellent PSRR: 1.8, 2.5, or 3.3 V Output driver supply voltage independent of core supply: 1.5, 1.8, 2.5, or 3.3 V Loss Of Signal (LOS) indicator allows system clock monitoring Output Enable (OEB) pin allows glitchless control of output clocks Low power: 10 mA typical core current Industrial temperature range: -40 to +85 C
Ordering Information: See page 14.
Pin Assignments
IN1 IN2 IN3
CLK1A CLK1B VDDO1 VDDO2 CLK2A CLK2B
1
Applications
2 3
High Speed Clock Distribution Ethernet Switch/Router SONET / SDH
PCI Express 2.0/3.0 Fibre Channel MSAN/DSLAM/PON Telecom Line Cards
GND GND
RSVD_GND RSVD_GND RSVD_GND
4 5
Functional Block Diagram
VDD VDDO0 CLK0
Si5330
VDDO1 CLK1
Single-ended or Differential
IN VDDO2 CLK2
Single-ended or Differential
VDDO3 LOS OEB Control CLK3
Rev. 0.35 5/10
Copyright (c) 2010 by Silicon Laboratories
RSVD_GND
LOS
VDDO3
VDD
CLK3B
CLK3A
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
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Si5330
Si5330
1. Functional Block Diagrams Based on Orderable Part Number*
1:4 Differential to Differential Buffer
Si5330A/B/C
VDDO0 CLK0A CLK0B IN1 IN2 IN3 VDDO1 CLK1A CLK1B VDDO2 CLK2A CLK2B LOS OEB Control VDDO3 CLK3A CLK3B LOS OEB Control IN1 IN2 IN3
1:8 Single-Ended to Single-Ended Buffer
Si5330F
VDDO0 CLK0A CLK0B VDDO1 CLK1A CLK1B VDDO2 CLK2A CLK2B VDDO3 CLK3A CLK3B
1:8 Differential to Single-Ended Buffer
Si5330G/H/J
VDDO0 CLK0A CLK0B IN1 IN2 IN3 VDDO1 CLK1A CLK1B VDDO2 CLK2A CLK2B LOS OEB
1:4 Single-Ended to Differential Buffer
Si5330K/L/M
VDDO0 CLK0A CLK0B IN3 IN1 IN2 VDDO1 CLK1A CLK1B VDDO2 CLK2A CLK2B LOS OEB Control VDDO3 CLK3A CLK3B
Control
VDDO3 CLK3A CLK3B
Figure 1. Si5330 Functional Block Diagrams
*Note: See Table 10 for detailed ordering information.
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Rev. 0.35
Si5330 TABLE O F CONTENTS
Section Page
1. Functional Block Diagrams Based on Orderable Part Number* . . . . . . . . . . . . . . . . . . .2 2. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 3. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 3.1. VDD and VDDO Supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 3.2. Loss Of Signal Indicator (LOS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 3.3. Output Enable (OEB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 3.4. Input Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 3.5. Output Driver Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 3.6. Input and Output Terminations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 4. Ordering the Si5330 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 5. Pin Descriptions--Si5330 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 6. Orderable Part Numbers and Device Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 7. Package Outline: 24-Lead QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 8. Recommended PCB Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Rev. 0.35
3
Si5330
2. Electrical Specifications
Table 1. Recommended Operating Conditions
(VDD = 1.8 V -5% to +10%, 2.5 V 10%, or 3.3 V 10%, TA = -40 to 85C)
Parameter
Ambient Temperature
Symbol
TA
Test Condition
Min
-40 2.97
Typ
25 3.3 2.5 1.8 --
Max
85 3.63 2.75 1.98 3.63
Unit
C V V V V
Core Supply Voltage
VDD
2.25 1.71
Output Buffer Supply Voltage
VDDOn
1.4
Note: All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions. Typical values apply at nominal supply voltages and an operating temperature of 25 C unless otherwise noted.
Table 2. Absolute Maximum Ratings
Parameter
DC Supply Voltage Storage Temperature Range ESD Tolerance ESD Tolerance ESD Tolerance Latch-up Tolerance
Symbol
VDD TSTG
Test Condition
Value
-0.5 to 3.8 -55 to 150
Unit
V C kV V V
HBM (100 pF, 1.5 k) CDM MM
2.5 550 175
JESD78 Compliant
Note: Permanent device damage may occur if the absolute maximum ratings are exceeded. Functional operation should be restricted to the conditions as specified in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
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Si5330
Table 3. DC Characteristics
(VDD = 1.8 V -5% to +10%, 2.5 V 10%, or 3.3 V 10%, TA = -40 to 85C)
Parameter
Core Supply Current
Symbol
IDD
Test Condition
50 MHz refclk LVPECL, 710 MHz LVDS, 710 MHz HCSL, 250 MHz 2 pF load capacitance
Min
-- -- -- -- -- -- -- --
Typ
10 -- -- -- -- -- -- --
Max
-- 30 8 20 19 28 28 19
Unit
mA mA mA mA mA mA mA mA
Output Buffer Supply Current
IDDOx
SSTL, 350 MHz CMOS, 50 MHz 15 pF load capacitance CMOS, 200 MHz 2 pF load capacitance HSTL, 350 MHz
Table 4. Thermal Characteristics
Parameter
Thermal Resistance Junction to Ambient Thermal Resistance Junction to Case
Symbol
JA JC
Test Condition
Still Air Still Air
Value
37 25
Unit
C/W C/W
Table 5. Performance Characteristics
(VDD = 1.8 V -5% to +10%, 2.5 V 10%, or 3.3 V 10%, TA = -40 to 85C)
Parameter
CLKIN Loss of Signal Assert Time CLKIN Loss of Signal De-Assert Time Input-to-Output Propagation Delay Output-Output Skew
Symbol
tLOS tLOS_B tPROP tDSKEW
Test Condition
Min
-- 0.01 --
Typ
2.6 0.2 2.5 --
Max
5 1 -- 100
Unit
s s ns ps
Outputs at same frequency, signal format
--
Rev. 0.35
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Si5330
Table 6. Input and Output Clock Characteristics
(VDD = 1.8 V -5% to +10%, 2.5 V 10%, or 3.3 V 10%, TA = -40 to 85 C) Parameter Symbol Test Condition Min Typ Max Units
Input Clock (AC Coupled Differential Input Clocks on Pin IN1/2) Frequency Differential Voltage Swing Rise/Fall Time Duty Cycle Input Impedance Input Capacitance fIN VPP tR/tF DC RIN CIN 710 MHz input 20%-80% < 1 ns tr/tf 5 0.4 -- -- 10 -- -- -- -- 50 -- 3.5 710 2.4 1.0 -- -- -- MHz VPP ns % k pF
Input Clock (DC-Coupled Single-Ended Input Clock on Pin IN3) Frequency Input Voltage Input Voltage Swing (CMOS Standard) Rise/Fall Time Duty Cycle Input Capacitance Output Clocks (Differential) Frequency fOUT VOC LVPECL Output Voltage VSEPP LVDS Output Voltage (2.5/3.3 V) VOC VSEPP VOC VSEPP VOC HCSL Output Voltage Rise/Fall Time Duty Cycle* Output Clocks (Single-Ended) Frequency fOUT CMOS SSTL, HSTL 5 5 -- -- 200 350 MHz MHz VSEPP tR/tF DC LVPECL, LVDS HCSL common mode peak-to-peak singleended swing common mode peak-to-peak singleended swing common mode peak-to-peak singleended swing common mode peak-to-peak singleended swing 20%-80% CKn < 350 MHz 350 MHz < CLKn < 710 MHz 5 5 -- 0.55 1.125 0.25 0.8 0.25 0.35 0.575 -- 45 40 -- -- VDDO - 1.4 V 0.8 1.2 0.35 0.875 0.35 0.375 0.725 -- -- -- 710 250 -- 0.96 1.275 0.45 0.95 0.45 0.400 0.85 450 55 60 MHz MHz V VPP V VPP V VPP V VPP ps % % tR/tF DC CIN fIN VI 200 MHz, Tr/Tf = 1.3 ns 20%-80% < 2 ns tr/tf CMOS 5 -0.1 0.8 -- -- -- -- -- -- -- 50 2 200 3.63 3.73 4 -- -- MHz Vpp V ns % pF
LVDS Output Voltage (1.8 V)
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Si5330
Table 6. Input and Output Clock Characteristics (Continued)
(VDD = 1.8 V -5% to +10%, 2.5 V 10%, or 3.3 V 10%, TA = -40 to 85 C) Parameter CMOS 20%-80% Rise/Fall Time CMOS 20%-80% Rise/Fall Time CMOS Output Resistance SSTL Output Resistance HSTL Output Resistance CMOS Output Voltage VOH VOL VOH VOL VOH SSTL Output Voltage VOL VOH VOL VOH HSTL Output Voltage Duty Cycle* VOL DC VDDO = 1.4 to 1.6 V 4 mA load 4 mA load SSTL-3 VDDOx = 2.97 to 3.63 V 0.45xVDDO+0.41 -- 0.5xVDDO+0.41 -- 0.5xVDDO+0.34 -- 0.5xVDDO +0.3 -- 45 Symbol tR/tF tR/tF Test Condition 2 pF load 15 pF load Min -- -- -- -- -- VDDO-0.3 Typ 0.45 -- 50 50 50 -- -- -- -- -- -- -- -- -- -- -- 0.5xVDDO- 0.34 -- 0.5xVDDO -0.3 55 0.3 -- 0.45xVDDO -0.41 -- 0.5xVDDO- 0.41 Max 0.85 1.7 -- -- -- Units ns ns V V V V V V V V V V %
SSTL-2 VDDOx = 2.25 to 2.75 V
SSTL-18 VDDOx = 1.71 to 1.98 V
*Note: Input clock has a 50% duty cycle.
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Si5330
Table 7. OEB Input Specifications
Parameter
Input Voltage Low Input Voltage High Input Resistance
Symbol
VIL VIH RIN
Test Condition
Min
-- 0.7 x VDD 20
Typ
-- -- --
Max
0.3 x VDD -- --
Unit
V V k
Table 8. Jitter Specifications
(VDD = 1.8 V -5% to +10%, 2.5 V 10%, or 3.3 V 10%, TA = -40 to 85C)
Parameter
Additive Phase Jitter (12 kHz-20 MHz) Additive Phase Jitter (50 kHz-80 MHz)
Symbol
tRPHASE
Test Condition
0.7 V pk-pk differential input clock at 622.08 MHz with 70 ps rise/fall time 0.7 V pk-pk differential input clock at 622.08 MHz with 70 ps rise/fall time
Min
--
Typ
0.150
Max
--
Unit
ps RMS
tRPHASEWB
--
0.225
--
ps RMS
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Rev. 0.35
Si5330
3. Functional Description
The Si5330 is a low-jitter, low-skew fanout buffer optimized for high-performance PCB clock distribution applications. The device produces four differential or eight single-ended, low-jitter output clocks from a single input clock. The input can accept either a single-ended or a differential clock allowing the device to function as a clock level translator.
3.3. Output Enable (OEB)
The output enable (OEB) pin allows disabling or enabling of the outputs clocks (CLK0-CLK3). The output enable is logically controlled to ensure that no glitches or runt pulses are generated at the output as shown in Figure 3.
IN
3.1. VDD and VDDO Supplies
The core VDD and output VDDO supplies have separate and independent supply pins allowing the core supply to operate at a different voltage than the I/O voltage levels. The VDD supply powers the core functions of the device, which operates from 1.8, 2.5, or 3.3 V. Using a lower supply voltage helps minimize the device's power consumption. The VDDO supply pins are used to set the output signal levels and must be set at a voltage level compatible with the output signal format.
CLKn Disable OEB Enable Disable Enable
Figure 3. OEB Glitchless Operation
All outputs are enabled when the OEB pin is connected to ground or below the VIL voltage for this pin. Connecting the OEB pin to VDD or above the VIH level will disable the outputs. Both VIL and VIH are specified in Table 7. All outputs are forced to a logic "low" when disabled. The OEB pin is 3.3 V tolerant.
3.2. Loss Of Signal Indicator (LOS)
The input is monitored for a valid clock signal using an LOS circuit that monitors input clock edges and declares an LOS condition when signal edges are not detected over a 5 s observation period. The LOS pin is asserted "low" when valid clock is present. A "high" level on the LOS pin indicates a loss of signal (LOS). The LOS pin must be pulled to VDD as shown in Figure 2.
VDDO0 CLK0
3.4. Input Signals
The Si5330 can accept single-ended and differential input clocks. See "AN408: Termination Options for AnyFrequency, Any-Output Clock Generators and Clock Buffers--Si5338, Si5334, Si5330" for details on connecting a wide variety of signals to the Si5330 inputs.
3.5. Output Driver Formats
The Si5330 supports single-ended output formats of CMOS, SSTL, and HSTL and differential formats of LVDS, LVPECL, and HCSL. It is normally required that the LVDS driver be dc-coupled to the 100 termination at the receiver end. If your application requires an accoupled 100 load, contact the applications team for advice. See AN408 for additional information on the terminations for these driver types.
Si5330
VDDO1 CLK1 IN VDDO2 CLK2
VDD 1k
LOS 0 Valid Clock 1 No Clock Control
3.6. Input and Output Terminations
See AN408 for detailed information.
VDDO3 CLK3
4. Ordering the Si5330
The Si5330 can be ordered to meet the requirements of the most commonly-used input and output signal types, such as CMOS, SSTL, HSTL, LVPECL, LVDS, and HSCL. See Figure 1, "Si5330 Functional Block Diagrams," on page 2 and Table 10, "Order Numbers and Device Functionality," on page 14 for specific ordering information.
Figure 2. LOS Indicator with External Pull-Up
Rev. 0.35
9
Si5330
5. Pin Descriptions--Si5330
RSVD_GND
CLK0A
CLK0B
VDDO0
20
VDD
24
23
22
21
OEB
19 18 17 16 15 14 13
IN1 IN2 IN3 RSVD_GND RSVD_GND RSVD_GND
CLK1A CLK1B VDDO1 VDDO2 CLK2A CLK2B
Note: Center pad must be tied to GND for normal operation.
Table 9. Si5330 Pin Descriptions
Pin #
1
Pin Name
IN1 IN2
I/O
I I
Signal Type
Multi Multi
RSVD_GND
LOS
VDDO3
VDD
CLK3B
CLK3A
1 2 3
GND GND
4 5 6 7 8 9 10 11 12
Description Si5330A/B/C/G/H/J Differential Input Devices.
These pins are used as the differential clock input. IN1 is the positive input; IN2 is the negative input. Refer to "AN408: Termination Options for Any-Frequency, AnyOutput Clock Generators and Clock Buffers--Si5338, Si5334, Si5330" for interfacing and termination details.
2
Si5330F/K/L/M Single-Ended Input Devices. These pins are not used. Leave IN1 unconnected and IN2 connected to ground. Si5330F/K/L/M Single-Ended Devices.
This is the single-ended clock input. Refer to AN408 for interfacing and termination details.
3
IN3
I
Multi
Si5330A/B/C/G/H/J Differential Input Devices. This pin is not used. Connect to ground.
4 5 6 RSVD_GND RSVD_GND RSVD_GND
Ground. Must be connected to system ground. Ground. Must be connected to system ground. Ground. Must be connected to system ground.
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Si5330
Table 9. Si5330 Pin Descriptions (Continued)
Pin # Pin Name I/O Signal Type Description Core Supply Voltage. The device operates from a 1.8, 2.5, or 3.3 V supply. A 0.1 F bypass capacitor should be located very close to this pin. Loss of Signal Indicator. 0 = CLKIN present. 1 = Loss of signal (LOS). This pin requires an external 1 kpull-up resistor. Si5330A/B/C/K/L/M Differential Output Devices. This is the negative side of the differential CLK3 output. Refer to AN408 for interfacing and termination details. Leave unconnected when not in use.
9 CLK3B O Multi
7
VDD
VDD
Supply
8
LOS
O
Open Drain
Si5330F/G/H/J Single-Ended Output Devices. This is one of the single-ended CLK3 outputs. Both CLK3A and CLK3B single-ended outputs are in phase. Refer to AN408 for interfacing and termination details. Leave unconnected when not is use. Si5330A/B/C/K/L/M Differential Devices. This is the positive side of the differential CLK3 output. Refer to AN408 for interfacing and termination details. Leave unconnected when not in use.
10
CLK3A
O
Multi
Si5330F/G/H/J Single-Ended Devices. This is one of the single-ended CLK3 outputs. Both CLK3A and CLK3B single-ended outputs are in phase. Refer to AN408 for interfacing and termination details. Leave unconnected when not is use. Output Clock Supply Voltage. Supply voltage for CLK3A/B. Use a 0.1 F bypass cap as close as possible to this pin. If CLK3 is not used, this pin must be tied to VDD (pin 7 and/or pin 24). Ground. Must be connected to system ground. Si5330A/B/C/K/L/M Differential Output Devices. This is the negative side of the differential CLK2 output. Refer to AN408 for interfacing and termination details. Leave unconnected when not in use.
11
VDDO3
VDD
Supply
12
RSVD_GND
13
CLK2B
O
Multi
Si5330F/G/H/J Single-Ended Output Devices. This is one of the single-ended CLK2 outputs. Both CLK2A and CLK2B single-ended outputs are in phase. Refer to AN408 for interfacing and termination details. Leave unconnected when not is use.
Rev. 0.35
11
Si5330
Table 9. Si5330 Pin Descriptions (Continued)
Pin # Pin Name I/O Signal Type Description Si5330A/B/C/K/L/M Differential Devices. This is the positive side of the differential CLK2 output. Refer to AN408 for interfacing and termination details. Leave unconnected when not in use.
14 CLK2A O Multi
Si5330F/G/H/J Single-Ended Devices. This is one of the single-ended CLK2 outputs. Both CLK2A and CLK2B single-ended outputs are in phase. Refer to AN408 for interfacing and termination details. Leave unconnected when not is use. Output Clock Supply Voltage. Supply voltage for CLK2A/B. Use a 0.1 F bypass cap as close as possible to this pin. If CLK2 is not used, this pin must be tied to VDD (pin 7 and/or pin 24). Output Clock Supply Voltage. Supply voltage for CLK1A,B. Use a 0.1 F bypass cap as close as possible to this pin. If CLK1 is not used, this pin must be tied to VDD (pin 7 and/or pin 24). Si5330A/B/C/K/L/M Differential Output Devices. This is the negative side of the differential CLK1 output. Refer to AN408 for interfacing and termination details. Leave unconnected when not in use.
15
VDDO2
VDD
Supply
16
VDDO1
VDD
Supply
17
CLK1B
O
Multi
Si5330F/G/H/J Single-Ended Output Devices. This is one of the single-ended CLK1 outputs. Both CLK1A and CLK1B single-ended outputs are in phase. Refer to AN408 for interfacing and termination details. Leave unconnected when not is use. Si5330A/B/C/K/L/M Differential Devices. This is the positive side of the differential CLK1 output. Refer to AN408 for interfacing and termination details. Leave unconnected when not in use.
18
CLK1A
O
Multi
Si5330F/G/H/J Single-Ended Devices. This is one of the single-ended CLK1 outputs. Both CLK1A and CLK1B single-ended outputs are in phase. Refer to AN408 for interfacing and termination details. Leave unconnected when not is use. Output Enable. All outputs are enabled when the OEB pin is connected to ground or below the VIL voltage for this pin. Connecting the OEB pin to VDD or above the VIH level will disable the outputs. Both VIL and VIH are specified in Table 7. All outputs are forced to a logic "low" when disabled. This pin is 3.3 V tolerant.
19
OEB
I
CMOS
12
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Si5330
Table 9. Si5330 Pin Descriptions (Continued)
Pin # Pin Name I/O Signal Type Description Output Clock Supply Voltage. Supply voltage for CLK0A,B. Use a 0.1 F bypass cap as close as possible to this pin. If CLK2 is not used, this pin must be tied to VDD (pin 7 and/or pin 24). Si5330A/B/C/K/L/M Differential Output Devices. This is the negative side of the differential CLK0 output. Refer to AN408 for interfacing and termination details. Leave unconnected when not in use.
21 CLK0B O Multi
20
VDDO0
VDD
Supply
Si5330F/G/H/J Single-ended Output Devices. This is one of the single-ended CLK0 outputs. Both CLK0A and CLK0B single-ended outputs are in phase. Refer to AN408 for interfacing and termination details. Leave unconnected when not is use. Si5330A/B/C/K/L/M Differential Devices. This is the positive side of the differential CLK0 output. Refer to AN408 for interfacing and termination details. Leave unconnected when not in use.
22
CLK0A
O
Multi
Si5330F/G/H/J Single-ended Devices. This is one of the single-ended CLK0 outputs. Both CLK0A and CLK0B single-ended outputs are in phase. Refer to AN408 for interfacing and termination details. Leave unconnected when not is use. Ground. Must be connected to system ground.
23
RSVD_GND
24
VDD
VDD
Supply
Core Supply Voltage. The device operates from a 1.8, 2.5, or 3.3 V supply. A 0.1 F bypass capacitor should be located very close to this pin. Ground Pad. This is main ground connection for this device. It is located at the bottom center of the package. Use as many vias as possible to connect this pad to the main ground plane.
GND PAD
GND
GND
Supply
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Si5330
6. Orderable Part Numbers and Device Functionality
Table 10. Order Numbers and Device Functionality
Part Number Input Signal Format Output Signal Format Number of Outputs Frequency Range
LVPECL Buffers
SI5330A-A00200-GM Si5330A-A00202-GM Differential Differential 3.3 V LVPECL 2.5 V LVPECL 4 4 5 to 710 MHz 5 to 710 MHz
LVDS Buffers
Si5330B-A00204-GM Si5330B-A00205-GM Si5330B-A00206-GM Differential Differential Differential 3.3 V LVDS 2.5 V LVDS 1.8 V LVDS 4 4 4 5 to 710 MHz 5 to 710 MHz 5 to 710 MHz
HCSL Buffers
Si5330C-A00207-GM Si5330C-A00208-GM Si5330C-A00209-GM Differential Differential Differential 3.3 V HCSL 2.5 V HCSL 1.8 V HCSL 4 4 4 5 to 250 MHz 5 to 250 MHz 5 to 250 MHz
CMOS Buffers
Si5330F-A00214-GM Si5330F-A00215-GM Si5330F-A00216-GM Single-Ended Single-Ended Single-Ended 3.3 V CMOS 2.5 V CMOS 1.8 V CMOS 8 8 8 5 to 200 MHz 5 to 200 MHz 5 to 200 MHz
CMOS Buffers (Differential Input)
Si5330G-A00217-GM Si5330G-A00218-GM Si5330G-A00219-GM Differential Differential Differential 3.3 V CMOS 2.5 V CMOS 1.8 V CMOS 8 8 8 5 to 200 MHz 5 to 200 MHz 5 to 200 MHz
SSTL Buffers (Differential Input)
Si5330H-A00220-GM Si5330H-A00221-GM Si5330H-A00222-GM Differential Differential Differential 3.3 V SSTL 2.5 V SSTL 1.8 V SSTL 8 8 8 5 to 350 MHz 5 to 350 MHz 5 to 350 MHz
HSTL Buffers (Differential Input)
Si5330J-A00223-GM Differential 1.5 V HSTL 8 5 to 350 MHz
LVPECL Buffers (Single-Ended Input)
Si5330K-A00224-GM Si5330K-A00226-GM Single-Ended Single-Ended 3.3 V LVPECL 2.5 V LVPECL 4 4 5 to 350 MHz 5 to 350 MHz
Note: Custom configurations with mixed output types are also available. Please contact the factory for ordering details.
14
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Si5330
Table 10. Order Numbers and Device Functionality (Continued)
Part Number Input Signal Format Output Signal Format Number of Outputs Frequency Range
LVDS Buffers (Single-Ended Input)
Si5330L-A00228-GM Si5330L-A00229-GM Si5330L-A00230-GM Single-Ended Single-Ended Single-Ended 3.3 V LVDS 2.5 V LVDS 1.8 V LVDS 4 4 4 5 to 350 MHz 5 to 350 MHz 5 to 350 MHz
HCSL Buffers (Single-Ended Input)
Si5330M-A00231-GM Si5330M-A00232-GM Si5330M-A00233-GM Single-Ended Single-Ended Single-Ended 3.3 V HCSL 2.5 V HCSL 1.8 V HCSL 4 4 4 5 to 250 MHz 5 to 250 MHz 5 to 250 MHz
Note: Custom configurations with mixed output types are also available. Please contact the factory for ordering details.
Rev. 0.35
15
Si5330
7. Package Outline: 24-Lead QFN
Figure 4. 24-Lead Quad Flat No-lead (QFN) Table 11. Package Dimensions
Dimension
A A1 b D D2 e E E2 L aaa bbb ccc ddd eee
Notes:
Min
0.80 0.00 0.18 2.35
Nom
0.85 0.02 0.25 4.00 BSC. 2.50 0.50 BSC. 4.00 BSC.
Max
0.90 0.05 0.30 2.65
2.35 0.30
2.50 0.40 0.10 0.10 0.08 0.10 0.05
2.65 0.50
1. 2. 3. 4.
All dimensions shown are in millimeters (mm) unless otherwise noted. Dimensioning and Tolerancing per ANSI Y14.5M-1994. This drawing conforms to the JEDEC Outline MO-220, variation VGGD-8. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components.
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8. Recommended PCB Layout
Table 12. PCB Land Pattern
Dimension
P1 P2 X1 Y1 C1 C2 E
Notes:
Min
2.50 2.50 0.20 0.75
Nom
2.55 2.55 0.25 0.80 3.90 3.90 0.50
Max
2.60 2.60 0.30 0.85
General
1. 2. 3. 4. All dimensions shown are in millimeters (mm) unless otherwise noted. Dimensioning and Tolerancing per ANSI Y14.5M-1994 specification. This Land Pattern Design is based on the IPC-7351 guidelines. Connect the center ground pad to a ground plane with no less than five vias to a ground plane that is no more than 20 mils below it. Via drill size should be no smaller than 10 mils. A longer distance to the ground plane is allowed if more vias are used to keep the inductance from increasing.
Solder Mask Design
5. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is to be 60 m minimum, all the way around the pad.
Stencil Design
6. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release. 7. The stencil thickness should be 0.125 mm (5 mils). 8. The ratio of stencil aperture to land pad size should be 1:1 for all perimeter pins. 9. A 2x2 array of 1.0 mm square openings on 1.25 mm pitch should be used for the center ground pad.
Card Assembly
10. A No-Clean, Type-3 solder paste is recommended. 11. The recommended card reflow profile is per the JEDEC/IPC J-STD-020C specification for Small Body Components.
Rev. 0.35
17
Si5330
DOCUMENT CHANGE LIST
Revision 0.1 to Revision 0.2
Clarified documentation to reflect that Pin 19 is OEB (OE Enable Low). Updated Table 4, "Jitter Specifications" on page 7.
Revision 0.2 to Revision 0.3

Major editorial updates to improve clarity. Updated "Additive Jitter" Specification Table. Updated "Core Supply Current" Specification in Table 3. Removed the Low-Power LVPECL output options from the ordering table in section 6. Removed D/E ordering options.
Revision 0.3 to Revision 0.35
Typo of 150 ps on front page changed to 150 fs. Updated PCB layout notes. Added no ac coupling for LVDS outputs. Changed input rise/fall time spec to 2 ns.
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Si5330
NOTES:
Rev. 0.35
19
Si5330
CONTACT INFORMATION
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The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features or parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Silicon Laboratories assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. Silicon Laboratories products are not designed, intended, or authorized for use in applications intended to support or sustain life, or for any other application in which the failure of the Silicon Laboratories product could create a situation where personal injury or death may occur. Should Buyer purchase or use Silicon Laboratories products for any such unintended or unauthorized application, Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and damages. Silicon Laboratories and Silicon Labs are trademarks of Silicon Laboratories Inc. Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders.
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Rev. 0.35

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