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USB3320
Highly Integrated Full Featured Hi-Speed USB 2.0 ULPI Transceiver
PRODUCT FEATURES
Integrated ESD protection circuits -- Up to 15kV IEC Air Discharge without external devices Over-Voltage Protection circuit (OVP) protects the VBUS pin from continuous DC voltages up to 30V Integrated USB Switch -- No degradation of Hi-Speed electrical characteristics -- Allows single USB port of connection by providing switching function for: - Battery charging - Stereo and mono/mic audio - USB Full-Speed/Low-Speed data flexPWR(R) Technology -- Low current design ideal for battery powered applications -- "Sleep" mode tri-states all ULPI pins and places the part in a low current state -- 1.8V to 3.3V IO Voltage (10%) Integrated battery to 3.3V regulator -- 2.2uF bypass capacitor -- 100mV dropout voltage "Wrapper-less" design for optimal timing performance and design ease -- Low Latency Hi-Speed Receiver (43 Hi-Speed clocks Max) allows use of legacy UTMI Links with a ULPI bridge Selectable Reference Clock Frequency -- Frequencies: 12, 13, 19.2, 24, 26, 27, 38.4, 52 or 60MHz - pin selectable External Reference Clock operation available -- ULPI Input Clock Mode (60MHz sourced by Link) -- 0 to 3.6V input drive tolerant -- Able to accept "noisy" clock sources as reference to internal, low-jitter PLL Internal Oscillator operation available -- This mode requires external Quartz Crystal or Ceramic Resonator Smart detection circuits allow identification of USB charger, headset, or data cable insertion Datasheet Includes full support for the optional On-The-Go (OTG) protocol detailed in the On-The-Go Supplement Revision 2.0 specification Supports Headset Audio Mode Supports the OTG Host Negotiation Protocol (HNP) and Session Request Protocol (SRP) UART mode for non-USB serial data transfers Internal 5V cable short-circuit protection of ID, DP and DM lines to VBUS or ground Industrial Operating Temperature -40C to +85C 32 pin, QFN Lead-free RoHS Compliant Package (5 x 5 x 0.90 mm height)
Applications
The USB3320 is targeted for any application where a HiSpeed USB connection is desired and when board space, power, and interface pins must be minimized. The USB3320 is well suited for: Networking Audio Video Medical Industrial Computers Printers Repeaters Communication
SMSC USB3320
DATASHEET
Revision 1.0 (07-14-09)
Highly Integrated Full Featured Hi-Speed USB 2.0 ULPI Transceiver
Datasheet
ORDER NUMBER(S):
USB3320C-EZK for 32 pin, QFN Lead-Free RoHS Compliant Package USB3320C-EZK-TR for 32 pin, QFN Lead-Free RoHS Compliant Package (tape and reel) Reel size is 4000 pieces.
80 ARKAY DRIVE, HAUPPAUGE, NY 11788 (631) 435-6000, FAX (631) 273-3123 Copyright (c) 2009 SMSC or its subsidiaries. All rights reserved. Circuit diagrams and other information relating to SMSC products are included as a means of illustrating typical applications. Consequently, complete information sufficient for construction purposes is not necessarily given. Although the information has been checked and is believed to be accurate, no responsibility is assumed for inaccuracies. SMSC reserves the right to make changes to specifications and product descriptions at any time without notice. Contact your local SMSC sales office to obtain the latest specifications before placing your product order. The provision of this information does not convey to the purchaser of the described semiconductor devices any licenses under any patent rights or other intellectual property rights of SMSC or others. All sales are expressly conditional on your agreement to the terms and conditions of the most recently dated version of SMSC's standard Terms of Sale Agreement dated before the date of your order (the "Terms of Sale Agreement"). The product may contain design defects or errors known as anomalies which may cause the product's functions to deviate from published specifications. Anomaly sheets are available upon request. SMSC products are not designed, intended, authorized or warranted for use in any life support or other application where product failure could cause or contribute to personal injury or severe property damage. Any and all such uses without prior written approval of an Officer of SMSC and further testing and/or modification will be fully at the risk of the customer. Copies of this document or other SMSC literature, as well as the Terms of Sale Agreement, may be obtained by visiting SMSC's website at http://www.smsc.com. SMSC is a registered trademark of Standard Microsystems Corporation ("SMSC"). Product names and company names are the trademarks of their respective holders. SMSC DISCLAIMS AND EXCLUDES ANY AND ALL WARRANTIES, INCLUDING WITHOUT LIMITATION ANY AND ALL IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, TITLE, AND AGAINST INFRINGEMENT AND THE LIKE, AND ANY AND ALL WARRANTIES ARISING FROM ANY COURSE OF DEALING OR USAGE OF TRADE. IN NO EVENT SHALL SMSC BE LIABLE FOR ANY DIRECT, INCIDENTAL, INDIRECT, SPECIAL, PUNITIVE, OR CONSEQUENTIAL DAMAGES; OR FOR LOST DATA, PROFITS, SAVINGS OR REVENUES OF ANY KIND; REGARDLESS OF THE FORM OF ACTION, WHETHER BASED ON CONTRACT; TORT; NEGLIGENCE OF SMSC OR OTHERS; STRICT LIABILITY; BREACH OF WARRANTY; OR OTHERWISE; WHETHER OR NOT ANY REMEDY OF BUYER IS HELD TO HAVE FAILED OF ITS ESSENTIAL PURPOSE, AND WHETHER OR NOT SMSC HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
Revision 1.0 (07-14-09)
DATASHEET
2
SMSC USB3320
Highly Integrated Full Featured Hi-Speed USB 2.0 ULPI Transceiver
Datasheet
0.1
Reference Documents
Universal Serial Bus Specification, Revision 2.0, April 27, 2000 On-The-Go Supplement to the USB 2.0 Specification, Revision 2.0, May 8, 2009 USB Specification Revision 2.0 "Pull-up/pull-down resistors" ECN (27% Resistor ECN) USB 2.0 Transceiver Macrocell Interface (UTMI) Specification, Version 1.02, May 27, 2000 UTMI+ Specification, Revision 1.0, February 25, 2004 UTMI+ Low Pin Interface (ULPI) Specification, Revision 1.1, October 20th, 2004 Technical Requirements and Test Methods of Charger and Interface for Mobile Telecommunication Terminal Equipment (Chinese Charger Specification Approval Draft 11/29/2006)
SMSC USB3320
DATASHEET
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Revision 1.0 (07-14-09)
Highly Integrated Full Featured Hi-Speed USB 2.0 ULPI Transceiver
Datasheet
Table of Contents
0.1 Reference Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Chapter 1 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Chapter 2 USB3320 Pin Locations and Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.1 USB3320 Pin Locations and Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.1.1 Package Diagram with Pin Locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.1.2 Pin Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Chapter 3 Limiting Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.1 3.2 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Recommended Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Chapter 4 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8 4.9 4.10 Operating Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clock Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ULPI Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Digital IO Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DC Characteristics: Analog I/O Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Dynamic Characteristics: Analog I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . OTG Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . USB Audio Switch Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Regulator Output Voltages and Capacitor Requirement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Piezoelectric Resonator for Internal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 16 16 17 17 19 20 20 21 22
Chapter 5 Architecture Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.1 5.2 5.3 5.4 ULPI Digital Operation and Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . USB 2.0 Hi-Speed Transceiver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.2.1 USB Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.2.2 Termination Resistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bias Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Integrated Low Jitter PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.4.1 REFCLK Mode Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.4.2 REFCLK Amplitude . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.4.3 REFCLK Jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.4.4 REFCLK Enable/Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Internal Regulators and POR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5.1 Integrated Low Dropout Regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5.2 Power On Reset (POR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5.3 Recommended Power Supply Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5.4 Start-Up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . USB On-The-Go (OTG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.6.1 ID Resistor Detection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.6.2 VBUS Monitor and Pulsing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.6.3 Driving External VBUS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . USB UART Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . USB Charger Detection Support. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . USB Audio Support. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reference Frequency Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 23 23 24 26 26 26 28 29 29 29 29 31 31 32 33 33 36 39 39 39 40 41
5.5
5.6
5.7 5.8 5.9 5.10
Chapter 6 ULPI Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
6.1 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
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SMSC USB3320
Highly Integrated Full Featured Hi-Speed USB 2.0 ULPI Transceiver
Datasheet
6.2
6.3
6.4 6.5 6.6 6.7
6.1.1 ULPI Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.1.2 ULPI Interface Timing in Synchronous Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ULPI Register Access. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.2.1 ULPI Register Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.2.2 ULPI Register Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.2.3 ULPI RXCMD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.2.4 USB3320 Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.2.5 USB Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Low Power Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.3.1 Entering Low Power/Suspend Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.3.2 Exiting Low Power Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.3.3 Interface Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.3.4 Minimizing Current in Low Power Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Full Speed/Low Speed Serial Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Carkit Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.5.1 USB UART Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.5.2 USB Audio Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RID Converter Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Headset Audio Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
43 44 44 45 47 48 49 51 52 53 54 54 55 56 57 58 59 59 59
Chapter 7 ULPI Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
7.1 ULPI Register Array . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.1.1 ULPI Register Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.1.2 Carkit Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.1.3 Vendor Register Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 62 67 70
Chapter 8 Application Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
8.1 8.2 8.3 Application Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reference Designs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ESD Performance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.3.1 Human Body Model (HBM) Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.3.2 EN/IEC 61000-4-2 Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.3.3 Air Discharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.3.4 Contact Discharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 76 76 77 77 77 77
Chapter 9 Package Outline, Tape & Reel Drawings, Package Marking . . . . . . . . . . . . . . 78 Chapter 10 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
SMSC USB3320
DATASHEET
5
Revision 1.0 (07-14-09)
Highly Integrated Full Featured Hi-Speed USB 2.0 ULPI Transceiver
Datasheet
List of Figures
Figure 1.1 Figure 2.1 Figure 5.1 Figure 5.2 Figure 5.3 Figure 5.4 Figure 5.5 Figure 5.6 Figure 5.7 Figure 5.8 Figure 5.9 Figure 5.10 Figure 5.11 Figure 5.12 Figure 6.1 Figure 6.2 Figure 6.3 Figure 6.4 Figure 6.5 Figure 6.6 Figure 6.7 Figure 6.8 Figure 6.9 Figure 6.10 Figure 8.1 Figure 8.2 Figure 8.3 Figure 9.1 Figure 9.2 Figure 9.3 Figure 9.4 Figure 9.5 USB3320 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 USB3320 Pin Locations - Top View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 USB3320 Internal Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Configuring the USB332X for ULPI Input Clock Mode (60 MHz) . . . . . . . . . . . . . . . . . . . . . . 27 Configuring the USB332X for ULPI Output Clock Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 ULPI Output Clock Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Example of Circuit Used to Shift a Reference Clock Common-mode Voltage Level . . . . . . . 28 Powering the USB3320 from a Battery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Powering the USB3320 from a 3.3V Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Powering the USB3320 from VBUS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 ULPI Start-up Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 USB3320 ID Resistor Detection Circuitry. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 USB3320 OTG VBUS Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 USB3320 Drives Control Signal (CPEN) to External Vbus Switch. . . . . . . . . . . . . . . . . . . . . 39 ULPI Digital Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 ULPI Single Data Rate Timing Diagram in Synchronous Mode. . . . . . . . . . . . . . . . . . . . . . . 44 ULPI Register Write in Synchronous Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 ULPI Extended Register Write in Synchronous Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 ULPI Register Read in Synchronous Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 ULPI Extended Register Read in Synchronous Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 ULPI Transmit in Synchronous Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 ULPI Receive in Synchronous Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Entering Low Power Mode from Synchronous Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Exiting Low Power Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 USB3320 Application Diagram (Device, ULPI Output Clock mode, 24MHz) . . . . . . . . . . . . . 74 USB3320 Application Diagram (Device, ULPI Input Clock mode, 60MHz) . . . . . . . . . . . . . . 75 USB3320 Application Diagram (Host or OTG, ULPI Output Clock Mode, 24MHz) . . . . . . . . 76 USB3320 32 Pin QFN Package Outline, 5 x 5 x 0.9 mm Body (Lead-Free) . . . . . . . . . . . . . 78 QFN, 5x5 Taping Dimensions and Part Orientation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Reel Dimensions for 12mm Carrier Tape. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Tape Length and Part Quantity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 Package Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
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Highly Integrated Full Featured Hi-Speed USB 2.0 ULPI Transceiver
Datasheet
List of Tables
Table 2.1 USB3320 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 3.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 3.2 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 4.1 Electrical Characteristics: Operating Current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 4.2 ULPI Clock Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 4.3 ULPI Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 4.4 Digital IO Characteristics: RESETB, CLKOUT, STP, DIR, NXT, DATA[7:0] & REFCLK Pins. Table 4.5 DC Characteristics: Analog I/O Pins (DP/DM). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 4.6 Dynamic Characteristics: Analog I/O Pins (DP/DM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 4.7 OTG Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 4.8 USB Audio Switch Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 4.9 Regulator Output Voltages and Capacitor Requirement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 4.10 ESD and LATCH-UP Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 4.11 USB3320 Quartz Crystal Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 4.12 USB3320 Ceramic Resonator Part Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 5.1 DP/DM Termination vs. Signaling Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 5.2 REFCLK Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 5.3 Operating Mode vs. Power Supply Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 5.4 Valid Values of ID Resistance to Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 5.5 IdGnd and IdFloat vs. ID Resistance to Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 5.6 External VBUS Indicator Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 5.7 Required RVBUS Resistor Value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 5.8 USB Weak Pull-up Enable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 5.9 USB Audio Switch Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 5.10 Configuration to Select Reference Clock Frequency. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 6.1 ULPI Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 6.2 ULPI TXD CMD Byte Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 6.3 ULPI RX CMD Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 6.4 Interface Signal Mapping During Low Power Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 6.5 Pin Definitions in 3 Pin Serial Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 6.6 Pin Definitions in 6 Pin Serial Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 6.7 ULPI Register Programming Example to Enter UART Mode . . . . . . . . . . . . . . . . . . . . . . . . . Table 6.8 Pin Definitions in Carkit Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 6.9 ULPI Register Programming Example to Enter Audio Mode . . . . . . . . . . . . . . . . . . . . . . . . . . Table 6.10 Pin Definitions in Headset Audio Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 7.1 ULPI Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 8.1 Component Values in Application Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 8.2 Capacitance Values at VBUS of USB Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 9.1 32 Terminal QFN Package Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 10.1 Customer Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 14 14 15 16 16 17 17 19 20 20 21 21 22 22 24 26 32 35 35 37 38 40 40 41 43 45 49 53 56 57 58 58 59 60 61 73 73 78 82
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Highly Integrated Full Featured Hi-Speed USB 2.0 ULPI Transceiver
Datasheet
Chapter 1 General Description
The SMSC USB3320 is a Hi-Speed USB 2.0 Transceiver that provides a configurable physical layer (PHY) solution and is an excellent match for a wide variety of products. Both commercial and industrial temperature applications are supported. The frequency of the reference clock is user selectable. The USB3320 includes an internal oscillator that may be used with either a quartz crystal or a ceramic resonator. Alternatively, the crystal input can be driven by an external clock oscillator. Another option is the use of a 60MHz external clock when using the ULPI Input Clock mode. Several advanced features make the USB3320 the transceiver of choice by reducing both electrical bill of material (eBOM) part count and printed circuit board (PCB) area. Outstanding ESD robustness eliminates the need for external ESD protection devices in typical applications. The internal OverVoltage Protection circuit (OVP) protects the USB3320 from voltages up to 30V. By using a reference clock from the Link, the USB3320 removes the cost of a dedicated crystal reference from the design. And the integrated USB switch enables unique product features with a single USB port of connection. The USB3320 meets all of the electrical requirements to be used as a Hi-Speed USB Host, Device, or an On-the-Go (OTG) transceiver. In addition to the supporting USB signaling, the USB3320 also provides USB UART mode and USB Audio mode. USB3320 uses the industry standard UTMI+ Low Pin Interface (ULPI) to connect the USB Transceiver to the Link. ULPI uses a method of in-band signaling and status byte transfers between the Link and transceiver to facilitate a USB session with only 12 pins. The USB3320 uses SMSC's "wrapper-less" technology to implement the ULPI interface. This "wrapperless" technology allows the transceiver to achieve a low latency transmit and receive time. SMSC's low latency transceiver allows an existing UTMI Link to be reused by adding a UTMI to ULPI bridge. By adding a bridge to the ASIC the existing and proven UTMI Link IP can be reused.
REFCLK XO CPEN
REFSEL[2:0]
ESD Protection
VBUS ID
OTG
Crystal Oscillator and Low Jitter Integrated PLL
BIAS Integrated Power Management
RBIAS RESETB VBAT VDD33 VDD18 VDDIO
DP DM
Hi-Speed USB Transceiver
USB DP/DM Switch
ULPI Registers and State Machine
ULPI Interface
STP NXT DIR CLKOUT
SPK_L
SPK_R
DATA[7:0]
Figure 1.1 USB3320 Block Diagram
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Highly Integrated Full Featured Hi-Speed USB 2.0 ULPI Transceiver
Datasheet
The USB3320 includes an integrated 3.3V Low Drop Out (LDO) regulator that may optionally be used to generate 3.3V from power applied at the VBAT pin. The voltage on the VBAT pin can range from 3.1 to 5.5V. The regulator dropout voltage is less than 100mV which allows the transceiver to continue USB signaling when the voltage on VBAT drops to 3.1V. The USB transceiver will continue to operate at lower voltages, although some parameters may be outside the limits of the USB specifications. If the user would like to provide a 3.3V supply to the USB3320, the VBAT and VDD33 pins should be connected together as described in Section 5.5.1. The USB3320 also includes integrated pull-up resistors that can be used for detecting the attachment of a USB Charger. By sensing the attachment to a USB Charger, a product using the USB3320 can charge its battery at more than the 500mA allowed when charging from a USB Host. Please see SMSC Application Note AN 19.7 - Battery Charging Using SMSC USB Transceivers for more information on battery charging. In USB UART mode, the USB3320 DP and DM pins are redefined to enable pass-through of asynchronous serial data. The USB3320 can only enter UART mode when the user programs the part into this mode, as described in Section 6.5.1. In USB audio mode, a switch connects the DP pin to the SPK_R pin, and another switch connects he DM pin to the SPK_L pin. These switches are shown in the lower left-hand corner of Figure 5.1. The USB3320 can be configured to enter USB audio mode as described in Section 6.5.2. In addition, these switches are on when the RESETB pin of the USB3320 is asserted. The USB audio mode enables audio signalling from a single USB port of connection, and the switches may also be used to connect Full Speed USB from another transceiver onto the USB cable.
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Chapter 2 USB3320 Pin Locations and Definitions
2.1
2.1.1
USB3320 Pin Locations and Descriptions
Package Diagram with Pin Locations
The illustration below is viewed from the top of the package.
RESETB
REFCLK 26
VDD18
VDD18
VDDIO
STP
DIR
32
31
30
29
28
27
CLKOUT NXT DATA0 DATA1 DATA2 DATA3 DATA4 REFSEL0
1 2 3 4 5 6 7 8 10 11 9 GND FLAG 12 13 14 15 16
25 24 23
XO
RBIAS ID VBUS VBAT VDD33 DM DP CPEN
USB3300 Hi-Speed USB Hi-Speed USB2 ULPI PHY ULPI PHY 32 Pin QFN 32 Pin QFN
22 21 20 19 18 17
DATA5
DATA6
REFSEL1
REFSEL2
SPK_L
Figure 2.1 USB3320 Pin Locations - Top View
2.1.2
Pin Definitions
The following table details the pin definitions for the figure above. Table 2.1 USB3320 Pin Description DIRECTION/ TYPE Output, CMOS ACTIVE LEVEL N/A
PIN 1
NAME CLKOUT
SPK_R
N/C
DATA7
DESCRIPTION ULPI Output Clock Mode: 60MHz ULPI clock output. All ULPI signals are driven synchronous to the rising edge of this clock. ULPI Input Clock Mode: This pin is connected to VDDIO to configure 60MHz ULPI Input Clock mode as described in Section 5.4.1. Following POR or hardware reset, the voltage at CLKOUT must not exceed VIH_ED as provided inTable 4.4.
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Highly Integrated Full Featured Hi-Speed USB 2.0 ULPI Transceiver
Datasheet
Table 2.1 USB3320 Pin Description (continued) DIRECTION/ TYPE Output, CMOS ACTIVE LEVEL High
PIN 2
NAME NXT
DESCRIPTION The transceiver asserts NXT to throttle the data. When the Link is sending data to the transceiver, NXT indicates when the current byte has been accepted by the transceiver. The Link places the next byte on the data bus in the following clock cycle. ULPI bi-directional data bus. ULPI bi-directional data bus. ULPI bi-directional data bus. ULPI bi-directional data bus. ULPI bi-directional data bus. This signal, along with REFSEL[1] and REFSEL[2] selects one of the available reference frequencies as defined in Table 5.10. Note: This signal must be tied to VDDIO when in ULPI 60MHz REFCLK IN mode. ULPI bi-directional data bus. ULPI bi-directional data bus. This signal, along with REFSEL[0] and REFSEL[2] selects one of the available reference frequencies as defined in Table 5.10. Note: This signal must be tied to VDDIO when in ULPI 60MHz REFCLK IN mode. This pin must not be connected. ULPI bi-directional data bus. This signal, along with REFSEL[0] and REFSEL[1] selects one of the available reference frequencies as defined in Table 5.10. Note: This signal must be tied to VDDIO when in ULPI 60MHz REFCLK IN mode. USB switch in/out for DM signals USB switch in/out for DP signals
3 4 5 6 7 8
DATA[0] DATA[1] DATA[2] DATA[3] DATA[4] REFSEL[0]
I/O, CMOS I/O, CMOS I/O, CMOS I/O, CMOS I/O, CMOS Input, CMOS
N/A N/A N/A N/A N/A N/A
9 10 11
DATA[5] DATA[6] REFSEL[1]
I/O, CMOS I/O, CMOS Input, CMOS
N/A N/A N/A
12 13 14
N/C DATA[7] REFSEL[2] I/O, CMOS Input, CMOS
N/A N/A N/A
15 16
SPK_L SPK_R
I/O, Analog I/O, Analog
N/A N/A
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Table 2.1 USB3320 Pin Description (continued) DIRECTION/ TYPE Output, CMOS I/O, Analog I/O, Analog Power ACTIVE LEVEL N/A
PIN 17
NAME CPEN
DESCRIPTION External 5V supply enable. Controls the external VBUS power switch. CPEN is low on POR. D+ pin of the USB cable. D- pin of the USB cable. 3.3V Regulator Output. A 2.2uF (<1 ohm ESR) bypass capacitor to ground is required for regulator stability. The bypass capacitor should be placed as close as possible to the USB3320. Regulator input. This pin connects to an external resistor (RVBUS) connected to the VBUS pin of the USB cable. This pin is used for the VBUS comparator inputs and for VBUS pulsing during session request protocol. See Table 5.7, "Required RVBUS Resistor Value". ID pin of the USB cable. For applications not using ID this pin can be connected to VDD33. For an A-Device ID is grounded. For a B-Device ID is floated. Bias Resistor pin. This pin requires an 8.06k (1%) resistor to ground, placed as close as possible to the USB3320. Nominal voltage during ULPI operation is 0.8V. External resonator pin. When using an external clock on REFCLK, this pin should be floated. ULPI Output Clock Mode: Reference frequency as defined in Table 5.10. ULPI Input Clock Mode: 60MHz ULPI clock input. When low, the part is suspended with all ULPI outputs tri-stated. When high, the USB3320 will operate as a normal ULPI device, as described in Section 5.5.2. The state of this pin may be changed asynchronously to the clock signals. When asserted for a minimum of 1 microsecond and then de-asserted, the ULPI registers are reset to their default state and all internal state machines are reset. External 1.8V Supply input pin. This pad needs to be bypassed with a 0.1uF capacitor to ground, placed as close as possible to the USB3320.
18 19 20
DP DM VDD33
N/A N/A N/A
21 22
VBAT VBUS
Power I/O, Analog
N/A N/A
23
ID
Input, Analog
N/A
24
RBIAS
Analog, CMOS
N/A
25
XO
Output, CMOS Input, CMOS
N/A
26
REFCLK
N/A
27
RESETB
Input, CMOS,
Low
28
VDD18
Power
N/A
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Highly Integrated Full Featured Hi-Speed USB 2.0 ULPI Transceiver
Datasheet
Table 2.1 USB3320 Pin Description (continued) DIRECTION/ TYPE Input, CMOS ACTIVE LEVEL High
PIN 29
NAME STP
DESCRIPTION The Link asserts STP for one clock cycle to stop the data stream currently on the bus. If the Link is sending data to the transceiver, STP indicates the last byte of data was on the bus in the previous cycle. External 1.8V Supply input pin. This pad needs to be bypassed with a 0.1uF capacitor to ground, placed as close as possible to the USB3320. Controls the direction of the data bus. When the transceiver has data to transfer to the Link, it drives DIR high to take ownership of the bus. When the transceiver has no data to transfer it drives DIR low and monitors the bus for commands from the Link. External 1.8V to 3.3V ULPI supply input pin. This voltage sets the value of VOH for the ULPI signals. This pad needs to be bypassed with a 0.1uF capacitor to ground, placed as close as possible to the USB3320. Ground.
30
VDD18
Power
N/A
31
DIR
Output, CMOS
N/A
32
VDDIO
Power
N/A
FLAG
GND
Ground
N/A
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Chapter 3 Limiting Values
3.1 Absolute Maximum Ratings
Table 3.1 Absolute Maximum Ratings PARAMETER VBUS, VBAT, ID, CPEN, DP, DM, SPK_L, and SPK_R voltage to GND Maximum VDD18 voltage to Ground Maximum VDDIO voltage to Ground Maximum VDDIO voltage to Ground Maximum VDD33 voltage to Ground Maximum I/O voltage to Ground Operating Temperature Storage Temperature SYMBOL VMAX_5V CONDITIONS Voltage measured at pin. VBUS tolerant to 30V with external RVBUS. MIN -0.5 TYP MAX +6.0 UNITS V
VMAX_18V VMAX_IOV VMAX_IOV VMAX_33V VMAX_IN TMAX_OP TMAX_STG VDD18 = VDD18 VDD18 = 0V
-0.5 -0.5 -0.5 -0.5 -0.5 -40 -55
2.5 4.0 0.7 4.0 VDDIO + 0.7 85 150
V V V V V C C
Note: Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
3.2
Recommended Operating Conditions
Table 3.2 Recommended Operating Conditions PARAMETER SYMBOL VVBAT VDD33 VDDIO VDD18 VI VDDIO VDD18 ( min ) CONDITIONS MIN 3.1 3.0 1.6 1.6 0.0 3.3 1.8-3.3 1.8 TYP MAX 5.5 3.6 3.6 2.0 VDDIO UNITS V V V V V
VBAT to GND VDD33 to GND VDDIO to GND VDD18 to GND Input Voltage on Digital Pins (RESETB, STP, DIR, NXT, DATA[7:0]) Voltage on Analog I/O Pins (DP, DM, ID, CPEN, SPK_L, SPK_R) VBUS to GND Ambient Temperature
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VI(I/O)
0.0
VDD33
V
VVMAX TA
14
0.0 -40
5.5 85
V C
DATASHEET
SMSC USB3320
Highly Integrated Full Featured Hi-Speed USB 2.0 ULPI Transceiver
Datasheet
Chapter 4 Electrical Characteristics
The following conditions are assumed unless otherwise specified: VVBAT = 3.1 to 5.5V; VDD18 = 1.6 to 2.0V; VDDIO = 1.6 to 2.0V; VSS = 0V; TA = -40C to +85C The current for 3.3V circuits is sourced at the VBAT pin, except when using an external 3.3V supply as shown in Figure 5.7.
4.1
Operating Current
Table 4.1 Electrical Characteristics: Operating Current PARAMETER SYMBOL I33AVG(SYNC) I18AVG(SYNC) IIOAVG(SYNC) CONDITIONS Start-up sequence defined in Section 5.5.4 has completed. MIN TYP 7.5 28.0 4.1 Active USB Transfer 11.1 29.4 5.9 Active USB Transfer 6.3 22.5 5.0 5.6 2.4 86 5.6 2.4 58 VVBAT = 4.2V VDD18 = 1.8V VDDIO = 1.8V 18.8 0.7 30 RESETB = 0 VVBAT = 4.2V VDD18 = 1.8V VDDIO = 1.8V 18 0.6 0.1 MAX UNITS mA mA mA mA mA mA mA mA mA mA mA uA mA mA uA uA uA uA uA uA uA
Synchronous Mode Current (Default Configuration)
Synchronous Mode Current (HS USB operation)
I33AVG(HS) I18AVG(HS) IIOAVG(HS)
Synchronous Mode Current (FS/LS USB operation)
I33AVG(FS) I18AVG(FS) IIOAVG(FS)
Serial Mode Current (FS/LS USB) Note 4.1 USB UART Current Note 4.1
I33AVG(FS_S) I18AVG(FS_S) IIOAVG(FS_S) I33AVG(UART) I18AVG(UART) IIOAVG(UART)
Low Power Mode Note 4.2
IDD33(LPM) IDD18(LPM) IDDIO(LPM)
Standby Mode
IDD33(RSTB) IDD18(RSTB) IDDIO(RSTB)
Note 4.1 Note 4.2
ClockSuspendM bit = 0. SessEnd, VbusVld, and IdFloat comparators disabled. STP Interface protection disabled.
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4.2
Clock Specifications
Table 4.2 ULPI Clock Specifications PARAMETER SYMBOL TSTART CONDITIONS 26MHz REFCLK 12MHz REFCLK 52MHz REFCLK 24MHz REFCLK 19.2MHz REFCLK 27MHz REFCLK 38.4MHz REFCLK 13MHz REFCLK MIN TYP 1.03 2.24 0.52 1.12 1.40 1.00 0.70 2.07 0.4 45 20 -500 0.45 MAX 2.28 3.49 1.77 2.37 2.65 2.25 1.95 3.32 0.5 55 80 +500 UNITS ms ms ms ms ms ms ms ms ms % % PPM
Suspend Recovery Time Note 4.3
PHY Preparation Time CLKOUT Duty Cycle REFCLK Duty Cycle REFCLK Frequency Accuracy Note 4.3
TPREP DCCLKOUT DCREFCLK FREFCLK
60MHz REFCLK ULPI Input Clock Mode ULPI Input Clock Mode
The Suspend Recovery Time is measured from the start of the REFCLK to when the USB3320 de-asserts DIR.
Note: The USB3320 uses the AutoResume feature, Section 6.2.4.4, to allow a host start-up time of less than 1ms
4.3
ULPI Interface Timing
Table 4.3 ULPI Interface Timing PARAMETER SYMBOL CONDITIONS MIN MAX UNITS
60MHz ULPI Output Clock Note 4.4 Setup time (STP, data in) Hold time (STP, data in) Output delay (control out, 8-bit data out) 60MHz ULPI Input Clock Setup time (STP, data in) Hold time (STP, data in) Output delay (control out, 8-bit data out) TSC, TSD THC, THD TDC, TDD 60MHz REFCLK 60MHz REFCLK 60Mhz REFCLK 1.5 -0.5 1.5 6.0 ns ns ns TSC, TSD THC, THD TDC, TDD Model-specific REFCLK Model-specific REFCLK Model-specific REFCLK 5.0 0.0 1.0 3.5 ns ns ns
Note: VDD18 = 1.6 to 2.0V; VSS = 0V; TA = -40C to +85C Note 4.4 REFCLK does not need to be aligned in any way to the ULPI signals.
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4.4
Digital IO Pins
Table 4.4 Digital IO Characteristics: RESETB, CLKOUT, STP, DIR, NXT, DATA[7:0] & REFCLK Pins PARAMETER SYMBOL VIL VIH VIH VOL VOH VOH ILI Cpin RSTP RDATA_PD VIH_ED InterfaceProtectDisable = 0 ULPI Synchronous Mode At start-up or following reset 55 55 67 67 IOL = 8mA IOH = -8mA IOH = -8mA VDDIO 0.4 VDD33 - 0.4 VDD33 - 0.4 10 4 77 77 0.4 * VDDIO CONDITIONS MIN VSS 0.68 * VDDIO 0.68 * VDD18 TYP MAX 0.4 * VDDIO VDDIO VDD33 0.4 UNITS V V V V V V uA pF k k V
Low-Level Input Voltage High-Level Input Voltage High-Level Input Voltage REFCLK only Low-Level Output Voltage High-Level Output Voltage High-Level Output Voltage CPEN Only Input Leakage Current Pin Capacitance STP pull-up resistance DATA[7:0] pull-dn resistance CLKOUT External Drive
4.5
DC Characteristics: Analog I/O Pins
Table 4.5 DC Characteristics: Analog I/O Pins (DP/DM) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
LS/FS FUNCTIONALITY Input levels Differential Receiver Input Sensitivity Differential Receiver Common-Mode Voltage Single-Ended Receiver Low Level Input Voltage Single-Ended Receiver High Level Input Voltage Single-Ended Receiver Hysteresis Output Levels Low Level Output Voltage VFSOL Pull-up resistor on DP; RL = 1.5k to VDD33
17
VDIFS VCMFS VILSE VIHSE VHYSSE
| V(DP) - V(DM) |
0.2 0.8 2.5 0.8 2.0 0.050 0.150
V V V V V
Note 4.6 Note 4.6
0.3
V
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Table 4.5 DC Characteristics: Analog I/O Pins (DP/DM) (continued) PARAMETER High Level Output Voltage SYMBOL VFSOH CONDITIONS Pull-down resistor on DP, DM; Note 4.6 RL = 15k to GND MIN 2.8 TYP MAX 3.6 UNITS V
Termination Driver Output Impedance for HS and FS Input Impedance Pull-up Resistor Impedance Pull-up Resistor Impedance Pull-dn Resistor Impedance Weak Pull-up Resistor Impedance HS FUNCTIONALITY Input levels HS Differential Input Sensitivity HS Data Signaling Common Mode Voltage Range High-Speed Squelch Detection Threshold (Differential Signal Amplitude) Output Levels Hi-Speed Low Level Output Voltage (DP/DM referenced to GND) Hi-Speed High Level Output Voltage (DP/DM referenced to GND) Hi-Speed IDLE Level Output Voltage (DP/DM referenced to GND) Chirp-J Output Voltage (Differential) Chirp-K Output Voltage (Differential) Leakage Current OFF-State Leakage Current ILZ 10 uA VHSOL 45 load -10 10 mV VDIHS VCMHS Note 4.7 | V(DP) - V(DM) | 100 -50 100 500 150 mV mV mV ZHSDRV ZINP RPU RPU RPD RCD Steady state drive RX, RPU, RPD disabled Bus Idle, Note 4.5 Device Receiving, Note 4.5 Note 4.5 Configured by bits 4 and 5 in USB IO & Power Management register. 40.5 1.0 0.900 1.425 14.25 128 1.24 2.26 16.9 170 1.575 3.09 20 212 45 49.5 M k k k k
VHSSQ
VHSOH
45 load
360
440
mV
VOLHS
45 load
-10
10
mV
VCHIRPJ
HS termination resistor disabled, pull-up resistor connected. 45 load. HS termination resistor disabled, pull-up resistor connected. 45 load.
700
1100
mV
VCHIRPK
-900
-500
mV
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Table 4.5 DC Characteristics: Analog I/O Pins (DP/DM) (continued) PARAMETER Port Capacitance Transceiver Input Capacitance Note 4.5 Note 4.6 Note 4.7 CIN Pin to GND 5 10 pF SYMBOL CONDITIONS MIN TYP MAX UNITS
The resistor value follows the 27% Resistor ECN published by the USB-IF. The values shown are valid when the USB RegOutput bits in the USB IO & Power Management register are set to the default value. An automatic waiver up to 200mV is granted to accommodate system-level elements such as measurement/test fixtures, captive cables, EMI components, and ESD suppression.
4.6
Dynamic Characteristics: Analog I/O Pins
Table 4.6 Dynamic Characteristics: Analog I/O Pins (DP/DM) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
FS Output Driver Timing FS Rise Time FS Fall Time Output Signal Crossover Voltage Differential Rise/Fall Time Matching LS Output Driver Timing LS Rise Time TLR CL = 50-600pF; 10 to 90% of |VOH - VOL| CL = 50-600pF; 10 to 90% of |VOH - VOL| Excluding the first transition from IDLE state 75 300 ns TFR TFF VCRS TFRFM CL = 50pF; 10 to 90% of |VOH - VOL| CL = 50pF; 10 to 90% of |VOH - VOL| Excluding the first transition from IDLE state Excluding the first transition from IDLE state 4 4 1.3 90 20 20 2.0 111.1 ns ns V %
LS Fall Time
TLF
75
300
ns
Differential Rise/Fall Time Matching HS Output Driver Timing Differential Rise Time Differential Fall Time Driver Waveform Requirements Hi-Speed Mode Timing Receiver Waveform Requirements Data Source Jitter and Receiver Jitter Tolerance
SMSC USB3320
TLRFM
80
125
%
THSR THSF Eye pattern of Template 1 in USB 2.0 specification
500 500
ps ps
Eye pattern of Template 4 in USB 2.0 specification Eye pattern of Template 4 in USB 2.0 specification
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4.7
OTG Electrical Characteristics
Table 4.7 OTG Electrical Characteristics PARAMETER SYMBOL VSessEnd VSessVld VVbusVld RIdGnd Maximum A device Impedance to ground on ID pin 1.9 VBUS to VDD33 Note 4.8 (ChargeVbus = 1) VBUS to GND Note 4.8 (DisChargeVbus = 1) VBUS to GND IdPullup = 1 IdPullup = 0 IdGndDrv = 1 1.29 1.55 40 80 1 1000 2.2 1.34 1.7 75 100 CONDITIONS MIN 0.2 0.8 4.4 TYP 0.5 1.4 4.58 MAX 0.8 2.0 4.75 100 UNITS V V V k
SessEnd trip point SessVld trip point VbusVld trip point A-Device Impedance
ID Float trip point VBUS Pull-Up VBUS Pull-down VBUS Impedance ID pull-up resistance ID weak pull-up resistance ID pull-dn resistance Note 4.8
VIdFloat RVPU RVPD RVB RID RIDW RIDPD
2.5 1.45 1.85 100 120
V k k k k M
The RVPD and RVPU values include the required 1k external RVBUS resistor.
4.8
USB Audio Switch Characteristics
Table 4.8 USB Audio Switch Characteristics PARAMETER SYMBOL RON_Min RON_Max ROFF_Min CONDITIONS 0 < Vswitch < VDD33 0 < Vswitch < VDD33 0 < Vswitch < VDD33 MIN 2.7 4.5 1 TYP 5 7 MAX 5.8 10 UNITS M
Minimum "ON" Resistance Maximum "ON" Resistance Minimum "OFF" Resistance
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4.9
Regulator Output Voltages and Capacitor Requirement
Table 4.9 Regulator Output Voltages and Capacitor Requirement PARAMETER SYMBOL VDD33 VDD33 CONDITIONS 6V > VBAT > 3.1V USB UART Mode & UART RegOutput[1:0] = 01 6V > VBAT > 3.1V USB UART Mode & UART RegOutput[1:0] = 10 6V > VBAT > 3.1V USB UART Mode & UART RegOutput[1:0] = 11 6V > VBAT > 3.1V MIN 3.0 2.7 TYP 3.3 3.0 MAX 3.6 3.3 UNITS V V
Regulator Output Voltage Regulator Output Voltage
Regulator Output Voltage
VDD33
2.47
2.75
3.03
V
Regulator Output Voltage
VDD33
2.25
2.5
2.75
V
Regulator Bypass Capacitor Bypass Capacitor ESR
COUT CESR
2.2 1
uF
Table 4.10 ESD and LATCH-UP Performance PARAMETER CONDITIONS MIN TYP MAX UNITS COMMENTS
ESD PERFORMANCE Note 4.9 System System Human Body Model EN/IEC 61000-4-2 Contact Discharge EN/IEC 61000-4-2 Air-gap Discharge LATCH-UP PERFORMANCE All Pins EIA/JESD 78, Class II Note 4.9 150 mA 8 8 15 kV kV kV Device 3rd party system test 3rd party system test
REFCLK, XO, SPK_L and SPK_R pins: 5kV Human Body Model.
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4.10
Piezoelectric Resonator for Internal Oscillator
The internal oscillator may be used with an external quartz crystal or ceramic resonator as described in Section 5.4.1.2. See Table 4.11 for the recommended crystal specifications. See Table 4.12 for the ceramic resonator part numbers for commercial temperature applications. At this time, the ceramic resonator does not offer sufficient temperature stability to operate over the industrial temperature range. Table 4.11 USB3320 Quartz Crystal Specifications PARAMETER SYMBOL MIN NOM AT, typ Fundamental Mode Parallel Resonant Mode Ffund CO CL PW R1 0.5 Note 4.11 Table 5.10 7 typ 20 typ 3 typ 3 typ 500 30 Note 4.12 MHz PPM pF pF mW Ohm
oC
MAX
UNITS
NOTES
Crystal Cut Crystal Oscillation Mode Crystal Calibration Mode Frequency Total Allowable PPM Budget Shunt Capacitance Load Capacitance Drive Level Equivalent Series Resistance Operating Temperature Range USB3320 REFCLK Pin Capacitance USB3320 XO Pin Capacitance
Note 4.10
pF pF
Note 4.13 Note 4.13
Note 4.10 The required bit rate accuracy for Hi-Speed USB applications is 500 ppm as provided in the USB 2.0 Specification. This takes into account the effect of voltage, temperature, aging, etc. Note 4.11 0oC for commercial applications, -40oC for industrial applications. Note 4.12 +70oC for commercial applications, +85oC for industrial applications. Note 4.13 This number includes the pad, the bond wire and the lead frame. Printed Circuit Board (PCB) capacitance is not included in this value. The PCB capacitance value and the capacitance value of the XO and REFCLK pins are required to accurately calculate the value of the two external load capacitors. Table 4.12 USB3320 Ceramic Resonator Part Numbers FREQUENCY 24 MHz 26 MHz MURATA PART NUMBER CSTCE24M0XK1***-R0 CSTCE26M0XK1***-R0 NOTES Commercial Temp Only, Note 4.14 Commercial Temp Only, Note 4.14
Note 4.14 This is a generic part number assigned by Murata. The oscillating frequency is affected by stray capacitance on the Printed Circuit Board (PCB). Murata will assign the final part number for each customer's PCB after characterizing the customer's PCB design.
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Chapter 5 Architecture Overview
The USB3320 consists of the blocks shown in the diagram below. All pull-up resistors shown in this diagram are connected internally to the VDD33 pin.
DrvVbus or'd with DrvVbusExternal VDD33 RIDW
RID
CPEN ID
IdGnd
OTG Module
Rid Value VDD33 RVPU
ULPI Digitial
VBUS ESD Protection VBAT VDD33
OVP
SessEnd SessValid
RVPD
RVB
TX Data
VDD33
RX Data
LDO
VbusValid
Digital IO
IdFloat
DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0 STP NXT DIR CLKOUT RESETB VDDIO VDD18 REFCLK XO REFSEL0 REFSEL1 REFSEL2 RBIAS
DP DM
RPD
TX
HS/FS/LS TX Encoding HS/FS/LS RX Decoding
Integrated Low Jitter PLL
RCD
RCD
RPU
RPU
SPK_L SPK_R
Figure 5.1 USB3320 Internal Block Diagram
5.1
ULPI Digital Operation and Interface
This section of the USB3320 is covered in detail in Chapter 6, ULPI Operation.
5.2
5.2.1
USB 2.0 Hi-Speed Transceiver
The blocks in the lower left-hand corner of Figure 5.1 interface to the DP/DM pins.
USB Transceiver
The USB3320 includes the receivers and transmitters that are compliant to the Universal Serial Bus Specification Rev 2.0. The DP/DM signals in the USB cable connect directly to the receivers and transmitters. The RX block consists of a differential receiver for HS and separate receivers for FS/LS mode. Depending on the mode, the selected receiver provides the serial data stream through the multiplexer to the RX Logic block. For HS mode support, the HS RX block contains a squelch circuit to insure that noise is not interpreted as data. The RX block also includes a single-ended receiver on each of the data lines to determine the correct FS linestate. Data from the TX Logic block is encoded, bit stuffed, serialized and transmitted onto the USB cable by the TX block. Separate differential FS/LS and HS transmitters are included to support all modes. The USB3320 TX block meets the HS signalling level requirements in the USB 2.0 Specification when the PCB traces from the DP and DM pins to the USB connector have very little loss. In some systems,
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BIAS
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it may be desirable to compensate for loss by adjusting the HS transmitter amplitude. The Boost bits in the HS TX Boost register may be configured to adjust the HS transmitter amplitude at the DP and DM pins.
5.2.2
Termination Resistors
The USB3320 transceiver fully integrates all of the USB termination resistors on both DP and DM. This includes 1.5k pull-up resistors, 15k pull-down resistors and the 45 high speed termination resistors. These resistors require no tuning or trimming by the Link. The state of the resistors is determined by the operating mode of the transceiver when operating in synchronous mode. The XcvrSelect[1:0], TermSelect and OpMode[1:0] bits in the Function Control register, and the DpPulldown and DmPulldown bits in the OTG Control register control the configuration. The possible valid resistor combinations are shown in Table 5.1, and operation is guaranteed in only the configurations shown. If a ULPI Register Setting is configured that does not match a setting in the table, the transceiver operation is not guaranteed and the settings in the last row of Table 5.1 will be used. RPU_DP_EN activates the 1.5k DP pull-up resistor RPU_DM_EN activates the 1.5k DM pull-up resistor RPD_DP_EN activates the 15k DP pull-down resistor RPD_DM_EN activates the 15k DM pull-down resistor HSTERM_EN activates the 45 DP and DM high speed termination resistors The USB3320 also includes two DP and DM pull-up resistors described in Section 5.8. Table 5.1 DP/DM Termination vs. Signaling Mode USB3320 TERMINATION RESISTOR SETTINGS
ULPI REGISTER SETTINGS XCVRSELECT[1:0] DMPULLDOWN DPPULLDOWN
TERMSELECT
OPMODE[1:0]
SIGNALING MODE General Settings Tri-State Drivers Power-up or VBUS < VSESSEND Host Settings Host Chirp Host Hi-Speed Host Full Speed Host HS/FS Suspend Host HS/FS Resume Host low Speed Host LS Suspend
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XXb 01b
Xb 0b
01b 00b
Xb 1b
Xb 1b
0b 0b
0b 0b
0b 1b
0b 1b
0b 0b
00b 00b X1b 01b 01b 10b 10b
0b 0b 1b 1b 1b 1b 1b
24
10b 00b 00b 00b 10b 00b 00b
1b 1b 1b 1b 1b 1b 1b
1b 1b 1b 1b 1b 1b 1b
0b 0b 0b 0b 0b 0b 0b
0b 0b 0b 0b 0b 0b 0b
1b 1b 1b 1b 1b 1b 1b
1b 1b 1b 1b 1b 1b 1b
1b 1b 0b 0b 0b 0b 0b
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HSTERM_EN
RPU_DM_EN
RPD_DM_EN
RPU_DP_EN
RPD_DP_EN
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Table 5.1 DP/DM Termination vs. Signaling Mode (continued) USB3320 TERMINATION RESISTOR SETTINGS
ULPI REGISTER SETTINGS XCVRSELECT[1:0] DMPULLDOWN DPPULLDOWN
TERMSELECT
OPMODE[1:0]
RPU_DM_EN
SIGNALING MODE Host LS Resume Host Test J/Test_K Peripheral Settings Peripheral Chirp Peripheral HS Peripheral FS Peripheral HS/FS Suspend Peripheral HS/FS Resume Peripheral LS Peripheral LS Suspend Peripheral LS Resume Peripheral Test J/Test K OTG device, Peripheral Chirp OTG device, Peripheral HS OTG device, Peripheral FS OTG device, Peripheral HS/FS Suspend OTG device, Peripheral HS/FS Resume OTG device, Peripheral Test J/Test K Any combination not defined above Note 5.1
10b 00b
1b 0b
10b 10b
1b 1b
1b 1b
0b 0b
0b 0b
1b 1b
1b 1b
0b 1b
00b 00b 01b 01b 01b 10b 10b 10b 00b 00b 00b 01b 01b 01b 00b
1b 0b 1b 1b 1b 1b 1b 1b 0b 1b 0b 1b 1b 1b 0b
10b 00b 00b 00b 10b 00b 00b 10b 10b 10b 00b 00b 00b 10b 10b
0b 0b 0b 0b 0b 0b 0b 0b 0b 0b 0b 0b 0b 0b 0b
0b 0b 0b 0b 0b 0b 0b 0b 0b 1b 1b 1b 1b 1b 1b
1b 0b 1b 1b 1b 0b 0b 0b 0b 1b 0b 1b 1b 1b 0b 0b
0b 0b 0b 0b 0b 1b 1b 1b 0b 0b 0b 0b 0b 0b 0b 0b
0b 0b 0b 0b 0b 0b 0b 0b 0b 0b 0b 0b 0b 0b 0b 0b
0b 0b 0b 0b 0b 0b 0b 0b 0b 1b 1b 1b 1b 1b 1b 0b
0b 1b 0b 0b 0b 0b 0b 0b 1b 0b 1b 0b 0b 0b 1b 0b
Note: This is the same as Table 40, Section 4.4 of the ULPI 1.1 specification. Note: USB3320 does not support operation as an upstream hub port. See Section 6.2.4.3, "UTMI+ Level 3". Note 5.1 The transceiver operation is not guaranteed in a combination that is not defined.
The USB3320 uses the 27% resistor ECN resistor tolerances. The resistor values are shown in Table 4.5.
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RPD_DP_EN
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5.3
Bias Generator
This block consists of an internal bandgap reference circuit used for generating the driver current and the biasing of the analog circuits. This block requires an external 8.06K, 1% tolerance, reference resistor connected from RBIAS to ground. This resistor should be placed as close as possible to the USB3320 to minimize the trace length. The nominal voltage at RBIAS is 0.8V +/- 10% and therefore the resistor will dissipate approximately 80W of power.
5.4
Integrated Low Jitter PLL
The USB3320 uses an integrated low jitter phase locked loop (PLL) to provide a clean 480MHz clock required for HS USB signal quality. This clock is used by the transceiver during both transmit and receive. The USB3320 PLL requires an accurate frequency reference to be driven on the REFCLK pin.
5.4.1
REFCLK Mode Selection
The USB3320 is designed to operate in one of two available modes as shown in Table 5.2. In the first mode, a 60MHz ULPI clock is driven on the REFCLK pin as described in Section 5.4.1.1. In the second mode, the USB3320 generates the ULPI clock as described in Section 5.4.1.2. When using the second mode, the frequency of the reference clock is configured by REFSEL[2], REFSEL[1] and REFSEL[0] as described in Section 5.10. Table 5.2 REFCLK Modes REFCLK FREQUENCY 60Mhz Table 5.10
MODE ULPI Input Clock Mode ULPI Output Clock Mode
ULPI CLOCK DESCRIPTION Sourced by Link, driven on the REFCLK pin Sourced by USB3320 at the CLKOUT pin
During start-up, the USB3320 monitors the CLKOUT pin to determine which mode has been configured as described in Section 5.4.1.1. The system must not drive voltage on the CLKOUT pin following POR or hardware reset that exceeds the value of VIH_ED provided in Table 4.4.
5.4.1.1
ULPI Input Clock Mode (60MHz REFCLK Mode)
When using ULPI Input Clock Mode, the Link must supply the 60MHz ULPI clock to the USB3320. As shown in Figure 5.2, the 60MHz ULPI Clock is connected to the REFCLK pin, and the CLKOUT pin is tied high to VDDIO. A simplified schematic using the ULPI Input Clock Mode is shown in Figure 8.2. After the PLL has locked to the correct frequency, the USB3320 will de-assert DIR and the Link can begin using the ULPI interface. The USB3320 is guaranteed to start the clock within the time specified in Table 4.2. For Host applications, the ULPI AutoResume bit should be enabled. This is described in Section 6.2.4.4. REFSEL[2], REFSEL[1] and REFSEL[0] should all be tied to VDDIO for ULPI Input Clock Mode.
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VDDIO CLKOUT ULPI Clk Out Link Reference Clk In REFCLK
Clock Source
Figure 5.2 Configuring the USB332X for ULPI Input Clock Mode (60 MHz)
5.4.1.2
ULPI Output Clock
When using ULPI Output Clock Mode, the USB3320 generates the 60MHz ULPI clock used by the Link. The frequency of the reference clock is configured by REFSEL[2], REFSEL[1] and REFSEL[0] as described in Table 5.10. As shown in Figure 5.3, the CLKOUT pin sources the 60MHz ULPI clock to the Link.
ULPI Clk In Link
CLKOUT
From PLL
Clock Source
REFCLK
To PLL
SMSC PHY
Figure 5.3 Configuring the USB332X for ULPI Output Clock Mode In this mode, the REFCLK pin may be driven at the reference clock frequency. Alternatively, the internal oscillator may be used with an external crystal or resonator as shown in Figure 5.4. An example of ULPI Output Clock Mode is shown in Figure 8.1.
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~ ~
To PLL
SMSC PHY
~ ~ ~ ~ ~ ~
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Link
ULPI Clk In
CLKOUT
From PLL
REFCLK
Resonator - or Crystal and Caps XO ~ ~ SMSC PHY
C LOAD
Figure 5.4 ULPI Output Clock Mode After the PLL has locked to the correct frequency, the USB3320 generates the 60MHz ULPI clock on the CLKOUT pin, and de-asserts DIR to indicate that the PLL is locked. The USB3320 is guaranteed to start the clock within the time specified in Table 4.2, and it will be accurate to within 500ppm. For Host applications the ULPI AutoResume bit should be enabled. This is described in Section 6.2.4.4. When using ULPI Output Clock Mode, the edges of the reference clock do not need to be aligned in any way to the ULPI interface signals; in other words, there is no need to align the phase of the REFCLK and the CLKOUT.
5.4.2
REFCLK Amplitude
The reference clock is connected to the REFCLK pin as shown in the application diagrams, Figure 8.1, Figure 8.2 and Figure 8.3. The REFCLK pin is designed to be driven with a square wave from 0V to VDD18, but can be driven with a square wave from 0V to as high as 3.6V. The USB3320 uses only the positive edge of the REFCLK. If a digital reference is not available, the REFCLK pin can be driven by an analog sine wave that is AC coupled into the REFCLK pin. If using an analog clock, the DC bias should be set at the mid-point of the VDD18 supply using a bias circuit as shown in Figure 5.5. The amplitude must be greater than 300mV peak to peak. The component values provided in Figure 5.5 are for example only. The actual values should be selected to satisfy system requirements. The REFCLK amplitude must comply with the signal amplitudes shown in Table 4.4 and the duty cycle in Table 4.2.
VDD18
47k
To REFCLK pin
Clock 47k 0.1uF
Figure 5.5 Example of Circuit Used to Shift a Reference Clock Common-mode Voltage Level
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~ ~ Internal Oscillator
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5.4.3
REFCLK Jitter
The USB3320 is tolerant to jitter on the reference clock. The REFCLK jitter should be limited to a peak to peak jitter of less than 1nS over a 10uS time interval. If this level of jitter is exceeded when configured for either ULPI Input Clock Mode or ULPI Output Clock Mode, the USB3320 Hi-Speed eye diagram may be degraded. The frequency accuracy of the REFCLK must meet the +/- 500ppm requirement as shown in Table 4.2.
5.4.4
REFCLK Enable/Disable
The REFCLK should be enabled when the RESETB pin is brought high. The ULPI interface will start running after the time specified in Table 4.2. If the REFCLK enable is delayed relative to the RESETB pin, the ULPI interface will start operation delayed by the same amount. The REFCLK can be run at anytime the RESETB pin is low without causing the USB3320 to start-up or draw current. When the USB3320 is placed in Low Power Mode or Carkit Mode, the REFCLK can be stopped after the final ULPI register write is complete. The STP pin is asserted to bring the USB3320 out of Low Power Mode. The REFCLK should be started at the same time STP is asserted to minimize the USB3320 start-up time. If the REFCLK is stopped while CLKOUT is running, the PLL will come out of lock and the frequency of the CLKOUT signal will decrease to the minimum allowed by the PLL design. If the REFCLK is stopped during a USB session, the session may drop.
5.5
Internal Regulators and POR
The USB3320 includes integrated power management functions, including a Low-Dropout regulator that can be used to generate the 3.3V USB supply, and a POR generator described in Section 5.5.2.
5.5.1
Integrated Low Dropout Regulator
The USB3320 has an integrated linear regulator. Power sourced at the VBAT pin is regulated to 3.3V and the regulator output is on the VDD33 pin. To ensure stability, the regulator requires an external bypass capacitor (COUT) as specified in Table 4.9 placed as close to the pin as possible. The USB3320 regulator is designed to generate a 3.3 volt supply for the USB3320 only. Using the regulator to provide current for other circuits is not recommended and SMSC does not guarantee USB performance or regulator stability. During USB UART mode the regulator output voltage can be changed to allow the USB3320 to work with UARTs operating at different operating voltages. The regulator output is configured to the voltages shown in Table 4.9 with the UART RegOutput[1:0] bits in the USB IO & Power Management register. The USB3320 regulator can be powered in the three methods as shown below. For USB Peripheral, Host, and OTG operations the regulator can be connected as shown in Figure 5.6 or Figure 5.7 below. For OTG operation, the VDD33 supply on the USB3320 must be powered to detect devices attaching to the USB connector and detect a SRP during an OTG session. When using a battery to supply the USB3320, the battery voltage must be within the range of 3.1V to 5.5V.
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.
VBUS
To USB Con.
RVBUS
VBUS VBAT VDD33
To OTG
COUT
GND SMSC PHY ~ ~
Figure 5.6 Powering the USB3320 from a Battery
The USB3320 can be powered from an external 3.3V supply as shown below in Figure 5.7. When using the external supply, both the VBAT and VDD33 pins are connected together. The bypass capacitor, CBYP, is recommended when using the external supply.
VBUS
To USB Con.
RVBUS
VBUS VBAT VDD33
To OTG
Vdd 3.3V
CBYP
GND SMSC PHY ~ ~
Figure 5.7 Powering the USB3320 from a 3.3V Supply
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For peripheral only or host only operation, the VBAT supply shown below in Figure 5.8 may be connected to the VBUS pin of the USB connector for bus powered applications. In this configuration, external overvoltage protection is required to protect the VBAT supply from any transient voltage present at the VBUS pin of the USB connector. The VBAT input must never be exposed to a voltage that exceeds VVBAT. (See Table 3.2)
VBUS
To USB Con.
RVBUS
VBUS VBAT VDD33
To OTG
OVP
COUT
GND SMSC PHY ~ ~
Figure 5.8 Powering the USB3320 from VBUS
5.5.2
Power On Reset (POR)
The USB3320 provides a POR circuit that generates an internal reset pulse after the VDD18 supply is stable. After the internal POR goes high and the RESETB pin is high, the USB3320 will release from reset and begin normal ULPI operation as described in Section 5.5.4. The ULPI registers will power up in their default state summarized in Table 7.1 when the 1.8V supply is brought up. Cycling the 1.8 volt power supply will reset the ULPI registers to their default states. The RESETB pin can also be used to reset the ULPI registers to their default state (and reset all internal state machines) by bringing the pin low for a minimum of 1 microsecond and then high. The Link is not required to assert the RESETB pin. A pull-down resistor is not present on the RESETB pin and therefore the Link must drive the RESETB pin to the desired state at all times (including system start-up) or connect the RESETB pin to VDDIO.
5.5.3
Recommended Power Supply Sequence
For USB operation the USB3320 requires the VBAT, VDD33, VDDIO and VDD18 supples. VBAT, VDD33, and VDD18 can be applied in any order. The VDD18 supply must be turned on and stable before the VDDIO supply is applied. This does not apply in cases where the VDD18 and VDDIO supply pins are tied together. When the VBAT supply is applied, the integrated regulator will automatically start-up and regulate VBAT to VDD33. If the VDD33 supply is powered and the VDD18 supply is not powered, the 3.3V circuits are powered off and the VDD33 current will be limited as shown in Table 4.1. The ULPI interface will start operating after the VDD18 and VDDIO supplies are applied and the RESETB pin is brought high. The RESETB pin must be held low until the VDD18 and VDDIO supplies are stable. If the Link is not ready to interface the USB3320, the Link may choose to hold the RESETB pin low until it is ready to control the ULPI interface.
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Table 5.3 Operating Mode vs. Power Supply Configuration VDD33 0 0 0 VDD18 0 1 1 RESETB 0 0 1 OPERATING MODES AVAILABLE Powered Off RESET Mode. In this configuration the ULPI interface is available and can be programed into all operating modes described in Chapter 6. All USB signals will read 0. In this mode the ULPI interface is not active and the circuits powered from the VDD33 supply are turned off and the current will be limited to the RESET Mode current. (Note 5.2) RESET Mode Full USB operation as described in Chapter 6.
1
0
X
1 1
1 1
0 1
Note: Anytime VBAT is powered per Table 3.2, the VDD33 pin will be powered up. Note 5.2 VDDIO must be powered to tri-state the ULPI interface in this configuration.
5.5.4
Start-Up
The power on default state of the USB3320 is ULPI Synchronous mode. The USB3320 requires the following conditions to begin operation: the power supplies must be stable, the REFCLK must be present and the RESETB pin must be high. After these conditions are met, the USB3320 will begin ULPI operation that is described in Chapter 6. Figure 5.9 below shows a timing diagram to illustrate the start-up of the USB3320. At T0, the supplies are stable and the USB3320 is held in reset mode. At T1, the Link drives RESETB high after the REFCLK has started. The RESETB pin may be brought high asynchronously to REFCLK. At this point the USB3320 will drive idle on the data bus and assert DIR until the internal PLL has locked. After the PLL has locked, the USB3320 will check that the Link has de-asserted STP and at T2 it will de-assert DIR and begin ULPI operation. The ULPI bus will be available as shown in Figure 5.9 in the time defined as TSTART given in Table 4.2. If the REFCLK signal starts after the RESETB pin is brought high, then time T0 will begin when REFCLK starts. TSTART also assumes that the Link has de-asserted STP. If the Link has held STP high the USB3320 will hold DIR high until STP is de-asserted. When the LINK de-asserts STP, it must drive a ULPI IDLE one cycle after DIR de-asserts.
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T0 SUPPLIES STABLE
T1
T2
REFCLK RESETB DATA[7:0] DIR STP
REFCLK valid
PHY Tri-States
PHY Drives Idle
IDLE
RXCMD
IDLE
PHY Tri-States
PHY Drives High
LINK Drives Low
TSTART
Figure 5.9 ULPI Start-up Timing
5.6
USB On-The-Go (OTG)
The USB3320 provides full support for USB OTG protocol. OTG allows the USB3320 to be dynamically configured as a host or device depending on the type of cable inserted into the receptacle. When the Micro-A plug of a cable is inserted into the Micro-AB receptacle, the USB device becomes the Adevice. When a Micro-B plug is inserted, the device becomes the B-device. The OTG A-device behaves similar to a Host while the B-device behaves similar to a peripheral. The differences are covered in the "On-The-Go Supplement to the USB 2.0 Specification". In applications where only Host or Device is required, the OTG Module is unused.
5.6.1
ID Resistor Detection
The ID pin of the USB connector is monitored by the ID pin of the USB3320 to detect the attachment of different types of USB devices and cables. For device only applications that do not use the ID signal the ID pin should be connected to VDD33. The block diagram of the ID detection circuitry is shown in Figure 5.10 and the related parameters are given in Table 4.7.
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VDD33
IdPullup RID=100K RIDW>1M
ID
To USB Con.
5.6.1.1
USB OTG Operation
The USB3320 can detect ID grounded and ID floating to determine if an A or B cable has been inserted. The A plug will ground the ID pin while the B plug will float the ID pin. These are the only two valid states allowed in the OTG Protocol. To monitor the status of the ID pin, the Link activates the IdPullup bit in the OTG Control register, waits 50mS and then reads the status of the IdGnd bit in the USB Interrupt Status register. If an A cable has been inserted the IdGnd bit will read 0. If a B cable is inserted, the ID pin is floating and the IdGnd bit will read 1. The USB3320 provides an integrated weak pull-up resistor on the ID pin, RIDW. This resistor is present to keep the ID pin in a known state when the IdPullup bit is disabled and the ID pin is floated. In addition to keeping the ID pin in a known state, it enables the USB3320 to generate an interrupt to inform the link when a cable with a resistor to ground has been attached to the ID pin. The weak pullup is small enough that the largest valid Rid resistor pulls the ID pin low and causes the IdGnd comparator to go low. After the link has detected an ID pin state change, the RID converter can be used to determine the resistor value as described in Section 5.6.1.2.
5.6.1.2
Measuring ID Resistance to Ground
The Link can used the integrated resistance measurement capabilities to determine the value of an ID resistance to ground. Table 5.4 lists the valid values of resistance, to ground, that the USB3320 can detect.
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~ ~
Vref IdGnd
en
IdGnd IdGnd Rise or IdGnd Fall IdFloat
en
IdGndDrv Vref IdFloat
IdFloatRise or IdFloatFall RidValue
Rid ADC OTG Module
~ ~
Figure 5.10 USB3320 ID Resistor Detection Circuitry
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Table 5.4 Valid Values of ID Resistance to Ground ID RESISTANCE TO GROUND Ground 75 +/-1% 102k +/-1% 200k+/-1% 440k +/-1% Floating Note: IdPullUp = 0 The Rid resistance can be read while the USB3320 is in Synchronous Mode. When a resistor to ground is attached to the ID pin, the state of the IdGnd comparator will change. After the Link has detected ID transition to ground, it can use the methods described in Section 6.6 to operate the Rid converter. RID VALUE 000 001 010 011 100 101
5.6.1.3
Using IdFloat Comparator
Note: The ULPI specification details a method to detect a 102k resistance to ground using the IdFloat comparator. This method can only detect 0ohms, 102k, and floating terminations of the ID pin. Due to this limitation it is recommended to use the RID Converter as described in Section 5.6.1.2. The ID pin can be either grounded, floated, or connected to ground with a 102k external resistor. To detect the 102K resistor, set the idPullup bit in the OTG Control register, causing the USB3320 to apply the 100K internal pull-up connected between the ID pin and VDD33. Set the idFloatRise and idFloatFall bits in both the USB Interrupt Enable Rising and USB Interrupt Enable Falling registers to enable the IdFloat comparator to generate an RXCMD to the Link when the state of the IdFloat changes. As described in Figure 6.3, the alt_int bit of the RXCMD will be set. The values of IdGnd and IdFloat are shown for the three types cables that can attach to the USB Connector in Table 5.5. Table 5.5 IdGnd and IdFloat vs. ID Resistance to Ground ID RESISTANCE Float 102K GND IDGND 1 1 0 IDFLOAT 1 0 0
Note: The ULPI register bits IdPullUp, IdFloatRise, and IdFloatFall should be enabled. To save current when an A Plug is inserted, the internal 102k pull-up resistor can be disabled by clearing the IdPullUp bit in the OTG Control register and the IdFloatRise and IdFloatFall bits in both the USB Interrupt Enable Rising and USB Interrupt Enable Falling registers. If the cable is removed the weak RIDW will pull the ID pin high. The IdGnd value can be read using the ULPI USB Interrupt Status register, bit 4. In host mode, it can be set to generate an interrupt when IdGnd changes by setting the appropriate bits in the USB Interrupt Enable Rising and USB Interrupt Enable Falling registers. The IdFloat value can be read by reading the ULPI Carkit Interrupt Status register bit 0.
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Note: The IdGnd switch has been provided to ground the ID pin for future applications.
5.6.2
VBUS Monitor and Pulsing
The USB3320 includes all of the VBUS comparators required for OTG. The VBUSVld, SessVld, and SessEnd comparators shown in Figure 5.11 are fully integrated into the USB3320. These comparators are used to monitor changes in the VBUS voltage, and the state of each comparator can be read from the USB Interrupt Status register. The VbusVld comparator is used by the Link, when configured as an A device, to ensure that the VBUS voltage on the cable is valid. The SessVld comparator is used by the Link when configured as both an A or B device to indicate a session is requested or valid. Finally the SessEnd comparator is used by the B-device to indicate a USB session has ended. Also included in the VBUS Monitor and Pulsing block are the resistors used for VBUS pulsing in SRP. The resistors used for VBUS pulsing include a pull-down to ground and a pull-up to VDD33. In some applications, voltages much greater than 5.5V may be present at the VBUS pin of the USB connector. The USB3320 includes an overvoltage protection circuit that protects the VBUS pin of the USB3320 from excessive voltages as described in Section 5.6.2.6, and shown in Figure 5.11.
VDD33
ChrgVbus 0.5V SessEnd
en
RVPU
VBUS
To USB Con.
RVBUS
RVPD
RVB
5.6.2.1
SessEnd Comparator
The SessEnd comparator is designed to trip when VBUS is less than 0.5 volts. When VBUS goes below 0.5 volts the USB session is considered to be ended, and SessEnd will transition from 0 to 1. The SessEnd comparator can be disabled by clearing this bit in both the USB Interrupt Enable Rising and USB Interrupt Enable Falling registers. When disabled, the SessEnd bit in the USB Interrupt Status register will read 0. The SessEnd comparator trip points are detailed in Table 4.7.
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~ ~
SessEnd Rise or SessEnd Fall SessValid 1.4V VBUS Overvoltage Protection VbusValid 4.575V DischrgVbus
en
VbusValid Rise or VbusValid Fall [0, X] [1, 0] RXCMD VbusValid
EXTVBUS (logic 1) IndicatorComplement
[1, 1]
[UseExternalVbusindicator, IndicatorPassThru]
SMSC PHY
~ ~
36
Figure 5.11 USB3320 OTG VBUS Block
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Highly Integrated Full Featured Hi-Speed USB 2.0 ULPI Transceiver
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5.6.2.2
SessVld Comparator
The SessVld comparator is used when the transceiver is configured as both an A and B device. When configured as an A device, the SessVld is used to detect Session Request protocol (SRP). When configured as a B device, SessVld is used to detect the presence of VBUS. The SessVld interrupts can be disabled by clearing this bit in both the USB Interrupt Enable Rising and USB Interrupt Enable Falling registers. When the interrupts are disabled, the SessVld comparator is not disabled and its state can be read in the USB Interrupt Status register. The SessVld comparator trip point is detailed in Table 4.7. Note: The OTG Supplement specifies a voltage range for A-Device Session Valid and B-Device Session Valid comparator. The USB3320 transceiver combines the two comparators into one and uses the narrower threshold range.
5.6.2.3
VbusVld Comparator
The final VBUS comparator is the VbusVld comparator. This comparator is only used when the USB3320 is configured as an A-device. In the USB protocol the A-device supplies the VBUS voltage and is responsible to ensure it remains within a specified voltage range. The VbusVld comparator can be disabled by clearing this bit in both the USB Interrupt Enable Rising and USB Interrupt Enable Falling registers. When disabled, bit 1 of the USB Interrupt Status register will return a 0. The VbusVld comparator trip points are detailed in Table 4.7. The internal VbusValid comparator is designed to ensure the VBUS voltage remains above 4.4V. The USB3320 includes the external vbus valid indicator logic as detail in the ULPI Specification. The external vbus valid indicator is tied to a logic one. The decoding of this logic is shown in Table 5.6 below. By default this logic is disabled. Table 5.6 External VBUS Indicator Logic USE EXTERNAL VBUS INDICATOR 0 1 1 1 1
TYPICAL APPLICATION OTG Device
INDICATOR PASS THRU X 1 1 0 0 1 1 X
INDICATOR COMPLEMENT X 0 1 0 1 0 1 X
RXCMD VBUS VALID ENCODING SOURCE Internal VbusVld comparator (Default) Fixed 1 Fixed 0 Internal VbusVld comparator. Fixed 0 Fixed 1 Fixed 0 Internal VbusVld comparator. This information should not be used by the Link. (Note 5.3)
Standard Host
1 1
Standard Peripheral
0
Note 5.3
A peripheral should not use VbusVld to begin operation. The peripheral should use SessVld because the internal VbusVld threshold can be above the VBUS voltage required for USB peripheral operation.
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5.6.2.4
VBUS Pulsing with Pull-up and Pull-down Resistors
In addition to the internal VBUS comparators, the USB3320 also includes the integrated VBUS pull-up and pull-down resistors used for VBUS Pulsing during OTG Session Request Protocol. To discharge the VBUS voltage so that a Session Request can begin, the USB3320 provides a pull-down resistor from VBUS to Ground. This resistor is controlled by the DischargeVbus bit 3 of the OTG Control register. The pull-up resistor is connected between VBUS and VDD33. This resistor is used to pull VBUS above 2.1 volts so that the A-Device knows that a USB session has been requested. The state of the pull-up resistor is controlled by the bit 4 ChargeVbus of the OTG Control register. The Pull-Up and Pull-Down resistor values are detailed in Table 4.7. The internal VBUS Pull-up and Pull-down resistors are designed to include the RVBUS external resistor in series. This external resistor is used by the VBUS Overvoltage protection described below.
5.6.2.5
VBUS Input Impedance
The OTG Supplement requires an A-Device that supports Session Request Protocol to have a VBUS input impedance less than 100k and greater the 40k to ground. The USB3320 provides a 75k resistance to ground, RVB. The RVB resistor tolerance is detailed in Table 4.7.
5.6.2.6
VBUS Overvoltage Protection
The USB3320 provides an integrated overvoltage protection circuit to protect the VBUS pin from excessive voltages that may be present at the USB connector. The overvoltage protection circuit works with an external resistor (RVBUS) by drawing current across the resistor to reduce the voltage at the VBUS pin. When voltage at the VBUS pin exceeds 5.5V, the Overvoltage Protection block will sink current to ground until VBUS is below 5.5V. The current drops the excess voltage across RVBUS and protects the USB3320 VBUS pin. The required RVBUS value is dependent on the operating mode of the USB3320 as shown in Table 5.7. Table 5.7 Required RVBUS Resistor Value OPERATING MODE Device only OTG Capable Host UseExternalVbusIndicator = 1 RVBUS 10k 5% 1k 5% 10k 5%
The Overvoltage Protection circuit is designed to protect the USB3320 from continuous voltages up to 30V on the RVBUS resistor. The RVBUS resistor must be sized to handle the power dissipated across the resistor. The resistor power can be found using the equation below:
( Vprotect - 5.0 ) P RVBUS = ------------------------------------------R VBUS
Where: Vprotect is the VBUS protection required RVBUS is the resistor value, 1k or 10k. PRVBUS is the required power rating of RVBUS
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For example, protecting a peripheral or device only application to 15V would require a 10k RVBUS resistor with a power rating of 0.01W. To protect an OTG product to 15V would require a 1k RVBUS resistor with a power rating of 0.1W.
5.6.3
Driving External VBUS
The USB3320 monitors VBUS as described in VBUS Monitor and Pulsing. For OTG and Host applications, the system is required to source 5 volts on VBUS. The USB3320 fully supports VBUS power control using an external VBUS switch as shown in Figure 8.3. The USB3320 provides an active high control signal, CPEN, that is dedicated to controlling the Vbus supply when configured as an ADevice. CPEN is asserted by setting the DrvVbus or DrvVbusExternal bit of the OTG Control register. To be compatible with Link designs that support both internal and external Vbus supplies the DrvVbus and DrvVbusExternal bits in the OTG Control Register are or'd together. This enables the Link to set either bit to access the external Vbus enable (CPEN). This logic is shown in Figure 5.12. DrvVbus and DrvVbusExternal are set to 0 on Power On Reset (POR) as shown in Section 7.1.1.7.
USB Transceiver
CPEN VBUS Switch +5V VBUS Supply EN 5V IN
RVBUS
DrvVbus DrvVbusExternal
Link Controller
OUT
VBUS ULPI CPEN Logic
USB Connector VBUS DM DP DM DP
Figure 5.12 USB3320 Drives Control Signal (CPEN) to External Vbus Switch
5.7
USB UART Support
The USB3320 provides support for the USB UART interface as detailed in the ULPI specification and the former CEA-936A specification. The USB3320 can be placed in UART Mode using the method described in Section 6.5, and the regulator output will automatically switch to the value configured by the UART RegOutput bits in the USB IO & Power Management register. While in UART mode, the Linestate signals cannot be monitored on the DATA[0] and DATA[1] pins.
5.8
USB Charger Detection Support
To support the detection and identification of different types of USB chargers the USB3320 provides integrated pull-up resistors, RCD, on both DP and DM. These pull-up resistors along with the single ended receivers can be used to help determine the type of USB charger attached. Reference information on implementing charger detection is provided in SMSC Application Note AN 19.7 - Battery Charging Using SMSC USB Transceivers.
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Table 5.8 USB Weak Pull-up Enable RESETB 0 1 DP PULLUP ENABLE 0 ChargerPullupEnableDP DM PULLUP ENABLE 0 ChargerPullupEnableDM
Note: ChargerPullupEnableDP and ChargerPullupEnableDM are enabled in the USB IO & Power Management register.
5.9
USB Audio Support
Note: The USB3320 supports "USB Digital Audio" through the USB protocol in ULPI and USB Serial modes described in Section 6. The USB3320 provides two low resistance analog switches that allow analog audio to be multiplexed over the DP and DM terminals of the USB connector. The audio switches are shown in Figure 5.1. The electrical characteristics of the USB Audio Switches are provided in Table 4.8. During normal USB operation the switches are off. When USB Audio is desired the switches can be turned "on" by enabling the SpkLeftEn, SpkRightEn, or MicEn bits in the Carkit Control register as described in Section 6.5.2. These bits are disabled by default. The USB Audio Switches can also be enabled by asserting the RESETB pin or removing the voltage at VDD18 as shown in Table 5.9. While using the USB switches, VDD18 is not required, but 3.3V must be present at VDD33. The integrated 3.3V LDO regulator may be used to generate VDD33 from power applied at the VBAT pin. Table 5.9 USB Audio Switch Enable RESETB X 0 1 VDD18 0 1 1 DP SWITCH ENABLE 1 1 SpkLeftEn DM SWITCH ENABLE 1 1 SpkRightEn or MicEn
Note: SpkLeftEn, SpkRightEn, and MicEn are enabled in the Carkit Control register. In addition to USB Audio support the switches can also be used to multiplexed a second FS USB transceiver to the USB connector. The signal quality will be degraded slightly due to the "on" resistance of the switches. The USB3320 single-ended receivers described in Section 5.2.1 are disabled when either USB Audio switch is enabled. The USB3320 does not provide the DC bias for the audio signals. The SPK_R and SPK_L pins should be biased to 1.65V when audio signals are routed through the USB3320. This DC bias is necessary to prevent the audio signal from swinging below ground and being clipped by ESD Diodes. When the system is not using the USB Audio switches, the SPK_R and SPK_L pins should not be connected.
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5.10
Reference Frequency Selection
The USB3320 is configured for the desired reference frequency by the REFSEL[2], REFSEL[1] and REFSEL[0] pins. If a pin is connected to VDDIO, the value of "1" is assigned. Connect the pin to ground to assign a "0." When using the ULPI Input Clock Mode (60MHz REFCLK Mode), the reference frequency is always fixed at 60 MHz. Eight reference clock frequencies are available as described in Table 5.10. Table 5.10 Configuration to Select Reference Clock Frequency CONFIGURATION PINS DESCRIPTION REFSEL[0] 0 1 0 1 0 1 0 1 52 MHz 38.4 MHz 12 MHz 27 MHz 13 MHz 19.2 MHz 26 MHz 24 MHz REFERENCE FREQUENCY
REFSEL[2] 0 0 0 0 1 1 1 1
REFSEL[1] 0 0 1 1 0 0 1 1
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Chapter 6 ULPI Operation
6.1 Overview
The USB3320 uses the industry standard ULPI digital interface to facilitate communication between the USB Transceiver (PHY) and Link (device controller). The ULPI interface is designed to reduce the number of pins required to connect a discrete USB Transceiver to an ASIC or digital controller. For example, a full UTMI+ Level 3 OTG interface requires 54 signals while a ULPI interface requires only 12 signals. The ULPI interface is documented completely in the "UTMI+ Low Pin Interface (ULPI) Specification Revision 1.1". The following sections describe the operating modes of the USB3320 digital interface. Figure 6.1 illustrates the block diagram of the ULPI digital functions. It should be noted that this USB3320 does not use a "ULPI wrapper" around a UTMI+ PHY core as the ULPI specification implies.
USB Transmit and Receive Logic
Tx Data Data[7:0] DIR NXT STP High Speed TX Full Speed TX Low Speed TX HS Tx Data FS/LS Tx Data
To TX Analog
NOTE: The ULPI interface is a wrapperless design.
ULPI Protocol Block
Rx Data High Speed Data Recovery Full / Low Speed Data Recovery HS RX Data FS/LS Data
To RX Analog
Transceiver Control
ULPI Register Access
To OTG Analog
Rid State Machine
VbusValid SessionValid SessionEnd IdGnd IdFloat RidValue[2:0] RidCon...Start Linestates[1:0] HostDisconnect RidCon...Done
To USB Audio Analog
Interrupt Control
RESETB POR
ULPI Register Array
Figure 6.1 ULPI Digital Block Diagram The advantage of a "wrapper less" architecture is that the USB3320 has a lower USB latency than a design which must first register signals into the PHY's wrapper before the transfer to the PHY core. A
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Interface Protect Disable UseExternal Vbus Indicator Indicator Complement Indicator Pass Thru DischrgVbus ChrgVbus IdGndDrv IdPullUp SpkLeftEn SpkRightEn/MicEn ChargerPullupEnDP ChargerPullupEnDM
SuspendM 6pinSerial Mode 3pinSerial Mode ClockSuspendM AutoResume CarkitMode
ULPI Interupt XcvrSelect[1:0] TermSelect OpMode[1:0] Reset DpPulldown DmPulldown SwapDP/DM RegOutput[1:0] TxdEn RxdEn
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low latency PHY allows a Link to use a wrapper around a UTMI Link and still make the required USB turn-around timing given in the USB 2.0 specification. RxEndDelay maximum allowed by the UTMI+/ULPI for 8-bit data is 63 high speed clocks. USB3320 uses a low latency high speed receiver path to lower the RxEndDelay to 43 high speed clocks. This low latency design gives the Link more cycles to make decisions and reduces the Link complexity. This is the result of the "wrapper less" architecture of the USB3320. This low RxEndDelay should allow legacy UTMI Links to use a "wrapper" to convert the UTMI+ interface to a ULPI interface. In Figure 6.1, a single ULPI Protocol Block decodes the ULPI 8-bit bi-directional bus when the Link addresses the PHY. The Link must use the DIR output to determine direction of the ULPI data bus. The USB3320 is the "bus arbitrator". The ULPI Protocol Block will route data/commands to the transmitter or the ULPI register array.
6.1.1
ULPI Interface Signals
The UTIM+ Low Pin Interface (ULPI) uses twelve pins to connect a full OTG Host / Device USB Transceiver to an SOC. A reduction of external pins on the transceiver is accomplished by realizing that many of the relatively static configuration pins (xcvrselect[1:0], termselect, opmode[1:0], and DpPullDown DmPulldown to list a few,) can be implemented by having an internal static register array. An 8-bit bi-directional data bus clocked at 60MHz allows the Link to access this internal register array and transfer USB packets to and from the transceiver. The remaining 3 pins function to control the data flow and arbitrate the data bus. Direction of the 8-bit data bus is controlled by the DIR output from the transceiver. Another output, NXT, is used to control data flow into and out of the device. Finally, STP, which is in input to the transceiver, terminates transfers and is used to start up and resume from Low Power Mode. The twelve signals are described below in Table 6.1. Table 6.1 ULPI Interface Signals
SIGNAL CLK
DIRECTION I/O
DESCRIPTION 60MHz ULPI clock. All ULPI signals are driven synchronous to the rising edge of this clock. This clock can be either driven by the transceiver or the Link as described in Section 5.4.1 8-bit bi-directional data bus. Bus ownership is determined by DIR. The Link and transceiver initiate data transfers by driving a non-zero pattern onto the data bus. ULPI defines interface timing for a single-edge data transfers with respect to rising edge of the ULPI clock. Controls the direction of the data bus. When the transceiver has data to transfer to the Link, it drives DIR high to take ownership of the bus. When the transceiver has no data to transfer it drives DIR low and monitors the bus for commands from the Link. The transceiver will pull DIR high whenever the interface cannot accept data from the Link, such as during PLL start-up. The Link asserts STP for one clock cycle to stop the data stream currently on the bus. If the Link is sending data to the transceiver, STP indicates the last byte of data was on the bus in the previous cycle. The transceiver asserts NXT to throttle the data. When the Link is sending data to the transceiver, NXT indicates when the current byte has been accepted by the transceiver. The Link places the next byte on the data bus in the following clock cycle.
DATA[7:0]
I/O
DIR
OUT
STP
IN
NXT
OUT
USB3320 implements a Single Data Rate (SDR) ULPI interface with all data transfers happening on the rising edge of the 60MHz ULPI Clock while operating in Synchronous Mode. The direction of the data bus is determined by the state of DIR. When DIR is high, the transceiver is driving DATA[7:0]. When DIR is low, the Link is driving DATA[7:0].
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Each time DIR changes, a "turn-around" cycle occurs where neither the Link nor transceiver drive the data bus for one clock cycle. During the "turn-around"cycle, the state of DATA[7:0] is unknown and the transceiver will not read the data bus. Because USB uses a bit-stuffing encoding, some means of allowing the transceiver to throttle the USB transmit data is needed. The ULPI signal NXT is used to request the next byte to be placed on the data bus by the Link layer. The ULPI interface supports the two basic modes of operation: Synchronous Mode and asynchronous modes that include Low Power Mode, Serial Modes, and Carkit Mode. In Synchronous Mode, all signals change synchronously with the 60MHz ULPI clock. In asynchronous modes the clock is off and the ULPI bus is redefined to bring out the signals required for that particular mode of operations. The description of synchronous Mode is described in the following sections while the descriptions of the asynchronous modes are described in Section 6.3, Section 6.4, and Section 6.5.
6.1.2
ULPI Interface Timing in Synchronous Mode
The control and data timing relationships are given in Figure 6.2 and Table 4.3. All timing is relative to the rising clock edge of the 60MHz ULPI Clock.
60MHz ULPI CLK TSC Control In STP TSD Data In DATA[7:0] TDC Control Out DIR, NXT TDD Data Out DATA[7:0] TDC THD THC
Figure 6.2 ULPI Single Data Rate Timing Diagram in Synchronous Mode
6.2
ULPI Register Access
A command from the Link begins a ULPI transfer from the Link to the USB3320. Before reading a ULPI register, the Link must wait until DIR is low, and then send a Transmit Command Byte (TXD CMD) byte. The TXD CMD byte informs the USB3320 of the type of data being sent. The TXD CMD is followed by a data transfer to or from the USB3320. Table 6.2 gives the TXD command byte (TXD CMD) encoding for the USB3320. The upper two bits of the TX CMD instruct the transceiver as to what type of packet the Link is transmitting. The ULPI registers retain their contents when the transceiver is in Low Power Mode, Full Speed/Low Speed Serial Mode, or Carkit Mode.
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Table 6.2 ULPI TXD CMD Byte Encoding CMD BITS[7:6] 00b 01b
COMMAND NAME Idle Transmit
CMD BITS[5:0] 000000b 000000b 00XXXXb
COMMAND DESCRIPTION ULPI Idle USB Transmit Packet with No Packet Identifier (NOPID) USB Transmit Packet Identifier (PID) where DATA[3:0] is equal to the 4-bit PID. P3P2P1P0 where P3 is the MSB. Immediate Register Write Command where: DATA[5:0] = 6-bit register address Extended Register Write Command where the 8-bit register address is available on the next cycle. Immediate Register Read Command where: DATA[5:0] = 6-bit register address Extended Register Read Command where the 8-bit register address is available on the next cycle.
Register Write
10b
XXXXXXb 101111b
Register Read
11b
XXXXXXb 101111b
6.2.1
ULPI Register Write
A ULPI register write operation is given in Figure 6.3. The TXD command with a register write DATA[7:6] = 10b is driven by the Link at T0. The register address is encoded into DATA[5:0] of the TXD CMD byte.
T0
T1
T2
T3
T4
T5
T6
CLK DATA[7:0] DIR STP NXT
TXD CMD (reg write)
Idle
Reg Data[n]
Idle
ULPI Register
Reg Data [n-1]
Reg Data [n]
Figure 6.3 ULPI Register Write in Synchronous Mode To write a register, the Link will wait until DIR is low, and at T0, drive the TXD CMD on the data bus. At T2 the transceiver will drive NXT high. On the next rising clock edge, T3, the Link will write the
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register data. At T4, the transceiver will accept the register data and drive NXT low. The Link will drive an Idle on the bus and drive STP high to signal the end of the data packet. Finally, at T5, the transceiver will latch the data into the register and the Link will pull STP low. NXT is used to control when the Link drives the register data on the bus. DIR is low throughout this transaction since the transceiver is receiving data from the Link. STP is used to end the transaction and data is registered after the de-assertion of STP. After the write operation completes, the Link must drive a ULPI Idle (00h) on the data bus or the USB3320 may decode the bus value as a ULPI command. A ULPI extended register write operation is shown in Figure 6.4. To write an extended register, the Link will wait until DIR is low, and at T0, drive the TXD CMD on the data bus. At T2 the transceiver will drive NXT high. On the next clock T3 the Link will drive the extended address. On the next rising clock edge, T4, the Link will write the register data. At T5, the transceiver will accept the register data and drive NXT low. The Link will drive an Idle on the bus and drive STP high to signal the end of the data packet. Finally, at T5, the transceiver will latch the data into the register. The Link will pull STP low.
T0
T1
T2
T3
T4
T5
T6
T7
CLK DATA[7:0] DIR STP NXT
TXD CMD (extended reg write) Extended address
Idle
Reg Data[n]
Idle
ULPI Register
Reg Data [n-1]
Reg Data [n]
Figure 6.4 ULPI Extended Register Write in Synchronous Mode
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6.2.2
ULPI Register Read
A ULPI register read operation is given in Figure 6.5. The Link drives a TXD CMD byte with DATA[7:6] = 11h for a register read. DATA[5:0] of the ULPI TXD command bye contain the register address.
T0
T1
T2
T3
T4
T5
T6
CLK DATA[7:0] DIR STP NXT
Figure 6.5 ULPI Register Read in Synchronous Mode At T0, the Link will place the TXD CMD on the data bus. At T2, the transceiver will bring NXT high, signaling the Link it is ready to accept the data transfer. At T3, the transceiver reads the TXD CMD, determines it is a register read, and asserts DIR to gain control of the bus. The transceiver will also de-assert NXT. At T4, the bus ownership has transferred back to the transceiver and the transceiver drives the requested register onto the data bus. At T5, the Link will read the data bus and the transceiver will drop DIR low returning control of the bus back to the Link. After the turn around cycle, the Link must drive a ULPI Idle command at T6. A ULPI extended register read operation is shown in Figure 6.6.To read an extended register, the Link writes the TX CMD with the address set to 2Fh. At T2, the transceiver will assert NXT, signaling the Link it is ready to accept the extended address. At T3, the Link places the extended register address on the bus. At T4, the transceiver reads the extended address, and asserts DIR to gain control of the bus. The transceiver will also de-assert NXT. At T5, the bus ownership has transferred back to the transceiver and the transceiver drives the requested register onto the data bus. At T6, the Link will read the data bus and the transceiver will de-assert DIR returning control of the bus back to the Link. After the turn around cycle, the Link must drive a ULPI Idle command at T6.
TXD CMD reg read
Idle
Turn around
Reg Data
Turn around
Idle
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T0
T1
T2
T3
T4
T5
T6
T7
CLK DATA[7:0] DIR STP NXT
TXD CMD extended reg read Extended address
Idle
Turn around
Reg Data
Turn around
Idle
Figure 6.6 ULPI Extended Register Read in Synchronous Mode
6.2.3
ULPI RXCMD
The ULPI Link needs information which was provided by the following pins in a UTMI implementation: linestate[1:0], rxactive, rxvalid and rxerror. When implementing the OTG functions, the VBUS and ID pin states must also be transferred to the Link. ULPI defines a Receive Command Byte (RXCMD) that contains this information. The Encoding of the RXCMD byte is given in the Table 6.3. Transfer of the RXCMD byte occurs in Synchronous Mode when the transceiver has control of the bus. The ULPI Protocol Block shown in Figure 6.1 determines when to send an RXCMD. A RXCMD can occur: When a linestate change occurs. When VBUS or ID comparators change state. During a USB receive when NXT is low. After the USB3320 deasserts DIR and STP is low during start-up After the USB3320 exits Low Power Mode, Serial Modes, or Carkit Mode after detecting that the Link has de-asserted STP, and DIR is low. When a USB Receive is occurring, RXCMD's are sent whenever NXT = 0 and DIR = 1. During a USB Transmit, the RXCMD's are returned to the Link after STP is asserted. If an RXCMD event occurs during a USB transmit, the RXCMD is blocked until STP de-asserts at the end of the transmit. The RXCMD contains the status that is current at the time the RXCMD is sent.
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Table 6.3 ULPI RX CMD Encoding DATA[7:0] [1:0] [3:2] NAME Linestate Encoded VBUS State DESCRIPTION AND VALUE UTMI Linestate Signals Note 6.1 ENCODED VBUS VOLTAGE STATES VALUE 00 01 10 11 [5:4] Rx Event Encoding VBUS VOLTAGE VVBUS < VSESS_END VSESS_END < VVBUS < VSESS_VLD VSESS_VLD < VVBUS < VVBUS_VLD VVBUS_VLD < VVBUS SESSEND 1 0 X X SESSVLD 0 0 1 X VBUSVLD2 0 0 0 1
ENCODED UTMI EVENT SIGNALS VALUE 00 01 11 10 RXACTIVE 0 1 1 X RXERROR 0 0 1 X HOSTDISCONNECT 0 0 0 1
[6] [7]
State of ID pin alt_int
Set to the logic state of the ID pin. A logic low indicates an A device. A logic high indicates a B device. Asserted when a non-USB interrupt occurs. This bit is set when an unmasked event occurs on any bit in the Carkit Interrupt Latch register. The Link must read the Carkit Interrupt Latch register to determine the source of the interrupt. Section 5.6.1.3 describes how a change on the ID pin can generate an interrupt. Section 6.6 describes how an interrupt can be generated when the RidConversionDone bit is set.
Notes: 1. An `X' is a do not care and can be either a logic 0 or 1. 2. The value of VbusValid is defined in Table 5.6. Note 6.1 LineState: These bits in the RXCMD byte reflect the current state of the Full-Speed single ended receivers. LineState[0] directly reflects the current state of DP. LineState[1] directly reflects the current state of DM. When DP=DM=0 this is called "Single Ended Zero" (SE0). When DP=DM=1, this is called "Single Ended One" (SE1).
6.2.4
USB3320 Transmitter
The USB3320 ULPI transmitter fully supports HS, FS, and LS transmit operations. Figure 6.1 shows the high speed, full speed, and low speed transmitter block controlled by ULPI Protocol Block. Encoding of the USB packet follows the bit-stuffing and NRZI outlined in the USB 2.0 specification. Many of these functions are re-used between the HS and FS/LS transmitters. When using the USB3320, Table 5.1 should always be used as a guideline on how to configure for various modes of operation. The transmitter decodes the inputs of XcvrSelect[1:0], TermSelect, OpMode[1:0], DpPulldown, and DmPulldown to determine what operation is expected. Users must strictly adhere to the modes of operation given in Table 5.1.
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Several important functions for a device and host are designed into the transmitter blocks. The USB3320 transmitter will transmit a 32-bit long high speed sync before every high speed packet. In full and low speed modes a 8-bit sync is transmitted. When the device or host needs to chirp for high speed port negotiation, the OpMode = 10b setting in the Function Control register will turn off the bit-stuffing and NRZI encoding in the transmitter. At the end of a chirp, the USB3320 OpMode bits should be changed only after the RXCMD linestate encoding indicates that the transmitter has completed transmitting. Should the opmode be switched to normal bit-stuffing and NRZI encoding before the transmit pipeline is empty, the remaining data in the pipeline may be transmitted in an bit-stuff encoding format. Please refer to the ULPI specification for a detailed discussion of USB reset and HS chirp.
6.2.4.1
High Speed Long EOP
When operating as a Hi-Speed host, the USB3320 will automatically generate a 40 bit long End of Packet (EOP) after a SOF PID (A5h). The USB3320 determines when to send the 40-bit long EOP by decoding the ULPI TXD CMD bits [3:0] for the SOF. The 40-bit long EOP is only transmitted when the DpPulldown and DmPulldown bits in the OTG Control register are asserted. The Hi-Speed 40-bit long EOP is used to detect a disconnect in high speed mode. In device mode, the USB3320 will not send a long EOP after a SOF PID.
6.2.4.2
Low Speed Keep-Alive
Low speed keep alive is supported by the USB3320. When in Low speed (XcvrSelect = 10b in the Function Control register), the USB3320 will send out two Low speed bit times of SE0 when a SOF PID is received.
6.2.4.3
UTMI+ Level 3
Pre-amble is supported for UTMI+ Level 3 compatibility. When XcvrSelect = 11b in the Function Control register in host mode (DpPulldown and DmPulldown both asserted), the USB3320 will pre-pend a full speed pre-amble before the low speed packet. Full speed rise and fall times are used in this mode. The pre-amble consists of the following: Full speed sync, the encoded pre-PID (C3h) and then full speed idle (DP=1 and DM = 0). A low speed packet follows with a sync, data and a LS EOP. The USB3320 will only support UTMI+ Level 3 as a host. The USB3320 does not support UTMI+ Level 3 as a peripheral. A UTMI+ Level 3 peripheral is an upstream hub port. The USB3320 will not decode a pre-amble packet intended for a LS device when the USB3320 is configured as the upstream port of a FS hub, XcvrSelect = 11b, DpPulldown = 0b, DmPulldown =0b.
6.2.4.4
Host Resume K
Resume K generation is supported by the USB3320. When the USB3320 exits the suspended (Low Power Mode), the USB3320, when operating as a host, will transmit a K on DP/DM. The transmitters will end the K with SE0 for two Low Speed bit times. If the USB3320 was operating in high speed mode before the suspend, the host must change to high speed mode before the SE0 ends. SE0 is two low speed bit times which is about 1.2 us. For more details please see sections 7.1.77 and 7.9 of the USB Specification. In device mode, the resume K will not append an SE0, but release the bus to the correct idle state, depending upon the operational mode as shown in Table 5.1. The ULPI specification includes a detailed discussion of the resume sequence and the order of operations required. To support Host start-up of less than 1mS the USB3320 implements the ULPI AutoResume bit in the Interface Control register. The default AutoResume state is 0 and this bit should be enabled for Host applications.
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6.2.4.5
No SYNC and EOP Generation (OpMode = 11)
UTMI+ defines OpMode = 11 where no sync and EOP generation occurs in Hi-Speed operation. This is an option to the ULPI specification and not implemented in the USB3320.
6.2.4.6
Typical USB Transmit with ULPI
Figure 6.7 shows a typical USB transmit sequence. A transmit sequence starts by the Link sending a TXD CMD where DATA[7:6] = 01b, DATA[5:4] = 00b, and Data[3:0] = PID. The TX CMD with the PID is followed by transmit data.
CLK DATA[7:0] DIR NXT
TXD CMD (USB tx) Turn Around RXD CMD Turn Around
Idle
D0
D1
D2
D3
IDLE
STP DP/DM
SE0
!SQUELCH
SE0
Figure 6.7 ULPI Transmit in Synchronous Mode During transmit the transceiver will use NXT to control the rate of data flow into the transceiver. If the USB3320 pipeline is full or bit-stuffing causes the data pipeline to overfill NXT is de-asserted and the Link will hold the value on Data until NXT is asserted. The USB Transmit ends when the Link asserts STP while NXT is asserted. Note: The Link cannot assert STP with NXT de-asserted since the USB3320 is expecting to fetch another byte from the Link. After the USB3320 completes transmitting, the DP and DM lines return to idle and a RXCMD is returned to the Link so the inter-packet timers may be updated by linestate. While operating in Full Speed or Low Speed, an End-of-Packet (EOP) is defined as SE0 for approximately two bit times, followed by J for one bit time. The transceiver drives a J state for one bit time following the SE0 to complete the EOP. The Link must wait for one bit time following line state indication of the SE0 to J transition to allow the transceiver to complete the one bit time J state. All bit times are relative to the speed of transmission. In the case of Full Speed or Low Speed, after STP is asserted each FS/LS bit transition will generate a RXCMD since the bit times are relatively slow.
6.2.5
USB Receiver
The USB3320 ULPI receiver fully supports HS, FS, and LS transmit operations. In all three modes the receiver detects the start of packet and synchronizes to the incoming data packet. In the ULPI protocol, a received packet has the priority and will immediately follow register reads and RXCMD transfers. Figure 6.8 shows a basic USB packet received by the USB3320 over the ULPI interface.
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CLK DATA[7:0] DIR STP NXT
Turn around Rxd Cmd Rxd Cmd Turn around
Idle
PID
D1
D2
Figure 6.8 ULPI Receive in Synchronous Mode In Figure 6.8 the transceiver asserts DIR to take control of the data bus from the Link. The assertion of DIR and NXT in the same cycle contains additional information that Rxactive has been asserted. When NXT is de-asserted and DIR is asserted, the RXCMD data is transferred to the Link. After the last byte of the USB receive packet is transferred to the transceiver, the linestate will return to idle. The ULPI full speed receiver operates according to the UTMI / ULPI specification. In the full speed case, the NXT signal will assert only when the Data bus has a valid received data byte. When NXT is low with DIR high, the RXCMD is driven on the data bus. In full speed, the USB3320 will not issue a Rxactive de-assertion in the RXCMD until the DP/DM linestate transitions to idle. This prevents the Link from violating the two full speed bit times minimum turn around time.
6.2.5.1
Disconnect Detection
A High Speed host must detect a disconnect by sampling the transmitter outputs during the long EOP transmitted during a SOF packet. The USB3320 only looks for a high speed disconnect during the long EOP where the period is long enough for the disconnect reflection to return to the host transceiver. When a high speed disconnect occurs, the USB3320 will return a RXCMD and set the host disconnect bit in the USB Interrupt Status register. When in FS or LS modes, the Link is expected to handle all disconnect detection.
6.3
Low Power Mode
Low Power Mode is a power down state to save current when the USB session is suspended. The Link controls when the transceiver is placed into or out of Low Power Mode. In Low Power Mode all of the circuits are powered down except the interface pins, full speed receiver, VBUS comparators, and IdGnd comparator. Before entering Low Power Mode, the USB3320 must be configured to set the desired state of the USB transceiver. The XcvrSelect[1:0], TermSelect and OpMode[1:0] bits in the Function Control register, and the DpPulldown and DmPulldown bits in the OTG Control register control the configuration as shown in Table 5.1. The DP and DM pins are configured to a high impedance state by configuring OpMode[1:0] = 01. Pull-down resistors with a value of approximately 2M are present
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on the DP and DM pins to avoid false linestate indications that could result if the pins were allowed to float.
6.3.1
Entering Low Power/Suspend Mode
To enter Low Power Mode, the Link will write a 0 or clear the SuspendM bit in the Function Control register. After this write is complete, the transceiver will assert DIR high and after a minimum of five rising edges of CLKOUT, drive the clock low. After the clock is stopped, the transceiver will enter a low power state to conserve current. Placing the transceiver in Suspend Mode is not related to USB Suspend. To clarify this point, USB Suspend is initiated when a USB host stops data transmissions and enters Full-Speed mode with 15K pull-down resistors on DP and DM. The suspended device goes to Full-Speed mode with a pull-up on DP. Both the host and device remain in this state until one of them drives DM high (this is called a resume).
T0
T1
T2
T3
T4
T5
T6
CLK DATA[7:0] DIR STP NXT SUSPENDM
(ULPI Register Bit)
TXD CMD (reg write) Turn Around
...
T10
Idle
Reg Data[n]
Idle
Low Power Mode
Figure 6.9 Entering Low Power Mode from Synchronous Mode While in Low Power Mode, the Data interface is redefined so that the Link can monitor Linestate and the VBUS voltage. In Low Power Mode DATA[3:0] are redefined as shown in Table 6.4. Linestate[1:0] is the combinational output of the Single-Ended Receivers. The "int" or interrupt signal indicates an unmasked interrupt has occurred. When an unmasked interrupt or linestate change has occurred, the Link is notified and can determine if it should wake-up the transceiver. Table 6.4 Interface Signal Mapping During Low Power Mode SIGNAL linestate[0] linestate[1] reserved int reserved
SMSC USB3320
MAPS TO DATA[0] DATA[1] DATA[2] DATA[3] DATA[7:4]
DIRECTION OUT OUT OUT OUT OUT
DESCRIPTION Combinatorial LineState[0] driven directly by the Full-Speed single ended receiver. Note 6.2 Combinatorial LineState[1] driven directly by the Full-Speed single ended receiver. Note 6.2 Driven Low Active high interrupt indication. Must be asserted whenever any unmasked interrupt occurs. Driven Low
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Note 6.2
LineState: These signals reflect the current state of the Full-Speed single ended receivers. LineState[0] directly reflects the current state of DP. LineState[1] directly reflects the current state of DM. When DP=DM=0 this is called "Single Ended Zero" (SE0). When DP=DM=1, this is called "Single Ended One" (SE1).
An unmasked interrupt can be caused by the following comparators changing state: VbusVld, SessVld, SessEnd, and IdGnd. If any of these signals change state during Low Power Mode and the bits are enabled in either the USB Interrupt Enable Rising or USB Interrupt Enable Falling registers, DATA[3] will assert. During Low Power Mode, the VbusVld and SessEnd comparators can have their interrupts masked to lower the suspend current as described in Section 6.3.4. While in Low Power Mode, the Data bus is driven asynchronously because all of the transceiver clocks are stopped during Low Power Mode.
6.3.2
Exiting Low Power Mode
To exit Low Power Mode, the Link will assert STP. Upon the assertion of STP, the USB3320 will begin its start-up procedure. After the transceiver start-up is complete, the transceiver will start the clock on CLKOUT and de-assert DIR. After DIR has been de-asserted, the Link can de-assert STP when ready and start operating in Synchronous Mode. The transceiver will automatically set the SuspendM bit to a 1 in the Function Control register.
T0
CLK DATA[7:0] DIR STP
LOW POWER MODE
...
T1
T2
T3
T4
T5
TURN AROUND
DATA BUS IGNORED (SLOW LINK) IDLE (FAST LINK)
IDLE
Fast Link Drives Bus Idle and STP low
Slow Link Drives Bus Idle and STP low
Note: Not to Scale
TSTART
Figure 6.10 Exiting Low Power Mode The value for TSTART is given in Table 4.2. Should the Link de-assert STP before DIR is de-asserted, the USB3320 will detect this as a false resume request and return to Low Power Mode. This is detailed in section 3.9.4 of the ULPI 1.1 specification.
6.3.3
Interface Protection
ULPI protocol assumes that both the Link and transceiver will keep the ULPI data bus driven by either the Link when DIR is low or the transceiver when DIR is high. The only exception is when DIR has changed state and a turn around cycle occurs for 1 clock period. In the design of a USB system, there can be cases where the Link may not be driving the ULPI bus to a known state while DIR is low. Two examples where this can happen is because of a slow Link start-up or a hardware reset.
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6.3.3.1
Start up Protection
Upon start-up, when the transceiver de-asserts DIR, the Link must be ready to receive commands and drive Idle on the data bus. If the Link is not ready to receive commands or drive Idle, it must assert STP before DIR is de-asserted. The Link can then de-assert STP when it has completed its start-up. If the Link doesn't assert STP before it can receive commands, the transceiver may interpret the data bus state as a TX CMD and transmit invalid data onto the USB bus, or make invalid register writes. When the USB3320 sends a RXCMD the Link is required to drive the data bus back to idle at the end of the turn around cycle. If the Link does not drive the databus to idle the USB3320 may take the information on the data bus as a TXCMD and transmit data on DP and DM until the Link asserts stop. If the ID pin is floated the last RXCMD from the USB3320 will remain on the bus after DIR is deasserted and the USB3320 will take this in as a TXCMD. A Link should be designed to have the default POR state of the STP output high and the data bus tristated. The USB3320 has weak pull-downs on the data bus to prevent these inputs from floating when not driven. These resistors are only used to prevent the ULPI interface from floating during events when the link ULPI pins may be tri-stated. The strength of the pull down resistors can be found in Table 4.4. The pull downs are not strong enough to pull the data bus low after a ULPI RXCMD, the Link must drive the data bus to idle after DIR is de-asserted. In some cases, a Link may be software configured and not have control of its STP pin until after the transceiver has started. In this case, the USB3320 has in internal pull-up on the STP input pad which will pull STP high while the Link's STP output is tri-stated. The STP pull-up resistor is enabled on POR and can be disabled by setting the InterfaceProtectDisable bit 7 of the Interface Control register. The STP pull-up resistor will pull-up the Link's STP input high until the Link configures and drives STP high. After the Link completes its start-up, STP can be synchronously driven low. A Link design which drives STP high during POR can disable the pull-up resistor on STP by setting InterfaceProtectDisable bit to 1. A motivation for this is to reduce the suspend current. In Low Power Mode, STP is held low, which would draw current through the pull-up resistor on STP.
6.3.3.2
Warm Reset
Designers should also consider the case of a warm restart of a Link with a transceiver in Low Power Mode. After the transceiver enters Low Power Mode, DIR is asserted and the clock is stopped. The USB3320 looks for STP to be asserted to re-start the clock and then resume normal synchronous operation. Should the USB3320 be suspended in Low Power Mode, and the Link receives a hardware reset, the transceiver must be able to recover from Low Power Mode and start its clock. If the Link asserts STP on reset, the transceiver will exit Low Power Mode and start its clock. If the Link does not assert STP on reset, the interface protection pull-up can be used. When the Link is reset, its STP output will tri-state and the pull-up resistor will pull STP high, signaling the transceiver to restart its clock.
6.3.4
Minimizing Current in Low Power Mode
In order to minimize the suspend current in Low Power Mode, the OTG comparators can be disabled to reduce suspend current. In Low Power Mode, the VbusVld and SessEnd comparators are not needed and can be disabled by clearing the associated bits in both the USB Interrupt Enable Rising and USB Interrupt Enable Falling registers. By disabling the interrupt in BOTH the rise and fall registers, the SessEnd and VbusVld comparators are turned off. The IdFloatRise and IdFloatFall bits in Carkit Interrupt Enable register should also be disabled if they were set. When exiting Low Power Mode, the Link should immediately re-enable the VbusVld and SessEnd comparators if host or OTG functionality is required. In addition to disabling the OTG comparators in Low Power Mode, the Link may choose to disable the Interface Protect Circuit. By setting the InterfaceProtectDisable bit high in the Interface Control register,
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the Link can disable the pull-up resistor on STP. When RESETB is low the Interface Protect Circuit will be disabled.
6.4
Full Speed/Low Speed Serial Modes
The USB3320 includes two serial modes to support legacy Links which use either the 3pin or 6pin serial format. To enter either serial mode, the Link will need to write a 1 to the 6-pin FsLsSerialMode or the 3-pin FsLsSerialMode bits in the Interface control register. Serial Mode may be used to conserve power when attached to a device that is not capable of operating in Hi-Speed. The serial modes are entered in the same manner as the entry into Low Power Mode. The Link writes the Interface Control register bit for the specific serial mode. The USB3320 will assert DIR and shut off the clock after at least five clock cycles. Then the data bus goes to the format of the serial mode selected. Before entering Serial Mode the Link must set the ULPI transceiver to the appropriate mode as defined in Table 5.1. In ULPI Output Clock Mode, the transceiver will shut off the 60MHz clock to conserve power. Should the Link need the 60MHz clock to continue during the serial mode of operation, the ClockSuspendM bit[3] of the Interface Control Register should be set before entering a serial mode. If set, the 60 MHz clock will be present during serial modes. In serial mode, interrupts are possible from unmasked sources. The state of each interrupt source is sampled prior to the assertion of DIR and this is compared against the asynchronous level from interrupt source. Exiting the serial modes is the same as exiting Low Power Mode. The Link must assert STP to signal the transceiver to exit serial mode. When the transceiver can accept a command, DIR is de-asserted and the transceiver will wait until the Link de-asserts STP to resume synchronous ULPI operation. The RESETB pin can also be pulsed low to reset the USB3320 and return it to Synchronous Mode.
6.4.0.1
3pin FS/LS Serial Mode
Three pin serial mode utilizes the data bus pins for the serial functions shown in Table 6.5. Table 6.5 Pin Definitions in 3 Pin Serial Mode CONNECTED TO DATA[0] DATA[1] DATA[2] DATA[3] DATA[7:4]
SIGNAL tx_enable data SE0 interrupt Reserved
DIRECTION IN I/O I/O OUT OUT
DESCRIPTION Active High transmit enable. TX differential data on DP/DM when tx_enable is high. RX differential data from DP/DM when tx_enable is low. TX SE0 on DP/DM when tx_enable is high. RX SE0_b from DP/DM when tx_enable is low. Asserted when any unmasked interrupt occurs. Active high. Driven Low.
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6.4.0.2
6Pin FS/LS Serial Mode
Six pin serial mode utilizes the data bus pins for the serial functions shown in Table 6.6. Table 6.6 Pin Definitions in 6 Pin Serial Mode CONNECTED TO DATA[0] DATA[1] DATA[2] DATA[3] DATA[4] DATA[5] DATA[6] DATA[7]
SIGNAL tx_enable tx_data tx_se0 interrupt rx_dp rx_dm rx_rcv Reserved
DIRECTION IN IN IN OUT OUT OUT OUT OUT
DESCRIPTION Active High transmit enable. Tx differential data on DP/DM when tx_enable is high. Tx SE0 on DP/DM when tx_enable is high. Asserted when any unmasked interrupt occurs. Active high. Single ended receive data on DP. Single ended receive data on DM. Differential receive data from DP and DM. Driven Low.
6.5
Carkit Mode
The USB3320 includes Carkit Mode to support a USB UART and USB Audio Mode. By entering Carkit Mode, the USB3320 current drain is minimized. When operating in ULPI Input Clock Mode (60MHz REFCLK Mode), the CLKOUT is stopped to conserve power by default. The Link may configure the 60MHz clock to continue by setting the ClockSuspendM bit of the Interface Control register before entering Carkit Mode. If set, the 60 MHz clock will continue during the Carkit Mode of operation. In Carkit Mode, interrupts are possible if they have been enabled in the Carkit Interrupt Enable register. The state of each interrupt source is sampled prior to the assertion of DIR and this is compared against the asynchronous level from interrupt source. In Carkit Mode, the Linestate signals are not available per the ULPI specification. Exiting Carkit Mode is the same as exiting Low Power Mode as described in Section 6.3.2. The Link must assert STP to signal the transceiver to exit serial mode. When the transceiver can accept a command, DIR is de-asserted and the transceiver will wait until the Link de-asserts STP to resume synchronous ULPI operation. The RESETB pin can also be pulsed low to reset the USB3320 and return it to Synchronous Mode.
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6.5.1
USB UART Mode
The USB3320 can be placed into UART Mode by first setting the TxdEn and RxdEn bits in the Carkit Control register. Then the Link can set the CarkitMode bit in the Interface Control register. The TxdEn and RxdEn bits must be written before the CarkitMode bit. Table 6.7 ULPI Register Programming Example to Enter UART Mode ADDRESS (HEX) 04 39 19 07 VALUE (HEX) 49 00 0C 04
R/W W W W W
DESCRIPTION Configure Non-Driving mode Select FS transmit edge rates Set regulator to 3.3V Enable UART connections Enable carkit mode
RESULT OpMode=01 XcvrSelect=01 UART RegOutput=00 RxdEn=1 TxdEn=1 CarkitMode=1
After the CarkitMode bit is set, the ULPI interface will become redefined as described in Table 6.8, and the USB3320 will transmit data through the DATA[0] to DM of the USB connector and receive data on DP and pass the information the Link on DATA[1]. When entering UART mode, the regulator output will automatically switch to the value configured by the UART RegOutput bits in the USB IO & Power Management register and a pull-up will be applied internally to DP and DM. This will hold the UART in its default operating state. While in UART mode, the transmit edge rates can be set to either the Full Speed USB or Low Speed USB edge rates by using the XcvrSelect[1:0] bits in the Function Control register. Table 6.8 Pin Definitions in Carkit Mode CONNECTED TO DATA[0] DATA[1] DATA[2] DATA[3] DATA[4:7]
SIGNAL txd rxd reserved int reserved
DIRECTION IN OUT OUT OUT OUT
DESCRIPTION UART TXD signal that is routed to the DM pin if the TxdEn is set in the Carkit Control register. UART RXD signal that is routed to the DP pin if the RxdEn bit is set in the Carkit Control register. Driven Low. Asserted when any unmasked interrupt occurs. Active high. Driven Low.
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6.5.2
USB Audio Mode
When the USB3320 is powered in Synchronous Mode, the Audio switches can be enabled by asserting the SpkLeftEn, or SpkRightEn bits in the Carkit Control register. After the register write is complete, the USB3320 will immediately enable or disable the audio switch. Then the Link can set the CarkitMode bit in the Interface Control register. The SpkLeftEn, or SpkRightEn bits must be written before the CarkitMode bit. Table 6.9 ULPI Register Programming Example to Enter Audio Mode ADDRESS (HEX) 04 19 07 VALUE (HEX) 48 30 04
R/W W W W
DESCRIPTION Configure Non-Driving mode Enable Audio connections Enable carkit mode
RESULT OpMode=01 SpkrRightEn=1, SpkrLeftEn=1 CarkitMode=1
After the CarkitMode bit is set, the ULPI interface will become redefined as described in Table 6.8.
6.6
RID Converter Operation
The RID converter is designed to read the value of the ID resistance to ground and report back its value through the ULPI interface. When a resistor to ground is applied to the ID pin the state of the IdGnd comparator will change from a 1 to a 0 as described in Section 5.6.1. If the USB3320 is in ULPI mode, an RXCMD will be generated with bit 6 low. If the USB3320 is in Low Power Mode (or one of the other non-ULPI modes), the DATA[3] interrupt signal will go high. After the USB3320 has detected the change of state on the ID pin, the RID converter can be used to determine the value of ID resistance. To start a ID resistance measurement, the RidConversionStart bit is set in the Vendor Rid Conversion register. The Link can use one of two methods to determine when the RID Conversion is complete. One method is polling the RidConversionStart bit as described in Section 7.1.3.3. The preferred method is to set the RidIntEn bit in the Vendor Rid Conversion register. When RidIntEn is set, an RXCMD will be generated after the RID conversion is complete. As described in Table 6.3, the alt_int bit of the RXCMD will be set. After the RID Conversion is complete, the Link can read RidValue from the Vendor Rid Conversion register.
6.7
Headset Audio Mode
This mode is designed to allow a user to view the status of several signals while using an analog audio headset with a USB connector. This feature, exclusive to SMSC, is provided as an alternate mode to the CarKit Mode defined in Section 6.5. In the CarKit Mode, the Link is unable to view the source of the interrupt on ID, except by returning to synchronous mode to read the ULPI registers. This forces the audio switches to be deactivated, and may glitch the audio signals. In addition, the Link cannot change the resistance on the ID pin without starting up the PHY to access the ULPI registers. The Headset Audio Mode is entered by writing to the Headset Audio Mode register, and allows the Link access to the state of the VBUS and ID pins during audio without glitching the audio connection. The Headset Audio mode also enables the Link to change the resistance on the ID pin and to change the audio headset attached from mono to stereo.
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The ULPI interface is redefined as shown in Table 6.10 when Headset Audio Mode is entered. Table 6.10 Pin Definitions in Headset Audio Mode CONNECTED TO DATA[0] DATA[1] DATA[2]
SIGNAL SessVld VbusVld IdGndDrv
DIRECTION OUT OUT IN
DESCRIPTION Output of SessVld comparator Output of VbusVld Comparator (interrupt must be enabled) Drives ID pin to ground when asserted 0b: Not connected 1b: Connects ID to ground. Driven low Asserted when the ID pin is grounded. 0b: ID pin is grounded 1b: ID pin is floating Asserted when the ID pin is floating. IdPullup or d_pullup330 must be enabled as shown below. When enabled a 330kpullup is applied to the ID pin. This bit will also change the trip point of the IdGnd comparator to the value shown in Table 4.7. 0b: Disables the pull-up resistor 1b: Enables the pull-up resistor Connects the 100k pull-up resistor from the ID pin to VDD3.3 0b: Disables the pull-up resistor 1b: Enables the pull-up resistor
DATA[3] IdGround DATA[4]
OUT OUT
IdFloat IdPullup330
DATA[5] DATA[6]
OUT IN
IdPullup
DATA[7]
IN
Exiting Headset Audio Mode is the same as exiting Low Power Mode as described in Section 6.3.2. The Link must assert STP to signal the PHY to exit. When the PHY can accept a command, DIR is de-asserted and the PHY will wait until the Link de-asserts STP to resume synchronous ULPI operation. The RESETB pin can also be pulsed low to reset the USB3320 and return it to Synchronous Mode.
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Chapter 7 ULPI Register Map
7.1 ULPI Register Array
The USB3320 Transceiver implements all of the ULPI registers detailed in the ULPI revision 1.1 specification. The complete USB3320 ULPI register set is shown in Table 7.1. All registers are 8 bits. This table also includes the default state of each register upon POR or de-assertion of RESETB, as described in Section 5.5.2. The RESET bit in the Function Control Register does not reset the bits of the ULPI register array. The Link should not read or write to any registers not listed in this table. The USB3320 supports extended register access. The immediate register set (00-3Fh) can be accessed through either a immediate address or an extended register address. Table 7.1 ULPI Register Map ADDRESS (6BIT) REGISTER NAME Vendor ID Low Vendor ID High Product ID Low Product ID High Function Control Interface Control OTG Control USB Interrupt Enable Rising USB Interrupt Enable Falling USB Interrupt Status (Note 7.1) USB Interrupt Latch Debug Scratch Register Carkit Control Reserved Carkit Interrupt Enable Carkit Interrupt Status Carkit Interrupt Latch Reserved HS TX Boost Reserved Headset Audio Mode DEFAULT STATE 24h 04h 07h 00h 41h 00h 06h 1Fh 1Fh 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 31h 32h 33h 31h 32h 33h 1D-1Fh 20h 21h 1Dh 22-30h READ 00h 01h 02h 03h 04-06h 07-09h 0A-0Ch 0D-0Fh 10-12h 13h 14h 15h 16-18h 19-1Bh WRITE 04h 07h 0Ah 0Dh 10h 16h 19h 1Ch 1Eh 1Fh SET 05h 08h 0Bh 0Eh 11h 17h 1Ah CLEAR 06h 09h 0Ch 0Fh 12h 18h 1Bh
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Table 7.1 ULPI Register Map (continued) ADDRESS (6BIT) REGISTER NAME Reserved Vendor Rid Conversion USB IO & Power Management Reserved Note 7.1 DEFAULT STATE 00h 00h 04h 00h 36-38h 39-3Bh 36h 39h 3C-3Fh READ WRITE 34-35h 37h 3Ah 38h 3Bh SET CLEAR
Dynamically updates to reflect current status of interrupt sources.
7.1.1
ULPI Register Set
The following registers are used for the ULPI interface.
7.1.1.1
Vendor ID Low
Address = 00h (read only)
FIELD NAME Vendor ID Low
BIT 7:0
ACCESS rd
DEFAULT 24h
DESCRIPTION SMSC Vendor ID
7.1.1.2
Vendor ID High
Address = 01h (read only)
FIELD NAME Vendor ID High
BIT 7:0
ACCESS rd
DEFAULT 04h
DESCRIPTION SMSC Vendor ID
7.1.1.3
Product ID Low
Address = 02h (read only)
FIELD NAME Product ID Low
BIT 7:0
ACCESS rd
DEFAULT 07h
DESCRIPTION SMSC Product ID
7.1.1.4
Product ID High
Address = 03h (read only)
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FIELD NAME Product ID High
BIT 7:0
ACCESS rd
DEFAULT 00h
DESCRIPTION SMSC Product ID
7.1.1.5
Function Control
Address = 04-06h (read), 04h (write), 05h (set), 06h (clear)
FIELD NAME XcvrSelect[1:0]
BIT 1:0
ACCESS rd/w/s/c
DEFAULT 01b
DESCRIPTION Selects the required transceiver speed. 00b: Enables HS transceiver 01b: Enables FS transceiver 10b: Enables LS transceiver 11b: Enables FS transceiver for LS packets (FS preamble automatically pre-pended) Controls the DP and DM termination depending on XcvrSelect, OpMode, DpPulldown, and DmPulldown. The DP and DM termination is detailed in Table 5.1. Selects the required bit encoding style during transmit. 00b: Normal Operation 01b: Non-Driving 10b: Disable bit-stuff and NRZI encoding 11b: Reserved
TermSelect
2
rd/w/s/c
0b
OpMode
4:3
rd/w/s/c
00b
Reset
5
rd/w/s/c
0b
Active high transceiver reset. This reset does not reset the ULPI interface or register set. Automatically clears after reset is complete. Active low PHY suspend. When cleared the transceiver will enter Low Power Mode as detailed in 6.3. Automatically set when exiting Low Power Mode. Read only, 0.
SuspendM
6
rd/w/s/c
1b
Reserved
7
rd
0b
7.1.1.6
Interface Control
Address = 07-09h (read), 07h (write), 08h (set), 09h (clear)
FIELD NAME 6-pin FsLsSerialMode
BIT 0
ACCESS rd/w/s/c
DEFAULT 0b
DESCRIPTION When asserted the ULPI interface is redefined to the 6-pin Serial Mode. The transceiver will automatically clear this bit when exiting serial mode. When asserted the ULPI interface is redefined to the 3-pin Serial Mode. The transceiver will automatically clear this bit when exiting serial mode. When asserted the ULPI interface is redefined to the Carkit interface. The transceiver will automatically clear this bit when exiting Carkit Mode.
3-pin FsLsSerialMode
1
rd/w/s/c
0b
CarkitMode
2
rd/w/s/c
0b
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FIELD NAME ClockSuspendM
BIT 3
ACCESS rd/w/s/c
DEFAULT 0b
DESCRIPTION Enables Link to turn on 60MHz CLKOUT in Serial Mode or Carkit Mode. 0b: Disable clock in serial or Carkit Mode. 1b: Enable clock in serial or Carkit Mode. Only applicable in Host mode. Enables the transceiver to automatically transmit resume signaling. This function is detailed in Section 6.2.4.4. Inverts the EXTVBUS signal. This function is detailed in Section 5.6.2. Note: The EXTVBUS signal is always high on the USB3320.
AutoResume
4
rd/w/s/c
0b
IndicatorComplement
5
rd/w/s/c
0b
IndicatorPassThru
6
rd/w/s/c
0b
Disables and'ing the internal VBUS comparator with the EXTVBUS signal when asserted. This function is detailed in Section 5.6.2. Note: The EXTVBUS signal is always high on the USB3320.
InterfaceProtectDisable
7
rd/w/s/c
0b
Used to disable the integrated STP pull-up resistor used for interface protection. This function is detailed in Section 6.3.3.
7.1.1.7
OTG Control
Address = 0A-0Ch (read), 0Ah (write), 0Bh (set), 0Ch (clear)
FIELD NAME IdPullup
BIT 0
ACCESS rd/w/s/c
DEFAULT 0b
DESCRIPTION Connects a 100k pull-up resistor from the ID pin to VDD33 0b: Disables the pull-up resistor 1b: Enables the pull-up resistor Enables the 15k Ohm pull-down resistor on DP. 0b: Pull-down resistor not connected 1b: Pull-down resistor connected Enables the 15k Ohm pull-down resistor on DM. 0b: Pull-down resistor not connected 1b: Pull-down resistor connected This bit is only used during SRP. Connects a resistor from VBUS to ground to discharge VBUS. 0b: disconnect resistor from VBUS to ground 1b: connect resistor from VBUS to ground This bit is only used during SRP. Connects a resistor from VBUS to VDD33 to charge VBUS above the SessValid threshold. 0b: disconnect resistor from VBUS to VDD33 1b: connect resistor from VBUS to VDD33 Enables external 5 volt supply to drive 5 volts on VBUS. This signal is or'ed with DrvVbusExternal. 0b: Do not drive Vbus, CPEN driven low. 1b: Drive Vbus, CPEN driven high.
DpPulldown
1
rd/w/s/c
1b
DmPulldown
2
rd/w/s/c
1b
DischrgVbus
3
rd/w/s/c
0b
ChrgVbus
4
rd/w/s/c
0b
DrvVbus
5
rd/w/s/c
0b
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FIELD NAME DrvVbusExternal
BIT 6
ACCESS rd/w/s/c
DEFAULT 0b
DESCRIPTION Enables external 5 volt supply to drive 5 volts on VBUS. This signal is or'ed with DrvVbus. 0b: Do not drive Vbus, CPEN driven low. 1b: Drive Vbus, CPEN driven high. Tells the transceiver to use an external VBUS overcurrent or voltage indicator. This function is detailed in Section 5.6.2. 0b: Use the internal VbusValid comparator 1b: Use the EXTVBUS input as for VbusValid signal. Note: The EXTVBUS signal is always high on the USB3320.
UseExternalVbus Indicator
7
rd/w/s/c
0b
7.1.1.8
USB Interrupt Enable Rising
Address = 0D-0Fh (read), 0Dh (write), 0Eh (set), 0Fh (clear)
FIELD NAME HostDisconnect Rise
BIT 0
ACCESS rd/w/s/c
DEFAULT 1b
DESCRIPTION Generate an interrupt event notification when Hostdisconnect changes from low to high. Applicable only in host mode. Generate an interrupt event notification when Vbusvalid changes from low to high. Generate an interrupt event notification when SessValid changes from low to high. Generate an interrupt event notification when SessEnd changes from low to high. Generate an interrupt event notification when IdGnd changes from low to high. Read only, 0.
VbusValid Rise SessValid Rise SessEnd Rise IdGnd Rise Reserved
1 2 3 4 7:5
rd/w/s/c rd/w/s/c rd/w/s/c rd/w/s/c rd
1b 1b 1b 1b 000b
7.1.1.9
USB Interrupt Enable Falling
Address = 10-12h (read), 10h (write), 11h (set), 12h (clear)
FIELD NAME HostDisconnect Fall
BIT 0
ACCESS rd/w/s/c
DEFAULT 1b
DESCRIPTION Generate an interrupt event notification when Hostdisconnect changes from high to low. Applicable only in host mode. Generate an interrupt event notification when Vbusvalid changes from high to low. Generate an interrupt event notification when SessValid changes from high to low. Generate an interrupt event notification when SessEnd changes from high to low. Generate an interrupt event notification when IdGnd changes from high to low.
VbusValid Fall SessValid Fall SessEnd Fall IdGnd Fall
SMSC USB3320
1 2 3 4
rd/w/s/c rd/w/s/c rd/w/s/c rd/w/s/c
1b 1b 1b 1b
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FIELD NAME Reserved
BIT 7:5
ACCESS rd
DEFAULT 000b
DESCRIPTION Read only, 0.
7.1.1.10
USB Interrupt Status
Address = 13h (read only) This register dynamically updates to reflect current status of interrupt sources.
FIELD NAME HostDisconnect VbusValid SessValid SessEnd IdGnd Reserved
BIT 0 1 2 3 4 7:5
ACCESS rd rd rd rd rd rd
DEFAULT 0b 0b 0b 0b 0b 000b
DESCRIPTION Current value of the UTMI+ Hi-Speed Hostdisconnect output. Applicable only in host mode. Current value of the UTMI+ Vbusvalid output. Current value of the UTMI+ SessValid output. Current value of the UTMI+ SessEnd output. Current value of the UTMI+ IdGnd output. Read only, 0.
Note: The default conditions will match the current status of the comparators. The values shown are for an unattached OTG device.
7.1.1.11
USB Interrupt Latch
Address = 14h (read only with auto clear)
FIELD NAME HostDisconnect Latch
BIT 0
ACCESS rd (Note 7.2) rd (Note 7.2) rd (Note 7.2) rd (Note 7.2) rd (Note 7.2) rd
DEFAULT 0b
DESCRIPTION Set to 1b by the transceiver when an unmasked event occurs on Hostdisconnect. Cleared when this register is read. Applicable only in host mode. Set to 1b by the transceiver when an unmasked event occurs on VbusValid. Cleared when this register is read. Set to 1b by the transceiver when an unmasked event occurs on SessValid. Cleared when this register is read. Set to 1b by the transceiver when an unmasked event occurs on SessEnd. Cleared when this register is read. Set to 1b by the transceiver when an unmasked event occurs on IdGnd. Cleared when this register is read. Read only, 0.
VbusValid Latch
1
0b
SessValid Latch
2
0b
SessEnd Latch
3
0b
IdGnd Latch
4
0b
Reserved Note 7.2
7:5
000b
rd: Read Only with auto clear.
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7.1.1.12
Debug
Address = 15h (read only)
FIELD NAME Linestate0 Linestate1 Reserved
BIT 0 1 7:2
ACCESS rd rd rd
DEFAULT 0b 0b 000000b
DESCRIPTION Contains the current value of Linestate[0]. Contains the current value of Linestate[1]. Read only, 0.
7.1.1.13
Scratch Register
Address = 16-18h (read), 16h (write), 17h (set), 18h (clear)
FIELD NAME Scratch
BIT 7:0
ACCESS rd/w/s/c
DEFAULT 00h
DESCRIPTION Empty register byte for testing purposes. Software can read, write, set, and clear this register and the transceiver functionality will not be affected.
7.1.2
Carkit Control Registers
The following registers are used to set-up and enable the USB UART and USB Audio functions.
7.1.2.1
Carkit Control
Address = 19-1Bh (read), 19h (write), 1Ah (set), 1Bh (clear) This register is used to program the USB3320 into and out of the Carkit Mode. When entering the UART mode the Link must first set the desired TxdEn and the RxdEn bits and then transition to Carkit Mode by setting the CarkitMode bit in the Interface Control Register. When RxdEn is not set then the DATA[1] pin is held to a logic high.
FIELD NAME CarkitPwr IdGndDrv TxdEn RxdEn SpkLeftEn SpkRightEn MicEn Reserved
BIT 0 1 2 3 4 5 6 7
ACCESS rd rd/w/s/c rd/w/s/c rd/w/s/c rd/w/s/c rd/w/s/c rd/w/s/c rd
DEFAULT 0b 0b 0b 0b 0b 0b 0b 0b
DESCRIPTION Read only, 0. Drives ID pin to ground Connects UART TXD (DATA[0]) to DM Connects UART RXD (DATA[1]) to DP Connects DM pin to SPK_L pin Connects DP pin to SPK_R pin. See Note below. Connects DP pin to SPK_R pin. See Note below. Read only, 0.
Note: If SpkRightEn or MicEn are asserted the DP pin will be connected to SPK_R. To disconnect the DP pin from the SPK_R pin both SpkrRightEn and MicEn must be set to de-asserted.
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If using USB UART mode the UART data will appear at the SPK_L and SPK_R pins if the corresponding SpkLeftEn, SpkRightEn, or MicEn switches are enabled. If using USB Audio the TxdEn and RxdEn bits should not be set when the SpkLeftEn, SpkRightEn, or MicEn switches are enabled. The USB single-ended receivers described in Section 5.2.1 are disabled when either SpkLeftEn, SpkRightEn, or MicEn are set.
7.1.2.2
Carkit Interrupt Enable
Address = 1D-1Fh (read), 1Dh (write), 1Eh (set), 1Fh (clear)
FIELD NAME IdFloatRise
BIT 0
ACCESS rd/w/s/c
DEFAULT 0b
DESCRIPTION When enabled an interrupt will be generated on the alt_int of the RXCMD byte when the ID pin transitions from non-floating to floating. The IdPullup bit in the OTG Control register should be set. When enabled an interrupt will be generated on the alt_int of the RXCMD byte when the ID pin transitions from floating to non-floating. The IdPullup bit in the OTG Control register should be set. Not Implemented. Reads as 0b. Not Implemented. Reads as 0b. Not Implemented. Reads as 0b. When enabled an interrupt will be generated on the alt_int of the RXCMD byte when RidConversionDone bit is asserted. Note: This register bit is or'ed with the RidIntEn bit of the Vendor Rid Conversion register described in Section 7.1.3.3.
IdFloatFall
1
rd/w/s/c
0b
CarIntDet CarDpRise CarDpFall RidIntEn
2 3 4 5
rd rd rd rd/w/s/c
0b 0b 0b 0b
Reserved
7:6
rd
00b
Read only, 0.
7.1.2.3
Carkit Interrupt Status
Address = 20h (read only)
FIELD NAME IdFloat CarIntDet CarDp
BIT 0 1 2
ACCESS rd rd rd
DEFAULT 0b 0b 0b
DESCRIPTION Asserted when the ID pin is floating. IdPullup must be enabled. Not Implemented. Reads as 0b. Not Implemented. Reads as 0b.
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FIELD NAME RidValue
BIT 5:3
ACCESS rd
DEFAULT 000b
DESCRIPTION Conversion value of Rid resistor 000: 0 ohms 001: 75 ohms 010: 102K ohms 011: 200K ohms 100: 440K ohms 101: ID floating 111: Error Note: RidValue can also be read from the Vendor Rid Conversion register described in Section 7.1.3.3.
RidConversionDone
6
rd
0b
Automatically asserted by the USB3320 when the Rid Conversion is finished. The conversion will take 282uS. This bit will auto clear when the RidValue is read from the Rid Conversion Register. Reading the RidValue from the Carkit Interrupt Status register will not clear either RidConversionDone status bit. Note: RidConversionDone can also be read from the Vendor Rid Conversion register described in Section 7.1.3.3.
Reserved
7
rd
0b
Read only, 0.
7.1.2.4
Carkit Interrupt Latch
Address = 21h (read only with auto-clear)
FIELD NAME IdFloat Latch
BIT 0
ACCESS rd (Note 7.3)
DEFAULT 0b
DESCRIPTION Asserted if the state of the ID pin changes from nonfloating to floating while the IdFloatRise bit is enabled or if the state of the ID pin changes from floating to non-floating while the IdFloatFall bit is enabled. Not Implemented. Reads as 0b. Not Implemented. Reads as 0b. If RidIntEn is set and the state of the RidConversionDone bit changes from a 0 to 1 this bit will be asserted. Read only, 0.
CarIntDet Latch CarDp Latch RidConversionLatch
1 2 3
rd rd rd (Note 7.3) rd
0b 0b 0b
Reserved Note 7.3
7:4
0000b
rd: Read Only with auto clear
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7.1.3
Vendor Register Access
The vendor specific registers include the range from 30h to 3Fh. These can be accessed by the ULPI immediate register read / write.
7.1.3.1
HS TX Boost
Address = 31h (read / write)
FIELD NAME Reserved Boost
BIT 4:0 6:5
ACCESS rd rd/w
DEFAULT 00000b 00b
DESCRIPTION Read only, 0. Sets the HS transmitter amplitude as described in Section 5.2.1. 00b: Nominal 01b: Enables 11.1% increased drive strength 10b: Enables 7.4% increased drive strength 11b: Enables 3.7% increased drive strength Read only, 0.
Reserved
7
rd
0b
7.1.3.2
Headset Audio Mode
Address = 33h (read / write)
FIELD NAME HeadsetAudioEn Reserved
BIT 3:0 7:4
ACCESS rd/w rd
DEFAULT 0000b 0h
DESCRIPTION When this field is set to a value of 1010, the Headset Audio Mode is enabled as described in Section 6.7. Read only, 0.
7.1.3.3
Vendor Rid Conversion
Address = 36-38h (read), 36h (write), 37h (set), 38h (clear)
FIELD NAME RidValue
BIT 2:0
ACCESS rd/w
DEFAULT 000b
DESCRIPTION Conversion value of Rid resistor 000: 0 ohms 001: 75 ohms 010: 100K ohms 011: 200K ohms 100: 440K ohms 101: ID floating 111: Error Note: RidValue can also be read from the Carkit Interrupt Status Register.
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FIELD NAME RidConversionDone
BIT 3
ACCESS rd (Note 7.4)
DEFAULT 0b
DESCRIPTION Automatically asserted by the USB3320 when the Rid Conversion is finished. The conversion will take 282uS. This bit will auto clear when the RidValue is read from the Rid Conversion Register. Reading the RidValue from the Carkit Interrupt Status Register will not clear either RidConversionDone status bit. Note: RidConversionDone can also be read from the Carkit Interrupt Status Register.
RidConversionStart
4
rd/w/s/c
0b
When this bit is asserted either through a register write or set, the Rid converter will read the value of the ID resistor. When the conversion is complete this bit will auto clear. This bit must remain at 0. When enabled an interrupt will be generated on the alt_int of the RXCMD byte when RidConversionDone bit is asserted. Note: This register bit is or'ed with the RidIntEn bit of the Carkit Interrupt Status register.
Reserved RidIntEn
5 6
rd/w/s/c rd/w/s/c
0b 0b
Reserved Note 7.4
7
rd
0b
Read only, 0.
rd: Read Only with auto clear.
7.1.3.4
USB IO & Power Management
Address = 39-3Bh (read), 39h (write), 3Ah (set), 3Bh (clear)
FIELD NAME Reserved SwapDP/DM
BIT 0 1
ACCESS rd/w/s/c rd/w/s/c
DEFAULT 0b 0b
DESCRIPTION Read only, 0. When asserted, the DP and DM pins of the USB transceiver are swapped. This bit can be used to prevent crossing the DP/DM traces on the board. In UART mode, it swaps the routing to the DP and DM pins. In USB Audio Mode, it does not affect the SPK_L and SPK_R pins. Controls the output voltage of the VBAT to VDD33 regulator in UART mode. When the transceiver is switched from USB mode to UART mode regulator output will automatically change to the value specified in this register when TxdEn is asserted. 00: 3.3V 01: 3.0V (default) 10: 2.75V 11: 2.5V Note: When in USB Audio Mode the regulator will remain at 3.3V. When using this register it is recommended that the Link exit UART mode by using the RESETB pin.
UART RegOutput
3:2
rd/w/s/c
01b
ChargerPullupEnDP
4
rd/w/s/c
0b
Enables a Pull-up for USB Charger Detection when set on the DP pin. (The pull-up is automatically enabled in UART mode)
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FIELD NAME ChargerPullupEnDM
BIT 5
ACCESS rd/w/s/c
DEFAULT 0b
DESCRIPTION Enables a Pull-up for USB Charger Detection when set on the DM pin. (The pull-up is automatically enabled in UART mode) Controls the output voltage of the VBAT to VDD33 regulator in USB mode. When the transceiver is in Synchronous Mode, Serial Mode, or Low Power Mode, the regulator output will be the value specified in this register. 00: 3.3V (default) 01: 3.0V 10: 2.75V 11: 2.5V
USB RegOutput
7:6
rd/w/s/c
00b
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Chapter 8 Application Notes
8.1 Application Diagram
The USB3320 requires few external components as shown in the application diagrams. The USB 2.0 Specification restricts the voltage at the VBUS pin to a maximum value of 5.25V. In some applications, the voltage will exceed this voltage, and the USB3320 provides an integrated overvoltage protection circuit. The overvoltage protection circuit works with an external resistor (RVBUS) to lower the voltage at the VBUS pin, as described in Section 5.6.2.6. Following POR or hardware reset, the voltage at CLKOUT must not exceed VIH_ED as provided in Table 4.4. Table 8.1 Component Values in Application Diagrams REFERENCE DESIGNATOR COUT CVBUS
VALUE 2.2F See Table 8.2
DESCRIPTION Bypass capacitor to ground (<1 ESR) for regulator stability. Capacitor to ground required by the USB Specification. SMSC recommends <1 ESR. Bypass capacitor to ground. Typical values used are 0.1 or 0.01 F. The USB connector housing may be ACcoupled to the device ground. Series resistor to work with internal overvoltage protection. 10k in device applications. See Table 5.7 for required values in Host or OTG applications. Series resistor to establish reference voltage.
NOTES Place as close as possible to the transceiver. Place near the USB connector.
CBYP CDC_LOAD
System dependent. System dependent. 1k or 10k
Place as close as possible to the transceiver. Industry convention is to ground only the host side of the cable shield. See Section 5.6.2.6 for information regarding power dissipation.
RVBUS
RBIAS
8.06k (1%)
See Section 5.3 for information regarding power dissipation.
Table 8.2 Capacitance Values at VBUS of USB Connector MODE Host Device OTG MIN VALUE 120F 1F 1F 10F 6.5F MAX VALUE
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VDDIO Supply
RVBUS must be installed to enable overvoltage protection of the VBUS pin. RVBUS 14 11 8 22 17 25 21 CBYP 20 CVBUS COUT 23 19 18 15 CDC_BLOCK 16
REFSEL2 REFSEL1 REFSEL0 VBUS CPEN XO VBAT VDD33
Link Controller
RESETB DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0 STP NXT DIR CLKOUT
27 13 10 9 7 6 5 4 3 29 2 31 1 Signal at REFCLK must comply with VIH and VIL
RESETB DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0 STP NXT DIR CLKIN REFCLK VDDIO Supply
3.1-5.5V Supply
The capacitor CVBUS must be installed on this side of RVBUS.
USB Receptacle
REFCLK 26 ID DM DP SPK_L SPK_R RBIAS 24 GND
VBUS DM DP SHIELD GND
1.8V Supply VDD18 28, 30
CBYP
VDDIO 32
CBYP
RBIAS
Optional Switched Signal to DP/DM
Figure 8.1 USB3320 Application Diagram (Device, ULPI Output Clock mode, 24MHz)
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VDDIO Supply
RVBUS must be installed to enable overvoltage protection of the VBUS pin. RVBUS 14 11 8 22 17 25 21 CBYP 20 CVBUS COUT
REFSEL2 REFSEL1 REFSEL0 VBUS CPEN XO VBAT VDD33
Link Controller
RESETB DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0 STP NXT DIR
27 13 10 9 7 6 5 4 3 29 2 31
RESETB DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0 STP NXT DIR CLKOUT VDDIO Supply
3.1-5.5V Supply
The capacitor CVBUS must be installed on this side of RVBUS.
USB Receptacle
REFCLK 26
23 19 18 15
VBUS DM DP SHIELD GND
CDC_BLOCK
ID DM DP SPK_L SPK_R RBIAS GND
ULPI Clock In Mode
CLKOUT 1 VDDIO 32
1.8V Supply VDD18 28, 30
CBYP 24 RBIAS
CBYP
16
Optional Switched Signal to DP/DM
Figure 8.2 USB3320 Application Diagram (Device, ULPI Input Clock mode, 60MHz)
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VDDIO Supply
14 11 8 17 RVBUS must be installed to enable overvoltage protection of the VBUS pin. RVBUS
REFSEL2 REFSEL1 REFSEL0 CPEN
Link Controller
RESETB DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0 STP NXT DIR CLKOUT XO
27 13 10 9 7 6 5 4 3 29 2 31 1 25 1M
RESETB DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0 STP NXT DIR CLKIN Resonator
VBUS Switch
EN 5V IN OUT
22
VBUS
The capacitor CVBUS must be installed on this side of RVBUS.
3.1-5.5V Supply
21 CBYP 20 CVBUS COUT
VBAT VDD33 REFCLK
26
- or Crystal and Caps
USB Receptacle
VBUS ID DM DP SHIELD GND
23 19 18 15 16
CLOAD
ID DM DP SPK_L SPK_R VDDIO VDD18 RBIAS GND
32
VDDIO Supply 1.8V Supply
28, 30 CBYP 24 RBIAS CBYP
For Host applications (non-OTG), the ID pin should be connected to GND.
Optional Switched Signal to DP/DM
Figure 8.3 USB3320 Application Diagram (Host or OTG, ULPI Output Clock Mode, 24MHz)
8.2
Reference Designs
SMSC has generated reference designs for connecting the USB3320 to SOCs with a ULPI port. Please contact the SMSC sales office for more details.
8.3
ESD Performance
The USB3320 is protected from ESD strikes. By eliminating the requirement for external ESD protection devices, board space is conserved, and the board manufacturer is enabled to reduce cost. The advanced ESD structures integrated into the USB3320 protect the device whether or not it is powered up.
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8.3.1
Human Body Model (HBM) Performance
HBM testing verifies the ability to withstand the ESD strikes like those that occur during handling and manufacturing, and is done without power applied to the IC. To pass the test, the device must have no change in operation or performance due to the event. All pins on the USB3320 except the REFCLK, SPK_L, and SPK_R pins provide 8kV HBM protection, as shown in Table 4.10.
8.3.2
EN/IEC 61000-4-2 Performance
The EN/IEC 61000-4-2 ESD specification is an international standard that addresses system-level immunity to ESD strikes while the end equipment is operational. In contrast, the HBM ESD tests are performed at the device level with the device powered down. SMSC contracts with Independent laboratories to test the USB3320 to EN/IEC 61000-4-2 in a working system. Reports are available upon request. Please contact your SMSC representative, and request information on 3rd party ESD test results. The reports show that systems designed with the USB3320 can safely provide the ESD performance shown in Table 4.10 without additional board level protection. In addition to defining the ESD tests, EN/IEC 61000-4-2 also categorizes the impact to equipment operation when the strike occurs (ESD Result Classification). The USB3320 maintains an ESD Result Classification 1 or 2 when subjected to an EN/IEC 61000-4-2 (level 4) ESD strike. Both air discharge and contact discharge test techniques for applying stress conditions are defined by the EN/IEC 61000-4-2 ESD document.
8.3.3
Air Discharge
To perform this test, a charged electrode is moved close to the system being tested until a spark is generated. This test is difficult to reproduce because the discharge is influenced by such factors as humidity, the speed of approach of the electrode, and construction of the test equipment.
8.3.4
Contact Discharge
The uncharged electrode first contacts the USB connector to prepare this test, and then the probe tip is energized. This yields more repeatable results, and is the preferred test method. The independent test laboratories contracted by SMSC provide test results for both types of discharge methods.
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Chapter 9 Package Outline, Tape & Reel Drawings, Package Marking
The USB3320 is offered in a compact 32 pin lead-free QFN package.
Figure 9.1 USB3320 32 Pin QFN Package Outline, 5 x 5 x 0.9 mm Body (Lead-Free) Table 9.1 32 Terminal QFN Package Parameters A A1 A2 A3 D D1 D2 E E1 E2 L e b ccc MIN 0.70 0 ~ 4.85 4.55 3.15 4.85 4.55 3.15 0.30 0.18 ~ NOMINAL ~ 0.02 ~ 0.20 REF 5.0 ~ 3.3 5.0 ~ 3.3 ~ 0.50 BSC 0.25 ~ MAX 1.00 0.05 0.90 5.15 4.95 3.45 5.15 4.95 3.45 0.50 0.30 0.08 REMARKS Overall Package Height Standoff Mold Thickness Copper Lead-frame Substrate X Overall Size X Mold Cap Size X exposed Pad Size Y Overall Size Y Mold Cap Size Y exposed Pad Size Terminal Length Terminal Pitch Terminal Width Coplanarity
Notes: 1. Controlling Unit: millimeter. 2. Dimension b applies to plated terminals and is measured between 0.15mm and 0.30mm from the terminal tip. Tolerance on the true position of the leads is 0.05 mm at maximum material conditions (MMC). 3. Details of terminal #1 identifier are optional but must be located within the zone indicated. 4. Coplanarity zone applies to exposed pad and terminals.
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Figure 9.2 QFN, 5x5 Taping Dimensions and Part Orientation
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Figure 9.3 Reel Dimensions for 12mm Carrier Tape
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Figure 9.4 Tape Length and Part Quantity Note: Standard reel size is 4000 pieces per reel.
Figure 9.5 Package Marking
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Chapter 10 Revision History
Table 10.1 Customer Revision History REVISION LEVEL & DATE Rev. 1.0 (07-14-09) SECTION/FIGURE/ENTRY Initial Release CORRECTION
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