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TM
HM-6642/883
512 x 8 CMOS PROM
Description
The HM-6642/883 is a 512 x 8 CMOS NiCr fusible link Programmable Read Only Memory in the popular 24 pin, byte wide pinout. Synchronous circuit design techniques combine with CMOS processing to give this device high speed performance with very low power dissipation. On-chip address latches are provided, allowing easy interfacing with recent generation microprocessors that use multiplexed address/data bus structures, such as the 8085. The output enable controls, both active low and active high, further simplify microprocessor system interfacing by allowing output data bus control independent of the chip enable control. The data output latches allow the use of the HM6642/883 in high speed pipelined architecture systems, and also in synchronous logic replacement functions. Applications for the HM-6642/883 CMOS PROM include low power hand held microprocessor based instrumentation and communications systems, remote data acquisition and processing systems, processor control store, and synchronous logic replacement. All bits are manufactured storing a logical "0" and can be selectively programmed for a logical "1" at any bit location.
March 1997
Features
* This Circuit is Processed in Accordance to MIL-STD883 and is Fully Conformant Under the Provisions of Paragraph 1.2.1. * Low Power Standby and Operating Power - ICCSB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100A - ICCOP . . . . . . . . . . . . . . . . . . . . . . . . . . 20mA at 1MHz * Fast Access Time . . . . . . . . . . . . . . . . . . . . . 120/200ns * Wide Operating . . . . . . . . . . . . . . . . . . -55oC to +125oC * Temperature Range * Industry Standard Pinout * Single 5.0V Supply * CMOS/TTL Compatible Inputs * Field Programmable * Synchronous Operation * On-Chip Address Latches * Separate Output Enable
\Ordering
Information
TEMP. RANGE 120ns 200ns HM16642/883 HM66642/883 HM46642/883 PKG. NO. D24.6 D24.3 J28.A
PACKAGE SBDIP SLIM SBDIP CLCC
-55oC to +125oC HM16642B/883 -55oC to +125oC HM66642B/883 -55oC to +125oC -
Pinouts
M-6642/883 (BDIP) TOP VIEW
A5 A7 A6 A5 A4 A3 A2 A1 A0 Q0 Q1 Q2 GND 1 2 3 4 5 6 7 8 9 10 11 12 24 VCC 23 A8 22 G1 21 G2 20 G3 19 E 18 P 17 Q7 16 Q6 15 Q5 14 Q4 13 Q3 A1 A0 NC Q0 8 9 10 11 12 Q1 13 Q2 14 GND 15 NC 16 Q3 17 Q4 18 Q5 22 P 21 NC 20 Q7 19 Q6 A4 A3 A2 5 6 7
HM-6642/883 (CLCC) TOP VIEW
VCC NC A7 G1 A6 A8
PIN DESCRIPTION PIN NC
25 G2 24 G3 23 E
DESCRIPTION No Connect Address Inputs Chip Enable Data Output Power (+5V)
4
3
2
1
28
27
26
A0-A8 E Q VCC
G1, G2, G3 Output Enable P (Note) Program Enable
NOTE: P should be hardwired to GND except during programming.
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a trademark of Intersil Americas Inc. Copyright (c) Intersil Americas Inc. 2002. All Rights Reserved
FN3013.1
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HM-6642/883 Functional Diagram
A8 A7 A6 A5 A4 A3 LATCHED ADDRESS REGISTER
A 6 A 6 GATED ROW DECODER 64 x 64 MATRIX ALL LINES POSITIVE LOGIC - ACTIVE HIGH THREE STATE BUFFERS: A HIGH OUTPUT ACTIVE 8 A 8 8 8 8 8 8 8 DATA LATCHES: L HIGH Q=D Q LATCHES ON RISING EDGE OF E ADDRESS LATCHES AND GATED DECODERS: LATCH ON FALLING EDGE OF E GATE ON FALLING EDGE OF E P SHOULD BE HARDWIRED TO GND EXCEPT DURING PROGRAMMING 8-BIT DATA LATCH
64
A2 A1 A0
LATCHED ADDRESS REGISTER
3 A 3 D
GATED COLUMN DECODER
E
G1 G2 G3 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
244
HM-6642/883
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7.0V Input, Output or I/O Voltage . . . . . . . . . . . . GND-0.3V to VCC+0.3V Typical Derating Factor . . . . . . . . . . . 5mA/MHz Increase in ICCOP ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1
Thermal Information
Thermal Resistance (Typical) JA JC SBDIP Package. . . . . . . . . . . . . . . . . . 52oC/W 14oC/W Slim SBDIP . . . . . . . . . . . . . . . . . . . . . 70oC/W 19oC/W CLCC Package . . . . . . . . . . . . . . . . . . 58oC/W 14oC/W Maximum Storage Temperature Range . . . . . . . . .-65oC to +150oC Maximum Junction Temperature. . . . . . . . . . . . . . . . . . . . . . +175oC Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . +300oC
Operating Conditions
Operating Voltage Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5V Operating Temperature Range. . . . . . . . . . . . . . . . -55oC to +125oC Input Low Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +0.8V Input High Voltage . . . . . . . . . . . . . . . . . . . . . . . . . 2.4 to VCC+0.3V
Die Characteristics
Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1680 Gates
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
TABLE 1. HM-6642/883 DC ELECTRICAL PERFORMANCE SPECIFICATIONS Device Guaranteed and 100% Tested LIMITS PARAMETER High Level Output Voltage Low Level Output Voltage High Impedance Output Leakage Current Input Leakage Current Standby Supply Current Operating Supply Current SYMBOL VOH (NOTES 1, 4) CONDITIONS VCC = 4.5V, IO = -1.0mA VCC = 4.5V, IO = +3.2mA VCC = 5.5V, G = 5.5V, VI/O = GND or VCC GROUP A SUBGROUPS 1, 2, 3 TEMPERATURE -55oC TA +125oC -55oC TA +125oC -55oC TA +125oC MIN 2.4 MAX UNITS V
VOL
1, 2, 3
-
0.4
V
IIOZ
1, 2, 3
-1.0
1.0
A
II
VCC = 5.5V, VI = GND or VCC, P Not Tested VI = VCC or GND, VCC = 5.5V, IO = 0mA VCC = 5.5V, G = GND, G = VCC, (Note 3), f = 1MHz,IO = 0mA, VI = VCC or GND VCC = 4.5V (Note 5)
1, 2, 3
-55oC TA +125oC -55oC TA +125oC -55oC TA +125oC
-1.0
1.0
A A
ICCSB
1, 2, 3
-
100
ICCOP
1, 2, 3
-
20
mA
Functional Test
FT
7, 8A, 8B
-55oC TA +125oC
-
-
-
TABLE 2. HM-6642/883 AC ELECTRICAL PERFORMANCE SPECIFICATIONS Device Guaranteed and 100% Tested LIMITS GROUP A SUBGROUPS 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 HM6642B/883 TEMPERATURE -55oC TA +125oC -55oC TA +125oC -55oC TA +125oC -55oC TA +125oC -55oC TA +125oC -55oC TA +125oC -55oC TA +125oC MIN 20 25 120 40 HM6642/883 MAX 220 150 200 UNITS ns ns ns ns ns ns ns
PARAMETER Address Access Time Output Enable Access Time Chip Enable Access Time Address Setup Time Address Hold Time Chip Enable Low Width Chip Enable High Width
SYMBOL TAVQV TGVQV TELQV TAVEL TELAX TELEH TEHEL
(NOTES 1, 2, 4) CONDITIONS VCC = 4.5V and 5.5V VCC = 4.5V and 5.5V VCC = 4.5V and 5.5V VCC = 4.5V and 5.5V VCC = 4.5V and 5.5V VCC = 4.5V and 5.5V VCC = 4.5V and 5.5V
MAX MIN 140 50 120 20 60 200 150
245
HM-6642/883
TABLE 2. HM-6642/883 AC ELECTRICAL PERFORMANCE SPECIFICATIONS (Continued) Device Guaranteed and 100% Tested LIMITS GROUP A SUBGROUPS 9, 10, 11 HM6642B/883 TEMPERATURE -55oC TA +125oC MIN 160 HM6642/883 MAX UNITS ns
PARAMETER Read Cycle Time NOTES:
SYMBOL TELEL
(NOTES 1, 2, 4) CONDITIONS VCC = 4.5V and 5.5V
MAX MIN 350
1. All voltages referenced to VSS. 2. A.C. measurements assume transition time < 5ns; input levels = 0.0V to 3.0V; timing reference levels = 1.5V; output load = 1TTL equivalent load and CL 50pF. 3. Typical derating = 5mA/MHz increase in ICCOP. 4. All tests performed with P hardwired to GND. 5. Tested as follows: f = 1MHz, VIH = 2.4V, VIL = 0.8V, IOH = -1mA, IOL = +1mA, VOH 1.5V, VOL 1.5V. TABLE 3. APPLICABLE SUBGROUPS CONFORMANCE GROUPS Initial Test Interim Test PDA Final Test Group A Groups C & D METHOD 100%/5004 100%/5004 100%/5004 100%/5004 Samples/5005 Samples/5005 SUBGROUPS 1, 7, 9 1 2, 3, 7, 8A, 8B, 10, 11 1, 2, 3, 7, 8A, 8B, 9, 10, 11 1, 7, 9
Switching Waveform
TAVQV TAVEL A TELAX ADD VALID TELEL TEHEL E TELQV TELEH TEHEL TAVEL NEXT ADD
Q TGVQX TGXQZ TGVQV G (NOTE) TIME REFERENCE -1 0 1 2
DATA VALID TGXQZ
3
456
NOTE: G has the same timing as G except signal is inverted. FIGURE 1. READ CYCLE
246
HM-6642/883 Test Load Circuit
DUT CL (NOTE)
IOH NOTE: TEST HEAD CAPACITANCE, INCLUDES STRAY AND JIG CAPACITANCE
1.5V
IOL
EQUIVALENT CIRCUIT
FIGURE 2. TEST LOAD CIRCUIT
Burn-In Circuits
HM-6642/883 (0.300 INCH) SBDIP
VCC C F8 F7 F6 F5 F4 F3 F2 F1 2.4K 2.4K VCC / 2 2.4K 1 2 3 4 5 6 7 8 9 A7 A6 A5 A4 A3 A2 A1 A0 Q0 VCC 24 A8 23 G1 22 G2 21 G3 20 E 19 P 18 Q7 17 Q6 16 Q5 15 Q4 14 Q3 13 2.4K 2.4K 2.4K 2.4K 2.4K VCC / 2 VCC / 2 F9 F10 F11 F12 F0 GND F10 F9 F8 F7 F6 F5 F4 F3 1 2 3 4 5 6 7 8 9 A7 A6 A5 A4 A3 A2 A1 A0 Q0 VCC A8 G1 G2 G3 E P Q7 Q6 Q5 Q4 Q3 24 23 22 21 20 19 18 17 16 15 14 13 VCC / 2 VCC F9 F10 F11 F12 F0 GND
HM-6642/883 (0.600 INCH) SBDIP
C
10 Q1 11 Q2 12 GND
10 Q1 11 Q2 12 GND
247
HM-6642/883 Burn-In Circuits
(Continued) HM-6642/883 CLCC
VCC
4 F5 F4 F3 F2 F1 5 6 7 8 9 NC 10 11
3
2
NC
C
1
28
27 26 25 24 23 22 21 NC 20 19 F11 F12 F0
12 13 14 15 16 17 18 NC VCC 1.5K 1.5K 1.5K 1.5K 1.5K 1.5K 1.5K 1.5K R1
F10
F6
F7
F8
F9
820 820 820 820 820 820 820 820 R2
NOTES: 1. F0 = 100kHz 10%. 2. All Resistors = 47k. 3. Unless Otherwise Noted. 4. VCC = 5.5V 0.5V. 5. VIL = 4.5V 10%. 6. C = 0.01F Min.
248
HM-6642/883 Die Characteristics
DIE DIMENSIONS: 136 x 168 x 19 1mils METALLIZATION: Type: Si - Al Thickness: 11kA 15kA GLASSIVATION: Type: SiO2 Thickness: 8kA 1kA WORST CASE CURRENT DENSITY: 1.7 x 105 A/cm 2
Metallization Mask Layout
HM-6642/883
A4 A5
A6 A7
VCC
A8
G1
G2
A3 A2
G3 E
P
A1 A0 Q0 Q1 Q2 GND Q3 Q4 Q5 Q6 Q7
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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