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| www..com VIS Description VG26(V)(S)17405 4,194,304 x 4 - Bit CMOS Dynamic RAM The device CMOS Dynamic RAM organized as 4,194,304 words x 4 bits with extended data out access mode. It is fabricated with an advanced submicron CMOS technology and designed to operate from a single 5V only or 3.3V oniy power supply. Low voltage operation is more suitable to be used on battery backup, portable electronic application. A new refresh feature called "self-refresh" is supported and very slow CBR cycles are being performed. lt is packaged in JEDEC standard 26/24-pin plastic SOJ or TSOP(II). Features * Single 5V( 10 %) or 3.3V( 10 %) only power supply * High speed tRAC acess time: 50/60ns * Low power dissipation - Active wode : 5V version 660/605 mW (Mas) 3.3V version 432/396 mW (Mas) - Standby mode: 5V version 1.375 mW (Mas) 3.3V version 0.54 mW (Mas) * Extended - data - out(EDO) page mode access * I/O level: TTL compatible (Vcc = 5V) LVTTL compatible (Vcc = 3.3V) .com * 2048 refresh cycle in 32 ms(Std.) or 128 ms(S-version) * 4 refresh modesh: - RAS only refresh - CAS - before - RAS refresh - Hidden refresh - Self-refresh(S-version) DataShe e .com Document:1G5-0124 Rev.1 Page 1 DataSheet4 U .com www..com VIS Pin Configuration 26/24-PIN 300mil Plastic SOJ VG26(V)(S)17405 4,194,304 x 4 - Bit CMOS Dynamic RAM 26/24-PIN 300mil Plastic TSOP (ll) VCC DQ1 DQ2 WE RAS NC A10 A0 A1 A2 A3 VCC 1 2 3 4 5 6 8 9 10 11 12 13 26 25 24 23 22 21 19 18 17 16 15 14 VSS DQ4 DQ3 CAS OE A9 A8 A7 A6 A5 A4 VSS VCC DQ1 DQ2 WE RAS NC A10 A0 A1 A2 A3 VCC 1 2 3 4 5 6 8 9 10 11 12 13 26 25 24 23 22 21 19 18 17 16 15 14 VSS DQ4 DQ3 CAS OE A9 A8 A7 A6 A5 A4 VSS VG26(V)(S)17405T VG26(V)(S)17405J t4U.com Pin Description Pin Name A0-A10 Function Address inputs - Row address - Column address - Refresh address Data-in / data-out Row address strobe Column address strobe Write enable Output enable Power (+5 V or + 3.3V) Ground .com DataShe e A0-A10 A0-A10 A0-A10 DQ1~DQ4 RAS CAS WE OE Vcc Vss .com Document:1G5-0124 Rev.1 Page 2 DataSheet4 U .com www..com VIS VG26(V)(S)17405 4,194,304 x 4 - Bit CMOS Dynamic RAM Block Diagram WE CAS CONTROL LOGIC DATA-IN BUFFER DQ1 . . DQ4 NO. 2 CLOCK GENERATOR DATA-OUT BUFFER OE COLUMN ADDRESS BUFFERS (11) A0 A1 A2 COLUMN DECODER t4U.com A3 A4 A5 A6 A7 A8 A9 REFRESH CONTROLLER 2048 .com SENSE AMPLIFIERS I/O GATING DataShe e REFRESH COUNTER 2048x4 ROW DECODER A10 ROW ADDRESS BUFFERS (11) 2048x2048x4 MEMORY ARRAY 2048 RAS NO. 1 CLOCK GENERATOR Vcc Vss .com Document:1G5-0124 Rev.1 Page 3 DataSheet 4 U .com www..com VIS TRUTH TABLE ADDRESSES FUNCTION RAS STANDBY READ WRITE: (EARLY WRITE ) READ WRITE EDO-PAGEMODE READ 1st Cycle 2nd Cycle EDO-PAGE 1st Cycle MODE WRITE 2nd Cycle EDOPAGE-MODE READ-WRITE HIDDEN REFRESH 1st Cycle 2nd Cycle READ WRITE H L L L L L L L L L L H L L H L L HL CAS HX L L L HL HL HL HL HL HL L L H L WE X H L HL H H L L HL HL H L X H OE X L X LH L L X X ROW X ROW ROW ROW ROW n/a ROW n/a ROW n/a ROW ROW ROW X COL X COL COL COL COL COL COL COL COL COL COL COL n/a X High-Z Data-Out Data-ln Data-Out,Data-ln Data-Out Data-Out Data-In Data-In Data-Out, Data-In Data-Out, Data-In Data-Out Data-In High-Z High-Z DQS VG26(V)(S)17405 4,194,304 x 4 - Bit CMOS Dynamic RAM Notes LH LH L X X 1 t4U.com RAS-ONLY REFRESH CBR REFRESH .com X DataShe e Notes: 1. EARLY WRITE only. .com Document:1G5-0124 Rev.1 Page 4 DataSheet4 U .com www..com VIS Absolute Maximum Ratings VG26(V)(S)17405 4,194,304 x 4 - Bit CMOS Dynamic RAM Parameter 5V Voltage on any pin relative to Vss 3.3V 5V Supply voltage relative to Vss 3.3V Short circuit output current Power dissipation Operating temperature Storage temperature Symbol VT Value -1.0 to + 7.0 -0.5 to + 4.6 -1.0 to + 7.0 Unit V V VCC -0.5 to + 4.6 IOUT PD TOPT TSTG 50 1.0 0 to + 70 -55 to + 125 mA W C C Recommended DC Operating Conditions Parameter/Condition Symbol Min 5 Volt Version Typ 5.0 Max 5.5 Min 3.3 Volt Version Typ 3.3 Max 3.6 Unit Supply Voltage Input High Voltage, all inputs VCC VIH VIL 4.5 2.4 -1.0 3.0 2.0 -0.3 V V V - VCC + 1.0 0.8 - VCC + 0.3 0.8 t4U.com Input Low Voltage, all inputs .com DataShe e Capacitance Ta = 25C, VCC = 5V 10 % or 3.3V 10 %, f = 1MHz Parameter Input capacitance (Address) Input capacitance (RAS, CAS, OE, WE) Output capacitance (Data-in, Data-out) Symbol CI1 CI2 CI/O Typ - Max 5 7 7 Unit pF pF pF Note 1 1 1, 2 Note: 1. Capacitance measured with effective capacitance measuring method. 2. RAS, CAS = V IH to disable Dout. .com Document:1G5-0124 Rev.1 Page 5 DataSheet4 U .com www..com VIS DC Characteristics; 5- Volt Verion (Ta = 0 to + 70 C, VCC= + 5V 10 %,VSS = 0V) Parameter Symbol Test Conditions VG26(V)(S)17405 -5 Min Operating current ICC1 RAS cycling CAS, cycling tRC = min TTL interface RAS, CAS = VIH Dout = High-Z CMOS interface Standby Current ICC2 Standard power version RAS, CAS Vcc -0.2V Dout = High-Z TTL interface RAS, CAS = VIH Dout = High-Z CMOS interface RAS, CAS Vcc -0.2V Dout = High-Z 2 Max 120 Min -6 VG26(V)(S)17405 4,194,304 x 4 - Bit CMOS Dynamic RAM Unit Notes Max 110 mA 1, 2 LOW power S-version - 2 - 2 mA - 0.25 - 0.25 mA 2 mA 1 - 1 mA t4U.com RAS-only refresh current EDO page mode current CAS-before-RAS refresh current Self-refresh current (S - Version) CAS- before- RAS long refresh current (S-Version) ICC3 ICC4 ICC5 ICC8 ICC9 RAS cycling, CAS = VIH .com tRC = min tRC = min tRC = min RAS, CAS cycling tRAS 100s Standby: VCC- 0.2V RAS CAS before RAS refresh: 2048 cycles / 128ms RAS, CAS: 0V V IL 0.2V VCC- 0.2V V IH V IH (Max) Dout = High-Z, t RAS 300ns - 120 - 110 mA 1, 2 DataShe e - 90 120 350 500 - 80 110 350 500 mA mA A A 1, 3 1, 2 .com Document:1G5-0124 Rev.1 Page 6 D a t 4S a U. h c eet om www..com VIS DC Characteristics ; 5-Volt Version (Cont.) (Ta = 0 to + 70C, VCC = + 5V 10 %,VSS = 0V) VG26(V)(S) 17405 -5 Parameter Input leakage current Output leakage current Symbol ILI ILO VOH VOL Test Conditions 0V V I N V C C + 0.5V 0V V OUT V CC + 0.5V Dout = Disable Output high Voltage Output low voltage IOH = - 5mA IOL = + 4.2mA 2.4 0.4 2.4 Min -5 -5 Max 5 5 Min -5 -5 -6 VG26(V)(S)17405 4,194,304 x 4 - Bit CMOS Dynamic RAM Max 5 5 Unit A A V V Notes 0.4 Notes: 1. ICC is specified as an average current. It depends on output loading condition and cycle rate when the device is selected. ICC max is specified at the output open condition. 2. Address can be changed once or less while RAS = VIL. 3. For ICC4, address can be changed once or less within one EDO page mode cycle time. t4U.com .com DataShe e .com Document:1G5-0124 Rev.1 Page 7 DataSheet4 U .com www..com VIS DC Characteristics ; 3.3 - Volt Version (Ta = 0 to 70C, VCC = + 3.3V 10 %, VSS = 0V) VG26(V)(S)17405 4,194,304 x 4 - Bit CMOS Dynamic RAM Parameter Symbol Test Conditions VG26(V)(S)17405 -5 Min Max 120 Min -6 Max 110 Unit Notes Operating current ICC1 RAS cycling CAS, cycling tRC = min LVTTL interface RAS, CAS = VIH Dout = High-Z CMOS interface RAS, CAS V C C -0.2V Dout = High-Z - mA 1, 2 LOW power S-version ICC2 - 0.5 - 0.5 mA - 0.15 - 0.15 mA Standby Current Standard power version LVTTL interface RAS, CAS = VIH Dout = High-Z CMOS interface RAS, CAS V C C -0.2V Dout = High-Z ICC3 ICC4 ICC5 ICC8 ICC9 RAS cycling, CAS = VIH tRC = min tPC = min tRC = min RAS, CAS cycling t RASS 100s Standby: VCC- 0.2V RAS CAS before RAS refresh: 2048 cycles / 128ms RAS, CAS: 0V V IL 0.2V VCC- 0.2V V IH V IH (max) Dout = High-Z, tRAS 300ns - 2 - 2 mA - 0.5 - 0.5 mA t4U.com RAS- only refresh current EDO page mode current CAS- before- RAS refresh current Self- refresh current (S-Version) CAS- before- RAS long refresh current (S-Version) .com 120 90 120 250 300 110 80 110 250 300 mA mA mA A A 1, 2 1, 3 1, 2 DataShe e .com Document:1G5-0124 Rev.1 Page 8 D a t 4S a U. h c eet om www..com VIS DC Characteristics ; 3.3 - Volt Version (Cont.) (Ta = 0 to 70C, VCC= +3.3V 10 %, VSS= 0V) VG26(V)(S) 17405 -5 Parameter Input leakage current Output leakage current Symbol ILI ILO VOH VOL Test Conditions 0V Vin V C C + 0.3V 0V Vout V CC + 0.3V Dout = Disable Output high Voltage Output low voltage IOH = -2mA IOL = +2mA 2.4 0.4 2.4 Min -5 -5 Max 5 5 Min -5 -5 -6 VG26(V)(S)17405 4,194,304 x 4 - Bit CMOS Dynamic RAM Unit Max 5 5 A A V V Notes 0.4 Notes: 1. ICC is specified as an average current. It depends on output loading condition and cycle rate when the device is selected. ICC max is specified at the output open condition. 2. Address can be changed once or less while RAS = VIL. 3. For I CC4, address can be changed once or less within one EDO page mode cycle time. t4U.com .com DataShe e .com Document:1G5-0124 Rev.1 Page 9 DtSet a he a 4 U .o cm www..com VIS AC Characteristics (Ta = 0 to + 70C, Vcc = 5V 10 % or 3.3V 10 %, Vss = 0V) *1, *2, *3, *4 VG26(V)(S)17405 4,194,304 x 4 - Bit CMOS Dynamic RAM Test conditions * Output load: two TTL Loads and 100pF (VCC = 5.0V 10 %) one TTL Load and 100pF (VCC = 3.3V 10 %) * Input timing reference levels: VIH = 2.4V, VIL = 0.8V (VCC = 5.0V 10 %); VIH = 2.0V, VIL = 0.8V (VCC = 3.3V 10 %) * Output timing reference levels: VOH = 2.0V, VOL = 0.8V (VCC = 5V 10 %, 3.3V 10 %) Read, Write, Read- Modify- Write and Refresh Cycles (Common Parameters) VG26(V)(S) 17405 -5 Parameter Random read or write cycle time RAS precharge time Symbol tRC tRP Min 84 30 Max Min 104 40 10 60 10 0 10 0 10 14 12 30 10 40 5 15 1 0 0 0 -6 Max 10000 10000 45 30 50 32 128 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms ms ns ns ns 11 10 8 9 7 5 6 Unit Notes t4U.com CAS precharge time in normal mode RAS pulse width CAS pulse width Row address setup time Row address hold time Column address setup time Column address hold time RAS to CAS delay time RAS to column address delay time Column address to RAS lead time RAS hold time CAS hold time CAS to RAS precharge time OE to Din delay time Transition time (rise and fall) Refresh period Refresh period (S- Version) CAS to output in Low- Z CAS delay time from Din OE delay time from Din tCPN 10 .com tRAS tCAS tASR tRAH tASC tCAH tRCD tRAD tRAL tRSH tCSH tCRP tOED tT tREF tREF tCLZ tDZC tDZO 50 8 0 8 0 8 12 10 25 8 38 5 12 1 0 0 0 10000 10000 37 25 50 32 128 - DataShe e .com Document:1G5-0124 Rev.1 Page 10 DataSheet4 U .com www..com VIS Read Cycle VG26(V)(S)17405 -5 Parameter Access time from RAS Access time from CAS Access time from column address Access time from OE Read command setup time Read command hold time to CAS Read command hold time to RAS Output buffer turn-off time Output buffer turn-off time from OE Symbol tRAC tCAC tAA tOEA tRCS tRCH tRRH tOFF tOEZ Min 0 0 10 0 0 Max 50 13 25 12 12 12 Min 0 0 10 0 0 -6 Max VG26(V)(S)17405 4,194,304 x 4 - Bit CMOS Dynamic RAM Unit Notes 60 15 30 15 15 15 ns ns ns ns ns ns ns ns ns 12 13, 14 14, 15 7 10, 16 16 17 17 Write Cycle VG26(V)(S) 17405 -5 -6 Max Min 0 10 10 15 10 0 10 10 Max ns ns ns ns ns ns ns ns 19 19 7, 18 Unit Notes t4U.com Parameter Write command setup time Write command hold time Write command pulse width Write command to RAS lead time Write command to CAS lead time Data-in setup time Data-in hold time WE to Data-in delay Min Symbol .com tWCS tWCH tWP tRWL tCWL tDS tDH tWED 0 8 8 13 8 0 8 10 DataShe e Read- Modify- Write Cycle VG26(V)(S) 17405 -5 Parameter Read-modify- write cycle time RAS to WE delay time CAS to WE dealy time Column address to WE delay time OE hold time from WE Symbol tRWC tRWD tCWD tAWD tOEH Min 108 64 26 39 8 Max Min 133 77 32 47 10 -6 Max ns ns ns ns ns 18 18 18 Unit Notes .com Document:1G5-0124 Rev.1 Page 11 DataSheet4 U .com www..com VIS Refresh Cycle VG26(V)(S)17405 4,194,304 x 4 - Bit CMOS Dynamic RAM VG26(V)(S)17405 -5 Parameter CAS setup time (CBR refresh) CAS hold time (CBR refresh) RAS precharge to CAS hold time RAS pulse width (self refresh) RAS precharge time (self refresh) CAS hold time (CBR self refresh) WE setup time WE hold time Symbol tCSR tCHR tRPC tRASS tRPS tCHS tWSR tWHR Min 5 8 5 100 90 -50 0 10 Max Min 5 10 5 100 110 -50 0 10 -6 Max Unit ns ns ns s ns ns ns ns 10 7 Notes EDO Page Mode Cycle VG26(V)(S) 17405 -5 Parameter Symbol tPC tCP Min 20 10 50 30 5 10 5 3 7 Max Min 25 10 60 35 5 10 5 3 7 -6 Max 105 35 10 Unit ns ns ns ns ns ns ns ns ns ns 20 10, 14 Notes t4U.com EDO page mode cycle time EDO page mode CAS precharge time EDO page mode RAS pulse width Access time from CAS precharge RAS hold time from CAS precharge OE high hold time from CAS high OE high pulse width Data output hold time after CAS low Output disable delay from WE WE pulse width for output disable when CAS high .com tRASP tCPA tCPRH tOEHC tOEP tCOH tWHZ tWPZ DataShe e 105 30 10 - .com Document:1G5-0124 Rev.1 Page 12 DataSheet4 U .com www..com VIS EDO Page Mode Read Modify Write Cycle VG26(V)(S) 17405 -5 Parameter EDO page mode read- modify- write cycle CAS precharge to WE delay time EDO page mode read- modify- write cycle time Symbol tCPW tPRWC Min 45 56 Max Min 55 68 -6 Max - VG26(V)(S)17405 4,194,304 x 4 - Bit CMOS Dynamic RAM Unit ns ns Notes 10 t4U.com .com DataShe e .com Document:1G5-0124 Rev.1 Page 13 DataSheet4 U .com www..com VIS Notes : 1. AC measurements assume t T = 2ns. VG26(V)(S)17405 4,194,304 x 4 - Bit CMOS Dynamic RAM 2. An initial pause of 100 s is required after power up, and it followed by a minimum of eight initialization cycles (RAS - only refresh cycle or CAS - before - RAS refresh cycle). If the internal refresh counter is used, a minimun of eight CAS - before - RAS refresh cycles are required. 3. In delayed write or read-modify-write cycles, OE must disable output buffer prior to applying data to the device. 4. All the VCC and VSS pins shall be supplied with the same voltages. 5. tRAS(min) = tRWD(min)+t RWL(min)+tT in read-modify-write cycle. 6. tCAS (min) = tCWD(min)+tCWL(min)+tT in read-modify-write cycle. 7. tASC(min), tRCS (min), tWCS(min), and tRPC are determined by the falling edge of CAS . 8. t RCD(max) is specified as a reference point only, and tRAC (max) can be met with the tRCD(max) limit. Otherwise, tRAC is controlled exclusively by tCAC if tRCD is greater than the specified tRCD(max) limit. 9. tRAD(max) is specified as a reference point only, and tRAC(max) can be met with the tRAD(max) limit. Otherwise, tRAC is controlled exclusively by tAA if tRAD is greater than the specified tRAD(max) limit. 10. tCRP, tCHR , tRCH, tCPA and tCPW are determined by the rising edge of CAS . 11. V IH(min) and VIL(max) are reference levels for measuring timing or input signals. Therefore, transition time is measured between VIH and VIL. t4U.com 12. Assumes that t RCD tRCD(max) and tRAD .com or tRAD is greater than the maximum tRAD(max). If tRCD DataShe e recommended value shown in this table, tRAC exceeds the value shown. 13. Assumes that tRCD t RCD (max) and tRAD t RAD (max). tRAD (max). 14. Access time is determined by the maximum of tAA , tCAC, tCPA. 15. Assumes that t RCD tRCD (max) and t RAD 16. Either tRCH or tRRH must be satisfied for a read cycle. 17. tOFF(max) and tOEZ(max) define the time at which the output achieves the open circuit condition (high impedance). t OFF is determined by the later rising edge of RAS or CAS. 18. tWCS, tRWD, tCWD, and tAWD are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only. If tWCS t WCS (min), the cycle is an early write cycle and the data out will remain open circuit (high impedance) throughout the entire cycle. If tRWD tCWD tRWD (min), t CWD (min), t AWD t AWD (min) and tCPW tCPW (min), the cycle is a read-modify-write and the data output will contain data read from the selected cell. If neither of the above sets of conditions is satisfied, the condition of the data output (at access time) is indeterminate. 19. These parameters are referenced to CAS separately in an early write cycle and to WE edge in a delayed write or a read-modify-write cycle. 20. tRASP defines RAS pulse width in EDO page mode cycles. .com Document:1G5-0124 Rev.1 Page 14 Dht ae Se t 4 Uc o . m www..com VIS Timing Waveforms * Read Cycle t RC t RAS t RP VG26(V)(S)17405 4,194,304 x 4 - Bit CMOS Dynamic RAM RAS t CRP t CSH t RCD t T t RSH t CAS t CPN CAS t RAD t RAL t ASR t RAH Row t ASC t CAH Column t RRH ADDRESS t4U.com WE t RCS .com t RCH DataShe e OE t OEA t CAC t AA t RAC t OEZ t OFF t OFF DQ1~DQ4 t CLZ Note : = don't care = Invalid Dout D OUT .com Document:1G5-0124 Rev.1 Page 15 DataSheet 4 U .com www..com VIS *Early Write Cycle t RC t RAS t RP VG26(V)(S)17405 4,194,304 x 4 - Bit CMOS Dynamic RAM RAS t CSH t RCD t T t RSH t CRP t CPN t CAS CAS t RAD t ASR t RAH Row t ASC t CAH t RAL ADDRESS Column t RAL t WCS t WCH t4U.com WE .com DataShe e t DS t DH DQ1~DQ4 DIN .com Document:1G5-0124 Rev.1 Page 16 DataSheet 4 U .com www..com VIS * Delayed Write Cycle t RC t RAS t RP VG26(V)(S)17405 4,194,304 x 4 - Bit CMOS Dynamic RAM RAS t CSH t RCD t T t RSH t CAS t CRP t CPN CAS t ASR t RAH t ASC t CAH ADDRESS Row Column t CWL t4U.com WE t RCS .com t t RWL WP DataShe e t OED t OEH OE t DS t DS t DH DQ1~DQ4 OPEN DIN .com Document:1G5-0124 Rev.1 Page 17 DataSheet 4 U .com www..com VIS * Read - Modify - Write Cycle t RWC t RAS t RP VG26(V)(S)17405 4,194,304 x 4 - Bit CMOS Dynamic RAM RAS t T t RCD t CAS t CRP t CPN CAS t RAD t ASR t RAH t ASC t CAH ADDRESS Row Column t RCS t CWD t AWD t RWD t CWL t RWL t WP t4U.com WE .com DataShe e t DZC t DS t DH DQ1~DQ4 OPEN DIN t DZO t OED t OEH OE t OEA t CAC t AA t OEZ t RAC DQ1~DQ4 DOUT .com Document:1G5-0124 Rev.1 Page 18 DataSheet4 U .com www..com VIS * EDO Page Mode Read Cycle t RASP t CPRH VG26(V)(S)17405 4,194,304 x 4 - Bit CMOS Dynamic RAM t RP RAS t CRP t CSH t CRP t RCD t CAS t CP t PC t CAS t CP t RSH t CAS t CPN CAS t RAD t ASR t RAH t ASC t CAH t ASC t CAH t ASC t RAL t CAH ADDRESS Row Column 1 Column 2 Column N Row t RCS t RRH t RCH WE WE t4U.com t OEA .com t OEHC DataShe t OEP t OEA e OE OE t RAC t AA t CPA t AA t CPA t AA t OEZ t CAC t CAC t COH t CAC t OFF t OEZ t OFF DQ1~DQ4 DOUT 1 DOUT 2 DOUT N OPEN .com Document:1G5-0124 Rev.1 Page 19 DataSheet 4 U .com www..com VIS * EDO Page Mode Early Write Cycle t RASP VG26(V)(S)17405 4,194,304 x 4 - Bit CMOS Dynamic RAM t RP RAS tT t CSH t RCD t CAS t CP t PC t CAS t CP t RSH t CAS t CRP t CPN CAS t ASR t RAH t ASC t CAH t ASC t CAH t ASC t CAH ADDRESS Row Column 1 Column 2 Column N t WCS t4U.com WE WE t WCH t WCS t WCH t WCS t WCH .com DataShe e t DS t DH t DS t DH t DS t DH DQ1~DQ4 DIN 1 DIN 2 DIN N .com Document:1G5-0124 Rev.1 Page 20 DataSheet 4 U .com www..com VIS * EDO Page Mode Read-Early-Write Cycle t RASP t CPRH VG26(V)(S)17405 4,194,304 x 4 - Bit CMOS Dynamic RAM t RP RAS t CRP t CSH t CRP t RCD t CAS t CP t PC t CAS t CP t RSH t CAS t CPN CAS t CSH t RAD t ASR t RAH t ASC t RAH t ASC t CAH t ASC t CAL t RAL t CAH ADDRESS Row Column 1 Column 2 Column N Row t RCS t RCH t WCS t WCH WE WE t4U.com t OEA .com t WED DataShe e OE OE t RAC t AA t CPA t AA t WHZ t CAC t COH t CAC t DS Data Doutput 2 Data Input N t DH DQ1~DQ4 OPEN Data Doutput 1 .com Document:1G5-0124 Rev.1 Page 21 DataSheet 4 U .com www..com VIS * EDO Page Mode Read-Modify-Write Cycle t RASP tCPRH VG26(V)(S)17405 4,194,304 x 4 - Bit CMOS Dynamic RAM t RP RAS t T t RCD t CAS t CP t PRWC t CAS t CP t CAS t CRP CAS t RAD t ASR t RAH t ASC t CAH t ASC t CAH t RAL t ASC t CAH ADDRESS Row Column 1 Column 1 t RWD t AWD t CWD t CWL Column 2 t CPW t AWD t CWD t CWL Column N t CWL t CPW t AWD t CWD t RWL t RCS t RCS t4U.com WE WE t RCS t WP t DS t DZC .com t WP t DZC t DH t DZC t DS t DH t WP t DS t DH OPEN DataShe e DQ1~DQ4 OPEN DIN 1 OPEN DIN 2 DIN N t DZO t DZO t OED t OEH t OED t OEH t DZO t OED t OEH OE t OEA t CAC t RAC t AA t OEZ t OEA t CAC t AA t CPA t OEZ t CAC t AA t CPA t OEZ t OEA DQ1~DQ4 DOUT 1 DOUT 2 DOUT N .com Document:1G5-0124 Rev.1 Page 22 DataSheet 4 U .com www..com VIS * Read Cycle with WE Controlled Disable RAS VG26(V)(S)17405 4,194,304 x 4 - Bit CMOS Dynamic RAM t CSH t RCD t T t CAS CAS t RAD t ASR t RAH t ASC t CAH ADDRESS Row Column t4U.com WE t RCS t RCH t WPZ .com DataShe e t WHZ OE t DS tOEA tCAC t AA t RAC tOEZ DQ1~DQ4 tCLZ DOUT .com Document:1G5-0124 Rev.1 Page 23 DataSheet4 U .com www..com VIS RAS-Only Refresh Cycle t RC t RAS t RP VG26(V)(S)17405 4,194,304 x 4 - Bit CMOS Dynamic RAM RAS tT t CRP tRPC tCRP CAS tASR tRAH ADDRESS ROW tOFF OPEN DQ1~DQ4 t4U.com CAS-Before-RAS Refresh Cycle .com DataShe e tRC tRP tRAS tRP t RAS tRC t RP RAS tRPC tT t CSR t CHR tRPC tCSR t CHR tCRP CAS tWSR tWHR tWSR tWHR WE tOFF OPEN DQ1~DQ4 .com Document:1G5-0124 Rev.1 Page 24 DataSheet4 U .com www..com VIS CBR Self-Refesh Cycle t RASS t RPS VG26(V)(S)17405 4,194,304 x 4 - Bit CMOS Dynamic RAM RAS t RPC t CSR tCHS CAS tOFF High lmpedance DQ1~DQ4 tWSR tWHR WE OPEN t4U.com .com DataShe e .com Document:1G5-0124 Rev.1 Page 25 DataSheet 4 U .com www..com VIS * Hidden Refresh Cycle VG26(V)(S)17405 4,194,304 x 4 - Bit CMOS Dynamic RAM t RC tRAS (READ) t RC t RP tRAS (REFRESH) t RC t RP tRAS (REFRESH) t RP RAS tT t CHR t RSH t RCD tCAS tCRP CAS t RAD t ASR t RAH tASC t RAL tCAH ADDRESS ROW COlumn t4U.com .com tRRH t RCS tRCH DataShe e WE OE t OEA t CAC t AA t RAC t OEZ t OFF t OFF DQ1~DQ4 D OUT .com Document:1G5-0124 Rev.1 Page 26 DataSheet 4 U .com www..com VIS Ordering information Part Number VG26(V)(S)17405DJ-5 VG26(V)(S)17405DJ-6 VG26(V)(S)17405EJ-5 VG26(V)(S)17405EJ-6 Access time 50 ns 60 ns 50 ns 60 ns 300mil 26/24-Pin Plastic SOJ Package VG26(V)(S)17405 4,194,304 x 4 - Bit CMOS Dynamic RAM VG26(V)(S) 17405EJ-5 * VG * 26 *V *S * 17405 *E * VIS Memory Product * Technology * 3.3V Version * Self refresh * Device Type and Configuation * Revision * Package Type (J : SOJ, T : TSOP II) * Speed (5 : 50 ns, 6 : 60 ns) *J t4U.com *5 .com Packaging information * 300 mil, 26/24-Pin Plastic SOJ D DIM A A1 A2 b b1 b2 c c1 D E E1 E2 e R1 INCHES MILLIMETERS MIN. NOM. MAX. MIN. NOM. MAX. 3.25 3.51 3.76 0.128 0.138 0.148 2.08 ----0.082 ----2.54 REF. 0.100 REF. 0.41 0.41 0.66 0.18 0.18 17.02 --0.46 --0.51 0.48 0.81 0.016 0.016 0.026 0.007 0.007 0.670 --0.018 --0.020 0.019 0.032 1 6 8 13 b 26 21 19 14 b1 c1 c E1 E BASE METAL WITH PLATING --0.30 --0.28 17.15 17.27 8.51 BASIC 7.49 7.62 7.75 6.78 BASIC 1.27 BASIC 0.76 --1.02 --0.012 0.011 --0.675 0.680 0.335 BASIC 0.295 0.300 0.305 0.267 BASIC 0.050 BASIC 0.030 --0.040 SECTION B-B C L A2 0.025" MIN. A A1 B B E2 NOTE: 1. CONTROLLING DIMENSION : INCHES 2. DIMENSION D DOES NOT INCLUDE MOLD PROTRUSION. MOLD PROTRUSION SHALL NOT EXCEED 0.006"(0.15mm) PER SIDE. DIMENSION E1 DOES NOT INCLUDE INTERLEAD PROTRUSION. INTERLEAD PROTRUSION SHALL NOT EXCEED 0.01"(0.25mm) PER SIDE. 3. DIMENSION b2 DOES NOT INCLUDE DAMBAR PROTRUSION OR INTRUSION. DAMBAR PROTRUSION SHALL NOT CAUSE THE SHOULDER WIDTH TO EXCEED b2 MAX BY MORE THAN 0.005"(0.127mm) DAMBAR INTRUSION SHALL NOT REDUCE THE SHOULDER WIDTH TO LESS THAN 0.001"(0.025mm) BELOW b2 MIN. e b2 b 0.007"M 4-e 0.004" RAD R1 SEATING PLANE .com Document:1G5-0124 Rev.1 Page 27 DataSheet4 U .com |
Price & Availability of VG2617405
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