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| K5L2731CAM-D770 Preliminary MCP MEMORY MCP Specification 128Mb NOR Flash + 32Mb UtRAM INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS, AND IS SUBJECT TO CHANGE WITHOUT NOTICE. NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL INFORMATION IN THIS DOCUMENT IS PROVIDED ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND. 1. For updates or additional information about Samsung products, contact your nearest Samsung office. 2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar applications where Product failure couldresult in loss of life or personal or physical harm, or any military or defense application, or any governmental procurement to which special terms or provisions may apply. * Samsung Electronics reserves the right to change products or specification without notice. 1 Revision 0.0 September 2006 www.DataSheet.in K5L2731CAM-D770 Document Title Multi-Chip Package MEMORY 128M Bit(8M x16) Page Mode, Multi Bank NOR Flash / 32M Bit(2M x16) Page Mode Uni-Transistor Random Access Memory Preliminary MCP MEMORY Revision History Revision No. 0.0 History Initial issue. - NOR Flash 128Mb B-die Ver_0.9 - UtRAM 32Mb D-die Ver_1.0 Draft Date Sep. 11, 2006 Remark Preliminary Note : For more detailed features and specifications including FAQ, please refer to Samsung's web site. http://samsungelectronics.com/semiconductors/products/products_index.html The attached datasheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions about device. If you have any questions, please contact the SAMSUNG branch office near you. 2 Revision 0.0 September 2006 www.DataSheet.in K5L2731CAM-D770 Multi-Chip Package MEMORY 128M Bit(8M x16) Page Mode, Multi Bank NOR Flash / 32M Bit(2M x16) Page Mode Uni-Transistor Random Access Memory Preliminary MCP MEMORY FEATURES GENERAL DESCRIPTION The K5L2731CAM is a Multi Chip Package Memory which combines 128Mbit NOR Flash Memory and 32Mbit Page UtRAM. The NOR Flash featuring single 3.0V power supply, is an 128Mbit NOR-type Flash Memory organized as 8M x16. The memory architecture of the device is designed to divide its memory arrays into 270 blocks with independent hardware protection. This block architecture provides highly flexible erase and program capability. The NOR Flash consists of four banks. This device is capable of reading data from one bank while programming or erasing in the other banks. The NOR Flash offers fast page access time of 20~30ns with random access time of 55~70ns. The devices fast access times allow high speed microprocessors to operate without wait states. The device performs a program operation in unit of 16 bits (Word) and erases in units of a block. Single or multiple blocks can be erased. The block erase operation is completed within typically 0.7 sec. The device requires 15mA as program/erase current in the commercial and industrial temperature ranges. The 32Mb UtRAM is fabricated by SAMSUNGs advanced CMOS technology using one transistor memory cell. The device support 4 page mode operation, Industrial temperature range and 48 ball Chip Scale Package for user flexibility of system design. The device also supports Internal Temperature Compensated Self Refresh for low standby current. The K5L2731CAM is suitable for the memory of mobile communication system to reduce not only mount area but also power consumption. This device is available in 64-ball FBGA package. SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice. 3 Revision 0.0 September 2006 www.DataSheet.in K5L2731CAM-D770 PIN CONFIGURATION Preliminary MCP MEMORY 1 2 3 4 5 6 7 8 9 10 A B C D E F G H J K L M DNU DNU NC NC A7ru LBu WPr/ACCr WEru A8ru A11ru A3ru A6ru UBu Resetr CS2u A19ru A12ru A15ru A2ru A5ru A18ru RYr/BYr A20ru A9ru A13ru A21r A1ru A4ru A17ru A10ru A14ru A22r A0ru VSSru DQ1ru DQ6ru NC A16ru CEr OEru DQ9ru DQ3ru DQ4ru DQ13ru DQ15ru NC CS1u DQ0ru DQ10ru VCCr VCCu DQ12ru DQ7ru VSSru DQ8ru DQ2ru DQ11ru NC DQ5ru DQ14ru NC NC DNU DNU 64 FBGA: Top View (Ball Down) NOR Flash UtRAM Common NC / DNU 4 Revision 0.0 September 2006 www.DataSheet.in K5L2731CAM-D770 PIN DESCRIPTION Ball Name A0ru to A20ru A21r to A22r DQ0ru to DQ15ru CEr CS1u,CS2u OEru RESETr WPr/ACCr RYr/BYr Description Address Inputs(Common) Address Inputs(NOR) Data Input/output(Common) Chip Enable (NOR) Chip Select (UtRAM) Output Enable (Common) Hardware Reset (NOR) Hardware Write Protection/ Program Acceleration(NOR) Ready/Busy Output(NOR) Ball Name WEru UBu LBu VCCr VCCu VSSru NC DNU Preliminary MCP MEMORY Description Write Enable(Common) Upper Byte(UtRAM) Lower Byte(UtRAM) Power Supply(NOR) Power Supply(UtRAM) Ground(Common) No Connection Do Not Use ORDERING INFORMATION K5 Samsung MCP Memory 2Chip MCP L 27 31 C A M-D 7 70 UtRAM Access Time 70 : 70ns Device Type L : De-muxed NOR Flash + UtRAM Flash Access Time 7 : 70ns NOR Flash Density 27 : 128Mb, x16 ,Page, 1CE Package D : FBGA(LF) Version M : 1st Generation UtRAM Density, (Organization) 31 : 32Mb, x16, Page Operating Voltage C : 3.0V/3.0V Block Architecture A : Top & Bottom Boot Block 5 Revision 0.0 September 2006 www.DataSheet.in K5L2731CAM-D770 FUNCTIONAL BLOCK DIAGRAM Preliminary MCP MEMORY VCCr VSSr Address(A0ru to A20ru) Address(A21r to A22r) OEru WEru CEr RESETr WPr/ACCr RYr/BYr VCCu VSSu 128M NOR Flash Memory DQ0ru to DQ15ru 64M bit UtRAM CS1u,CS2u UBu LBu 6 Revision 0.0 September 2006 www.DataSheet.in K5L2731CAM-D770 Preliminary MCP MEMORY 128M Bit(8Mx16) B-die Page Mode, Multi Bank NOR Flash 7 Revision 0.0 September 2006 www.DataSheet.in K5L2731CAM-D770 FUNCTIONAL BLOCK DIAGRAM Bank 0 Address Vcc Vss CE OE WE RESET RY/BY WP/ACC A0~A22 DQ0~DQ15 Block Inform Erase Control High Voltage Gen. I/O Interface & Bank Control Bank 1 Address X Dec X Dec Bank 0 Cell Array Preliminary MCP MEMORY Y Dec Latch & Control Y Dec Bank 1 Cell Array Latch & Control Bank 3 Address X Dec Bank 3 Cell Array Y Dec Latch & Control Program Control Table 1. PRODUCT LINE-UP Speed Item 4A Vcc VIO (1) Max. Address Access Time (ns) Max. CE Access Time (ns) Max. OE Access Time (ns) Max. Page Access Time (ns) Notes : 1. Only 4C or 4D speed options can be provided in case of using 1.65~1.95V VIO. Speed Option 4B 2.7V~3.6V 1.65~1.95V , 2.7~3.6V 55ns 55ns 20ns 20ns 60ns 60ns 25ns 25ns 65ns 65ns 25ns 25ns 70ns 70ns 30ns 30ns 4C 4D Table 2. DEVICE BANK DIVISIONS Bank 0, Bank 3 Mbit 16 Mbit Block Sizes 4 Kw x 8 and 32 Kw x 31 Mbit 48 Mbit Bank 1, Bank 2 Block Sizes 32 Kw x 96 Table 3. OTP BLOCK Block Address A22~A8 OTP Area Block Size Address Range 0000h Factory-Locked Area Customer-Locked Area 128 words 128 words 000000h-00007Fh 000080h-0000FFh After entering OTP block, any issued addresses should be in the range of OTP block address 8 Revision 0.0 September 2006 www.DataSheet.in K5L2731CAM-D770 Table 4. DEVICE BANK DIVISIONS Bank 0 31 1 2 3 8 96 96 31 Number of Blocks 8 Preliminary MCP MEMORY Block Size 4 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 4 Kwords 9 Revision 0.0 September 2006 w w w . D a t a S h e e t . i n K5L2731CAM-D770 PRODUCT INTRODUCTION Preliminary MCP MEMORY The device is an 128Mbit NOR-type Flash memory. The device features single voltage power supply operating within the range of 2.7V to 3.6V. The device is programmed by using the Channel Hot Electron (CHE) injection mechanism which is used to program EPROMs. The device is erased electrically by using Fowler-Nordheim tunneling mechanism. To provide highly flexible erase and program capability, the device adapts a block memory architecture that divides its memory array into 270 blocks (4 Kw x 16 , 32 Kw x 254). Programming is done in units of 16 bits (Word). All bits of data in one or multiple blocks can be erased simultaneously when the device executes the erase operation. To prevent the device from accidental erasing or over-writing the programmed data, 270 memory blocks can be hardware protected. The device offers fast page access time of 20~30ns with random access time of 55~70ns supporting high speed microprocessors to operate without any wait states. The command set of device is fully compatible with standard Flash devices. The device is controlled by chip enable (CE), output enable (OE) and write enable (WE). Device operations are executed by selective command codes. The command codes to be combined with addresses and data are sequentially written to the command registers using microprocessor write timing. The command codes serve as inputs to an internal state machine which controls the program/erase circuitry. Register contents also internally latch addresses and data necessary to execute the program and erase operations. The device is implemented with Internal Program/Erase Algorithms to execute the program/erase operations. The Internal Program/Erase Algorithms are invoked by program/erase command sequences. The Internal Program Algorithm automatically programs and verifies data at specified addresses. The Internal Erase Algorithm automatically pre-programs the memory cell which is not programmed and then executes the erase operation. The device has means to indicate the status of completion of program/ erase operations. The status can be indicated via the RY/BY pin, Data polling of DQ7, or the Toggle bit (DQ6). Once the operations have been completed, the device automatically resets itself to the read mode. Table 5. Operations Table Operation Read Stand-by Output Disable Reset Write Temporary Block Unprotect CE L Vcc 0.2V L X L X OE L X H X H X WE H X H X L X WP/ ACC L/H (2) L/H L/H (4) (4) A9 A9 X X X A9 X A6 A6 X X X A6 X A1 A1 X X X A1 X A0 A0 X X X A0 X DQ8/ DQ15 DOUT High-Z High-Z High-Z DIN X DQ0/ DQ7 DOUT High-Z High-Z High-Z DIN X RESET H (2) H L H VID Notes : 1. L = VIL (Low), H = VIH (High), VID = 8.5V to 9.5V, DIN = Data in, DOUT = Data out, X = Don't care. 2. WP/ACC and RESET pin are asserted at Vcc0.2 V or Vss0.2 V in the Stand-by mode. 3. If WP/ACC=VIL, the two outermost boot blocks is protected. If WP/ACC=VIH, the two outermost boot block protection depends on whether those blocks were last protected or unprotected using the method described in "Block Protection and Unprotection". If WP/ACC=VHH, all blocks will be temporarily unprotected. 10 Revision 0.0 September 2006 www.DataSheet.in K5L2731CAM-D770 COMMAND DEFINITIONS Preliminary MCP MEMORY The device operates by selecting and executing its operational modes. Each operational mode has its own command set. In order to select a certain mode, a proper command with specific address and data sequences must be written into the command register. Writing incorrect information which include address and data or writing an improper command will reset the device to the read mode. The defined valid register command sequences are stated in Table 6. Note that Erase Suspend (B0H) and Erase Resume (30H) commands are valid only while the Block Erase Operation is in progress. Program Suspend (B0H) and Program Resume (30H) commands are valid during Program Operation and Erase Suspend - Program Operation. Only Read Operation is available after Program Suspend Operation. Table 6. Command Sequences Command Sequence Addr Read Data Addr Reset Data Autoselect Manufacturer ID (1,2) Autoselect Device Code (1,2,3) Autoselect Block Protect Verify (1,2) Autoselect OTP Factory Protect Program Data Addr Unlock Bypass Data Unlock Bypass Program Unlock Bypass Block Erase Unlock Bypass Chip Erase Data Addr Unlock Bypass Reset Data Addr Unlock Bypass CFI Data Addr Chip Erase Data Addr Block Erase Data Block Erase Suspend (4, 5) Block Erase Resume Data Addr Program Suspend (6,7) Data Addr Program Resume Data Addr CFI Query (8) Data 1 98H 1 30H 55H 1 B0H DA Addr 1 Data Addr 1 30H DA B0H DA 6 AAH DA 55H 80H AAH 55H 30H 6 AAH 555H 55H 2AAH 80H 555H AAH 555H 55H 2AAH 10H BA 2 90H 00H XXH 98H 555H 2AAH 555H 555H 2AAH 555H Addr 2 Data Addr 2 Data Addr 2 80H XXXH 10H XXXH 80H XXXH 30H XXXH A0H XXXH PD BA 3 AAH XXXH 55H PA 20H Addr 4 Data Addr 4 Data Addr 4 Data Addr 4 Data Addr 4 AAH 555H 55H 2AAH A0H 555H PD AAH 555H 55H 2AAH 90H 555H (See Note 10) PA AAH 555H 55H 2AAH 90H DA/555H AAH 555H 55H 2AAH 90H DA/555H 257EH BA / X02H (See Table 7) X03H 2508H 2501H AAH 555H 55H 2AAH 90H DA/555H ECH DA/X01H DA/X0EH DA/X0FH 1 F0H 555H 2AAH DA/555H DA/X00H 1 RD XXXH Cycle 1st Cycle RA 2nd Cycle 3rd Cycle 4th Cycle 5th Cycle 6th Cycle 1 11 Revision 0.0 September 2006 www.DataSheet.in K5L2731CAM-D770 Table 6. Command Sequences (Continued) Command Definitions Addr Accelerated Program Data Addr Quadruple word Accelerated Program(9) Data Addr Enter OTP Block Region Data Addr Exit OTP Block Region Data Addr OTP Protection bit Program (11,12) Data Addr OTP Protection bit Status Data 4 AAH 55H 2AAH 55H 2AAH 55H 90H 555H 60H 555H 60H 00H OW 68H OW 48H 555H AAH 555H AAH 3 AAH 555H 55H 2AAH 88H 555H XXX 5 A5H 555H PD1 2AAH PD2 555H PD3 2 A0H XXXH PD PA1 PA2 PA3 Cycle 1st Cycle XXH 2nd Cycle PA 3rd Cycle 4th Cycle Preliminary MCP MEMORY 5th Cycle 6th Cycle PA4 PD4 6 5 OW 48H OW RD(0) OW RD(0) Notes : * RA : Read Address, PA : Program Address, RD : Read Data, PD : Program Data * DA : Bank Address (A20- A22), BA : Block Address (A12 - A22), ABP : Address of the block to be protected or unprotected, X = Don't care . * OW = Address (A7:A0) is (00011010), RD(0) = Read Data DQ0 for protection indicator bit ,RD(1) = Read Data DQ1 for PPB Lock status. * DQ8 - DQ15 are don't care in command sequence, except for RD and PD. * A11 - A22 are also don't care, except for the case of special notice. 1. To terminate the Autoselect Mode, it is necessary to write Reset command to the register. 2. The 4th cycle data of Autoselect mode is output data. The 3rd and 4th cycle bank addresses of Autoselect mode must be same. 3. Device ID must be read across cycles 4, 5 and 6. 128Mb(xOEh = 2508h, x0Fh = 2501h), 64Mb(xOEh = 2506h, x0Fh = 2501h),32Mb(xOEh = 2503h, x0Fh = 2501h) 4. The Read / Program operations at non-erasing blocks and the autoselect mode are allowed in the Erase Suspend mode. 5. The Erase Suspend command is applicable only to the Block Erase operation. 6. The Read Operation is allowed in the Program Suspend mode. 7. The Program Suspend command is applicable to Program and Erase Suspend - Program operation. 8. Command is valid when the device is in read mode or Autoselect mode. 9. Quadruple word accelerated program is invoked only at Vpp=Vid, Vpp setup is required prior to this command sequence. PA1,PA2,PA3,PA4 have the same A22~A2 address 10. The data is DQ6=1 for customer locked and DQ7=1 for factory locked. 11. Reset command returns device to reading array. 12. Cycle 4 programs the addressed locking bit. Cycle 5 and 6 validate bit has been fully programmed when DQ0=1. If DQ0=0 in cycle 6, program command must be issued and verified again. Table 7. Autoselect Codes Description Manufacturer ID Read Cycle 1 Device ID Read Cycle 2 Read Cycle 3 Block Protection Verification Read Data Address (DA) + 00H (DA) + 01H (DA) + 0EH (DA) + 0FH (BA) + 02H ECH 257EH 2508H 2501H 01H(Proected), 00H (Unproteced) OTP Indicator Bit (DQ7. DQ6) Master locking bit Indicator Bit Notes : (DA) + 03H DQ7=1(Factory locked), DQ6=1(Customer locked) (BA) + 07H 01H(Proected), 00H (Unproteced) 1. L=Logic Low=VIL, H=Logic High=VIH, DA= Bank Address, BA=Block Address, X=Don't care. 12 Revision 0.0 September 2006 www.DataSheet.in K5L2731CAM-D770 DEVICE OPERATION Read Mode Preliminary MCP MEMORY The device is controlled by Chip Enable (CE), Output Enable (OE) and Write Enable (WE). When CE and OE are low and WE is high, the data stored at the specified address location,will be the output of the device. The outputs are in high impedance state whenever CE or OE is high. The device is available for Page mode. Page mode provides fast access time for high performance system. Standby Mode The device features Stand-by Mode to reduce power consumption. This mode puts the device on hold when the device is deselected by making CE high (CE = VIH). Refer to the DC characteristics for more details on stand-by modes. Output Disable The device outputs are disabled when OE is High (OE = VIH). The output pins are in high impedance state. Automatic Sleep Mode The device features Automatic Sleep Mode to minimize the device power consumption. When addresses remain steady for tAA+30ns, the device automatically activates the Automatic Sleep Mode. In the sleep mode, output data is latched and always available to the system. When addresses are changed, the device provides new data without wait time. tAA + 30ns Address Outputs Data Data Data Data Data Auto Sleep Mode Data Figure 1. AutoSleep Mode Operation Autoselect Mode The device offers the Autoselect Mode to identify manufacturer, device type and block protection verification by reading a binary code. The Autoselect Mode allows programming equipment to automatically match the device to be programmed with its corresponding programming algorithm. In addition, this mode allows the verification of the status of write protected blocks. The manufacturer, device code and block protection verification can be read via the command register. The Command Sequence is shown in Table 6 and Figure 2. The autoselect operation of block protection verification is initiated by first writing two unlock cycle. The third cycle must contain the bank address and autoselect command (90H). To terminate the autoselect operation, write Reset command (F0H) into the command register. 13 Revision 0.0 September 2006 www.DataSheet.in K5L2731CAM-D770 WE Preliminary MCP MEMORY Address 555H 2AAH 555H 00H 01H 0EH 0FH DQ15DQ0 AAH 55H 90H ECH 257EH 2508H 2501H Manufacturer ID Device ID Note : The 3rd Cycle and 4th Cycle address must include the same bank address. Please refer to Table 7 for device code. Figure 2. Autoselect Operation ( by Command Sequence Method ) Write (Program/Erase) Mode The device executes its program/erase operations by writing commands into the command register. In order to write the commands to the register, CE and WE must be low and OE must be high. Addresses are latched on the falling edge of CE or WE (whichever occurs last) and the data are latched on the rising edge of CE or WE (whichever occurs first). The device uses standard microprocessor write timing. Program The device can be programmed in units of a word. Programming is writing 0's into the memory array by executing the Internal Program Routine. In order to perform the Internal Program Routine, a four-cycle command sequence is necessary. The first two cycles are unlock cycles. The third cycle is assigned for the program setup command. In the last cycle, the address of the memory location and the data to be programmed at that location are written. The device automatically generates adequate program pulses and verifies the programmed cell margin by the Internal Program Routine. During the execution of the Routine, the system is not required to provide further controls or timings. During the Internal Program Routine, commands written to the device will be ignored. Note that a hardware reset during a program operation will cause data corruption at the corresponding location. WE Address 555H 2AAH 555H Program Address A0H Program Data Program Start DQ15-DQ0 RY/BY AAH 55H Figure 3. Program Command Sequence 14 Revision 0.0 September 2006 www.DataSheet.in K5L2731CAM-D770 Preliminary MCP MEMORY In accross block boundaries and any sequence programming is allowed. A bit cannot be programmed from '0' back to '1'. If attempting to do, it may cause that bank to set DQ5 = 1, or cause the DQ7 and DQ6 status bits to indicate the operation was successful. However, a succeeding read will show that the data is still '0'. Only erase operations can convert a '0' to a '1'. Unlock Bypass The device provides the unlock bypass mode to save its operation time. This mode is possible for program, block erase and chip erase operation. There are two methods to enter the unlock bypass mode. The mode is invoked by the unlock bypass command sequence. Unlike the standard program/erase command sequence that contains four to six bus cycles, the unlock bypass program/erase command sequence comprises only two bus cycles. The unlock bypass mode is engaged by issuing the unlock bypass command sequence which is comprised of three bus cycles. Writing first two unlock cycles is followed by a third cycle containing the unlock bypass command (20H). Once the device is in the unlock bypass mode, the unlock bypass program/erase command sequence is necessary. The unlock bypass program command sequence is comprised of only two bus cycles; writing the unlock bypass program command (A0H) is followed by the program address and data. This command sequence is the only valid one for programming the device in the unlock bypass mode. Also, The unlock bypass erase command sequence is comprised of two bus cycles; writing the unlock bypass block erase command(80H-30H) or writing the unlock bypass chip erase command(80H-10H). This command sequences are the only valid ones for erasing the device in the unlock bypass mode. The unlock bypass reset command sequence is the only valid command sequence to exit the unlock bypass mode. The unlock bypass reset command sequence consists of two bus cycles. The first cycle must contain the data (90H). The second cycle contains only the data (00H). Then, the device returns to the read mode. Chip Erase To erase a chip is to write 1s into the entire memory array by executing the Internal Erase Routine. The Chip Erase requires six bus cycles to write the command sequence. The erase set-up command is written after first two "unlock" cycles. Then, there are two more write cycles prior to writing the chip erase command. The Internal Erase Routine automatically pre-programs and verifies the entire memory for an all zero data pattern prior to erasing. The automatic erase begins on the rising edge of the last WE or CE pulse in the command sequence and terminates when DQ7 is "1". After that the device returns to the read mode. WE Address 555H 2AAH 555H 555H 2AAH 555H DQ15-DQ0 AAH 55H 80H AAH 55H 10H Chip Erase Start RY/BY Figure 4. Chip Erase Command Sequence Block Erase To erase a block is to write 1s into the desired memory block by executing the Internal Erase Routine. The Block Erase requires six bus cycles to write the command sequence shown in Table 6. After the first two "unlock" cycles, the erase setup command (80H) is written at the third cycle. Then there are two more "unlock" cycles followed by the Block Erase command. The Internal Erase Routine automatically pre-programs and verifies the entire memory prior to erasing it. The block address is latched on the falling edge of WE or CE, while the Block Erase command is latched on the rising edge of WE or CE. Multiple blocks can be erased sequentially by writing the six bus-cycle operation in Figure 6. Upon completion of the last cycle for the Block Erase, additional block address and the Block Erase command (30H) can be written to perform the Multi-Block Erase. An 50us (typical) "time window" is required between the Block Erase command writes. The Block Erase command must be written within the 50us "time window", otherwise the Block Erase command will be ignored. The 50us "time window" is reset when the falling edge of the WE occurs within the 50us of "time window" to latch the Block Erase command. During the 50us of "time window", any command other than the Block Erase or the Erase Suspend command written to the device will reset the device to read mode. After the 50 us of "time window", the Block Erase command will initiate the Internal Erase Routine to erase the selected blocks. Any Block Erase address and command following the exceeded "time window" may or may not be accepted. No other commands will be recognized except the Erase Suspend command. 15 Revision 0.0 September 2006 www.DataSheet.in K5L2731CAM-D770 Preliminary MCP MEMORY WE Address DQ15-DQ0 555H 2AAH 555H 555H 2AAH Block Address 55H 30H Block Erase Start AAH 55H 80H AAH RY/BY Figure 5. Block Erase Command Sequence Erase Suspend / Resume The Erase Suspend command interrupts the Block Erase to read or program data in a block that is not being erased. The Erase Suspend command is only valid during the Block Erase operation including the time window of 50us. The Erase Suspend command is not valid while the Chip Erase or the Internal Program Routine sequence is running. When the Erase Suspend command is written during a Block Erase operation, the device requires a maximum of 20us to suspend the erase operation. But, when the Erase Suspend command is written during the block erase time window (50us) , the device immediately terminates the block erase time window and suspends the erase operation. After the erase operation has been suspended, the device is availble for reading or programming data in a block that is not being erased. The system may also write the autoselect command sequence when the device is in the Erase Suspend mode. When the Erase Resume command is executed, the Block Erase operation will resume. When the Erase Suspend or Erase Resume command is executed, the addresses are in Don't Care state. WE Address 555H Block Address AAH Block Erase Command Sequence 30H XXXH XXXH DQ15-DQ0 B0H 30H Block Erase Start Erase Suspend Erase Resume Figure 6. Erase Suspend/Resume Command Sequence Program Suspend / Resume The Program Suspend command interrupts the Program operation. Also the Program Suspend command interrupts the Program operation during Erase Suspend Mode. The Read operation is available only during Program Suspend. When the Program Suspend command is written during a Program operation, the device requires a maximum of 10us to suspend the Program operation. The system may also write the autoselect command sequence when the device is in the Program Suspend mode. When the Program Resume command is executed, the Program operation will resume. When the Program Suspend or Program Resume command is executed, the addresses are in Don't Care state. 16 Revision 0.0 September 2006 www.DataSheet.in K5L2731CAM-D770 Read While Write Preliminary MCP MEMORY The device provides multi-bank memory architecture that divides the memory array into four banks. The device is capable of reading data from one bank and writing data to the other bank simultaneously. This is so called the Read While Write operation with multi-bank architecture; this feature provides the capability of executing the read operation during Program/Erase or Erase-Suspend-Program operation. The Read While Write operation is prohibited during the chip erase operation. It is also allowed during erase operation when either single block or multiple blocks from same bank are loaded to be erased. It means that the Read While Write operation is prohibited when blocks from one Bank and another blocks from the other Bank are loaded all together for the multi-block erase operation. Write Protect (WP) The WP/ACC pin has two useful functions. The one is that certain boot block is protected by the hardware method not to use VID. The other is that program operation is accelerated to reduce the program time (Refer to Accelerated program Operation Paragraph). When the WP/ACC pin is asserted at VIL, the device can not perform program and erase operation in the two "outermost" 4Kword boot blocks on both ends of the flash array independently of whether those blocks were protected or unprotected using the method described in "Block protection/Unprotection". ( BA269 and BA268, BA0 and BA1) The write protected blocks can only be read. This is useful method to preserve an important program data. When the WP/ACC pin is asserted at VIH, the device reverts to whether the two outermost 4Kword boot blocks were last set to be protected or unprotected. That is, block protection or unprotection for these two blocks depends on whether they were last protected or unprotected using the method described in "Block protection/unprotection". Recommend that the WP/ACC pin must not be in the state of floating or unconnected, otherwise the device may be led to malfunction. Software Reset The reset command provides that the bank is reseted to read mode or erase-suspend-read mode. The addresses are in Don't Care state. The reset command is vaild between the sequence cycles in an erase command sequence before erasing begins, or in a program command sequence before programming begins. This resets the bank in which was operating to read mode. if the device is be erasing or programming, the reset command is invalid until the operation is completed. Also, the reset command is valid between the sequence cycles in an autoselect command sequence. In the autoselect mode, the reset command returns the bank to read mode. If a bank entered the autoselect mode in the Erase Suspend mode, the reset command returns the bank to erase-suspend-read mode. If DQ5 is high on erase or program operation, the reset command return the bank to read mode or erase-suspend-read mode if the bank was in the Erase Suspend state. Hardware Reset The device offers a reset feature by driving the RESET pin to VIL. The RESET pin must be kept low (VIL) for at least 500ns. When the RESET pin is driven low, any operation in progress will be terminated and the internal state machine will be reset to the standby mode after 20us. If a hardware reset occurs during a program operation, the data at that particular location will be lost. Once the RESET pin is taken high, the device requires 200ns of wake-up time until outputs are valid for read access. Also, note that all the data output pins are tri-stated for the duration of the RESET pulse. The RESET pin may be tied to the system reset pin. If a system reset occurs during the Internal Program and Erase Routine, the device will be automatically reset to the read mode ; this will enable the systems microprocessor to read the boot-up firmware from the Flash memory. 17 Revision 0.0 September 2006 www.DataSheet.in K5L2731CAM-D770 Power-up Protection Preliminary MCP MEMORY To avoid initiation of a write cycle during Vcc Power-up, RESET low must be asserted during power-up. After RESET goes high, the device is reset to the read mode. Low Vcc Write Inhibit To avoid initiation of a write cycle during Vcc power-up and power-down, a write cycle is locked out for Vcc less than 2.3V. If Vcc < VLKO (LockOut Voltage), the command register and all internal program/erase circuits are disabled. Under this condition the device will reset itself to the read mode. Subsequent writes will be ignored until the Vcc level is greater than VLKO. It is the users responsibility to ensure that the control pins are logically correct to prevent unintentional writes when Vcc is above 2.3V. Write Pulse Glitch Protection Noise pulses of less than 5ns(typical) on CE, OE, or WE will not initiate a write cycle. Logical Inhibit Writing is inhibited under any one of the following conditions : OE = VIL, CE = VIH or WE = VIH. To initiate a write, CE and WE must be "0", while OE is "1". Commom Flash Memory Interface Common Flash Momory Interface is contrived to increase the compatibility of host system software. It provides the specific information of the device, such as memory size, word configuration, and electrical features. Once this information has been obtained, the system software will know which command sets to use to enable flash writes, block erases, and control the flash component. When the system writes the CFI command(98H) to address 55H in word mode, the device enters the CFI mode. And then if the system writes the address shown in Table 8, the system can read the CFI data. Query data are always presented on the lowest-order data outputs(DQ0-7) only. In word(x16) mode, the upper data outputs(DQ8-15) is 00h. To terminate this operation, the system must write the reset command. OTP Block Region The OTP Block feature provides a 256-word Flash memory region that enables permanent part identification through an Electronic Serial Number (ESN). The OTP Block is customer lockable and shipped with itself unlocked, allowing customers to untilize the that block in any manner they choose. Indicator bits DQ6 and DQ7 are used to indicate the factory-locked and customer locked status of the part. The data is DQ6 = "1" for customer locked and DQ7 = "1" for factory locked. The system accesses the OTP Block through a command sequence (see "Enter OTP Block / Exit OTP Block Command sequence" at Table 6). After the system has written the "Enter OTP Block" Command sequence, it may read the OTP Block by using the addresses (000000h~0000FFh) normally and may check the Protection Verify Bit (DQ7,DQ6) by using the "Autoselect Block Protection Verify" Command sequence with OTP Block address. This mode of operation continues until the system issues the "Exit OTP Block" Command suquence, a hardware reset or until power is removed from the device. On power-up, or following a hardware reset, the device reverts to sending commands to main blocks. Note that the Accelerated function and unlock bypass modes are not available when the OTP Block is enabled. Customer Lockable In a Customer lockable device, The OTP Block is one-time programmable and can be locked only once. Note that the Accelerated programming and Unlock bypass functions are not available when programming the OTP Block. Locking operation to the OTP Block is started by writing the "Enter OTP Block" Command sequence, and it can be permanently locked to "1" by issuing the OTP Protection bit program Command sqeunce. Once the OTP block is locked and verified, the system must write the Exit OTP block command to return to reading and writing the remainder of the array. OTP Protection Bits OTP protection bits prevent programming of the OTP block memory area. Once set, the OTP area are non-modifiable. * The OTP Block Lock operation must be used with caution since, once locked, there is no procedure available for unlocking and none of the bits in the OTP Block space can be modified in any way. * Suspend and resume operation are not supported during OTP protect, nor is OTP protect supported during any suspend operation. 18 Revision 0.0 September 2006 www.DataSheet.in K5L2731CAM-D770 High Voltage Block Protection Preliminary MCP MEMORY Block protection and unprotection may also be implemented using programming equipment. The procedure requires high voltage (Vid) to be placed on the RESET# pin. Refer to Figure 8 for details on this procedure. Note that for block unprotect, all unprotected blocks must first be protected prior to the first sector write cycle. Accelerated Program Operation Accelerated program operation reduces the program time through the ACC function. This is one of two functions provided by the WP/ACC pin. When the WP/ACC pin is asserted as VHH, the device automatically enters the Unlock Bypass mode, temporarily unprotecting any protected blocks, and reduces the program operation time. The system would use a two-cycle program command sequence as required by the Unlock Bypass mode. Removing VHH from the WP/ACC pin returns the device to normal operation. Recommend that the WP/ACC pin must not be asserted at VHH except on accelerated program operation, or the device may be damaged. In addition, the WP/ACC pin must not be in the state of floating or unconnected, otherwise the device may be led to malfunction. Single word accelerated program operation The system would use two-cycle program sequence (One-cycle (XXX - A0H) is for single word program command, and Next one-cycle (PA PD) is for program address and data ). Quadruple word accelerated program operation As well as Single word accelerated program, the system would use five-cycle program sequence (One-cycle (XXX - A5H) is for quadruple word program command, and four cycles are for program address and data). * * * * Only four words programming is possible Each program address must have the same A22~A2 address The device automatically generates adequate program pulses and ignores other command after program command Program/Erase cycling must be limited below 100cycles for optimum performance. * Read while Write mode is not guaranteed Requirements : Ambient temperature : TA=30C10C 19 Revision 0.0 September 2006 www.DataSheet.in K5L2731CAM-D770 Preliminary MCP MEMORY START COUNT = 1 RESET=VID Wait 4s First Write Cycle=60h? Yes Yes Block Group Protection ? No No No Temporary Block Group Unprotect Mode Block Protect Algorithm Set up Block Group address Block Group Protect: Write 60H to Block Group address with A6=0,A1=1 A0=0 Wait 100s Verify Block Group Protect:Write 40H to Block Group address with A6=0, A1=1,A0=0 Read from Block Group address with A6=0, A1=1,A0=0 No COUNT =25? No All Block Groups Protected ? Yes Block Unprotect Algorithm Block Group , i= 0 Block Group Unprotect Write 60H with A6=1,A1=1 A0=0 Wait 1.2ms Reset COUNT=1 Increment COUNT Increment COUNT Verify Block Group Unprotect:Write 40H to Block Group address with A6=1, A1=1,A0=0 Read from Block Group address with A6=1, A1=1,A0=0 No COUNT =1000? No Set up next Block Group address Data=01h? Data=00h? Yes Yes Device failed Protect another Block Group? No Remove VID from RESET Write RESET command END Yes Yes Device failed Yes Yes Remove VID from RESET Write RESET command END Last Block Group verified ? No Note : All blocks must be protected before unprotect operation is executing. Figure 7. Block Group Protection & Unprotection Algorithms 20 Revision 0.0 September 2006 www.DataSheet.in K5L2731CAM-D770 Table 8. Block Protection Schemes DYB PPB PPB Lock Block State Preliminary MCP MEMORY 0 0 0 1 1 0 1 1 0 0 1 0 1 1 0 1 0 1 0 0 0 1 1 1 Unprotected-PPB and DYB are changeable Unprotected-PPB not changeable and DYB are changeable Protected-PPB and DYB are changeable Protected-PPB not changeable, DYB is changeable Block Protection The device features several levels of block protection, which can disable both the program and erase operations in certain blocks or block groups: Persistent Block Protection A command block protection method that replaces the old 12 V controlled protection method. Password Block Protection A highly sophisticated protection method that requires a password before changes to certain blocks or block groups are permitted Selecting a Block Protection Mode All parts default to operate in the Persistent Block Protection mode. The customer must then choose if the Persistent or Password Protection method is most desirable. There are two one-time programmable non-volatile bits that define which block protectionmethod will be used. If the Persistent Block Protection method is desired, programming the Persistent Block Protection Mode Locking Bit permanently sets the device to the Persistent Block Protection mode. If the Password Block Protection method is desired, programming the Password Mode Locking Bit permanently sets the device to the Password Block Protection mode. It is not possible to switch between the two protection modes once a locking bit has been set. One of the two modes must be selected when the device is first programmed. This prevents a program or virus from later setting the Password Mode Locking Bit, which would cause an unexpected shift from the default Persistent Block Protection Mode into the Password Protection Mode. The device is shipped with all blocks unprotected. Optional Samsung programming services enable programming and protecting blocks at the factory prior to shipping the device. Contact your local sales office for details. It is possible to determine whether a block is protected or unprotected. See Autoselect Mode for details. Persistent Block Protection The Persistent Block Protection method replaces the 12 V controlled protection method in previous flash devices. This new method provides three different block protection states: Persistently Locked - The block is protected and cannot be changed. Dynamically Locked - The block is protected and can be changed by a simple command. Unlocked - The block is unprotected and can be changed by a simple command. To achieve these states, three types of "bits" are used: Persistent Protection Bit Persistent Protection Bit Lock Persistent Block Protection Mode Locking Bit Persistent Protection Bit (PPB) A single Persistent (non-volatile) Protection Bit is assigned to a maximum four blocks (see the block address tables for specific block protection groupings). All 4 Kword boot-block sectors have individual block Persistent Protection Bits(PPBs) for greater flexibility. Each PPB is individually modifiable through the PPB Write Command. 21 Revision 0.0 September 2006 www.DataSheet.in K5L2731CAM-D770 Preliminary MCP MEMORY The device erases all PPBs in parallel. If any PPB requires erasure, the device must be instructed to preprogram all of the block PPBs prior to PPB erasure. Otherwise, a previously erased block PPBs can potentially be over-erased. The flash device does not have a built-in means of preventing block PPBs over-erasure. Persistent Protection Bit Lock (PPB Lock) The Persistent Protection Bit Lock (PPB Lock) is a global volatile bit. When set to "1", the PPBs cannot be changed. When cleared "0", the PPBs are changeable. There is only one PPB Lock bit per device. The PPB Lock is cleared after power-up or hardware reset. There is no command sequence to unlock the PPB Lock. Dynamic Protection Bit (DYB) A volatile protection bit is assigned for each block. After power-up or hardware reset, the contents of all DYBs is "0". Each DYB is individually modifiable through the DYB Write Command. When the parts are first shipped, the PPBs are cleared, the DYBs are cleared, and PPB Lock is defaulted to power up in the cleared state meaning the PPBs are changeable. When the device is first powered on the DYBs power up cleared (blocks not protected). The Protection State for each sector is determined by the logical OR of the PPB and the DYB related to that block. For the blocks that have the PPBs cleared, the DYBs control whether or not the block is protected or unprotected. By issuing the DYB Write command sequences, the DYBs will be set or cleared, thus placing each block in the protected or unprotected state. These are the so-called Dynamic Locked or Unlocked states. They are called dynamic states because it is very easy to switch back and forth between the protected and unprotected conditions. This allows software to easily protect blocks against inadvertent changes yet does not prevent the easy removal of protection when changes are needed. The DYBs maybe set or cleared as often as needed. The PPBs allow for a more static, and difficult to change, level of protection. The PPBs retain their state across power cycles because they are non-volatile. Individual PPBs are set with a command but must all be cleared as a group through a complex sequence of program and erasing commands. The PPBs are also limited to 100 erase cycles. The PPB Lock bit adds an additional level of protection. Once all PPBs are programmed to the desired settings, the PPB Lock may be set to "1". Setting the PPB Lock disables all program and erase commands to the non-volatile PPBs. In effect, the PPB Lock Bit locks the PPBs into their current state. The only way to clear the PPB Lock is to go through a power cycle. System boot code can determine if any changes to the PPB are needed; for example, to allow new system code to be downloaded. If no changes are needed then the boot code can set the PPB Lock to disable any further changes to the PPBs during system operation. The WP#/ACC write protect pin adds a final level of hardware protection to blocks BA269 and BA268, BA0 and BA1. When this pin is low it is not possible to change the contents of these blocks. These blocks generally hold system boot code. The WP#/ACC pin can prevent any changes to the boot code that could override the choices made while setting up block protection during system initialization. For customers who are concerned about malicious viruses there is another level of security - the persistently locked state. To persistently protect a given block or block group, the PPBs associated with that block need to be set to "1". Once all PPBs are programmed to the desired settings, the PPB Lock should be set to "1". Setting the PPB Lock automatically disables all program and erase commands to the Non-Volatile PPBs. In effect, the PPB Lock "freezes" the PPBs into their current state. The only way to clear the PPB Lock is to go through a power cycle. It is possible to have blocks that have been persistently locked, and blocks that are left in the dynamic state. The blocks in the dynamic state are all unprotected. If there is a need to protect some of them, a simple DYB Write command sequence is all that is necessary. The DYB write command for the dynamic blocks switch the DYBs to signify protected and unprotected, respectively. If there is a need to change the status of the persistently locked blocks, a few more steps are required. First, the PPB Lock bit must be disabled by either putting the device through a power-cycle, or hardware reset. The PPBs can then be changed to reflect the desired settings. Setting the PPB lock bit once again will lock the PPBs, and the device operates normally again. The best protection is achieved by executing the PPB lock bit set command early in the boot code, and protect the boot code by holding WP#/ ACC = VIL. Table 8 contains all possible combinations of the DYB, PPB, and PPB lock relating to the status of the block. In summary, if the PPB is set, and the PPB lock is set, the block is protected and the protection can not be removed until the next power cycle clears the PPB lock. If the PPB is cleared, the block can be dynamically locked or unlocked. The DYB then controls whether or not the block is protected or unprotected. 22 Revision 0.0 September 2006 www.DataSheet.in K5L2731CAM-D770 Preliminary MCP MEMORY If the user attempts to program or erase a protected block, the device ignores the command and returns to read mode. A program command to a protected block enables status polling for approximately 1us before the device returns to read mode without having modified the contents of the protected block. An erase command to a protected block enables status polling for approximately 50us after which the device returns to read mode without having erased the protected block. The programming of the DYB, PPB, and PPB lock for a given block can be verified by writing a DYB/PPB/PPB lock verify command to the device. Persistent Block Protection Mode Locking Bit Like the password mode locking bit, a Persistent Block Protection mode locking bit exists to guarantee that the device remain in software block protection. Once set, the Persistent Block Protection locking bit prevents programming of the password protection mode locking bit. This guarantees that a hacker could not place the device in password protection mode. Password Protection Mode The Password Block Protection Mode method allows an even higher level of security than the Persistent Block Protection Mode. There are two main differences between the Persistent Block Protection and the Password Block Protection Mode: When the device is first powered on, or comes out of a reset cycle, the PPB Lock bit set to the locked state, rather than cleared to the unlocked state. The only means to clear the PPB Lock bit is by writing a unique 64-bit Password to the device. The Password Block Protection method is otherwise identical to the Persistent Block Protection method. A 64-bit password is the only additional tool utilized in this method. Once the Password Mode Locking Bit is set, the password is permanently set with no means to read, program, or erase it. The password is used to clear the PPB Lock bit. The Password Unlock command must be written to the flash, along with a password. The flash device internally compares the given password with the pre-programmed password. If they match, the PPB Lock bit is cleared, and the PPBs can be altered. If they do not match, the flash device does nothing. There is a built-in 2us delay for each "password check." This delay is intended to thwart any efforts to run a program that tries all possible combinations in order to crack the password. Password and Password Mode Locking Bit In order to select the Password block protection scheme, the customer must first program the password. The password may be correlated to the unique Electronic Serial Number (ESN) of the particular flash device. Each ESN is different for every flash device; therefore each password should be different for every flash device. While programming in the password region, the customer may perform Password Verify operations. Once the desired password is programmed in, the customer must then set the Password Mode Locking Bit. This operation achieves two objectives: Permanently sets the device to operate using the Password Protection Mode. It is not possible to reverse this function. Disables all further commands to the password region. All program, and read operations are ignored. Both of these objectives are important, and if not carefully considered, may lead to unrecoverable errors. The user must be sure that the Password Protection method is desired when setting the Password Mode Locking Bit. More importantly, the user must be sure that the password is correct when the Password Mode Locking Bit is set. Due to the fact that read operations are disabled, there is no means to verify what the password is afterwards. If the password is lost after setting the Password Mode Locking Bit, there will be no way to clear the PPB Lock bit. The Password Mode Locking Bit, once set, prevents reading the 64-bit password on the DQ bus and further password programming. The Password Mode Locking Bit is not erasable. Once Password Mode Locking Bit is programmed, the Persistent Block Protection Locking Bit is disabled from programming, guaranteeing that no changes to the protection scheme are allowed. 64-bit Password The 64-bit Password is located in its own memory space and is accessible through the use of the Password Program and Verify commands (see "Password Verify Command"). The password function works in conjunction with the Password Mode Locking Bit, which when set, prevents the Password Verify command from reading the contents of the password on the pins of the device. Write Protect (WP#) The Write Protect feature provides a hardware method of protecting the upper two and lower two blocks without using VID. This function is provided by the WP# pin and overrides the previously discussed "High Voltage Block Protection" section method. 23 Revision 0.0 September 2006 www.DataSheet.in K5L2731CAM-D770 Preliminary MCP MEMORY If the system asserts VIL on the WP#/ACC pin, the device disables program and erase functions in the two outermost 4 Kword blocks on both ends of the flash array independent of whether it was previously protected or unprotected. If the system asserts VIH on the WP#/ACC pin, the device reverts the upper two and lower two blocks to whether they were last set to be protected or unprotected. That is, block protection or unprotection for these sectors depends on whether they were last protected or unprotected using the method described in the "High Voltage Block Protection" section. Persistent Protection Bit Lock The Persistent Protection Bit (PPB) Lock is a volatile bit that reflects the state of the Password Mode Locking Bit after power-up reset. If the Password Mode Lock Bit is also set after a hardware reset (RESET# asserted) or a power-up reset, the ONLY means for clearing the PPB Lock Bit in Password Protection Mode is to issue the Password Unlock command. Successful execution of the Password Unlock command clears the PPB Lock Bit, allowing for block PPBs modifications. Asserting RESET#, taking the device through a power-on reset, or issuing the PPB Lock Bit Set command sets the PPB Lock Bit to a "1" when the Password Mode Lock Bit is not set. If the Password Mode Locking Bit is not set, including Persistent Protection Mode, the PPB Lock Bit is cleared after power-up or hardware reset. The PPB Lock Bit is set by issuing the PPB Lock Bit Set command. Once set the only means for clearing the PPB Lock Bit is by issuing a hardware or power-up reset. The Password Unlock command is ignored in Persistent Protection Mode. Master locking bit set This Master locking bit can ensure that protected blocks be permanently unalterable. Master locking bit is non-volatile bit. Master locking bit controls protection status of entire blocks. The usage of the master locking bit command sequence is absolutely required to ensure full protection of data from future alterations. If master locking bit is set ("1"), entire blocks are permanently protected. They are not changed and altered by any future lock/unlock commands. Anyone who uses this fuction needs much attention. Because there is no way to return to unlock status. Default status of master locking bit is unlock status("0"). If Master locking bit sets on unprotected block, the block still are remaining in status of unprotected block. The unprotected block can be protected by protection command. 24 Revision 0.0 September 2006 www.DataSheet.in K5L2731CAM-D770 Table 9. Boot Block/Block Addresses for Protection / Unprotection Block BA0 BA1 BA2 BA3 BA4 BA5 BA6 BA7 BA8 BA9 BA10 BA11-BA14 BA15-BA18 BA19-BA22 BA23-BA26 BA27-BA30 BA31-BA34 BA35-BA38 BA39-BA42 BA43-BA46 BA51-BA54 BA55-BA58 BA59-BA62 BA63-BA66 BA67-BA70 BA71-BA74 BA75-BA78 BA79-BA82 BA83-BA86 BA87-BA90 BA91-BA94 BA95-BA98 BA99-BA102 BA103-BA106 BA107-BA110 BA111-BA114 BA115-BA118 BA119-BA122 BA123-BA126 BA127-BA130 BA131-BA134 BA135-BA138 BA139-BA142 BA143-BA146 BA147-BA150 A22-A12 00000000000 00000000001 00000000010 00000000011 00000000100 00000000101 00000000110 00000000111 00000001XXX 00000010XXX 00000011XXX 000001XXXXX 000010XXXXX 000011XXXXX 000100XXXXX 000101XXXXX 000110XXXXX 000111XXXXX 001000XXXXX 001001XXXXX 001010XXXXX 001011XXXXX 001101XXXXX 001110XXXXX 001111XXXXX 010000XXXXX 010001XXXXX 010010XXXXX 010011XXXXX 010100XXXXX 010101XXXXX 010110XXXXX 010111XXXXX 011000XXXXX 011001XXXXX 011010XXXXX 011011XXXXX 011100XXXXX 011101XXXXX 011110XXXXX 011111XXXXX 100000XXXXX 100001XXXXX 100010XXXXX 100011XXXXX Preliminary MCP MEMORY Block Size 4 Kwords 4 Kwords 4 Kwords 4 Kwords 4 Kwords 4 Kwords 4 Kwords 4 Kwords 32 Kwords 32 Kwords 32 Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 25 Revision 0.0 September 2006 www.DataSheet.in K5L2731CAM-D770 Table 9. Boot Block/Block Addresses for Protection / Unprotection (Continued) Block BA151-BA154 BA155-BA158 BA159-BA162 BA163-BA166 BA167-BA170 BA171-BA174 BA175-BA178 BA179-BA182 BA183-BA186 BA187-BA190 BA191-BA194 BA195-BA198 BA199-BA202 BA203-BA206 BA207-BA210 BA211-BA214 BA215-BA218 BA219-BA222 BA223-BA226 BA227-BA230 BA231-BA234 BA235-BA238 BA239-BA242 BA243-BA246 BA247-BA250 BA251-BA254 BA255-BA258 BA259 BA260 BA261 BA262 BA263 BA264 BA265 A22-A12 100100XXXXX 100101XXXXX 100110XXXXX 100111XXXXX 101000XXXXX 101001XXXXX 101010XXXXX 101011XXXXX 101100XXXXX 101101XXXXX 101110XXXXX 101111XXXXX 110000XXXXX 110001XXXXX 110010XXXXX 110011XXXXX 110100XXXXX 110101XXXXX 110110XXXXX 110111XXXXX 111000XXXXX 111001XXXXX 111010XXXXX 111011XXXXX 111100XXXXX 111101XXXXX 111110XXXXX 11111100XXX 11111101XXX 11111110XXX 11111111000 11111111001 11111111010 11111111011 Preliminary MCP MEMORY Block Size 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 32 Kwords 32 Kwords 32 Kwords 4 Kwords 4 Kwords 4 Kwords 4 Kwords 26 Revision 0.0 September 2006 www.DataSheet.in K5L2731CAM-D770 Table 10. Block Protection Command Sequences Command Sequence Addr Password Program(1,2) Data Addr Password Verify(2,4,5) Data Addr Password Unlock(3,6,7) Data Addr PPB Program(1,2,8) 6 Data Addr Master locking bit Set Data Addr PPB Status Data Addr All PPB Erase(1,2,9,10) Data Addr PPB Lock Bit Set Data Addr PPB Lock Bit Status(11) Data Addr DYB Write(3) Data Addr DYB Erase(3) Data Addr DYB Status(2) Data Addr PPMLB Program(1,2,8) Data Addr PPMLB Status(1) Data Addr SPMLB Program(1,2,8) Data Addr SPMLB Status(1) Data 5 AAH 55H 60H 48 RD(0) 6 AAH 555H 55H 2AAH 60H 555H 68 BL 48 BL 5 AAH 555H 55H 2AAH 60H 555H 48H BL RD(0) BL 6 AAH 555H 55H 2AAH 60H 555H 68H PL 48H PL 4 AAH 555H 55H 2AAH 58H 555H RD(0) PL PL 4 AAH 555H 55H 2AAH 48H (DA)555H X0H BA 4 AAH 555H 55H 2AAH 48H 555H X1H BA 4 AAH 555H 55H 2AAH 58H 555H RD(1) BA 3 AAH 555H 55H 2AAH 78H 555H BA 6 AAH 555H 55H 2AAH 60H 555H 60H 40H 4 AAH 555H 55H 2AAH 90H 555H 3 AAH 555H 55H 2AAH F1H 555H (BA)WP RD(0) WP (BA) AAH 555H 55H 2AAH 60H 555H 68H 48H 7 AAH 555H 55H 2AAH 28H 555H PWD[0] (BA)WP PWD[1] (BA)WP 4 AAH 555H 55H 2AAH C8H 555H PWD[0-3] PWA[0] PWA[1] 4 AAH 555H 55H 2AAH 38H 555H PD[0-3] PWA[0-3] Cycle 1st Cycle 555H 2nd Cycle 2AAH 3rd Cycle 555H 4th Cycle XX[0-3]H 5th Cycle Preliminary MCP MEMORY 6th Cycle 7th Cycle PWA[2] PWD[2] (BA)WP RD(0) PWA[3] PWD[3] (BA)WP RD(0) PL RD(0) BL RD(0) Legend: DYB = Dynamic Protection Bit OW = Address (A7:A0) is (00011010) PD[3:0] = Password Data (1 of 4 portions) PPB = Persistent Protection Bit PWA = Password Address. A1:A0 selects portion of password. PWD = Password Data being verified. PL = Password Protection Mode Lock Address (A7:A0) is (00001010) RD(0) = Read Data DQ0 for protection indicator bit. RD(1) = Read Data DQ1 for PPB Lock status. BA = Block Address where security command applies. Address bits Amax:A12 uniquely select any block. BL = Persistent Protection Mode Lock Address (A7:A0) is (00010010) WP = PPB Address (A7:A0) is (00000010) X = Don't care PPMLB = Password Protection Mode Locking Bit SPMLB = Persistent Protection Mode Locking Bit 27 Revision 0.0 September 2006 www.DataSheet.in K5L2731CAM-D770 Preliminary MCP MEMORY Notes: * See the description of bus operations. * All values are in hexadecimal. * Shaded cells in table denote read cycles. All other cycles are write operations. * During unlock and command cycles, when lower address bits are 555 or 2AAh as shown in table, address bits higher than A11 (except where BA is required) and data bits higher than DQ7 are don't cares. 1. The reset command returns device to reading array. 2. Cycle 4 programs the addressed locking bit. Cycles 5 and 6 validate bit has been fully programmed when DQ0 = 1. If DQ0 = 0 in cycle 6, program command must be issued and verified again. 3. Data is latched on the rising edge of WE#. 4. Entire command sequence must be entered for each portion of password. 5. Command sequence returns FFh if PPMLB is set. 6. The password is written over four consecutive cycles, at addresses 0-3. 7. A 2us timeout is required between any two portions of password. 8. A 100us timeout is required between cycles 4 and 5. 9. A 1.2 ms timeout is required between cycles 4 and 5. 10. Cycle 4 erases all PPBs. Cycles 5 and 6 validate bits have been fully erased when DQ0 = 0. If DQ0 = 1 in cycle 6, erase command must be issued and verified again. Before issuing erase command, all PPBs should be programmed to prevent PPB overerasure. 11. DQ1 = 1 if PPB locked, 0 if unlocked. 28 Revision 0.0 September 2006 www.DataSheet.in K5L2731CAM-D770 Table 11. Common Flash Memory Interface Code Description Preliminary MCP MEMORY Addresses (Word Mode) 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 20H 21H 22H 23H 24H 25H 26H 27H 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH 30H 31H 32H 33H 34H 35H 36H 37H 38H 39H 3AH 3BH 3CH Data 0051H 0052H 0059H 0002H 0000H 0040H 0000H 0000H 0000H 0000H 0000H 0027H 0036H 0000H 0000H 0003H 0000H 0009H 0000H 0004H 0000H 0004H 0000H 0018H 0001H 0000H 0000H 0000H 0003H 0007H 0000H 0020H 0000H 00FDH 0000H 0000H 0001H 0007H 0000H 0020H 0000H 0000H 0000H 0000H 0000H Query Unique ASCII string "QRY" Primary OEM Command Set Address for Primary Extended Table Alternate OEM Command Set (00h = none exists) Address for Alternate OEM Extended Table (00h = none exists) Vcc Min. (write/erase) D7-D4: volt, D3-D0: 100 millivolt Vcc Max. (write/erase) D7-D4: volt, D3-D0: 100 millivolt Vpp Min. voltage(00H = no Vpp pin present) Vpp Max. voltage(00H = no Vpp pin present) Typical timeout per single word write 2 us Typical timeout for Min. size buffer write 2N us(00H = not supported) Typical timeout per individual block erase 2N ms Typical timeout for full chip erase 2N ms(00H = not supported) Max. timeout for word write 2 times typical Max. timeout for buffer write 2N times typical Max. timeout per individual block erase 2N times typical Max. timeout for full chip erase 2 times typical(00H = not supported) Device Size = 2N byte Flash Device Interface description Max. number of byte in multi-byte write = 2N Number of Erase Block Regions within device N N N Erase Block Region 1 Information Erase Block Region 2 Information Erase Block Region 3 Information Erase Block Region 4 Information 29 Revision 0.0 September 2006 www.DataSheet.in K5L2731CAM-D770 Table 11. Common Flash Memory Interface Code Description Preliminary MCP MEMORY Addresses (Word Mode) 40H 41H 42H 43H 44H 45H Data 0050H 0052H 0049H 0030H 0030H 0000H Query-unique ASCII string "PRI" Major version number, ASCII Minor version number, ASCII Address Sensitive Unlock(Bits 1-0) 0 = Required, 1= Not Required Silcon Revision Number(Bits 7-2) Erase Suspend 0 = Not Supported, 1 = To Read Only, 2 = To Read & Write Block Protect 00 = Not Supported, 01 = Supported Block Temporary Unprotect 00 = Not Supported, 01 = Supported Block Protect/Unprotect scheme, 00 = Not Supported, 01 = Supported Simultaneous Operation 00 = Not Supported, 01 = Supported Burst Mode Type 00 = Not Supported, 01 = Supported Page Mode Type 00 = Not Supported, 01 = 4 Word Page 02 = 8 Word Page ACC(Acceleration) Supply Minimum 00 = Not Supported, D7 - D4 : Volt, D3 - D0 : 100mV ACC(Acceleration) Supply Maximum 00 = Not Supported, D7 - D4 : Volt, D3 - D0 : 100mV Top/Bottom Boot Block Flag 02H = Bottom Boot Device, 03H = Top Boot Device, 04H = Top and Bottom Device 46H 47H 48H 49H 4AH 4BH 4CH 4DH 4EH 4FH 0002H 0001H 0001H 0001H 0001H 0000H 0002H 0085H 0095H 0004H 30 Revision 0.0 September 2006 www.DataSheet.in K5L2731CAM-D770 DEVICE STATUS FLAGS Preliminary MCP MEMORY The device has means to indicate its status of operation in the bank where a program or erase operation is in processes. Address must include bank address being excuted internal routine operation. The status is indicated by raising the device status flag via corresponding DQ pins or the RY/ BY pin. The corresponding DQ pins are DQ7, DQ6, DQ5, DQ3 and DQ2. The statuses are as follows : Table 12. Hardware Sequence Flags Status Programming Block Erase or Chip Erase Erase Suspend Read Erase Suspend Read In Progress Erase Suspend Program Program Suspend Read Program Suspend Read Programming Exceeded Time Limits Block Erase or Chip Erase Erase Suspend Program Erase Suspended Block Non-Erase Suspended Block Non-Erase Suspended Block Program Suspended Block Non-Program Suspended Block DQ7 DQ7 0 1 Data DQ7 DQ7 Data DQ7 0 DQ7 DQ6 Toggle Toggle 1 Data Toggle 1 Data Toggle Toggle Toggle DQ5 0 0 0 Data 0 0 Data 1 1 1 DQ3 0 1 0 Data 0 0 Data 0 1 0 DQ2 1 Toggle Toggle (Note 1) Data 1 Toggle (Note 1) Data No Toggle (Note 2) No Toggle RY/BY 0 0 1 1 0 1 1 0 0 0 Notes : 1. DQ2 will toggle when the device performs successive read operations from the erase/program suspended block. 2. If DQ5 is High (exceeded timing limits), successive reads from a problem block will cause DQ2 to toggle. DQ7 : Data Polling When an attempt to read the device is made while executing the Internal Program, the complement of the data is written to DQ7 as an indication of the Routine in progress. When the Routine is completed an attempt to access to the device will produce the true data written to DQ7. When a user attempts to read the block being erased, DQ7 will be low. If the device is placed in the Erase/Program Suspend Mode, the status can be detected via the DQ7 pin. If the system tries to read an address which belongs to a block that is being erase suspended, DQ7 will be high. And, if the system tries to read an address which belongs to a block that is being program suspended, the output will be the true data of DQ7 itself. If a non-erase-suspended or non-program-suspended block address is read, the device will produce the true data to DQ7. If an attempt is made to program a protected block, DQ7 outputs complements the data for approximately 1s and the device then returns to the Read Mode without changing data in the block. If an attempt is made to erase a protected block, DQ7 outputs complement data in approximately 100us and the device then returns to the Read Mode without erasing the data in the block. DQ6 : Toggle Bit Toggle bit is another option to detect whether an Internal Routine is in progress or completed. Once the device is at a busy state, DQ6 will toggle. Toggling DQ6 will stop after the device completes its Internal Routine. If the device is in the Erase/Program Suspend Mode, an attempt to read an address that belongs to a block that is being erased or programmed will produce a high output of DQ6. If an address belongs to a block that is not being erased or programmed, toggling is halted and valid data is produced at DQ6. If an attempt is made to program a protected block, DQ6 toggles for approximately 1us and the device then returns to the Read Mode without changing the data in the block. If an attempt is made to erase a protected block, DQ6 toggles for approximately 100s and the device then returns to the Read Mode without erasing the data in the block. 31 Revision 0.0 September 2006 www.DataSheet.in K5L2731CAM-D770 DQ5 : Exceed Timing Limits Preliminary MCP MEMORY If the Internal Program/Erase Routine extends beyond the timing limits, DQ5 will go High, indicating program/erase failure. DQ3 : Block Erase Timer The status of the multi-block erase operation can be detected via the DQ3 pin. DQ3 will go High if 50s of the block erase time window expires. In this case, the Internal Erase Routine will initiate the erase operation.Therefore, the device will not accept further write commands until the erase operation is completed. DQ3 is Low if the block erase time window is not expired. Within the block erase time window, an additional block erase command (30H) can be accepted. To confirm that the block erase command has been accepted, the software may check the status of DQ3 following each block erase command. DQ2 : Toggle Bit 2 The device generates a toggling pulse in DQ2 only if an Internal Erase Routine or an Erase/Program Suspend is in progress. When the device executes the Internal Erase Routine, DQ2 toggles only if an erasing bank is read. Although the Internal Erase Routine is in the Exceeded Time Limits, DQ2 toggles only if an erasing block in the Exceeded Time Limits is read. When the device is in the Erase/Program Suspend mode, DQ2 toggles only if an address in the erasing or programming block is read. If a non-erasing or non-programmed block address is read during the Erase/Program Suspend mode, then DQ2 will produce valid data. DQ2 will go High if the user tries to program a non-erase suspend block while the device is in the Erase Suspend mode. RY/BY : Ready/Busy The device has a Ready / Busy output that indicates either the completion of an operation or the status of Internal Algorithms. If the output is Low, the device is busy with either a program or an erase operation. If the output is High, the device is ready to accept any read/write or erase operation. When the RY/ BY pin is low, the device will not accept any additional program or erase commands with the exception of the Erase Suspend command. If the device is placed in an Erase Suspend mode, the RY/ BY output will be High. For programming, the RY/ BY is valid (RY/ BY = 0) after the rising edge of the fourth WE pulse in the four write pulse sequence. For Chip Erase, RY/ BY is also valid after the rising edge of WE pulse in the six write pulse sequence. For Block Erase, RY/ BY is also valid after the rising edge of the sixth WE pulse. The pin is an open drain output, allowing two or more Ready/ Busy outputs to be OR-tied. An appropriate pull-up resistor is required for proper operation. Rp VCC Vcc (Max.) - VOL (Max.) Rp = Ready / Busy open drain output 3.2 V = 2.1mA + IL IOL + IL where IL is the sum of the input currents of all devices tied to the Ready / Busy pin. GND Device 32 Revision 0.0 September 2006 www.DataSheet.in K5L2731CAM-D770 Start Read(DQ0~DQ7) Valid Address Preliminary MCP MEMORY Start Read(DQ0~DQ7) Valid Address Read(DQ0~DQ7) Valid Address DQ7 = Data ? Yes No No DQ6 = Toggle ? No Yes No DQ5 = 1 ? Yes DQ5 = 1 ? Yes Read(DQ0~DQ7) Valid Address Yes Read twice(DQ0~DQ7) Valid Address No DQ7 = Data ? No DQ6 = Toggle ? Yes Fail Pass Fail Pass Figure 8. Data Polling Algorithms Figure 9. Toggle Bit Algorithms 33 Revision 0.0 September 2006 www.DataSheet.in K5L2731CAM-D770 ABSOLUTE MAXIMUM RATINGS Parameter Vcc Voltage on any pin relative to VSS A9, OE , RESET WP/ACC All Other Pins Temperature Under Bias Storage Temperature Short Circuit Output Current Operating Temperature Tbias Tstg IOS TA VIN Symbol Vcc Rating -0.5 to +4.0 -0.5 to +9.5 -0.5 to +9.5 -0.5 to +2.5 -25 to +125 -65 to +150 5 -25 to + 85 Preliminary MCP MEMORY Unit V C C mA C Notes : 1. Minimum DC voltage is -0.5V on Input/ Output pins. During transitions, this level may fall to -2.0V for periods <20ns. Maximum DC voltage on input / output pins is Vcc+0.5V which, during transitions, may overshoot to Vcc+2.0V for periods <20ns. 2. Minimum DC voltage is -0.5V on A9, OE, RESET and WP/ACC pins. During transitions, this level may fall to -2.0V for periods <20ns. Maximum DC voltage on A9, OE, RESET, WP/ACC pins is 9.5V which, during transitions, may overshoot to 14.0V for periods <20ns. 3. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to the conditions detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect reliability. RECOMMENDED OPERATING CONDITIONS ( Voltage reference to GND ) Parameter Supply Voltage Supply Voltage Symbol VCC VSS Min 2.7 0 Typ. 3.0 0 Max 3.6 0 Unit V V DC CHARACTERISTICS Parameter Input Leakage Current A9,OE,RESET Input Leakage Current WP/ACC Input Leakage Current Output Leakage Current Active Read Current (1) Active Write Current (2) Read While Program Current (3) Read While Erase Current (3) Program While Erase Suspend Current Page Read Current Symbol ILI ILIT ILIW ILO ICC1 ICC2 ICC3 ICC4 ICC5 ICC6 IACC ISB1 ISB2 ISB3 VIL VIH VHH Test Conditions VIN=VSS to VCC, VCC=VCCmax VCC=VCCmax, A9,OE,RESET=9.5V VCC=VCCmax, WP/ACC=9.5V VOUT=VSS to VCC,VCC=VCCmax,OE=VIH OE=VIH, VCC=VCCmax CE=VIL, OE=VIH, WE=VIL CE=VIL, OE=VIH (@10Mhz) CE=VIL, OE=VIH (@10Mhz) CE=VIL, OE=VIH OE=VIH, 8 word Page Read CE=VIL, OE=VIH CE, RESET, WP/ACC= VIO 0.3 RESET= Vss 0.3 VIH=VIO 0.3V, VIL=VSS 0.2V Vio=1.65~1.95V(2.7~3.6V) Vio=1.65~1.95V(2.7~3.6V) Vcc = 3.0V Min - 1.0 - 1.0 10MHz 5MHz -0.4(-0.5) Vio-0.4(2.0) Typ 45 20 15 35 35 15 10 15 15 15 15 - Max + 1.0 35 35 + 1.0 55 30 30 55 55 35 15 30 30 30 30 0.4(0.8) Vio+0.4( Vcc+0.3) Unit A A A A mA mA mA mA mA mA mA A A A V V V ACC Accelerated Program Current Standby Current Standby Current During Reset Automatic Sleep Mode Input Low Level Input High Level Voltage for WP/ACC Block Temporarily Unprotect and Program Acceleration (4) 0.15V 8.5 9.5 34 Revision 0.0 September 2006 www.DataSheet.in K5L2731CAM-D770 Parameter Voltage for Autoselect and Block Protect (4) Preliminary MCP MEMORY Symbol VID Vcc = 3.0V Test Conditions Min 8.5 Vio-0.1 2.4 Typ - Max 9.5 0.1 0.4 Unit V V V V V V 10% IOL =100uA,Vcc=VCCmin, Output Low Level VOL Vio=1.65~1.95V IOL =2.0mA,Vcc=VCCmin, Vio=2.7~3.6V IOH = -100uA, Vcc=VCCmin, Output High Level VOH Vio=1.65~1.95V - 2.5 IOH = -2.0mA, Vcc=VCCmin, Vio=2.7~3.6V Low VCC Lock-out Voltage (5) VLKO 2.3 Notes : 1. The ICC current listed includes both the DC operating current and the frequency dependent component(at 10 MHz). 2. ICC active during Internal Routine(program or erase) is in progress. 3. ICC active during Read while Write is in progress. 4. The high voltage ( VHH or VID ) must be used in the range of Vcc = 3.0V 0.15V 5. Not 100% tested. 6. Typical value are measured at Vcc = 3.0V,TA=25C , Not 100% tested. CAPACITANCE(TA = 25 C, VCC = 3.0V, f = 1.0MHz) Item Input Capacitance Output Capacitance Control Pin Capacitance Symbol CIN COUT CIN2 Test Condition VIN=0V VOUT=0V VIN=0V Min Max 10 10 10 Unit pF pF pF Note : Capacitance is periodically sampled and not 100% tested. AC TEST CONDITION Parameter Input Pulse Levels Input Rise and Fall Times(Vio=1.8,3.0V) Input and Output Timing Levels Output Load Vcc Vcc/2 0V CL Input Pulse and Test Point Input & Output Test Point Value 0V to Vcc 5ns Vcc/2 CL = 30pF Vcc/2 Device * CL= 30pF including Scope and Jig Capacitance AC CHARACTERISTICS Read Operations Parameter Symbol Min Read Cycle Time (1) Address Access Time Chip Enable Access Time Output Enable Time Page Read Cycle Time (1) Page Address Access Time CE & OE Disable Time (1) Output Hold Time from Address, CE or OE (1) Note : 1. Not 100% tested. Output Load VCC=2.7V~3.6V 4A Max 55 55 20 20 16 Min 60 25 5 4B Max 60 60 25 25 16 Min 65 25 5 4C Max 65 65 30 25 16 Min 70 30 5 4D Max 70 70 30 30 16 ns ns ns ns ns ns ns ns Unit tRC tAA tCE tOE tPRC tPA tDF tOH 55 20 5 35 Revision 0.0 September 2006 www.DataSheet.in K5L2731CAM-D770 AC CHARACTERISTICS Write(Erase/Program)Operations Alternate WE Controlled Write VCC=2.7V ~ 3.6V Parameter Symbol Min Write Cycle Time (1) Address Setup Time tWC tAS tASO tAH tAHT tDS tDH tOES tOEH1 tOEH2 tCS tCH tWP tWPH tPGM tACCPGM tACCPGM_Q UAD Preliminary MCP MEMORY 4A Max 6(typ.) 4(typ.) 1.2(typ.) 0.7(typ.) 50 0 50 20 35 500 500 4 500 200 0 20 10 90 20 50 0 50 20 35 500 500 4 500 200 0 20 10 Min 60 0 15 35 0 30 0 0 0 10 0 0 35 25 4B Max 6(typ) 4(typ) 1.2(typ.) 0.7(typ) 90 20 Min 65 0 15 35 0 30 0 0 0 10 0 0 35 25 4C Max 6(typ.) 4(typ.) 1.2(typ.) 0.7(typ.) 50 0 50 20 35 500 500 4 500 200 0 20 10 90 20 Min 70 0 15 35 0 30 0 0 0 10 0 0 35 25 4D Max 6(typ.) 4(typ.) 1.2(typ.) 0.7(typ.) 50 0 50 20 35 500 500 4 500 200 0 20 10 90 20 - Uni t ns ns ns ns ns ns ns ns ns ns ns ns ns ns s s s sec s ns ns s ns ns ns s s ns ns ns ns ns 55 0 15 30 0 25 0 0 0 10 0 0 35 20 Address Hold Time Data Setup Time Data Hold Time Output Enable Setup Time (1) Output Enable Hold Read (1) Toggle and Data Polling (1) CE Setup Time CE Hold Time Write Pulse Width Write Pulse Width High Programming Operation Accelerated Programming Operation Accelerated Quad word gramming Operation Block Erase Operation (2) VCC Set Up Time Write Recovery Time from RY/BY RESET High Time Before Read RESET to Power Down Time Program/Erase Valid to RY/BY Delay VID Rising and Falling Time RESET Pulse Width RESET Low to RY/BY High RESET Setup Time for Temporary Unprotect RESET Low Setup Time RESET High to Address Valid Read Recovery Time Before Write CE High during toggling bit polling OE High during toggling bit polling Pro- tBERS tVCS tRB tRH tRPD tBUSY tVID tRP tRRB tRSP tRSTS tRSTW tGHWL tCEPH tOEPH Notes : 1. Not 100% tested. 2. The duration of the Program or Erase operation varies and is calculated in the internal algorithms. 36 Revision 0.0 September 2006 www.DataSheet.in K5L2731CAM-D770 AC CHARACTERISTICS Write(Erase/Program)Operations Alternate CE Controlled Writes VCC=2.7V ~ 3.6V Parameter Symbol Min Write Cycle Time (1) Address Setup Time Address Hold Time Data Setup Time Data Hold Time Output Enable Setup Time (1) Output Read (1) Enable Toggle and Data Hold Polling (1) Time WE Setup Time WE Hold Time CE Pulse Width CE Pulse Width High Programming Operation Accelerated Programming Operation Accelerated Quad word Programming Operation Block Erase Operation (2) tWC tAS tAH tDS tDH tOES tOEH1 tOEH2 tWS tWH tCP tCPH tPGM tACCPGM tACCPGM_QUAD Preliminary MCP MEMORY 4A Max 6(typ.) 4(typ.) 1.2(typ.) 0.7(typ.) Min 60 0 35 30 0 0 0 10 0 0 40 25 4B Max 6(typ) 4(typ) 1.2(typ.) 0.7(typ) Min 65 0 35 30 0 0 0 10 0 0 40 25 4C Max 6(typ.) 4typ.) 1.2(typ.) 0.7typ.) Min 70 0 35 30 0 0 0 10 0 0 40 25 4D Max 6(typ.) 4(typ.) 1.2(typ.) 0.7(typ.) Unit 55 0 30 25 0 0 0 10 0 0 35 20 ns ns ns ns ns ns ns ns ns ns ns ns s s s sec tBERS Notes : 1. Not 100% tested. 2.This does not include the preprogramming time. ERASE AND PROGRAM PERFORMANCE Parameter Block Erase Time Chip Erase Time Word Programming Time Accelerated Word Program Time Accelerated Quad Word Program Time Chip Programming Time Erase/Program Endurance Limits Min 100,000 Typ 0.7 135 6 4 1.2 50.4 Max 2 216 100 60 200 Unit sec sec s s s sec cycles Excludes system-level overhead Excludes system-level overhead Excludes system-level overhead Excludes system-level overhead Minimum 100,000 cycles guaranteed Comments Excludes 00H programming prior to erasure Notes : 1. 25 C, VCC = 3.0V 100,000 cycles, typical pattern. 2. System-level overhead is defined as the time required to execute the four bus cycle command necessary to program each word. In the preprogramming step of the Internal Erase Routine, all words are programmed to 00H before erasure. 37 Revision 0.0 September 2006 www.DataSheet.in K5L2731CAM-D770 SWITCHING WAVEFORMS Conventional Read Operations tRC Preliminary MCP MEMORY Address tAA Address Stable CE tOE tDF OE tOEH WE tCE tOH Outputs HIGH-Z Output Valid HIGH-Z RY/BY HIGH Figure 10. Conventional Read Operation Timings Parameter Read Cycle Time Address Access Time Chip Enable Access Time Output Enable Time CE & OE Disable Time (1) Output Hold Time from Address, CE or OE OE Hold Time Note : 1. Not 100% tested. Symbol tRC tAA tCE tOE tDF tOH tOEH 4A Min 55 5 0 Max 55 55 20 16 10 Min 60 5 0 4B Max 60 60 25 16 10 Min 65 5 0 4C Max 65 65 30 16 10 Min 70 5 0 4D Max 70 70 30 16 10 Unit ns ns ns ns ns ns ns 38 Revision 0.0 September 2006 www.DataSheet.in K5L2731CAM-D770 SWITCHING WAVEFORMS Page Read Operations A3 to A22 Same page Addresses Preliminary MCP MEMORY A0 to A2 Aa tRC tAA tCE Ab tPRC Ac Ad CE OE tOEH tOE tDF WE tPA tOH High-Z tPA tOH tOH Output Da Db Dc Dd Figure 11. Page Read Operation Timings Parameter Read Cycle Time Page Read Cycle Time Address Access Time Page Address Access Time Chip Enable Access Time Output Enable Time CE & OE Disable Time (1) Output Hold Time from Address, CE or OE OE Hold Time Note : 1. Not 100% tested. Symbol tRC tPRC tAA tPA tCE tOE tDF tOH tOEH 4A Min 55 20 5 0 Max 55 20 55 20 16 Min 60 25 5 0 4B Max 60 25 60 25 16 Min 65 25 5 0 4C Max 65 25 65 30 16 Min 70 30 5 0 4D Max 70 30 70 30 16 - Unit ns ns ns ns ns ns ns ns ns 39 Revision 0.0 September 2006 www.DataSheet.in K5L2731CAM-D770 SWITCHING WAVEFORMS Hardware Reset/Read Operations Preliminary MCP MEMORY tRC Address tAA Address Stable CE tRH tRP tRH tCE RESET tOH Outputs High-Z Output Valid Figure 12. Hardware Reset/Read Operation Timings Parameter Read Cycle Time Address Access Time Chip Enable Access Time Output Hold Time from Address, CE or OE RESET Pulse Width RESET High Time Before Read Symbol tRC tAA tCE tOH tRP tRH 4A Min 55 5 500 50 Max 55 55 Min 60 5 500 50 4B Max 60 60 Min 65 5 500 50 4C Max 65 65 Min 70 5 500 50 4D Max 70 70 - Unit ns ns ns ns ns ns 40 Revision 0.0 September 2006 www.DataSheet.in K5L2731CAM-D770 SWITCHING WAVEFORMS Alternate WE Controlled Program Operations tAS Preliminary MCP MEMORY Data Polling PA tAH PA tRC Address 555H CE tOES OE tWC tCH tWP tPGM WE tWPH tCS tDH A0H tDS PD tBUSY Status DOUT tRB tCE tOH tOE tDF DATA RY/BY Notes : 1. DQ7 is the output of the complement of the data written to the device. 2. DOUT is the output of the data written to the device. 3. PA : Program Address, PD : Program Data 4. The illustration shows the last two cycles of the program command sequence. Figure 13. Alternate WE Controlled Program Operation Timings Parameter Write Cycle Time Address Setup Time Address Hold Time Data Setup Time Data Hold Time CE Setup Time CE Hold Time OE Setup Time Write Pulse Width Write Pulse Width High Programming Operation Accelerated Programming Operation Read Cycle Time Chip Enable Access Time Output Enable Time CE & OE Disable Time Output Hold Time from Address, CE or OE Program/Erase Valid to RY/BY Delay Recovery Time from RY/BY Symbol tWC tAS tAH tDS tDH tCS tCH tOES tWP tWPH tPGM tACCPGM tRC tCE tOE tDF tOH tBUSY tRB 55 5 35 0 4A Min 55 0 30 25 0 0 0 0 35 20 6(typ.) 4(typ.) 55 20 16 90 60 5 35 0 Max Min 60 0 35 30 0 0 0 0 35 25 6(typ) 4(typ) 60 25 16 90 65 5 35 0 4B Max Min 65 0 35 30 0 0 0 0 35 25 6(typ.) 4(typ.) 65 30 16 90 70 5 35 0 4C Max Min 70 0 35 30 0 0 0 0 35 25 6(typ.) 4(typ.) 70 30 16 90 4D Max Unit ns ns ns ns ns ns ns ns ns ns us s ns ns ns ns ns ns ns 41 Revision 0.0 September 2006 www.DataSheet.in K5L2731CAM-D770 SWITCHING WAVEFORMS Alternate CE Controlled Program Operations tAS Preliminary MCP MEMORY Data Polling PA tAH PA Address 555H WE tOES OE tWC tCP tPGM CE tWS tDH A0H tDS tCPH DATA PD Status DOUT tBUSY tRB RY/BY Figure 14. Alternate CE Controlled Program Operation Timings Notes : 1. DQ7 is the output of the complement of the data written to the device. 2. DOUT is the output of the data written to the device. 3. PA : Program Address, PD : Program Data 4. The illustration shows the last two cycles of the program command sequence. Parameter Write Cycle Time Address Setup Time Address Hold Time Data Setup Time Data Hold Time OE Setup Time WE Setup Time WE Hold Time CE Pulse Width CE Pulse Width High Programming Operation Accelerated Programming Operation Program/Erase Valid to RY/ BY Delay Recovery Time from RY/BY Symbol tWC tAS tAH tDS tDH tOES tWS tWH tCP tCPH tPGM tACCPGM tBUSY tRB 4A Min 55 0 30 25 0 0 0 0 35 20 6(typ.) 4(typ.) 35 0 90 35 0 Max Min 60 0 35 30 0 0 0 0 40 25 4B Max 6(typ) 4(typ) 90 35 0 Min 65 0 35 30 0 0 0 0 40 25 4C Max 6(typ.) 4(typ.) 90 35 0 Min 70 0 35 30 0 0 0 0 40 25 4D Max 6(typ.) 4(typ.) 90 - Unit ns ns ns ns ns ns ns ns ns ns s s ns ns 42 Revision 0.0 September 2006 www.DataSheet.in K5L2731CAM-D770 SWITCHING WAVEFORMS Chip/Block Erase Operations Preliminary MCP MEMORY tAS 555H for Chip Erase 2AAH tAH Address 555H 555H 555H 2AAH BA tRC CE tOES OE tWP tWC WE tCS tWPH tDH 10H for Chip Erase 55H 80H AAH 55H 30H DATA AAH tDS RY/BY Vcc tVCS Figure 15. Chip/Block Erase Operation Timings Note : BA : Block Address Parameter Write Cycle Time Address Setup Time Address Hold Time Data Setup Time Data Hold Time OE Setup Time CE Setup Time Write Pulse Width Write Pulse Width High Read Cycle Time VCC Set Up Time Symbol tWC tAS tAH tDS tDH tOES tCS tWP tWPH tRC tVCS 4A Min 55 0 30 25 0 0 0 35 20 55 50 Max Min 60 0 35 30 0 0 0 35 25 60 50 4B Max Min 65 0 35 30 0 0 0 35 25 65 50 4C Max Min 70 0 35 30 0 0 0 35 25 70 50 4D Max - Unit ns ns ns ns ns ns ns ns ns ns s 43 Revision 0.0 September 2006 www.DataSheet.in K5L2731CAM-D770 SWITCHING WAVEFORMS Read While Write Operations Read tRC Command tWC DA2 (555H) tAS tAH tAA tCE Read tRC DA1 Command tWC DA2 (PA) Read tRC DA1 tAS tAHT Preliminary MCP MEMORY Read tRC DA2 (PA) Address DA1 CE tOE tCEPH OE tOES tWP tDF tOEH WE tDH tDS tDF DQ Valid Output Valid Input (A0H) Valid Output Valid Input (PD) Valid Output Status Figure 16. Read While Write Operation Timings Note : This is an example in the program-case of the Read While Write function. DA1 : Address of Bank1, DA2 : Address of Bank 2 PA = Program Address at one bank , RA = Read Address at the other bank, PD = Program Data In , RD = Read Data Out Parameter Write Cycle Time Write Pulse Width Write Pulse Width High Address Setup Time Address Hold Time Data Setup Time Data Hold Time Read Cycle Time Chip Enable Access Time Address Access Time Output Enable Access Time OE Setup Time OE Hold Time CE & OE Disable Time Address Hold Time CE High during toggle bit polling Symbol tWC tWP tWPH tAS tAH tDS tDH tRC tCE tAA tOE tOES tOEH tDF tAHT tCEPH 4A Min 55 35 20 0 30 25 0 55 0 10 30 20 Max 55 55 20 16 10 35 20 Min 60 35 25 0 35 30 0 60 - 4B Max 60 60 25 Min 65 35 25 0 35 30 0 65 0 16 10 35 20 4C Max 65 65 30 16 Min 70 35 25 0 35 30 0 70 0 10 35 20 4D Max 70 70 30 16 - Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 44 Revision 0.0 September 2006 www.DataSheet.in K5L2731CAM-D770 SWITCHING WAVEFORMS Data Polling During Internal Routine Operation CE tOE tDF Preliminary MCP MEMORY OE tOEH WE tCE tOH DQ7 Data In tPGM or tBERS DQ7 *DQ7 = Valid Data HIGH-Z DQ0-DQ6 Data In Status Data Note : *DQ7=Vaild Data (The device has completed the internal operation). Valid Data HIGH-Z Figure 17. Data Polling During Internal Routine Operation Timings RY/BY Timing Diagram During Program/Erase Operation CE The rising edge of the last WE signal WE Entire progrming or erase operation RY/BY tBUSY Figure 18. RY/BY Timing Diagram During Program/Erase Operation Timings Parameter Program/Erase Valid to RY/BY Delay Chip Enable Access Time Output Enable Time CE & OE Disable Time Output Hold Time from Address, CE or OE OE Hold Time Symbol tBUSY tCE tOE tDF tOH tOEH 4A Min 35 5 10 Max 90 55 20 16 Min 35 5 10 4B Max 90 60 25 16 Min 35 5 10 4C Max 90 65 30 16 Min 35 5 10 4D Max 90 70 30 16 - Unit ns ns ns ns ns ns 45 Revision 0.0 September 2006 www.DataSheet.in K5L2731CAM-D770 SWITCHING WAVEFORMS Toggle Bit During Internal Routine Operation tAHT Address* tASO CE tOEH WE tOEPH OE tDH DQ6/DQ2 Data In Status Data tOE Preliminary MCP MEMORY tAS tAHT tCEPH Status Data Status Data Array Data Out RY/BY Note : Address for the write operation must include a bank address (A19~A22) where the data is written. Enter Embedded Erasing Erase Suspend Erase Erase Suspend Read Enter Erase Suspend Program Erase Suspend Program Erase Suspend Read Erase Resume Erase Erase Complete WE DQ6 DQ2 Toggle DQ2 and DQ6 with OE or CE Note : DQ2 is read from the erase-suspended block. Figure 19. Toggle Bit During Internal Routine Operation Timings 4A Min 10 30 55 0 0 20 10 Max 20 Min 10 35 55 0 0 20 10 4B Max 25 Min 10 35 55 0 0 20 10 4C Max 30 Min 10 35 55 0 0 20 10 4D Max 30 - Parameter Output Enable Access Time OE Hold Time Address Hold Time Address Setup Address Setup Time Data Hold Time CE High during toggle bit polling OE High during toggle bit polling Symbol tOE tOEH tAHT tASO tAS tDH tCEPH tOEPH Unit ns ns ns ns ns ns ns ns 46 Revision 0.0 September 2006 www.DataSheet.in K5L2731CAM-D770 SWITCHING WAVEFORMS RESET Timing Diagram RY/BY High Preliminary MCP MEMORY CE or OE tRH RESET tRP tREADY Reset Timings NOT during Internal Routine tREADY RY/BY tRB CE or OE tRP RESET Reset Timings during Internal Routine Power-up and RESET Timing Diagram tRSTS RESET Vcc Address DATA tAA Figure 20. Power-up and RESET Timing Diagram Parameter RESET Pulse Width RESET Low to Valid Data (During Internal Routine) RESET Low to Valid Data (Not during Internal Routine) RESET High Time Before Read RY/BY Recovery Time RESET High to Address Valid RESET Low Set-up Time Symbol tRP tREADY tREADY tRH tRB tRSTW tRSTS 4A Min 500 50 0 200 500 Max 20 500 Min 500 50 0 200 500 4B Max 20 500 Min 500 50 0 200 500 4C Max 20 500 Min 500 50 0 200 500 4D Max 20 500 Unit ns s ns ns ns ns ns 47 Revision 0.0 September 2006 www.DataSheet.in K5L2731CAM-D770 SWITCHING WAVEFORMS Block Group Protect & Unprotect Operations VID Preliminary MCP MEMORY RESET Vss,VIL, or VIH Vss,VIL, or VIH BGA,A6 A1,A0 Valid Block Group Protect / Unprotect Valid Verify 40H Block Group Protect:100s Block Group UnProtect:1.2ms Valid DATA 60H 60H Status* 1s CE WE tRB OE tBUSY RY/BY Notes : Block Group Protect (A6=VIL , A1=VIH , A0=VIL) , Status=01H Block Group Unprotect (A6=VIH , A1=VIH, A0=VIL) , Status=00H BGA = Block Group Address (A12 ~ A22) Temporary Block Group Unprotect VID RESET Vss,VIL, or VIH Vss,VIL, or VIH CE WE Program or Erase Command Sequence tVID tRSP tRRB tVID RY/BY 48 Revision 0.0 September 2006 www.DataSheet.in K5L2731CAM-D770 SWITCHING WAVEFORMS Unlock Bypass Program Operations(Accelerated Program) Preliminary MCP MEMORY CE WE Address PA DQ0-DQ15 Don't Care A0h Don't Care PD Don't Care OE 1us VID tVPS VPP VIL or VIH tVPP Unlock Bypass Block Erase Operations CE WE Address BA 555h for chip erase 10h for chip erase 30h Don't Care DQ0-DQ15 Don't Care 80h Don't Care OE 1us VID tVPS VPP VIL or VIH Notes: tVPP 1. VPP can be left high for subsequent programming pulses. 2. Use setup and hold times from conventional program operations. 3. Unlock Bypass Program/Erase commands can be used when the VID is applied to Vpp. Figure 21. Unlock Bypass Operation Timings 49 Revision 0.0 September 2006 www.DataSheet.in K5L2731CAM-D770 SWITCHING WAVEFORMS Quad word Accelerated Program CE Preliminary MCP MEMORY WE Address Don't Care PA1 PA2 PA3 PA4 VA DQ15-DQ0 Don't Care A5H PD1 PD2 PD3 PD4 VA Complete OE 1us VID tVPS tACCPGM_QUAD VPP VIL or VIH tVPP Notes: 1. VPP can be left high for subsequent programming pulses. 2. Use setup and hold times from conventional program operations. 3. Quad word Acelerate program commands can be used when the VID is applied to Vpp. Figure 22. Quad word Accelerated Program Operation Timings 50 Revision 0.0 September 2006 www.DataSheet.in K5L2731CAM-D770 Table 13. Block Architecture Bank Block BA269 BA268 BA267 BA266 BA265 BA264 BA263 BA262 BA261 BA260 BA259 BA258 BA257 BA256 BA255 BA254 BA253 BA252 BA251 BA250 BA249 Bank 3 BA248 BA247 BA246 BA245 BA244 BA243 BA242 BA241 BA240 BA239 BA238 BA237 BA236 BA235 BA234 BA233 BA232 BA231 BA230 BA229 BA228 BA227 BA226 Block Size 4 Kwords 4 Kwords 4 Kwords 4 Kwords 4 Kwords 4 Kwords 4 Kwords 4 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords Preliminary MCP MEMORY (x16) Address Range 7FF000h-7FFFFFh 7FE000h-7FEFFFh 7FD000h-7FDFFFh 7FC000h-7FCFFFh 7FB000h-7FBFFFh 7FA000h-7FAFFFh 7F9000h-7F9FFFh 7F8000h-7F8FFFh 7F0000h-7F7FFFh 7E8000h-7EFFFFh 7E0000h-7E7FFFh 7D8000h-7DFFFFh 7D0000h-7D7FFFh 7C8000h-7CFFFFh 7C0000h-7C7FFFh 7B8000h-7BFFFFh 7B0000h-7B7FFFh 7A8000h-7AFFFFh 7A0000h-7A7FFFh 798000h-79FFFFh 790000h-797FFFh 788000h-78FFFFh 780000h-787FFFh 778000h-77FFFFh 770000h-777FFFh 768000h-76FFFFh 760000h-767FFFh 758000h-75FFFFh 750000h-757FFFh 748000h-74FFFFh 740000h-747FFFh 738000h-73FFFFh 730000h-737FFFh 728000h-72FFFFh 720000h-727FFFh 718000h-71FFFFh 710000h-717FFFh 708000h-70FFFFh 700000h-707FFFh 6F8000h-6FFFFFh 6F0000h-6F7FFFh 6E8000h-6EFFFFh 6E0000h-6E7FFFh 6D8000h-6DFFFFh 51 Revision 0.0 September 2006 www.DataSheet.in K5L2731CAM-D770 Table 13. Block Architecture Bank Block BA225 BA224 BA223 BA222 BA221 BA220 BA219 BA218 BA217 BA216 BA215 BA214 BA213 BA212 BA211 BA210 BA209 BA208 BA207 BA206 BA205 Bank 2 BA204 BA203 BA202 BA201 BA200 BA199 BA198 BA197 BA196 BA195 BA194 BA193 BA192 BA191 BA190 BA189 BA188 BA187 BA186 BA185 BA184 BA183 BA182 Block Size 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords Preliminary MCP MEMORY (x16) Address Range 6D0000h-6D7FFFh 6C8000h-6CFFFFh 6C0000h-6C7FFFh 6B8000h-6BFFFFh 6B0000h-6B7FFFh 6A8000h-6AFFFFh 6A0000h-6A7FFFh 698000h-69FFFFh 690000h-697FFFh 688000h-68FFFFh 680000h-687FFFh 678000h-67FFFFh 670000h-677FFFh 668000h-66FFFFh 660000h-667FFFh 658000h-65FFFFh 650000h-657FFFh 648000h-64FFFFh 640000h-647FFFh 638000h-63FFFFh 630000h-637FFFh 628000h-62FFFFh 620000h-627FFFh 618000h-61FFFFh 610000h-617FFFh 608000h-60FFFFh 600000h-607FFFh 5F8000h-5FFFFFh 5F0000h-5F7FFFh 5E8000h-5EFFFFh 5E0000h-5E7FFFh 5D8000h-5DFFFFh 5D0000h-5D7FFFh 5C8000h-5CFFFFh 5C0000h-5C7FFFh 5B8000h-5BFFFFh 5B0000h-5B7FFFh 5A8000h-5AFFFFh 5A0000h-5A7FFFh 598000h-59FFFFh 590000h-597FFFh 588000h-58FFFFh 580000h-587FFFh 578000h-57FFFFh 52 Revision 0.0 September 2006 www.DataSheet.in K5L2731CAM-D770 Table 13. Block Architecture Bank Block BA181 BA180 BA179 BA178 BA177 BA176 BA175 BA174 BA173 BA172 BA171 BA170 BA169 BA168 BA167 BA166 BA165 BA164 BA163 BA162 BA161 BA160 Bank 2 BA159 BA158 BA157 BA156 BA155 BA154 BA153 BA152 BA151 BA150 BA149 BA148 BA147 BA146 BA145 BA144 BA143 BA142 BA141 BA140 BA139 BA138 BA137 Block Size 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords Preliminary MCP MEMORY (x16) Address Range 570000h-577FFFh 568000h-56FFFFh 560000h-567FFFh 558000h-55FFFFh 550000h-557FFFh 548000h-54FFFFh 540000h-547FFFh 538000h-53FFFFh 530000h-537FFFh 528000h-52FFFFh 520000h-527FFFh 518000h-51FFFFh 510000h-517FFFh 508000h-50FFFFh 500000h-507FFFh 4F8000h-4FFFFFh 4F0000h-4F7FFFh 4E8000h-4EFFFFh 4E0000h-4E7FFFh 4D8000h-4DFFFFh 4D0000h-4D7FFFh 4C8000h-4CFFFFh 4C0000h-4C7FFFh 4B8000h-4BFFFFh 4B0000h-4B7FFFh 4A8000h-4AFFFFh 4A0000h-4A7FFFh 498000h-49FFFFh 490000h-497FFFh 488000h-48FFFFh 480000h-487FFFh 478000h-47FFFFh 470000h-477FFFh 468000h-46FFFFh 460000h-467FFFh 458000h-45FFFFh 450000h-457FFFh 448000h-44FFFFh 440000h-447FFFh 438000h-43FFFFh 430000h-437FFFh 428000h-42FFFFh 420000h-427FFFh 418000h-41FFFFh 410000h-417FFFh 53 Revision 0.0 September 2006 www.DataSheet.in K5L2731CAM-D770 Table 13. Block Architecture Bank Bank 2 BA135 BA134 BA133 BA132 BA131 BA130 BA129 BA128 BA127 BA126 BA125 BA124 BA123 BA122 BA121 BA120 BA119 BA118 BA117 BA116 BA115 BA114 Bank 1 BA113 BA112 BA111 BA110 BA109 BA108 BA107 BA106 BA105 BA104 BA103 BA102 BA101 BA100 BA99 BA98 BA97 BA96 BA95 BA94 BA93 BA92 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords Block BA136 Block Size 32 Kwords Preliminary MCP MEMORY (x16) Address Range 408000h-40FFFFh 400000h-407FFFh 3F8000h-3FFFFFh 3F0000h-3F7FFFh 3E8000h-3EFFFFh 3E0000h-3E7FFFh 3D8000h-3DFFFFh 3D0000h-3D7FFFh 3C8000h-3CFFFFh 3C0000h-3C7FFFh 3B8000h-3BFFFFh 3B0000h-3B7FFFh 3A8000h-3AFFFFh 3A0000h-3A7FFFh 398000h-39FFFFh 390000h-397FFFh 388000h-38FFFFh 380000h-387FFFh 378000h-37FFFFh 370000h-377FFFh 368000h-36FFFFh 360000h-367FFFh 358000h-35FFFFh 350000h-357FFFh 348000h-34FFFFh 340000h-347FFFh 338000h-33FFFFh 330000h-337FFFh 328000h-32FFFFh 320000h-327FFFh 318000h-31FFFFh 310000h-317FFFh 308000h-30FFFFh 300000h-307FFFh 2F8000h-2FFFFFh 2F0000h-2F7FFFh 2E8000h-2EFFFFh 2E0000h-2E7FFFh 2D8000h-2DFFFFh 2D0000h-2D7FFFh 2C8000h-2CFFFFh 2C0000h-2C7FFFh 2B8000h-2BFFFFh 2B0000h-2B7FFFh 2A8000h-2AFFFFh 54 Revision 0.0 September 2006 www.DataSheet.in K5L2731CAM-D770 Table 13. Block Architecture Bank Block BA91 BA90 BA89 BA88 BA87 BA86 BA85 BA84 BA83 BA82 BA81 BA80 BA79 BA78 BA77 BA76 BA75 BA74 BA73 BA72 BA71 BA70 Bank 1 BA69 BA68 BA67 BA66 BA65 BA64 BA63 BA62 BA61 BA60 BA59 BA58 BA57 BA56 BA55 BA54 BA53 BA52 BA51 BA50 BA49 BA48 BA47 Block Size 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords Preliminary MCP MEMORY (x16) Address Range 2A0000h-2A7FFFh 298000h-29FFFFh 290000h-297FFFh 288000h-28FFFFh 280000h-287FFFh 278000h-27FFFFh 270000h-277FFFh 268000h-26FFFFh 260000h-267FFFh 258000h-25FFFFh 250000h-257FFFh 248000h-24FFFFh 240000h-247FFFh 238000h-23FFFFh 230000h-237FFFh 228000h-22FFFFh 220000h-227FFFh 218000h-21FFFFh 210000h-217FFFh 208000h-20FFFFh 200000h-207FFFh 1F8000h-1FFFFFh 1F0000h-1F7FFFh 1E8000h-1EFFFFh 1E0000h-1E7FFFh 1D8000h-1DFFFFh 1D0000h-1D7FFFh 1C8000h-1CFFFFh 1C0000h-1C7FFFh 1B8000h-1BFFFFh 1B0000h-1B7FFFh 1A8000h-1AFFFFh 1A0000h-1A7FFFh 198000h-19FFFFh 190000h-197FFFh 188000h-18FFFFh 180000h-187FFFh 178000h-17FFFFh 170000h-177FFFh 168000h-16FFFFh 160000h-167FFFh 158000h-15FFFFh 150000h-157FFFh 148000h-14FFFFh 140000h-147FFFh 55 Revision 0.0 September 2006 www.DataSheet.in K5L2731CAM-D770 Table 13. Block Architecture Bank Block BA46 BA45 BA44 BA43 Bank 1 BA42 BA41 BA40 BA39 BA38 BA37 BA36 BA35 BA34 BA33 BA32 BA31 BA30 BA29 BA28 BA27 BA26 BA25 BA24 BA23 BA22 BA21 BA20 Bank 0 BA19 BA18 BA17 BA16 BA15 BA14 BA13 BA12 BA11 BA10 BA9 BA8 BA7 BA6 BA5 BA4 BA3 BA2 BA1 BA0 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 4 Kwords 4 Kwords 4 Kwords 4 Kwords 4 Kwords 4 Kwords 4 Kwords 4 Kwords Block Size 32 Kwords 32 Kwords 32 Kwords 32 Kwords Preliminary MCP MEMORY (x16) Address Range 138000h-13FFFFh 130000h-137FFFh 128000h-12FFFFh 120000h-127FFFh 118000h-11FFFFh 110000h-117FFFh 108000h-10FFFFh 100000h-107FFFh 0F8000h-0FFFFFh 0F0000h-0F7FFFh 0E8000h-0EFFFFh 0E0000h-0E7FFFh 0D8000h-0DFFFFh 0D0000h-0D7FFFh 0C8000h-0CFFFFh 0C0000h-0C7FFFh 0B8000h-0BFFFFh 0B0000h-0B7FFFh 0A8000h-0AFFFFh 0A0000h-0A7FFFh 098000h-09FFFFh 090000h-097FFFh 088000h-08FFFFh 080000h-087FFFh 078000h-07FFFFh 070000h-077FFFh 068000h-06FFFFh 060000h-067FFFh 058000h-05FFFFh 050000h-057FFFh 048000h-04FFFFh 040000h-047FFFh 038000h-03FFFFh 030000h-037FFFh 028000h-02FFFFh 020000h-027FFFh 018000h-01FFFFh 010000h-017FFFh 008000h-00FFFFh 007000h-007FFFh 006000h-006FFFh 005000h-005FFFh 004000h-004FFFh 003000h-003FFFh 002000h-002FFFh 001000h-001FFFh 000000h-000FFFh 56 Revision 0.0 September 2006 www.DataSheet.in K5L2731CAM-D770 Preliminary MCP MEMORY 32Mb(2M x16) C-die Page Mode UtRAM 57 Revision 0.0 September 2006 www.DataSheet.in K5L2731CAM-D770 POWER UP SEQUENCE 1. Apply power. 2. Maintain stable power(Vcc min.=2.7V) for a minimum 200s with CS1=high.or CS2=low. Preliminary MCP MEMORY TIMING WAVEFORM OF POWER UP(1) (CS1 controlled) VCC(Min) VCC Min. 200s CS1 CS2 Power Up Mode POWER UP(1) Normal Operation 1. After VCC reaches VCC(Min.), wait 200s with CS1 high. Then the device gets into the normal operation. TIMING WAVEFORM OF POWER UP(2) (CS2 controlled) VCC(Min) VCC Min. 200s CS1 CS2 Power Up Mode Normal Operation POWER UP(2) 1. After VCC reaches VCC(Min.), wait 200s with CS2 low. Then the device gets into the normal operation. 58 Revision 0.0 September 2006 www.DataSheet.in K5L2731CAM-D770 FUNCTIONAL DESCRIPTION CS1 H X1) X 1) Preliminary MCP MEMORY CS2 X 1) OE X 1) WE X 1) LB X 1) UB X 1) I/O1~8 High-Z High-Z High-Z High-Z High-Z Dout High-Z Dout Din High-Z Din I/O9~16 High-Z High-Z High-Z High-Z High-Z High-Z Dout Dout High-Z Din Din Mode Deselected Deselected Deselected Output Disabled Output Disabled Lower Byte Read Upper Byte Read Word Read Lower Byte Write Upper Byte Write Word Write Power Standby Standby Standby Active Active Active Active Active Active Active Active L X 1) X1) X 1) X1) X 1) X1) H L X 1) X1) H X1) L H L L H L L L L L L L L L L H H H H H H H H H H L L L X1) X 1) H H H H H L L L L H L L H L X1) 1. X means dont care. (Must be low or high state) ABSOLUTE MAXIMUM RATINGS1) Item Voltage on any pin relative to Vss Voltage on Vcc supply relative to Vss Power Dissipation Storage temperature Operating Temperature Symbol VIN, VOUT VCC PD TSTG TA Ratings -0.2 to VCC+0.3V -0.2 to 3.6V 1.0 -65 to 150 -25 to 85 Unit V V W C C 1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation should be restricted to be used under recommended operating condition. Exposure to absolute maximum rating conditions longer than 1 second may affect reliability. 59 Revision 0.0 September 2006 www.DataSheet.in K5L2731CAM-D770 RECOMMENDED DC OPERATING CONDITIONS1) Item Supply voltage Ground Input high voltage Input low voltage 1. TA=-25 to 85C, otherwise specified. 2. Overshoot: Vcc+1.0V in case of pulse width 20ns. 3. Undershoot: -1.0V in case of pulse width 20ns. 4. Overshoot and undershoot are sampled, not 100% tested. Preliminary MCP MEMORY Symbol Vcc Vss VIH VIL Min 2.7 0 2.2 -0.23) Typ 2.9 0 - Max 3.1 0 Vcc+0.3 0.6 2) Unit V V V V CAPACITANCE1)(f=1MHz, TA=25C) Item Input capacitance Input/Output capacitance 1. Capacitance is sampled, not 100% tested. Symbol CIN CIO Test Condition VIN=0V VIO=0V Min - Max 8 10 Unit pF pF DC AND OPERATING CHARACTERISTICS Item Input leakage current Output leakage current Symbol Test Conditions VIN=Vss to Vcc CS1=VIH or CS2=VIL or OE=VIH or WE=VIL or LB=UB=VIH, VIO=Vss to Vcc Cycle time=1s, 100% duty, IIO=0mA, CS10.2V, LB0.2V or/and UB0.2V, CS2Vcc-0.2V, VIN0.2V or VINVCC0.2V Cycle time=Min, IIO=0mA, 100% duty, CS1=VIL, CS2=VIH, LB=VIL or/and UB=VIL,VIN=VIL or VIH IOL=2.1mA IOH=-1.0mA Other inputs = 0~Vcc 1) CS1Vcc-0.2V, CS2Vcc-0.2V (CS1 controlled) or 2) 0VCS20.2V(CS2 controlled) Min -1 -1 Typ1) - Max 1 1 Unit A A ILI ILO ICC1 Average operating current ICC2 Output low voltage Output high voltage Standby Current(CMOS) VOL VOH ISB12) - - 7 mA 2.4 - 35 0.4 100 mA V V A 1. Typical values are tested at VCC=2.9V, TA=25C and not guaranteed. 2. ISB1 is measured after 60ms from the time when standby mode is set up. 60 Revision 0.0 September 2006 www.DataSheet.in K5L2731CAM-D770 AC OPERATING CONDITIONS TEST CONDITIONS(Test Load and Test Input/Output Reference) Input pulse level: 0.4 to 2.2V Input rising and falling time: 5ns Input and output reference voltage: 1.5V Output load: CL=50pF CL Dout Preliminary MCP MEMORY 1. Including scope and jig capacitance AC CHARACTERISTICS(Vcc=2.7~3.1V, TA=-25 to 85C) Speed Bin Parameter List Symbol Min Read Cycle Time Address Access Time Chip Select to Output Output Enable to Valid Output UB, LB Access Time Chip Select to Low-Z Output Read UB, LB Enable to Low-Z Output Output Enable to Low-Z Output Chip Disable to High-Z Output UB, LB Disable to High-Z Output Output Disable to High-Z Output Output Hold from Address Change Page Cycle Page Access Time Write Cycle Time Chip Select to End of Write Address Set-up Time Address Valid to End of Write UB, LB Valid to End of Write Write Write Pulse Width Write Recovery Time Write to Output High-Z Data to Write Time Overlap Data Hold from Write Time End Write to Output Low-Z 1. tWC(min)=90ns or tWP(min)=70ns for continuous write operation over 50 times. 70ns1) Max 70 70 35 70 25 25 25 20 25 - Units tRC tAA tCO tOE tBA tLZ tBLZ tOLZ tHZ tBHZ tOHZ tOH tPC tPA tWC tCW tAS tAW tBW tWP tWR tWHZ tDW tDH tOW 70 10 10 5 0 0 0 3 25 70 60 0 60 60 551) 0 0 30 0 5 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 61 Revision 0.0 September 2006 www.DataSheet.in K5L2731CAM-D770 TIMING DIAGRAMS TIMING WAVEFORM OF READ CYCLE(1)(Address Controlled, CS=OE=VIL, WE=VIH, UB or/and LB=VIL) tRC Address tOH Data Out Previous Data Valid tAA Data Valid Preliminary MCP MEMORY TIMING WAVEFORM OF READ CYCLE(2)(WE=VIH) tRC Address tAA CS1 tCO tOH CS2 tHZ tBA UB, LB tBHZ tOE OE tOLZ tBLZ tLZ Data Valid tOHZ Data out High-Z TIMING WAVEFORM OF PAGE CYCLE(READ ONLY) A20~A2 Valid Address A1~A0 Valid Address Valid Address Valid Address Valid Address tAA CS1 tPC CS2 tCO OE tOE DQ15~DQ0 (READ CYCLE) 1. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. 2. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device interconnection. 3. tOE(max) is met only when OE becomes enabled after tAA(max). 4. If invalid address signals shorter than min. tRC are continuously repeated for over 4us, the device needs a normal read timing(tRC) or needs to sustain standby state for min. tRC at least once in every 4us. tPA Data Valid Data Valid Data Valid Data Valid tOHZ High Z 62 Revision 0.0 September 2006 www.DataSheet.in K5L2731CAM-D770 TIMING WAVEFORM OF WRITE CYCLE(1) (WE Controlled) tWC Address tCW CS1 tWR Preliminary MCP MEMORY CS2 tAW tBW tWP WE tAS Data in High-Z tWHZ Data out Data Undefined tDW Data Valid tOW tDH High-Z UB, LB TIMING WAVEFORM OF WRITE CYCLE(2) (CS1 Controlled) tWC Address tAS CS1 tAW CS2 tBW UB, LB tWP WE tDW Data in Data Valid tDH tCW tWR Data out High-Z 63 Revision 0.0 September 2006 www.DataSheet.in K5L2731CAM-D770 TIMING WAVEFORM OF WRITE CYCLE(3) (CS2 Controlled) tWC Address tAS CS1 tAW CS2 tBW UB, LB tWP(1) WE tDW Data in Data Valid tDH tCW tWR Preliminary MCP MEMORY Data out High-Z TIMING WAVEFORM OF WRITE CYCLE(4) (UB, LB Controlled) tWC Address tCW CS1 tAW CS2 UB, LB tAS WE tDW Data in Data Valid tDH tBW tWP tWR Data out NOTES (WRITE CYCLE) High-Z 1. A write occurs during the overlap(tWP) of low CS1 and low WE. A write begins when CS1 goes low and WE goes low with asserting UB or LB for single byte operation or simultaneously asserting UB and LB for double byte operation. A write ends at the earliest transition when CS1 goes high and WE goes high. The tWP is measured from the beginning of write to the end of write. 2. tCW is measured from the CS1 going low to the end of write. 3. tAS is measured from the address valid to the beginning of write. 4. tWR is measured from the end of write to the address change. tWR is applied in case a write ends with CS1 or WE going high. 64 Revision 0.0 September 2006 www.DataSheet.in K5L2731CAM-D770 PACKAGE DIMENSION 64-Ball Fine pitch Ball Grid Array Package (measured in millimeters) Preliminary MCP MEMORY 0.08MAX 8.000.10 0.80 x 9 = 7.20 3.60 0.80 10 9 8 7 6 0.40 5 4 3 2 1 A #A1 INDEX MARK 8.000.10 B A #A1 B (Datum B) 4.40 0.80x11=8.80 0.40 C D 11.600.10 E F G H J K L M 0.80 0.230.05 1.100.10 (Datum A) 64- 0.400.05 0.20 M A B Top View Bottom View 65 Revision 0.0 September 2006 www.DataSheet.in 11.600.10 |
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