Following are the details: : Start signal SCL SDA High High High Low The Start signal is HIGH to LOW transition on the SDA line when SCL is HIGH. : Write Slave Address: 0h : Read Slave Address: 1h : Value of the AL440B register index. : Acknowledge stage The acknowledge-related clock pulse is generated by the host (master). The host releases the SDA line (HIGH) for the AL440B (slave) to pull down the SDA line during the acknowledge clock pulse. : Not Acknowledged stage The acknowledge-related clock pulse is generated by the host (master). The host releases the SDA line (HIGH) during the acknowledge clock pulse, but the AL440B does not pull it down during this stage. : Data bytes write to or read from the register index. In read operation, the host must release the SDA line (high) before the first clock pulse is transmitted to the AL440B. : Stop signal SCL SDA High Low High High The Stop signal is LOW to HIGH transition on the SDA line when SCL is HIGH.
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Suppose data F0h is to be written to register 0Fh using write slave address 0h, the timing is as follows:
Start Slave addr = 0h Ack Index = 0Fh Ack Data = F0h Ack Stop
SDA SCL
AL440B Serial bus Write timing
Suppose data is to be read from register 05h using read slave address 1h, the timing is as follows:
Start Ack Stop Read slave addr = 1h NAck Start Ack Data read cycle Stop
Slave addr = 0h
Index = 05h
Ack
SDA SCL
AL440B Serial bus read timing
11.0 Memory Operation
11.1 Power-On-Reset & Initialization
During the system power on, a 200s negative pulse on the /RESET pin is required and will automatically initialize chip logic and reset window mode registers to default value "0". Apply a valid reset pulse to WRST and RRST after power-on-reset to reset read/write address pointer to zero.
11.2 WRST, RRST Reset Operation
The reset signal can be given at any time regardless of the WE, RE and OE status, however, they still need to meet the setup time and hold time requirements with reference to the clock input. When the reset signal is provided during disabled cycles, the reset operation will not be executed until cycles are enabled again.
11.3 Control Signals Polarity Select
The AL440B provides the option for operating polarity on controlling signals. With this feature, the application design can benefit by matching up the operation polarity between AL440B and existing interfacing devices without additional glue logic. The operating polarity of control signals WE, RE, WRST, RRST, IE, OE, IRDY and ORDY are controlled by /PLRTY signal. When /PLRTY is pulled
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AL440B
high all eight signals will be active low. When /PLRTY is pulled low all eight signals will be active high.
11.4 FIFO Write Operation
In the FIFO write operation, 8 bits of write data are input in synchronization with the WCK clock. The FIFO write operation is determined by WRST, WE, IE and WCK signals and the combination of these signals could produce different write result. The /PLRTY signal determines the activated polarity of these control signals. The following tables describe the WRITE functions under different operating polarities.
/PLRTY = VDD
WRST L H H WE L L IE L H WCK Function Write reset. The write pointer is reset to zero. Normal Write operation. Write address pointer increases, but no new data will be written to memory. Old data is retained in memory. (Write mask function) Write operation stopped. Write address pointer is also stopped.
H
H
-
/PLRTY = GND
WRST H L L WE H H IE H L WCK Function Write reset. The write pointer is reset to zero. Normal Write operation. Write address pointer increases, but no new data will be written to memory. Old data is retained in memory. (Write mask function) Write operation stopped. Write address pointer is also stopped.
L
L
-
11.5 FIFO Read Operation
In the FIFO read operation, 8 bits of read data are available in synchronization with the RCK clock. The access time is stipulated from the rising edge of the RCK clock. The FIFO read operation is determined by RRST, RE, OE and RCK signals, consequently the combination of these signals could produce varying read results. The /PLRTY signal could decide the activated polarity of these control signals. The following tables describe the READ functions under different operating polarities.
/PLRTY = VDD
RRST L L RE L L OE L H RCK Function Read reset. The read pointer is reset to zero. Data in the address 0 is output. Read reset. The read pointer is reset to zero. Output is high impedance.
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AL440B
L
H
L
L
H
H
H H H H
L L H H
L H L H
Read address pointer is stopped. Output data is held. Read address pointer will be reset to zero and data in the address 0 is output after RE goes low. Read address pointer is stopped. Output data is held. Read address pointer will be reset to zero and output is high impedance after RE goes low. Normal Read operation. Read address pointer increases. Output is high impedance. (Data skipping function) Read address pointer is stopped. Output data is held. Read operation stopped. Read address pointer is stopped. Output is high impedance.
/PLRTY = GND
RRST H H H RE H H L OE H L H RCK Function Read reset. The read pointer is reset to zero. Data in the address 0 is output. Read reset. The read pointer is reset to zero. Output is high impedance. Read address pointer is stopped. Output data is held. Read address pointer will be reset to zero and data in the address 0 is output after RE goes low. Read address pointer is stopped. Output data is held. Read address pointer will be reset to zero and output is high impedance after RE goes low. Normal Read operation. Read address pointer increases. Output is high impedance. (Data skipping function) Read address pointer is stopped. Output data is held. Read operation stopped. Read address pointer is stopped. Output is high impedance.
H
L
L
L L L L
H H L L
H L H L
When the new data is read, the read address should be between 192 and 524,287 cycles after the write address pointer, otherwise the output for new data is not guarantee.
11.6 IRDY, ORDY Flags
The IRDY, ORDY flags indicate the status of FIFO. The IRDY signal reports whether or not there is space available for writing new data to the FIFO. An ORDY signal reports whether or not there is valid new data available at output. The IRDY and ORDY signals only report the status of the address pointer; they will not stop or affect the read/write operations. The following tables describe the IRDY/ORDY functions under different operating polarities.
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/PLRTY = VDD
Signal IRDY ORDY State H L H L Function No more free space is available for new input data Memory space is available for new input data. No new data is available in FIFO memory. New data are available in the FIFO memory.
/PLRTY = GND
Signal IRDY ORDY State H L H L Function Memory space is available for new input data. No more free space is available for new input data New data are available in the FIFO memory. No new data is available in FIFO memory.
11.7 Window Write Register Programming
Window data read/write is supported in the AL440B to benefit the designing effort for applications such as PIP display. The window mode register setup is enabled by driving low on /SDAEN signal. A serial bus can program window registers to set up coordinates of the window and the settings take effect following by the next read/write reset pulse. Window mirroring can cooperate with the window mode data access to flip window data in x or y direction. When window-mirroring function is turned on, write data can be stored in reverse sequence. The serial communication interface consists of three signals, they are SCL (serial clock), SDA (serial data) and /SDAEN (window mode enable). The serial communication interface is enabled by driving low on /SDAEN signal. The detail operation timing of the serial bus is illustrated in chapter 10. In Window read/write mode, read and/or write may begin at the starting address of any of the 8192 blocks. Each block is 64 bytes in length. (8192 blocks x 64 byte = 512 Kbytes)
8189 8190 8191 64 bytes each block Memory size: 8192 blocks x 64 bytes = 512 kbytes
AL440B Window mode block address
Block number:
All registers will be reset to default value 0 after global reset (/RESET) is applied. The Window Write related registers are listed as follows:
0 1 2
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WSTART_L and WSTART_H define the window data write starting address. Addr Name Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 02h WSTART_L [7] [6] [5] [4] [3] [2] [1] 03h WSTART_H 0 0 0 [12] [11] [10] [9] WSTART (Write Start address) <= WSTART_H[4:0] & WSTART_L ; WSTART range is from 0 to 8191 (block). WXSIZE_L and WXSIZE_H define the window data write horizontal size. Addr Name Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 04h WXSIZE_L [7] [6] [5] [4] [3] [2] 05h WXSIZE_H 0 0 0 0 0 0 WXSIZE (Write X Size) <= WXSIZE_H[2:0] & WXSIZE_L ; WXSIZE range is from 0 to 1023 (block).
Bit0 [0] [8]
Bit1 [1] [9]
Bit0 [0] [8]
WSTRIDE_L and WSTRIDE_H define the window data write horizontal width. Addr Name Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 06h WSTRIDE_L [7] [6] [5] [4] [3] [2] [1] [0] 07h WSTRIDE_H [15] [14] [13] [12] [11] [10] [9] [8] WSTRIDE (Write Stride) <= WSTRIDE_H[4:0] & WSTRIDE _L ; And WSTRIDE ( Write Stride) should greater or equal to WXSIZE (Write X Size) WSTRIDE range is from -4096 to +4095 (block). Bit [15] = Bit [14] = Bit [13] = Bit [12] under all conditions. When the value of WSTRIDE is negative, it is used to implement Y-Mirror function. WYSIZE_L and WYSIZE_H registers are reserved and must be 0. Addr Name Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 08h WYSIZE_L 0 0 0 0 0 0 0 0 09h WYSIZE_H 0 0 0 0 0 0 0 0 WYSIZE (Write Y Size) <= WYSIZE_H & WYSIZE_L; * WYSIZE (Write window Y Size) value is reserved and always 0. The write window vertical height is determined by the amount of data write into the window divided by WXSIZE. And write reset will reset the write pointer back to WSTART position. See diagrams for details. WWCTRL is the register that control window data write function enable/disable and the window mirroring write. Addr Name Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 0Ah WWCTRL [7] [6] [5] 0 0 0 0 0 WWCTRL[7] Window Write mode enable 1: enable Window Write mode 0: disable Window Write mode. The memory is operating in standard FIFO write mode. WWCTRL[6] X-mirror function enable
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1: 0:
enable X-mirror function disable X-mirror function
WWCTRL[5] Freeze function enable. This function is as same as hardware "Write Mask" function. When Window Write mode is enabled, software freeze function override hardware Write Mask function. On the other hand, in FIFO mode (WWCTRL[7] = `0'), Register WWCTRL[5] is ignored. 1: enable software Freeze function 0: disable software Freeze function A mirroring read/write function can be cooperated with the window-block data access function. By turning on the mirroring read/write function in the window block access mode, write data can be stored in reversed sequence. For some applications like video conferencing, this function can correct reciprocal positioning of a captured object. Please refer the following diagrams which illustrate Window Write operation.
Memory Area WSTRIDE WSTART WSTART+1xWSTRIDE WSTART+2xWSTRIDE WXSIZE WSTART+(WXSIZE-1)
Go ba c
kt
oW
ST
AR
T
Write Window Area WSTART+(Write_Window_Y) x WSTRIDE
AL440B Write Window(1)
For Write Window without mirroring: WSTRIDE = or > WXSIZE WYSIZE = 0 Write_Window_Y = Total bytes write into FIFO window / WXSIZE WWCTRL[6]: 0 -> No X-mirror WSTRIDE: positive number -> No Y-mirror
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AL440B
Memory Area WSTRIDE WXSIZE WSTART-XSIZE+1
WSTART WSTART+1xWSTRIDE WSTART+2xWSTRIDE
o G
ck ba
to
RT TA S W
Write Window Area WSTART+(Write_Window_Y-1)x WSTRIDE
AL440B Write Window(2)
For Write Window with X-mirror: WSTRIDE = or > WXSIZE WYSIZE = 0 Write_Window_Y = Total bytes write into FIFO window / WXSIZE WWCTRL[6]: 1 -> X-mirror WSTRIDE: positive number -> No Y-mirror
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AL440B
Memory Area WSTRIDE WXSIZE WSTART+(Write_Window_Y-1)x WSTRIDE Write Window Area
G o
ba ck
to
W ST AR T
WSTART-XSIZE+1
WSTART+2xWSTRIDE WSTART+1xWSTRIDE WSTART
AL440B Write Window(3)
For Write Window with both X-mirror and Y-mirror: WSTRIDE = or > WXSIZE WYSIZE = 0 Write_Window_Y = Total bytes write into FIFO window / WXSIZE WWCTRL[6]: 1 -> X-mirror WSTRIDE: negative number -> Y-mirror
11.8 Window Read Register Programming
The operations of Window Read function are same as Window Write. The operation of Window Read is operated independently from Window Write. The Window Read related registers are listed as follows: RSTART_L and RSTART_H define the window data read starting address. Addr Name Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 0Bh RSTART_L [7] [6] [5] [4] [3] [2] [1] [0] 0Ch RSTART_H 0 0 0 [12] [11] [10] [9] [8] RSTART (Read Start address) <= RSTART_H[4:0] & RSTART_L ; RSTART range is from 0 to 8191 (block).
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RXSIZE_L and RXSIZE_H define the window data read horizontal size. Addr Name Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 0Dh RXSIZE_L [7] [6] [5] [4] [3] [2] 0Eh RXSIZE_H 0 0 0 0 0 0 RXSIZE (Read X Size) <= RXSIZE_H[2:0] & RXSIZE_L ; WXSIZE range is from 0 to 1023 (block).
Bit1 [1] [9]
Bit0 [0] [8]
RSTRIDE_L and RSTRIDE_H define the window data write horizontal width. Addr Name Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 0Fh RSTRIDE_L [7] [6] [5] [4] [3] [2] [1] 10h RSTRIDE_H 0 0 0 0 [11] [10] [9] RSTRIDE (Read Stride) <= RSTRIDE_H[3:0] & RSTRIDE _L ; RSTRIDE range is from 0 to +4095 (block). RYSIZE_L and RYSIZE_H define the window data read vertical high. Addr Name Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 11h RYSIZE_L [7] [6] [5] [4] [3] [2] 12h RYSIZE_H [15] [14] [13] [12] [11] [10] RYSIZE (Read Y Size) <= RYSIZE_H & RYSIZE_L; Write Y Size range is from 0 to 65535.
Bit0 [0] [8]
Bit1 [1] [9]
Bit0 [0] [8]
RWCTRL is the register that control window data read function enable/disable. Addr Name Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 13h RWCTRL [7] 0 0 0 0 0 0
Bit0 0
RWCTRL[7] Read Write mode enable 1: enable Window Read mode 0: disable Window Read mode. The memory is operating in standard FIFO Read mode. Note: 1. X-mirror and Y-mirror functions are not needed in Window Read mode, so they are not implemented in Window Read operation. 2. There is no "freeze" function in Window Read mode. Please refer to the following illustration as an application example for the explanation of Window read operation.
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AL440B
Memory Area RSTART RSTART+1xRSTRIDE RSTART+2xRSTRIDE
Go
RXSIZE
RSTART+ (RXSIZE-1)
ba c
RYSIZE
kt oR
ST AR T
Read Window Area RSTART+ (RYSIZE-1)x RSTRIDE
AL440B Read Window
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AL440B
12.0 Electrical Characteristics
12.1 Absolute Maximum Ratings
Parameter VDD VP IO TAMB Tstg Supply Voltage Pin Voltage Output Current Ambient Op. Temperature Storage temperature Rating -0.3 ~ +3.8 -0.3 ~ +(VDD+0.3) -20 ~ +20 0 ~ +85 -40 ~ +125 Unit V V mA C C
12.2 Recommended Operating Conditions
Parameter VDD VIH VIL Supply Voltage High Level Input Voltage Low Level Input Voltage Min +3.0 0.7 VDD 0 Typ +3.3 Max +3.6 5 0.3 VDD Unit V V V
12.3 DC Characteristics
(VDD = 3.3V, Vss=0V. TAMB = 0 to 70C) Parameter IDD IDDS VOH VOL ILI ILO RL
1. 2.
Min 2.4 -5 -5
Typ 52 14 50
Max 62 VDD +0.4 +5 +5
Unit mA mA V V A A K
Operating Current Standby Current Hi-level Output Voltage Lo-level Output Voltage Input Leakage Current (No pull-up or pull-down) Output Leakage Current (No pull-up or pull-down) Input Pull-up/Pull-down Resistance
Tested with outputs disabled (IOUT = 0) RCLK and WCLK toggle at 20 MHz and data inputs switch at 10 MHz.
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AL440B
12.4 AC Characteristics
(VDD = 3.3V, Vss=0V, TAMB = 0 to 70C)
Parameter TWC TWPH TWPL TRC TRPH TRPL TAC TOH THZ TLZ TWRS TWRH TRRS TRRH TDS TDH TWES TWEH TWPW TRES TREH TRPW TIES TIEH TIPW TOES TOEH TOPW TTR CI WCK Cycle Time WCK High Pulse Width WCK Low Pulse Width RCK Cycle Time RCK High Pulse Width RCK Low Pulse Width Access Time Output Hold Time Output High-Z Setup Time Output Low-Z Setup Time WRST Setup Time WRST Hold Time RRST Setup Time RRST Hold Time Input Data Setup Time Input Data Hold Time WE Setup Time WE Hold Time WE Pulse Width RE Setup Time RE Hold Time RE Pulse Width IE Setup Time IE Hold Time IE Pulse Width OE Setup Time OE Hold Time OE Pulse Width Transition Time Input Capacitance 25 10 10 25 10 10 6 5 6 8 8 8 8 5 6 6 6 15 6 6 15 6 6 15 8 8 20 3 -
40MHz Min Max 20 -
80MHz Min 12.5 5 5 12.5 5 5 4 4 5 4 5 4 5 4 5 4 5 12 4 5 12 4 5 12 5 5 12 3 7 7 Max 12 -
Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns pF
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AL440B
CO
Output Capacitance
-
7
-
7
pF
*
The read address needs to be at least 192 cycles after the write address.
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AL440B
13.0 Timing Diagrams
cycle n
Reset cycle (s)
cycle 0
cycle 1
WCK
TTR TWRS TWRH
WRST
TDS
TDH
DI7~0
n-1
n
0
1
/PLRTY=VDD
, WE= "L"
, IE= "L"
Write Cycle Timing (Write Reset)
cycle n TWPL
cycle n+1
Disable cycle (s)
cycle n+2
WCK
TWPH TWC TWES TWEH
WE
TWPW TDS TDH
DI7~0
n-1
n
n+1
n+2
/PLRTY=VDD ,IE="L"
,WRST="H" Write Cycle Timing (Write Enable)
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AL440B
cycle n TWPL
cycle n+1
Disable cycle (s)
cycle 0
cycle 1
WCK
TWPH
TWC
TWRS
TWRH
WRST
TWES
TWEH
WE
TWPW TDS TDH
DI7~0
n-1
n
n+1
0
1
/PLRTY=VDD ,IE="L" Write Cycle Timing (WE, WRST)
cycle n TWPL
cycle n+1
cycle n+2
cycle n+3
cycle n+4
WCK
TWPH TWC TIES TIEH
IE
TIPW
TIH
DI7~0
n-1
n
n+1
n+4
/PLRTY=VDD ,WE="L"
,WRST="H" Write Cycle Timing (Input Enable)
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AL440B
cycle n TRPL Reset cycle (s) cycle 0 cycle 1
RCK
TRPH
TRRS
TRRH
RRST
TAC TOH
DO7~0
n-1
n
0
0
1
/PLRTY=VDD
,RE= "L"
,OE= "L"
Read Cycle Timing (Read Reset)
cycle n TRPL
cycle n+1
Disable cycle (s)
cycle n+2
RCK
TRPH TRC TRES TREH
RE
TRPW TAC TOH
DO7~0
n-1
n
n+1
n+2
/PLRTY=VDD ,OE="L" ,RRST="H" Read Cycle Timing (Read Enable)
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AL440B
cycle n TRPL
cycle n+1
Disable cycle (s)
cycle 0
RCK
TRPH TRC TRRS TRRH
RRST
TRES
TREH
RE
TRPW TAC TOH
DO7~0
n-1
n
n+1
0
/PLRTY=VDD ,OE="L" Read Cycle Timing (RE, RRST)
cycle n TRPL
cycle n+1
cycle n+2
cycle n+3
cycle n+4
RCK
TRPH TRC TOES TOEH
OE
TOPW TAC TOH THZ Hi-Z TLZ
DO7~0
n-1
n
n+1
n+4
/PLRTY=VDD ,RE="L"
,RRST="H" Read Cycle Timing (Output Enable)
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AL440B
cycle n
Reset cycle (s)
cycle 0
cycle 1
WCK
TTR TWRS TWRH
WRST
TDS
TDH
DI7~0
n-1
n
0
1
/PLRTY=GND
, WE= "H"
, IE= "H"
Write Cycle Timing (Write Reset)
cycle n TWPL
cycle n+1
Disable cycle (s)
cycle n+2
WCK
TWPH TWC TWES TWEH
WE
TWPW TDS TDH
DI7~0
n-1
n
n+1
n+2
/PLRTY=GND ,IE="H"
,WRST="L" Write Cycle Timing (Write Enable)
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AL440B
cycle n TWPL
cycle n+1
Disable cycle (s)
cycle 0
cycle 1
WCK
TWPH
TWC
TWRS
TWRH
WRST
TWES
TWEH
WE
TWPW TDS TDH
DI7~0
n-1
n
n+1
0
1
/PLRTY=GND ,IE="H" Write Cycle Timing (WE, WRST)
cycle n TWPL
cycle n+1
cycle n+2
cycle n+3
cycle n+4
WCK
TWPH TWC TIES TIEH
IE
TIPW
TIH
DI7~0
n-1
n
n+1
n+4
/PLRTY=GND ,WE="H"
,WRST="L" Write Cycle Timing (Input Enable)
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AL440B
cycle n TRPL Reset cycle (s) cycle 0 cycle 1
RCK
TRPH
TRRS
TRRH
RRST
TAC TOH
DO7~0
n-1
n
0
0
1
/PLRTY=GND ,RE= "H"
,OE= "H"
Read Cycle Timing (Read Reset)
cycle n TRPL
cycle n+1
Disable cycle (s)
cycle n+2
RCK
TRPH TRC TRES TREH
RE
TRPW TAC TOH
DO7~0
n-1
n
n+1
n+2
/PLRTY=GND ,OE="H"
,RRST="L" Read Cycle Timing (Read Enable)
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AL440B
cycle n TRPL
cycle n+1
Disable cycle (s)
cycle 0
RCK
TRPH TRC TRRS TRRH
RRST
TRES
TREH
RE
TRPW TAC TOH
DO7~0
n-1
n
n+1
0
/PLRTY=GND ,OE="H" Read Cycle Timing (RE, RRST)
cycle n TRPL
cycle n+1
cycle n+2
cycle n+3
cycle n+4
RCK
TRPH TRC TOES TOEH
OE
TOPW TAC TOH THZ Hi-Z TLZ
DO7~0
n-1
n
n+1
n+4
/PLRTY=GND
,RE="H"
,RRST="L" Read Cycle Timing (Output Enable)
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AL440B
14.0 Mechanical Drawing - 44 PIN PLASTIC TSOP (II)
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"D "
(Unit: mm)
"E1"
"b"
NOTE: 1. Controlling Dimension: Millimeters. 2. Dimension "D" does not include mold protrusion. Mold protrusion shall not exceed 0.15(0.006") per side. Dimension "E1" does not include interlead protrusion. Interlead protrusion shall not per side. 3. Dimension "b" does not include damar protrusions/intrusion. Allowable damar protrusion shall not cause the lead to be wider than the MAX "b" dimension by more than 0.13mm. Damar intrusion shall not cause the lead to be narrower than the MIN "b 0.07mm.
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15.0 Application Notes
15.1 Chip Global Reset Recommend Circuit
To ensure a proper reset pulse can be applied to /RESET pin (pin 27) to complete the power-on reset, the recommend reset circuit is to connect the AL440B /RESET pin (pin 27) to VDD with a 2k resistor and to Ground with a 10f capacitor as follows.
AL440B
8-bit Input DI[7:0] DO[7:0] 8-bit Output
VDD 2K Ohm
27
/RESET
50K Ohm
10 uf
AL440B Global Reset Circuit
It is also recommend adding buffers for the power-on reset circuit to increase the driving capability for any application with multiple AL440B chips.
15.2 The AL440B Reference Schematic
U8 AL440 VDD3S DI0 DI1 DI2 DI3 DI4 DI5 DI6 DI7 RNSMD1 1 2 3 4 R5 R3 10 8 7 6 5 10 2K 5 29 40 CTL0 CTL1 CTL2 CTL3 CTL4 CTL5 10 11 13 14 15 16 17 WE IE WCK WRST IRDY PLRTY TEST RE OE RCK RRST ORDY SDA SCL SDAEN 35 34 32 31 30 25 24 23 1 2 3 4 6 7 8 9 DI0 DI1 DI2 DI3 DI4 DI5 DI6 DI7 DO0 DO1 DO2 DO3 DO4 DO5 DO6 DO7 44 43 42 41 39 38 37 36 DO0 DO1 DO2 DO3 DO4 DO5 DO6 DO7 RNSMD3 CTL7 1 CTL8 2 CTL9 3 CTL10 4 CTL11 1 CTL12 2 CTL13 3 CTL14 4 RNSMD4 VDD VDD VDD /RESET AVDD 27 18 FAVDD 0.1uf 12 26 33 GND GND GND NC NC NC NC AGND 22 C62 R5 1 10 2 VDD3S + C67 10uF 10 8 7 6 5 8 7 6 5 10 R1 RE OE RCK RRST ORDY SDA SCL SDAEN 2K VDD3S R6 R7 4.7K 4.7K
WE IE WCK WRST IRDY R2 VDD3S 2K
Populate R2 or R3 to select Control Singals polarity
VDD3S 1 L5 F B FB C54 + 10uF 0.1uf C55 2 FDVDD 0.1uf 0.1uf C56 C57
F L7
B FB
28 19 20 21
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CONTACT INFORMATION
AverLogic Technologies, Inc. 90 Great Oaks Blvd. #204 San Jose, CA 95119 USA Tel : +1 408 361-0400 Fax : +1 408 361-0404 E-mail : sales@averlogic.com URL : www.averlogic.com
AverLogic Technologies, Corp. 4F., No.514, Sec.2, Cheng Kung Rd., Nei-Hu Dist., Taipei, Taiwan R.O.C Tel : +886 2-27915050 Fax : +886 2-27912132 E-mail : sales@averlogic.com.tw URL : www.averlogic.com.tw