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| Preliminary Product Description The XD010-35S-D2F 10W power module is a 2-stage Class A/AB RF amplifier module for use in the driver stages of WCDMA power amplifiers. The power transistors are fabricated using Sirenza's latest, high performance LDMOS II process. The unit operates from a single voltage and has internal temperature compensation of the bias voltage to ensure stable performance over the full temperature range. Functional Block Diagram Stage 1 Stage 2 XD010-35S-D2F 2110-2170 MHz Class A/AB 10W Power Amplifier Module Product Features Temperature Compensation Temperature Compensation * * * * * * * 5 50 W RF impedance 10W Output P1dB Single Voltage Operation High Gain: 26.5 dB Typical High Efficiency Advanced, XeMOS II LDMOS FETS Temperature Compensation 1 2 3 4 Applications RF in 28 VDC Case Flange = Ground 28 VDC RF out * * * Base Station PA driver Repeater WCDMA Key Specifications Parameter Frequency P1dB Gain Gain Flatness IRL Efficiency Linearity Delay Phase Linearity RTH, j-l RTH, j-2 Description: Test Conditions Zin = Zout = 50, VDD = 28.0V, IDD1 = 240mA, IDD2 = 150mA, TFlange = 25C Frequency of Operation Output Power at 1dB Compression, 2140MHz Gain at 1W Output Power, 2140MHz Peak to Peak Gain Variation, 2110-2170MHz Input Return Loss 1W Output Power, 2110-2170MHz Drain Efficiency at 10W CW Drain Efficiency at 1W CDMA (Single Carrier) ACPR at 1W SC W-CDMA Output 3rd Order IMD at 8W PEP (Two Tone) Signal Delay from Pin 1 to Pin 5 Deviation from Linear Phase (Peak to Peak) Thermal Resistance Stage 1 (Junction to Case) Thermal Resistance Stage 2 (Junction to Case) Unit MHz W dB dB dB % % dB dBc nS Deg C/W C/W Min. 2110 10 26.5 0.4 14 29 6.5 -50 -30 3.0 0.5 11 4 Typ. Max. 2170 The information provided herein is believed to be reliable at press time. Sirenza Microdevices assumes no responsibility for inaccuracies or ommisions. Sirenza Microdevices assumes no responsibility for the use of this information, and all such information shall be entirely at the user's own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. Sirenza Microdevices does not authorize or warrant any Sirenza Microdevices product for use in life-support devices and/or systems. Copyright 2003 Sirenza Microdevices, Inc. All worldwide rights reserved. 522 Almanor Ave., Sunnyvale, CA 94085 Phone: (800) SMI-MMIC 1 http://www.sirenza.com EDS-102978 Rev A Preliminary XD010-35S-D2F 2110-2170 MHz 10W Pin Out Description Pin # 1 2 3,4 5 Flange Function RF Input VDD1 VDD2 RF Output Gnd Description Module RF input. This pin is internally connected to DC ground. Do not apply DC voltages to the RF leads. Care must be taken to protect against video transients that may damage the active devices. This is the bias feed for the 1st stage of the amplifier module. The gate bias is temperature compensated to maintain constant current over the operating temperature range. See Note 1. This is the bias feed for the 2nd stage of the amplifier module. The gate bias is temperature compensated to maintain constant current over the operating temperature range. See Note 1. Module RF output. This pin is internally connected to DC ground. Do not apply DC voltages to the RF leads. Care must be taken to protect against video transients that may damage the active devices. Exposed area on the bottom side of the package needs to be mechanically attached to the ground plane of the board for optimum thermal and RF performance. See mounting instructions for recommendation. Simplified Device Schematic 2 Vdd1 3 4 Vdd2 Temperature Compensation Temperature Compensation RF in 1 Q1 Q2 RF out 5 Case Flange = Ground Absolute Maximum Ratings Parameters 1st Stage Bias Voltage (VDD1 ) 2nd Stage Bias Voltage (VDD2) RF Input Power Load Impedance for Continuous Operation Without Damage Output Device Channel Temperature Lead Temperature During Solder Reflow Operating Temperature Range Storage Temperature Range Value 35 35 +23 5:1 +200 +210 -20 to +90 -40 to +100 Unit V V dBm VSWR C C C C Note 1: The internal generated gate voltage is thermally compensated to maintain constant quiescent current over the temperature range listed in the data sheet. No compensation is provided for gain changes with temperature. This can only be provided with AGC external to the module. Note 2: Internal RF decoupling is included on all bias leads. No additional bypass elements are required, however some applications may require energy storage on the drain leads to accommodate time-varying waveforms. Operation of this device beyond any one of these limits may cause permanent damage. For reliable continuous operation see typical setup values specified in the table on page one. Caution: ESD Sensitive Appropriate precaution in handling, packaging and testing devices must be observed. 522 Almanor Ave., Sunnyvale, CA 94085 Phone: (800) SMI-MMIC 2 http://www.sirenza.com EDS-102978 Rev A Preliminary XD010-35S-D2F 2110-2170 MHz 10W Test Board Schematic with module attachments shown Test Board Layout and Bill of Materials Component PCB J1, J2 J3, J4 C1, C2 C4, C6 C3, C5 JP1 Header JP1 Shunt Mounting Screws Description Rogers 4350, er=3.5 Thickness=30mils SMA, RF, Panel Mount Tab W / Flange MTA Post Header, 5 Pin, Rectangle, Polarized, Surface Mount Cap, 220mF 50V, -40 to 85oC, Electrolytic, G Cap, 0.01mF, 100V, 10%, 1206 Cap, 1000pF, 100V, 10%, 1206 SMT Header, Low Profile, 2mm Shunt, Mate to Header, 2mm 4-40 X 0.250" Manufacturer Rogers AMP AMP Panasonic Johanson Johanson Specialty Electronics Specialty Electronics Various To download Gerber files, DXF drawings, a detailed BOM, and assembly recommendations for the test board with fixture click here 522 Almanor Ave., Sunnyvale, CA 94085 Phone: (800) SMI-MMIC 3 http://www.sirenza.com EDS-102978 Rev A Preliminary XD010-35S-D2F 2110-2170 MHz 10W Package Outline Drawing Recommended PCB Cutout and Landing Pads for the D2F Package Note 3: Dimensions are in inches 522 Almanor Ave., Sunnyvale, CA 94085 Phone: (800) SMI-MMIC 4 http://www.sirenza.com EDS-102978 Rev A |
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