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(R)
PIC16C7X
PIC16C7X
A/D CMOS
(c) 1996 Microchip Technology Inc.
DS30390B-J00 - page 1
PIC16C7X
PDIP, SOIC, Windowed CERDIP
RA2/AN2 RA3/AN3/VREF RA4/T0CKI MCLR/VPP VSS RB0/INT RB1 RB2 RB3 *1 18 RA1/AN1 RA0/AN0 OSC1/CLKIN OSC2/CLKOUT VDD RB7 RB6 RB5 RB4 RA2/AN2 RA3/AN3/VREF RA4/T0CKI MCLR/VPP VSS VSS RB0/INT RB1 RB2 RB3 *1 2 3 4 5 6 7 8 9 10
SSOP
20 19 18 17 16 15 14 13 12 11 RA1/AN1 RA0/AN0 OSC1/CLKIN OSC2/CLKOUT VDD VDD RB7 RB6 RB5 RB4
PIC16C710
2 3 4 5 6 7 8 9
17 16 15 14 13 12 11 10
PIC16C710
PDIP, SOIC, Windowed CERDIP
RA2/AN2 RA3/AN3/VREF RA4/T0CKI MCLR/VPP VSS RB0/INT RB1 RB2 RB3 *1 18 RA1/AN1 RA0/AN0 OSC1/CLKIN OSC2/CLKOUT VDD RB7 RB6 RB5 RB4
PIC16C71
2 3 4 5 6 7 8 9
17 16 15 14 13 12 11 10
PDIP, SOIC, Windowed CERDIP
RA2/AN2 RA3/AN3/VREF RA4/T0CKI MCLR/VPP VSS RB0/INT RB1 RB2 RB3 *1 18 RA1/AN1 RA0/AN0 OSC1/CLKIN OSC2/CLKOUT VDD RB7 RB6 RB5 RB4 RA2/AN2 RA3/AN3/VREF RA4/T0CKI MCLR/VPP VSS VSS RB0/INT RB1 RB2 RB3 *1 2 3 4 5 6 7 8 9 10
SSOP
20 19 18 17 16 15 14 13 12 11 RA1/AN1 RA0/AN0 OSC1/CLKIN OSC2/CLKOUT VDD VDD RB7 RB6 RB5 RB4
PIC16C711
2 3 4 5 6 7 8 9
17 16 15 14 13 12 11 10
PIC16C711
SDIP, SOIC, Windowed Side Brazed Ceramic
MCLR/VPP RA0/AN0 RA1/AN1 RA2/AN2 RA3/AN3/VREF RA4/T0CKI RA5/AN4/SS VSS OSC1/CLKIN OSC2/CLKOUT RC0/T1OSO/T1CKI RC1/T1OSI RC2/CCP1 RC3/SCK/SCL *1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0/INT VDD VSS RC7 RC6 RC5/SDO RC4/SDI/SDA MCLR/VPP RA0/AN0 RA1/AN1 RA2/AN2 RA3/AN3/VREF RA4/T0CKI RA5/AN4/SS VSS OSC1/CLKIN OSC2/CLKOUT RC0/T1OSO/T1CKI RC1/T1OSI RC2/CCP1 RC3/SCK/SCL *1 2 3 4 5 6 7 8 9 10 11 12 13 14
SSOP
28 27 26 25 24 23 22 21 20 19 18 17 16 15 RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0/INT VDD VSS RC7 RC6 RC5/SDO RC4/SDI/SDA
PIC16C72
PIC16C72
DS30390B-J00 - page 2
(c) 1996 Microchip Technology Inc.
PIC16C7X
RC6/TX/CK RC5/SDO RC4/SDI/SDA RD3/PSP3 RD2/PSP2 RD1/PSP1 RD0/PSP0 RC3/SCK/SCL RC2/CCP1 RC1/T1OSI/CCP2 NC 44 43 42 41 40 39 38 37 36 35 34
SDIP, SOIC, Windowed Side Brazed Ceramic
MCLR/VPP RA0/AN0 RA1/AN1 RA2/AN2 RA3/AN3/VREF RA4/T0CKI RA5/AN4/SS VSS OSC1/CLKIN OSC2/CLKOUT RC0/T1OSO/T1CKI RC1/T1OSI/CCP2 RC2/CCP1 RC3/SCK/SCL *1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0/INT VDD VSS RC7/RX/DT RC6/TX/CK RC5/SDO RC4/SDI/SDA
MQFP
PLCC
RA3/AN3/VREF RA2/AN2 RA1/AN1 RA0/AN0 MCLR/VPP NC RB7 RB6 RB5 RB4 NC
MQFP TQFP
6 5 4 3 2 1 44 43 42 41 40
44 43 42 41 40 39 38 37 36 35 34
RC6/TX/CK RC5/SDO RC4/SDI/SDA RD3/PSP3 RD2/PSP2 RD1/PSP1 RD0/PSP0 RC3/SCK/SCL RC2/CCP1 RC1/T1OSI/CCP2 NC
PIC16C73 PIC16C73A
RC7/RX/DT RD4/PSP4 RD5/PSP5 RD6/PSP6 RD7/PSP7 VSS VDD RB0/INT RB1 RB2 RB3
1 2 3 4 5 6 7 8 9 10 11
PIC16C74
33 32 31 30 29 28 27 26 25 24 23
NC RC0/T1OSO/T1CK OSC2/CLKOUT OSC1/CLKIN VSS VDD RE2/CS/AN7 RE1/WR/AN6 RE0/RD/AN5 RA5/AN4/SS RA4/T0CKI
RA4/T0CKI RA5/AN4/SS RE0/RD/AN5 RE1/WR/AN6 RE2/CS/AN7 VDD VSS OSC1/CLKIN OSC2/CLKOUT RC0/T1OSO/T1CKI NC
7 8 9 10 11 12 13 14 15 16 17
PIC16C74 PIC16C74A
28 27 26 25 24 23 22 21 20 19 18
39 38 37 36 35 34 33 32 31 30 29
RB3 RB2 RB1 RB0/INT VDD VSS RD7/PSP7 RD6/PSP6 RD5/PSP5 RD4/PSP4 RC7/RX/DT
RC7/RX/DT RD4/PSP4 RD5/PSP5 RD6/PSP6 RD7/PSP7 VSS VDD RB0/INT RB1 RB2 RB3
1 2 3 4 5 6 7 8 9 10 11
22 21 20 19 18 17 16 15 14 13 12 RA3/AN3/VREF RA2/AN2 RA1/AN1 RA0/AN0 MCLR/VPP RB7 RB6 RB5 RB4 NC NC
PIC16C74A
33 32 31 30 29 28 27 26 25 24 23
NC RC0/T1OSO/T1CK OSC2/CLKOUT OSC1/CLKIN VSS VDD RE2/CS/AN7 RE1/WR/AN6 RE0/RD/AN5 RA5/AN4/SS RA4/T0CKI
22 21 20 19 18 17 16 15 14 13 12 RA3/AN3/VREF RA2/AN2 RA1/AN1 RA0/AN0 MCLR/VPP RB7 RB6 RB5 RB4 NC NC
(c) 1996 Microchip Technology Inc.
NC RC6/TX/CK RC5/SDO RC4/SDI/SDA RD3/PSP3 RD2/PSP2 RD1/PSP1 RD0/PSP0 RC3/SCK/SCL RC2/CCP1 RC1/T1OSI /CCP2
PDIP, Windowed CERDIP
MCLR/VPP RA0/AN0 RA1/AN1 RA2/AN2 RA3/AN3/VREF RA4/T0CKI RA5/AN4/SS RE0/RD/AN5 RE1/WR/AN6 RE2/CS/AN7 VDD VSS OSC1/CLKIN OSC2/CLKOUT RC0/T1OSO/T1CKI RC1/T1OSI/CCP2 RC2/CCP1 RC3/SCK/SCL RD0/PSP0 RD1/PSP1
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21
RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0/INT VDD VSS RD7/PSP7 RD6/PSP6 RD5/PSP5 RD4/PSP4 RC7/RX/DT RC6/TX/CK RC5/SDO RC4/SDI/SDA RD3/PSP3 RD2/PSP2
PIC16C74A
PIC16C74
DS30390B-J00 - page 3
PIC16C7X
DS30390B-J00 - page 4
(c) 1996 Microchip Technology Inc.
PIC16C7X
(c) 1996 Microchip Technology Inc.
DS30390B-J00-page 5
PIC16C7X
DS30390B-J00-page 6
(c) 1996 Microchip Technology Inc.
PIC16C7X
Microchip
Microchip
Microchip PIC16C7X
PICSTARTTM
PRO MATE TM
(c) 1996 Microchip Technology Inc.
DS30390B-J00 - page 7
PIC16C7X
DS30390B-J00 - page 8
(c) 1996 Microchip Technology Inc.
PIC16C7X
(c) 1996 Microchip Technology Inc.
DS30390B-J00 - page - 9
PIC16C7X
Device PIC16C710 PIC16C71 PIC16C711
Program Memory Data Memory (RAM) 512 x 14 1K x 14 1K x 14 36 x 8 36 x 8 68 x 8
13 Program Counter EPROM Program Memory Program Bus 8 Level Stack (13-bit)
Data Bus
8
PORTA RA0/AN0 RA1/AN1 RA2/AN2 RA3/AN3/VREF RA4/T0CKI PORTB
RAM File Registers RAM Addr (1) 9
14 Instruction reg Direct Addr 7
Addr MUX 8 Indirect Addr RB0/INT RB7:RB1
FSR reg STATUS reg 8 3 Power-up Timer Instruction Decode & Control Timing Generation OSC1/CLKIN OSC2/CLKOUT Oscillator Start-up Timer Power-on Reset Watchdog Timer Brown-out Reset(2) Timer0 8 W reg ALU
MUX
MCLR
VDD, VSS A/D
Note 1: Higher order bits are from the STATUS register. 2: Brown-out Reset is not available on the PIC16C71.
DS30390B-J00 - page 10
(c) 1996 Microchip Technology Inc.
PIC16C7X
13 EPROM Program Memory 2K x 14 Program Bus 14 Instruction reg Direct Addr 7 8 Level Stack (13-bit) Program Counter
Data Bus
8
PORTA RA0/AN0 RA1/AN1 RA2/AN2 RA3/AN3/VREF RA4/T0CKI RA5/AN4/SS PORTB
RAM File Registers 128 x 8 RAM Addr(1) 9
Addr MUX 8 Indirect Addr RB0/INT RB7:RB1
FSR reg STATUS reg 8 3 PORTC
Power-up Timer Instruction Decode & Control Timing Generation OSC1/CLKIN OSC2/CLKOUT Oscillator Start-up Timer Power-on Reset Watchdog Timer Brown-out Reset 8
MUX
ALU
RC0/T1OSO/T1CKI RC1/T1OSI RC2/CCP1 RC3/SCK/SCL RC4/SDI/SDA RC5/SDO RC6 RC7
W reg
MCLR
VDD, VSS
Timer0
Timer1
Timer2
A/D
Synchronous Serial Port
CCP1
Note 1: Higher order bits are from the STATUS register.
(c) 1996 Microchip Technology Inc.
DS30390B-J00 - page - 11
PIC16C7X
13 EPROM Program Memory 4K x 14 Program Bus 14 Instruction reg Direct Addr 7 8 Level Stack (13-bit) Program Counter
Data Bus
8
PORTA RA0/AN0 RA1/AN1 RA2/AN2 RA3/AN3/VREF RA4/T0CKI RA5/AN4/SS PORTB
RAM File Registers 192 x 8 RAM Addr(1) 9
Addr MUX 8 Indirect Addr RB0/INT RB7:RB1
FSR reg STATUS reg 8 3 Power-up Timer Instruction Decode & Control Timing Generation OSC1/CLKIN OSC2/CLKOUT Oscillator Start-up Timer Power-on Reset Watchdog Timer Brown-out Reset(2) 8 W reg ALU PORTC
MUX
RC0/T1OSO/T1CKI RC1/T1OSI/CCP2 RC2/CCP1 RC3/SCK/SCL RC4/SDI/SDA RC5/SDO RC6/TX/CK RC7/RX/DT
MCLR
VDD, VSS
Timer0
Timer1
Timer2
A/D
CCP1
CCP2
Synchronous Serial Port
USART
Note 1: Higher order bits are from the STATUS register. 2: Brown-out Reset is not available on the PIC16C73.
DS30390B-J00 - page 12
(c) 1996 Microchip Technology Inc.
PIC16C7X
13 EPROM Program Memory 4K x 14 Program Bus 14 Instruction reg Direct Addr 7 8 Level Stack (13-bit) Program Counter
Data Bus
8
PORTA RA0/AN0 RA1/AN1 RA2/AN2 RA3/AN3/VREF RA4/T0CKI RA5/AN4/SS PORTB
RAM File Registers 192 x 8 RAM Addr (1) 9
Addr MUX 8 Indirect Addr RB0/INT RB7:RB1 PORTC RC0/T1OSO/T1CKI RC1/T1OSI/CCP2 RC2/CCP1 RC3/SCK/SCL RC4/SDI/SDA RC5/SDO RC6/TX/CK RC7/RX/DT PORTD W reg RD7/PSP7:RD0/PSP0
FSR reg STATUS reg 8 3
Power-up Timer Instruction Decode & Control Timing Generation OSC1/CLKIN OSC2/CLKOUT Oscillator Start-up Timer Power-on Reset Watchdog Timer Brown-out Reset(2) 8
MUX
ALU
Parallel Slave Port MCLR VDD, VSS
PORTE RE0/RD/AN5 RE1/WR/AN6
Timer0
Timer1
Timer2
A/D
RE2/CS/AN7
CCP1
CCP2
Synchronous Serial Port
USART
Note 1: Higher order bits are from the STATUS register. 2: Brown-out Reset is not available on the PIC16C74.
(c) 1996 Microchip Technology Inc.
DS30390B-J00 - page - 13
PIC16C7X
DS30390B-J00 - page 14
(c) 1996 Microchip Technology Inc.
PIC16C7X
(c) 1996 Microchip Technology Inc.
DS30390B-J00 - page - 15
PIC16C7X
DS30390B-J00 - page 16
(c) 1996 Microchip Technology Inc.
PIC16C7X
(c) 1996 Microchip Technology Inc.
DS30390B-J00 - page - 17
PIC16C7X
DS30390B-J00 - page 18
(c) 1996 Microchip Technology Inc.
PIC16C7X
(c) 1996 Microchip Technology Inc.
DS30390B-J00 - page - 19
PIC16C7X
Q1 OSC1 Q1 Q2 Q3 Q4 PC OSC2/CLKOUT (RC mode)
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Internal phase clock
PC
PC+1
PC+2
Fetch INST (PC) Execute INST (PC-1)
Fetch INST (PC+1) Execute INST (PC)
Fetch INST (PC+2) Execute INST (PC+1)
1. MOVLW 55h 2. MOVWF PORTB 3. CALL SUB_1 4. BSF PORTA,BIT3
Fetch1
Execute1 Fetch2
Execute2 Fetch3
Execute3 Fetch4
Flush
Fetch SUB_1
Execute SUB_1
DS30390B-J00 - page 20
(c) 1996 Microchip Technology Inc.
PIC16C7X
PC<12:0>
CALL, RETURN RETFIE, RETLW
13
Stack Level 1
Stack Level 8 Reset Vector
0000h
Interrupt Vector On-chip Program Memory
0004h 0005h 03FFh 0200h
1FFFh
PC<12:0>
CALL, RETURN RETFIE, RETLW
13
Stack Level 1
Stack Level 8 Reset Vector
0000h
Interrupt Vector On-chip Program Memory
0004h 0005h 01FFh 0200h
1FFFh
(c) 1996 Microchip Technology Inc.
DS30390B-J00 - page 21
PIC16C7X
PC<12:0>
CALL, RETURN RETFIE, RETLW
PC<12:0>
CALL, RETURN RETFIE, RETLW
13
13
Stack Level 1
Stack Level 1
Stack Level 8 Reset Vector
Stack Level 8
0000h
Reset Vector
0000h
Interrupt Vector
0004h 0005h
Interrupt Vector On-chip Program Memory (Page 0)
0004h 0005h 07FFh
On-chip Program Memory 07FFh 0800h
On-chip Program Memory (Page 1)
0800h
0FFFh 1000h
1FFFh
1FFFh
DS30390B-J00 - page 22
(c) 1996 Microchip Technology Inc.
PIC16C7X
File Address 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch INDF(1) TMR0 PCL STATUS FSR PORTA PORTB ADCON0 ADRES PCLATH INTCON INDF(1) OPTION PCL STATUS FSR TRISA TRISB PCON(2) ADCON1 ADRES PCLATH INTCON General Purpose Register Mapped in Bank 0(3)
File Address 80h 81h 82h 83h 84h 85h 86h 87h 88h 89h 8Ah 8Bh 8Ch
File Address 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch INDF(1) TMR0 PCL STATUS FSR PORTA PORTB ADCON0 ADRES PCLATH INTCON INDF(1) OPTION PCL STATUS FSR TRISA TRISB PCON ADCON1 ADRES PCLATH INTCON General Purpose Register Mapped in Bank 0(2)
File Address 80h 81h 82h 83h 84h 85h 86h 87h 88h 89h 8Ah 8Bh 8Ch
General Purpose Register 2Fh 30h
General Purpose Register
AFh B0h
4Fh 50h
CFh D0h
7Fh Bank 0 Bank 1
FFh
7Fh Bank 0 Bank 1
FFh
Unimplemented data memory locations, read as '0'. Note 1: Not a physical register. 2: The PCON register is not implemented on the PIC16C71. 3: These locations are unimplemented in Bank 1. Any access to these locations will access the corresponding Bank 0 register.
Unimplemented data memory locations, read as '0'. Note 1: Not a physical register. 2: These locations are unimplemented in Bank 1. Any access to these locations will access the corresponding Bank 0 register.
(c) 1996 Microchip Technology Inc.
DS30390B-J00 - page 23
PIC16C7X
File Address 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh 20h INDF(1) TMR0 PCL STATUS FSR PORTA PORTB PORTC INDF(1) OPTION PCL STATUS FSR TRISA TRISB TRISC
File Address 80h 81h 82h 83h 84h 85h 86h 87h 88h 89h 8Ah 8Bh 8Ch 8Dh 8Eh 8Fh 90h 91h 92h 93h 94h 95h 96h 97h 98h 99h 9Ah 9Bh 9Ch 9Dh 9Eh 9Fh A0h
File Address 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh 20h INDF(1) TMR0 PCL STATUS FSR PORTA PORTB PORTC PORTD(2) PORTE(2) PCLATH INTCON PIR1 PIR2 TMR1L TMR1H T1CON TMR2 T2CON SSPBUF SSPCON CCPR1L CCPR1H CCP1CON RCSTA TXREG RCREG CCPR2L CCPR2H CCP2CON ADRES ADCON0 INDF(1) OPTION PCL STATUS FSR TRISA TRISB TRISC TRISD(2) TRISE(2) PCLATH INTCON PIE1 PIE2 PCON
File Address 80h 81h 82h 83h 84h 85h 86h 87h 88h 89h 8Ah 8Bh 8Ch 8Dh 8Eh 8Fh 90h 91h 92h 93h 94h 95h 96h 97h 98h 99h 9Ah 9Bh 9Ch 9Dh 9Eh 9Fh A0h
PCLATH INTCON PIR1 TMR1L TMR1H T1CON TMR2 T2CON SSPBUF SSPCON CCPR1L CCPR1H CCP1CON
PCLATH INTCON PIE1 PCON
PR2 SSPADD SSPSTAT
PR2 SSPADD SSPSTAT
TXSTA SPBRG
ADRES ADCON0 General Purpose Register
ADCON1
ADCON1 General Purpose Register
BFh C0h
7Fh
General Purpose Register
General Purpose Register
FFh Bank 0 Bank 1
7Fh
FFh Bank 0 Bank 1
Note 1: 2: Unimplemented data memory locations, read as '0'. Not a physical register. These registers are not physically implemented on the PIC16C73/73A, read as '0'.
Unimplemented data memory locations, read as '0'. Note 1: Not a physical register.
DS30390B-J00 - page 24
(c) 1996 Microchip Technology Inc.
PIC16C7X
(c) 1996 Microchip Technology Inc.
DS30390B-J00 - page 25
PIC16C7X
DS30390B-J00 - page 26
(c) 1996 Microchip Technology Inc.
PIC16C7X
(c) 1996 Microchip Technology Inc.
DS30390B-J00 - page 27
PIC16C7X
DS30390B-J00 - page 28
(c) 1996 Microchip Technology Inc.
PIC16C7X
(c) 1996 Microchip Technology Inc.
DS30390B-J00 - page 29
PIC16C7X
R/W-0 IRP bit7
R/W-0 RP1
R/W-0 RP0
R-1 TO
R-1 PD
R/W-x Z
R/W-x DC
R/W-x C bit0
DS30390B-J00 - page 30
(c) 1996 Microchip Technology Inc.
PIC16C7X
R/W-1 RBPU bit7
R/W-1 INTEDG
R/W-1 T0CS
R/W-1 T0SE
R/W-1 PSA
R/W-1 PS2
R/W-1 PS1
R/W-1 PS0 bit0
(c) 1996 Microchip Technology Inc.
DS30390B-J00 - page 31
PIC16C7X
R/W-0 R/W-0 R/W-0 GIE bit7 ADIE T0IE
R/W-0 INTE
R/W-0 RBIE
R/W-0 T0IF INTF
R/W-0 RBIF bit0
R/W-x
DS30390B-J00 - page 32
(c) 1996 Microchip Technology Inc.
PIC16C7X
R/W-0 GIE bit7
R/W-0 PEIE
R/W-0 T0IE
R/W-0 R/W-0 R/W-0 INTE RBIE T0IF
R/W-0 INTF
R/W-x RBIF bit0
(c) 1996 Microchip Technology Inc.
DS30390B-J00 - page 33
PIC16C7X
U-0 bit7
R/W-0 ADIE
U-0 -
U-0 -
R/W-0 SSPIE
R/W-0 CCP1IE
R/W-0
R/W-0
TMR2IE TMR1IE bit0
DS30390B-J00 - page 34
(c) 1996 Microchip Technology Inc.
PIC16C7X
R/W-0 PSPIE bit7
(1)
R/W-0 ADIE
R/W-0 RCIE
R/W-0 TXIE
R/W-0 SSPIE
R/W-0 CCP1IE
R/W-0 TMR2IE
R/W-0 TMR1IE bit0
(c) 1996 Microchip Technology Inc.
DS30390B-J00 - page 35
PIC16C7X
U-0 bit7
R/W-0 ADIF
U-0 -
U-0 -
R/W-0 SSPIF
R/W-0 CCP1IF
R/W-0
R/W-0
TMR2IF TMR1IF bit0
DS30390B-J00 - page 36
(c) 1996 Microchip Technology Inc.
PIC16C7X
R/W-0 PSPIF bit7
(1)
R/W-0 ADIF
R-0 RCIF
R-0 TXIF
R/W-0 SSPIF
R/W-0 CCP1IF
R/W-0
R/W-0
TMR2IF TMR1IF bit0
(c) 1996 Microchip Technology Inc.
DS30390B-J00 - page 37
PIC16C7X
U-0 bit7
U-0 -
U-0 -
U-0 -
U-0 -
U-0 -
U-0
R/W-0
-
CCP2IE
bit0
DS30390B-J00 - page 38
(c) 1996 Microchip Technology Inc.
PIC16C7X
U-0 bit7
U-0 -
U-0 -
U-0 -
U-0 -
U-0 -
U-0
R/W-0
-
CCP2IF
bit0
(c) 1996 Microchip Technology Inc.
DS30390B-J00 - page 39
PIC16C7X
U-0 bit7
U-0 -
U-0 -
U-0
U-0 -
U-0 -
R/W-q
R/W-q
POR
BOR(1)
bit0
DS30390B-J00 - page 40
(c) 1996 Microchip Technology Inc.
PIC16C7X
PCH 12 PC 5 8 7
PCL 0 Instruction with PCL as Destination ALU result
PCLATH<4:0>
8
PCLATH PCH 12 PC 2 PCLATH<4:3> 11 Opcode <10:0> PCLATH 11 10 8 7 PCL 0 GOTO, CALL
(c) 1996 Microchip Technology Inc.
DS30390B-J00 - page 41
PIC16C7X
ORG BSF CALL
0x500 PCLATH,3 SUB1_P1 : : : ORG 0x900 SUB1_P1 : : : RETURN
;Select page1(800h-FFFh) ;Call subroutine in ;page1 (800h-FFFh)
;called subroutine ;page1 (800h-FFFh) ;return to Call subroutine ;in page 0 (000h-7FFh)
movlw movwf NEXT clrf incf btfss goto CONTINUE :
0x20 FSR INDF FSR,F FSR,4 NEXT
;initialize pointer ;to RAM ;clear INDF register ;inc pointer ;all done? ;no clear next ;yes continue
Direct Addressing
(1)RP1
Indirect Addressing
0 IRP(1) 7 FSR register 0
RP0
6
from opcode
bank select
location select 00 00h 01 10 11
bank select 00h
location select
not used Data Memory
7Fh
7Fh
Bank 0
Bank 1
Bank 2
Bank 3
For register file map detail see Figure 4-5, Figure 4-6, Figure 4-7, and Figure 4-8. Note 1: The RP1 and IRP bits are reserved, always maintain these bits clear.
DS30390B-J00 - page 42
(c) 1996 Microchip Technology Inc.
PIC16C7X
CLRF
BSF MOVLW
MOVWF
; ; ; STATUS, RP0 ; 0xCF ; ; ; TRISA ; ; ; ;
PORTA
Initialize PORTA by setting output data latches Select Bank 1 Value used to initialize data direction Set RA<3:0> as inputs RA<5:4> as outputs TRISA<7:6> are always read as 0'.
Data bus WR PORT
D CK
Q VDD Q P
Data Latch D WR TRIS CK Q Q Analog input mode N I/O pin
TRIS Latch
RD TRIS Q D EN RD PORT To A/D Converter
TTL input buffer
(c) 1996 Microchip Technology Inc.
DS30390B-J00 - page 43
PIC16C7X
Data Bus WR PORT
D
Q Q
CK
N VSS
RA4/T0CKI pin
Data Latch
D
Q Q
WR TRIS
CK
TRIS Latch
Schmitt Trigger input buffer
RD TRIS
Q
D EN EN
RD PORT TMR0 clock input Note: I/O pin has protection diodes to VSS only.
DS30390B-J00 - page 44
(c) 1996 Microchip Technology Inc.
PIC16C7X
CLRF
PORTB
BSF MOVLW
STATUS, RP0 0xCF
MOVWF
TRISB
; ; ; ; ; ; ; ; ; ;
Initialize PORTB by setting output data latches Select Bank 1 Value used to initialize data direction Set RB<3:0> as inputs RB<5:4> as outputs RB<7:6> as inputs
VDD
RBPU(2) Data Latch D Q CK TRIS Latch D Q WR TRIS CK I/O pin(1) weak P pull-up
VDD RBPU(2) Data Latch Data bus WR PORT D CK TRIS Latch D WR TRIS CK Q TTL Input Buffer ST Buffer Q I/O pin(1) weak pull-up
Data bus WR Port
TTL Input Buffer
RD TRIS Q RD Port D EN
RD TRIS
Latch Q D EN
RB0/INT Schmitt Trigger Buffer Note 1: I/O pins have diode protection to VDD and VSS. 2: TRISB = '1' enables weak pull-up if RBPU = '0' (OPTION<7>). RD Port
RD Port Set RBIF Q From other RB7:RB4 pins
D EN
RD Port
RB7:RB6 in serial programming mode
(c) 1996 Microchip Technology Inc.
DS30390B-J00 - page 45
PIC16C7X
DS30390B-J00 - page 46
(c) 1996 Microchip Technology Inc.
PIC16C7X
; ; ; BSF STATUS, RP0 ; MOVLW 0xCF ; ; ; MOVWF TRISC ; ; ; CLRF PORTC Initialize PORTC by setting output data latches Select Bank 1 Value used to initialize data direction Set RC<3:0> as inputs RC<5:4> as outputs RC<7:6> as inputs
PORT/PERIPHERAL Select(1) Peripheral Data-out 0 VDD Data Bus WR PORT 1
D Q Q
P
CK
Data Latch
D Q Q
I/O pin N VSS Schmitt Trigger
Q D EN EN
WR TRIS
CK
TRIS Latch RD TRIS
Peripheral OE(2)
RD PORT Peripheral input Note 1: Port/Peripheral select signal selects between port data and peripheral output. 2: Peripheral OE (output enable) is only activated if peripheral select is active. 3: I/O pins have diode protection to VDD and VSS.
RD PORT
(c) 1996 Microchip Technology Inc.
DS30390B-J00 - page 47
PIC16C7X
DS30390B-J00 - page 48
(c) 1996 Microchip Technology Inc.
PIC16C7X
Data Bus WR PORT
D
Q
I/O pin
CK Q
Data Latch
D
Q Q
WR TRIS
CK
TRIS Latch
Schmitt Trigger input buffer
RD TRIS
Q D EN EN
RD PORT
Note: I/O pins has protection diodes to VDD and VSS.
(c) 1996 Microchip Technology Inc.
DS30390B-J00 - page 49
PIC16C7X
DS30390B-J00 - page 50
(c) 1996 Microchip Technology Inc.
PIC16C7X
R-0 IBF bit7
R-0 OBF
R/W-0 IBOV
R/W-0 PSPMODE
U-0 -
R/W-1 TRISE2
R/W-1 TRISE1
R/W-1 TRISE0 bit0
(c) 1996 Microchip Technology Inc.
DS30390B-J00 - page 51
PIC16C7X
Data Bus WR PORT
D
Q
I/O pin
CK Q
Data Latch
D
Q Q
WR TRIS
CK
TRIS Latch
Schmitt Trigger input buffer
RD TRIS
Q
D EN EN
RD PORT
DS30390B-J00 - page 52
(c) 1996 Microchip Technology Inc.
PIC16C7X
;Initial PORT settings: PORTB<7:4> Inputs ; PORTB<3:0> Outputs ;PORTB<7:6> have external pull-ups and are ;not connected to other circuitry ; ; PORT latch PORT pins ; ----- ----BCF PORTB, 7 ; 01pp ppp 11pp ppp BCF PORTB, 6 ; 10pp ppp 11pp ppp BSF STATUS, RP0 ; BCF TRISB, 7 ; 10pp ppp 11pp ppp BCF TRISB, 6 ; 10pp ppp 10pp ppp ; ;Note that the user may have expected the ;pin values to be 00pp ppp. The 2nd BCF ;caused RB7 to be latched as the pin value ;(high).
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
PC Instruction fetched PC
MOVWF PORTB write to PORTB
PC + 1
MOVWF PORTB,W
PC + 2
NOP
PC + 3
NOP
RB7:RB0
Port pin sampled here TPD
Instruction executed
MOVWF PORTB write to PORTB
MOVWF PORTB,W
NOP
(c) 1996 Microchip Technology Inc.
DS30390B-J00 - page 53
PIC16C7X
Data bus WR Port
Q CK EN
D
RDx pin
D
Q
TTL RD Port One bit of PORTD Set interrupt flag PSPIF (PIR1<7>)
EN EN
Read
TTL RD
Chip Select Write
CS WR
Note: I/O pins has protection diodes to VDD and VSS.
DS30390B-J00 - page 54
(c) 1996 Microchip Technology Inc.
PIC16C7X
(c) 1996 Microchip Technology Inc.
DS30390B-J00 - page 55
PIC16C7X
NOTES:
DS30390B-J00 - page 56
(c) 1996 Microchip Technology Inc.
PIC16C7X
(c) 1996 Microchip Technology Inc.
DS30390B-J00 - page 57
PIC16C7X
NOTES:
DS30390B-J00 - page 58
(c) 1996 Microchip Technology Inc.
PIC16C7X
Data bus FOSC/4 0 1 1 RA4/T0CKI pin T0SE 3 PS2, PS1, PS0 T0CS PSA Set interrupt flag bit T0IF on overflow Programmable Prescaler 0 PSout Sync with Internal clocks (2 cycle delay) TMR0 PSout 8
Note 1: T0CS, T0SE, PSA, PS2:PS0 (OPTION<5:0>). 2: The prescaler is shared with Watchdog Timer (refer to Figure 7-6 for detailed block diagram).
PC (Program Counter) Instruction Fetch
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 PC-1 PC MOVWF TMR0 PC+1 MOVF TMR0,W PC+2 MOVF TMR0,W PC+3 MOVF TMR0,W PC+4 MOVF TMR0,W PC+5 MOVF TMR0,W PC+6
TMR0 Instruction Executed
T0
T0+1
T0+2
NT0
NT0
NT0
NT0+1
NT0+2
T
Write TMR0 executed
Read TMR0 reads NT0
Read TMR0 reads NT0
Read TMR0 reads NT0
Read TMR0 reads NT0 + 1
Read TMR0 reads NT0 + 2
(c) 1996 Microchip Technology Inc.
DS30390B-J00 - page 59
PIC16C7X
PC (Program Counter) Instruction Fetch TMR0
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 PC-1 PC MOVWF TMR0 PC+1 MOVF TMR0,W PC+2 MOVF TMR0,W PC+3 MOVF TMR0,W PC+4 MOVF TMR0,W PC+5 MOVF TMR0,W PC+6
T0
T0+1
NT0
NT0+1
PC
Instruction Execute
Write TMR0 executed
Read TMR0 reads NT0
Read TMR0 reads NT0
Read TMR0 reads NT0
Read TMR0 reads NT0
Read TMR0 reads NT0 + 1
Q1 OSC1 CLKOUT(3) Timer0 T0IF bit (INTCON<2>) GIE bit (INTCON<7>) INSTRUCTION FLOW PC Instruction fetched Instruction executed
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
FEh 1
FFh 1
00h
01h
02h
PC Inst (PC) Inst (PC-1)
PC +1 Inst (PC+1)
PC +1
0004h Inst (0004h)
0005h Inst (0005h) Inst (0004h)
Inst (PC)
Dummy cycle
Dummy cycle
Note 1: Interrupt flag bit T0IF is sampled here (every Q1). 2: Interrupt latency = 4Tcy where Tcy = instruction cycle time. 3: CLKOUT is available only in RC oscillator mode.
DS30390B-J00 - page 60
(c) 1996 Microchip Technology Inc.
PIC16C7X
Q1 Q2 Q3 Q4 External Clock Input or Prescaler output (2)
(1) (3)
Q1 Q2 Q3 Q4
Q1 Q2 Q3 Q4
Q1 Q2 Q3 Q4 Small pulse misses sampling
External Clock/Prescaler Output after sampling Increment Timer0 (Q4) Timer0 T0 T0 + 1 T0 + 2
Note 1: Delay from clock input change to Timer0 increment is 3Tosc to 7Tosc. (Duration of Q = Tosc). Therefore, the error in measuring the interval between two edges on Timer0 input = 4Tosc max. 2: External clock if no prescaler selected, Prescaler output otherwise. 3: The arrows indicate the points in time where sampling occurs.
(c) 1996 Microchip Technology Inc.
DS30390B-J00 - page 61
PIC16C7X
CLKOUT (=Fosc/4)
Data Bus 8 1 0 M U X SYNC 2 Cycles TMR0 reg
0 RA4/T0CKI pin 1 T0SE
M U X
T0CS
PSA
Set flag bit T0IF on Overflow
0 M U X
8-bit Prescaler 8 8 - to - 1MUX PS2:PS0
Watchdog Timer
1
PSA 0 MUX 1 PSA
WDT Enable bit
WDT Time-out Note: T0CS, T0SE, PSA, PS2:PS0 are (OPTION<5:0>).
DS30390B-J00 - page 62
(c) 1996 Microchip Technology Inc.
PIC16C7X
CLRWDT BSF MOVLW MOVWF BCF
;Clear WDT and ;prescaler STATUS, RP0 ;Bank 1 b'xxxx0xxx' ;Select TMR0, new ;prescale value and OPTION ;clock source STATUS, RP0 ;Bank 0
BCF CLRF BSF CLRWDT MOVLW MOVWF BCF
STATUS, RP0 TMR0 STATUS, RP0 b'xxxx1xxx' OPTION STATUS, RP0
;Bank 0 ;Clear TMR0 & Prescaler ;Bank 1 ;Clears WDT ;Select new prescale ;value & WDT ;Bank 0
(c) 1996 Microchip Technology Inc.
DS30390B-J00 - page 63
PIC16C7X
NOTES:
DS30390B-J00 - page 64
(c) 1996 Microchip Technology Inc.
PIC16C7X
U-0 bit7
U-0 -
R/W-0 T1CKPS1
R/W-0
R/W-0
R/W-0 T1SYNC
R/W-0
R/W-0
T1CKPS0 T1OSCEN
TMR1CS TMR1ON bit0
(c) 1996 Microchip Technology Inc.
DS30390B-J00 - page 65
PIC16C7X
Set flag bit TMR1IF on Overflow TMR1H
TMR1 TMR1L
0 1 TMR1ON on/off T1SYNC
Synchronized clock input
T1OSC RC0/T1OSO/T1CKI
(3)
1 T1OSCEN OSC/4 Enable Internal Oscillator(1) Clock Prescaler 1, 2, 4, 8 0 2 T1CKPS1:T1CKPS0 TMR1CS
Synchronize det SLEEP input
RC1/T1OSI/CCP2(2)
Note 1: When the T1OSCEN bit is cleared, the inverter and feedback resistor are turned off. This eliminates power drain. 2: The CCP2 module is not implemented in the PIC16C72. 3: For the PIC16C73 and PIC16C74, the Schmitt Trigger is not implemented in external clock mode.
DS30390B-J00 - page 66
(c) 1996 Microchip Technology Inc.
PIC16C7X
MOVF MOVWF MOVF MOVWF MOVF SUBWF BTFSC GOTO
TMR1H, W TMPH TMR1L, W TMPL TMR1H, W TMPH, W STATUS,Z CONTINUE
;Read high byte ; ;Read low byte ; ;Read high byte ;Sub 1st read ; with 2nd read ;Is result = 0 ;Good 16-bit read
; ; TMR1L may have rolled over between the read ; of the high and low bytes. Reading the high ; and low bytes now will read a good value. ; MOVF TMR1H, W ;Read high byte MOVWF TMPH ; MOVF TMR1L, W ;Read low byte MOVWF TMPL ; ; Re-enable the Interrupt (if required) CONTINUE ;Continue with ;your code
Osc Type Freq LP 32 kHz(1) 100 kHz 200 kHz
C1 15 pF 15 pF 0 - 15 pF
C2 15 pF 15 pF 0 - 15 pF
1
V DD
4.5V
C1 = C2
30pF
Crystals Tested: 32.768 kHz Epson C-001R32.768K-A 100 kHz 200 kHz Epson C-2 100.00 KC-P STD XTL 200.000 kHz
20 PPM 20 PPM 20 PPM
(c) 1996 Microchip Technology Inc.
DS30390B-J00 - page 67
PIC16C7X
DS30390B-J00 - page 68
(c) 1996 Microchip Technology Inc.
PIC16C7X
Sets flag bit TMR2IF
TMR2 output (1) Reset Prescaler 1:1, 1:4, 1:16 2
TMR2 reg Comparator
OSC/4
Postscaler 1:1 to 1:16 4
EQ
PR2 reg
Note 1: TMR2 register output can be software selected by the SSP Module as a baud clock.
(c) 1996 Microchip Technology Inc.
DS30390B-J00 - page 69
PIC16C7X
U-0
bit7
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
T2CKPS0 bit0
TOUTPS3 TOUTPS2 TOUTPS1
TOUTPS0 TMR2ON T2CKPS1
DS30390B-J00 - page 70
(c) 1996 Microchip Technology Inc.
PIC16C7X
(c) 1996 Microchip Technology Inc.
DS30390B-J00 - page 71
PIC16C7X
U-0 bit7
U-0 -
R/W-0 CCPxX
R/W-0 CCPxY
R/W-0 CCPxM3
R/W-0 CCPxM2
R/W-0 CCPxM1
R/W-0 CCPxM0 bit0
DS30390B-J00 - page 72
(c) 1996 Microchip Technology Inc.
PIC16C7X
CLRF CCP1CON MOVLW NEW_CAPT_PS
MOVWF CCP1CON
;Turn CCP module off ;Load the W reg with ; the new prescaler ; mode value and CCP ON ;Load CCP1CON with this ; value
Prescaler / 1, 4, 16 RC2/CCP1 Pin and edge detect
Set flag bit CCP1IF (PIR1<2>)
CCPR1H Capture Enable TMR1H CCP1CON<3:0> Q's
CCPR1L
TMR1L
Special Event(1)
Trigger
Set flag bit CCP1IF (PIR1<2>) CCPR1H CCPR1L Comparator TMR1H TMR1L
Q S Output Logic match RC2/CCP1 R Pin TRISC<2> Output Enable CCP1CON<3:0> Mode Select
Note 1: For CCP1 (if enabled), reset Timer1.
For CCP2 (if enabled), reset Timer1, and set bit GO/ DONE (ADCON0<2>), which starts an A/D conversion.
(c) 1996 Microchip Technology Inc.
DS30390B-J00 - page 73
PIC16C7X
Duty cycle registers CCPRxL
CCPxCON<5:4>
CCPRxH (Slave)
Comparator
R
Q RCy/CCPx Pin
TMR2
(Note 1) S
Comparator Clear Timer, CCP1 pin and latch Duty Cycle
TRISC
PR2
Note 1: 8-bit timer is concatenated with 2-bit internal Q clock or 2-bits of the prescaler to create 10-bit time-base.
DS30390B-J00 - page 74
(c) 1996 Microchip Technology Inc.
PIC16C7X
(c) 1996 Microchip Technology Inc.
DS30390B-J00 - page 75
PIC16C7X
DS30390B-J00 - page 76
(c) 1996 Microchip Technology Inc.
PIC16C7X
U-0 bit7
U-0 -
R-0 D/A
R-0 P
R-0 S
R-0 R/W
R-0 UA
R-0 BF bit0
R= W= U= -n =
(c) 1996 Microchip Technology Inc.
DS30390B-J00 - page 77
PIC16C7X
R/W-0 WCOL bit7
R/W-0 SSPOV
R/W-0 SSPEN
R/W-0 CKP
R/W-0 SSPM3
R/W-0 SSPM2
R/W-0 SSPM1
R/W-0 SSPM0 bit0 R= W= U= -n =
DS30390B-J00 - page 78
(c) 1996 Microchip Technology Inc.
PIC16C7X
BSF BTFSS STATUS,RP0 SSPSTAT,BF ;Specify Bank 1 ;Has data been ;received ;(transmit ;complete)? ;No ;Specify Bank 0 ;W reg = contents ; of SSPBUF ;Save in user RAM ;W reg = contents ; of TXDATA ;New data to xmit
LOOP
GOTO BCF MOVF
LOOP STATUS,RP0 SSPBUF,W
MOVWF RXDATA MOVF TXDATA,W MOVWF SSPBUF
Internal data bus Read SSPBUF reg Write
SSPSR reg SDI bit0 shift clock
SDO SS Control Enable SS Edge Select 2 Clock Select SSPM3:SSPM0 4 Edge Select SCK
TMR2 output 2 Prescaler TCY 4, 16, 64
Data from TX/RX in SSPSR TRISC<3>
(c) 1996 Microchip Technology Inc.
DS30390B-J00 - page 79
PIC16C7X
SPI Master (SSPM3:SSPM0 = 00xxb) SDO SDI
SPI Slave (SSPM3:SSPM0 = 010xb)
Serial Input Buffer (SSPBUF)
Serial Input Buffer (SSPBUF)
Shift Register (SSPSR) MSb LSb
SDI
SDO
Shift Register (SSPSR) MSb LSb
Serial Clock
SCK PROCESSOR 1 SCK PROCESSOR 2
DS30390B-J00 - page 80
(c) 1996 Microchip Technology Inc.
PIC16C7X
SCK (CKP = 0) SCK (CKP = 1)
SDO
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
SDI bit7 SSPIF Interrupt flag bit0
SS SCK (CKP = 0) SCK (CKP = 1)
SDO
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
SDI bit7 SSPIF bit0
(c) 1996 Microchip Technology Inc.
DS30390B-J00 - page 81
PIC16C7X
DS30390B-J00 - page 82
(c) 1996 Microchip Technology Inc.
PIC16C7X
SDA
SCL
S Change of Data Allowed Change of Data Allowed
P Stop Condition
Start Condition
(c) 1996 Microchip Technology Inc.
DS30390B-J00 - page 83
PIC16C7X
MSb S
slave address
LSb R/W ACK
Sent by Slave
Data Output by Transmitter Data Output by Receiver SCL from Master S Start Condition not acknowledge acknowledge 1 2 8 9
S R/W ACK
Start Condition Read/Write pulse Acknowledge
Clock Pulse for Acknowledgment
S 1 1 1 1 0 A9 A8 R/W ACK
A7 A6 A5 A4 A3 A2 A1 A0 ACK sent by slave = 0 for write
S R/W ACK
- Start Condition - Read/Write Pulse - Acknowledge
SDA MSB acknowledgment signal from receiver byte complete interrupt with receiver acknowledgment signal from receiver
clock line held low while interrupts are serviced SCL S Start Condition 1 2 Address 7 8 R/W 9 ACK Wait State 1 2 Data 3*8 9 ACK P Stop Condition
DS30390B-J00 - page 84
(c) 1996 Microchip Technology Inc.
PIC16C7X
For 7-bit address: S Slave Address R/W A Data A Data A/A P data transferred (n bytes - acknowledge) A master transmitter addresses a slave receiver with a 7-bit address. The transfer direction is not changed. From master to slave From slave to master '0' (write)
For 10-bit address: S Slave Address R/W A1 Slave Address A2 First 7 bits Second byte (write) Data A Data A/A P
A = acknowledge (SDA low) A = not acknowledge (SDA high) S = Start Condition P = Stop Condition
A master transmitter addresses a slave receiver with a 10-bit address.
For 7-bit address: S Slave Address R/W A Data A Data A P data transferred (n bytes - acknowledge) A master reads a slave immediately after the first byte. '1' (read)
For 10-bit address: S Slave Address R/W A1 Slave Address A2 First 7 bits Second byte (write) Sr Slave Address R/W A3 Data A First 7 bits Data A P
From master to slave From slave to master
A = acknowledge (SDA low) A = not acknowledge (SDA high) S = Start Condition P = Stop Condition
(read) A master transmitter addresses a slave receiver with a 10-bit address.
(read or write) (n bytes + acknowledge) S Slave Address R/W A Data A/A Sr Slave Address R/W A Data A/A P (read) Sr = repeated Start Condition (write) Direction of transfer may change at this point
Transfer direction of data and acknowledgment bits depends on R/W bits. Combined format: Sr Slave Address R/W A Slave Address A Data A First 7 bits Second byte (write) Data A/A Sr Slave Address R/W A Data A First 7 bits (read) Data A P
Combined format - A master addresses a slave with a 10-bit address, then transmits data to this slave and reads data from this slave. From master to slave From slave to master A = acknowledge (SDA low) A = not acknowledge (SDA high) S = Start Condition P = Stop Condition
(c) 1996 Microchip Technology Inc.
DS30390B-J00 - page 85
PIC16C7X
transmitter 1 loses arbitration DATA 1 SDA DATA 1 DATA 2
CLK 1 wait state start counting HIGH period
SDA SCL
CLK 2 counter reset
SCL
DS30390B-J00 - page 86
(c) 1996 Microchip Technology Inc.
PIC16C7X
Internal data bus Read SSPBUF reg shift clock SSPSR reg RC4/ SDI/ SDA MSb LSb Addr Match Write
RC3/SCK/SCL
Match detect
SSPADD reg Start and Stop bit detect Set, Reset S, P bits (SSPSTAT reg)
(c) 1996 Microchip Technology Inc.
DS30390B-J00 - page 87
PIC16C7X
DS30390B-J00 - page 88
(c) 1996 Microchip Technology Inc.
PIC16C7X
SDA
Receiving Address Receiving Data R/W=0 Receiving Data ACK ACK ACK A7 A6 A5 A4 A3 A2 A1 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 S 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 P
SCL
SSPIF (PIR1<3>)
Bus Master terminates transfer Cleared in software SSPBUF register is read
BF (SSPSTAT<0>)
SSPOV (SSPCON<6>) Bit SSPOV is set because the SSPBUF register is still full. ACK is not sent.
(c) 1996 Microchip Technology Inc.
DS30390B-J00 - page 89
PIC16C7X
Receiving Address SDA A7 A6 A5 A4 A3 A2 A1
R/W = 1 ACK D7 D6 D5 D4
Transmitting Data D3 D2 D1 D0
ACK
SCL
S
1 2 Data in sampled
3
4
5
6
7
8
9
1 SCL held low while CPU responds to SSPIF
2
3
4
5
6
7
8
9
P
SSPIF (PIR1<3>) BF (SSPSTAT<0>) cleared in software SSPBUF is written in software CKP (SSPCON<4>) Set bit after writing to SSPBUF From SSP interrupt service routine
DS30390B-J00 - page 90
(c) 1996 Microchip Technology Inc.
PIC16C7X
(c) 1996 Microchip Technology Inc.
DS30390B-J00 - page 91
PIC16C7X
IDLE_MODE (7-bit): if (Addr_match ) { Set interrupt; { } else if (R/W = 0) set RCV_MODE; } RCV_MODE: if ((SSPBUF=Full) OR (SSPOV = 1)) { } else { } Receive 8-bits in SSPSR; Set interrupt; XMIT_MODE: While ((SSPBUF = Empty) AND (CKP=0)) Hold SCL Low; Send byte; Set interrupt; if ( ACK Received = 1) { } else if ( ACK Received = 0) IDLE_MODE (10-Bit): If (High_byte_addr_match AND (R/W = 0)) { PRIOR_ADDR_MATCH = FALSE; Set interrupt; if ((SSPBUF = Full) OR ((SSPOV = 1)) { } else { Set UA = 1; Send ACK = 0; While (SSPADD not updated) Hold SCL low; Clear UA = 0; Receive Low_addr_byte; Set interrupt; Set UA = 1; If (Low_byte_addr_match) { PRIOR_ADDR_MATCH = TRUE; Send ACK = 0; while (SSPADD not updated) Hold SCL low; Clear UA = 0; Set RCV_MODE; } } } else if (High_byte_addr_match AND (R/W = 1) { if (PRIOR_ADDR_MATCH) { send ACK = 0; set XMIT_MODE; } else PRIOR_ADDR_MATCH = FALSE; } Set SSPOV; Do not acknowledge; Go back to XMIT_MODE; End of transmission; Go back to IDLE_MODE; transfer SSPSR SSPBUF; send ACK = 0; Set SSPOV; Do not acknowledge; Send ACK = 0; set XMIT_MODE; if (R/W = 1)
DS30390B-J00 - page 92
(c) 1996 Microchip Technology Inc.
PIC16C7X
R/W-0 CSRC bit7 bit 7:
R/W-0 TX9
R/W-0 TXEN
R/W-0 SYNC
U-0 -
R/W-0 BRGH
R-1 TRMT
R/W-0 TX9D bit0
bit 6
bit 5
bit 4
bit 3 bit 2
bit 1
bit 0
(c) 1996 Microchip Technology Inc.
DS30390B-J00 - page 93
PIC16C7X
R/W-0 SPEN bit7
R/W-0 RX9
R/W-0 SREN
R/W-0 CREN
U-0 -
R-0 FERR
R-0 OERR
R-x RX9D bit0
bit 7:
bit 6:
bit 5:
bit 4:
bit 3: bit 2:
bit 1:
bit 0:
DS30390B-J00 - page 94
(c) 1996 Microchip Technology Inc.
PIC16C7X
Desired Baud rate = 9600 = X = Fosc / (64 (X + 1))
16000000 /(64 (X + 1)) e25.042u = 25 16000000 / (64 (25 + 1))
Calculated Baud Rate = = Error = 9615
(Calculated Baud Rate - Desired Baud Rate) Desired Baud Rate (9615 - 9600) / 9600 0.16%
= =
x=
,-=
(c) 1996 Microchip Technology Inc.
DS30390B-J00 - page 95
PIC16C7X
DS30390B-J00 - page 96
(c) 1996 Microchip Technology Inc.
PIC16C7X
(c) 1996 Microchip Technology Inc.
DS30390B-J00 - page 97
PIC16C7X
RX (RC7/RX/DT pin) baud CLK x16 CLK 1 2 3 4 5 6 7 8
Start bit Baud CLK for all but start bit
Bit0
9
10
11
12
13
14
15
16
1
2
3
Samples
RX pin Start Bit
bit0
bit1
baud clk First falling edge after RX pin goes low Second rising edge x4 clk 1 Q2, Q4 clk 2 3 4 1 2 3 4 1 2
Samples
Samples
Samples
RX pin Start Bit Baud clk for all but start bit First falling edge after RX pin goes low Second rising edge x4 clk 1 Q2, Q4 clk 2 3 4 bit0
baud clk
Samples
DS30390B-J00 - page 98
(c) 1996 Microchip Technology Inc.
PIC16C7X
Data Bus TXIF TXIE MSb (8) Interrupt TXEN Baud Rate CLK TRMT SPBRG Baud Rate Generator TX9 TX9D SPEN *** TSR register TXREG register 8 LSb 0 Pin Buffer and Control RC6/TX/CK pin
(c) 1996 Microchip Technology Inc.
DS30390B-J00 - page 99
PIC16C7X
Write to TXREG BRG output (shift clock) RC6/TX/CK (pin) TXIF bit (Transmit buffer reg. empty flag) Word 1
Start Bit
Bit 0
Bit 1 WORD 1
Bit 7/8
Stop Bit
TRMT bit (Transmit shift reg. empty flag)
WORD 1 Transmit Shift Reg
Write to TXREG BRG output (shift clock) RC6/TX/CK (pin) TXIF bit (interrupt reg. flag) Word 1 Word 2
Start Bit
Bit 0
Bit 1 WORD 1
Bit 7/8
Stop Bit
Start Bit WORD 2
Bit 0
TRMT bit (Transmit shift reg. empty flag)
WORD 1 Transmit Shift Reg.
WORD 2 Transmit Shift Reg.
Note: This timing diagram shows two consecutive transmissions.
DS30390B-J00 - page 100
(c) 1996 Microchip Technology Inc.
PIC16C7X
x64 Baud Rate CLK CREN SPBRG / 64 or / 16
OERR
FERR
MSb Stop (8) 7
RSR register *** 1
LSb 0 Start
Baud Rate Generator RC7/RX/DT Pin Buffer and Control Data Recovery
RX9
SPEN
RX9D
RCREG register FIFO
8 Interrupt RCIF RCIE Data Bus
RX (pin) Rcv shift reg Rcv buffer reg Read Rcv buffer reg RCREG RCIF (interrupt flag) OERR bit CREN
Start bit
bit0
bit1
bit7/8 Stop bit
Start bit
bit0
bit7/8
Stop bit
Start bit
bit7/8
Stop bit
WORD 1 RCREG
WORD 2 RCREG
Note: This timing diagram shows three words appearing on the RX input. The RCREG (receive buffer) is read after the third word, causing the OERR (overrun) bit to be set.
(c) 1996 Microchip Technology Inc.
DS30390B-J00 - page 101
PIC16C7X
DS30390B-J00 - page 102
(c) 1996 Microchip Technology Inc.
PIC16C7X
(c) 1996 Microchip Technology Inc.
DS30390B-J00 - page 103
PIC16C7X
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
RC7/RX/DT pin RC6/TX/CK pin Write to TXREG reg
Write word1
Bit 0
Bit 1 WORD 1
Bit 2
Bit 7
Bit 0
Bit 1 WORD 2
Bit 7
Write word2
TXIF bit
(Interrupt flag) TRMT TRMT bit
TXEN bit
'1'
Note: Sync master mode; SPBRG = '0'. Continuous transmission of two 8-bit words
'1'
RC7/RX/DT pin RC6/TX/CK pin Write to TXREG reg
bit0
bit1
bit2
bit6
bit7
TXIF bit
TRMT bit
DS30390B-J00 - page 104
(c) 1996 Microchip Technology Inc.
PIC16C7X
(c) 1996 Microchip Technology Inc.
DS30390B-J00 - page 105
PIC16C7X
Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
DT pin CK pin Write to SREN bit SREN bit CREN bit '0' RCIF bit (interrupt) Read RXREG
bit0
bit1
bit2
bit3
bit4
bit5
bit6
bit7
'0'
Note: Timing diagram demonstrates SYNC master mode with SREN = '1' and BRG = '0'.
DS30390B-J00 - page 106
(c) 1996 Microchip Technology Inc.
PIC16C7X
(c) 1996 Microchip Technology Inc.
DS30390B-J00 - page 107
PIC16C7X
DS30390B-J00 - page 108
(c) 1996 Microchip Technology Inc.
PIC16C7X
R/W-0 ADCS1
R/W-0 ADCS0
U-0 - (1)
R/W-0 CHS1
R/W-0
R/W-0
R/W-0 ADIF
R/W-0 ADON
CHS0 GO/DONE
bit7
bit0
(c) 1996 Microchip Technology Inc.
DS30390B-J00-page 109
PIC16C7X
R/W-0 ADCS1 bit7
R/W-0 ADCS0
R/W-0 CHS2
R/W-0 CHS1
R/W-0 CHS0
R/W-0 GO/DONE
U-0 -
R/W-0 ADON bit0
U-0 bit7 bit 7-2:
U-0 -
U-0 -
U-0 -
U-0 -
U-0 -
R/W-0 PCFG1
R/W-0 PCFG0 bit0
bit 1-0: PCFG1:PCFG0: PCFG1:PCFG0 00 01 10 11 A= D= RA1 & RA0 A A A D RA2 A A D D RA3 A VREF D D VREF VDD RA3 VDD VDD
DS30390B-J00-page 110
(c) 1996 Microchip Technology Inc.
PIC16C7X
U-0 bit7 bit 7-3: bit 2-0: PCFG2:PCFG0: PCFG2:PCFG0 000 001 010 011 100 101 11x A= D= RA0 A A A A A A D RA1 A A A A A A D RA2 A A A A D D D RA5 A A A A D D D RA3 A VREF A VREF A VREF D RE0 A A D D D D D RE1 A A D D D D D RE2 A A D D D D D VREF VDD RA3 VDD RA3 VDD RA3 U-0 U-0 U-0 U-0 R/W-0 PCFG2 R/W-0 PCFG1 R/W-0 PCFG0 bit0
(c) 1996 Microchip Technology Inc.
DS30390B-J00-page 111
PIC16C7X
CHS1:CHS0
11 VIN (Input voltage) A/D Converter 10 01 00 VDD VREF (Reference voltage) PCFG1:PCFG0
00 or 10 or 11 01
RA3/AN3/VREF RA2/AN2 RA1/AN1 RA0/AN0
DS30390B-J00-page 112
(c) 1996 Microchip Technology Inc.
PIC16C7X
CHS2:CHS0
111 RE2/AN7(1) 110 RE1/AN6(1) 101 RE0/AN5(1) 100 RA5/AN4 011 VIN (Input voltage) A/D Converter 010 001 000 VDD VREF (Reference voltage) PCFG2:PCFG0
000 or 010 or 100 001 or 011 or 101
RA3/AN3/VREF RA2/AN2 RA1/AN1 RA0/AN0
(c) 1996 Microchip Technology Inc.
DS30390B-J00-page 113
PIC16C7X
TACQ = Amplifier Settling Time + Holding Capacitor Charging Time + Temperature Coefficient TACQ = 5 s + Tc + [(Temp - 25 Tc = Vhold = (Vref - (Vref/512)) x (1 - e (-Tc/CHOLD(RIC + RSS + RS)))
Tc = -(51.2 pF)(1 kW + Rss + Rs) ln(1/511)
)(0.05 ms/
)]
-Chold (RIC + Rss + Rs) ln(1/512) -51.2 pF (1 k + 7 k + 10 k) ln(0.0020) -51.2 pF (18 k) ln(0.0020) -0.921 s (-6.2146) 5.724 s
TACQ = 5 s + 5.724 s + [(50 10.724 s + 1.25 s Rs = 10 k 1/2 LSb error Vdd = 5V Rss = 7 k Temp (system max.) = 50C Vhold = 0 @ t = 0 11.974 s
- 25
)(0.05 s/ )]
VDD Rs VT=0.6V
RIC
1k
Sampling Switch SS Rss
VA
CPIN 5nF
VT=0.6V
I leakage 500 nA
CHOLD = DAC capacitance = 51.2pF VSS
6V 5V
VDD 4V
3V 2V
5 6 7 8 9 1011 Sampling Switch
DS30390B-J00-page 114
(c) 1996 Microchip Technology Inc.
PIC16C7X
(c) 1996 Microchip Technology Inc.
DS30390B-J00-page 115
PIC16C7X
BSF CLRF BCF MOVLW MOVWF BSF BSF ; ; ; ;
STATUS,RP0 ADCON1 STATUS,RP0 0xC1 ADCON0 INTCON,ADIE INTCON,GIE
; ; ; ; ; ; ;
Select Page 1 Configure A/D inputs Select Page 0 RC Clock, A/D is on, Channel 0 is selected Enable A/D Interrupt Enable all interrupts
Ensure that the required sampling time for the selected input channel has elapsed. Then the conversion may be started. BSF : : ADCON0,GO ; Start A/D Conversion ; The ADIF bit will be set and the GO/DONE bit ; is cleared upon completion of the A/D Conversion.
BSF CLRF BSF BCF MOVLW MOVWF BCF BSF BSF ; ; ; ;
STATUS,RP0 ADCON1 PIE1,ADIE STATUS,RP0 0xC1 ADCON0 PIR1,ADIF INTCON,PEIE INTCON,GIE
; ; ; ; ; ; ; ; ;
Select Page 1 Configure A/D inputs Enable A/D interrupts Select Page 0 RC Clock, A/D is on, Channel 0 is selected Clear A/D interrupt flag bit Enable peripheral interrupts Enable all interrupts
Ensure that the required sampling time for the selected input channel has elapsed. Then the conversion may be started. BSF : : ADCON0,GO ; Start A/D Conversion ; The ADIF bit will be set and the GO/DONE bit ; is cleared upon completion of the A/D Conversion.
DS30390B-J00-page 116
(c) 1996 Microchip Technology Inc.
PIC16C7X
= 2Tad + N TAD + (8 - N)(2Tosc) :N=
Freq. (MHz)(1) 4-bit 8-bit
TAD TOSC 2Tad + N TAD + (8 - N)(2Tosc)
20 16 20 16 20 16
1.6 s 2.0 s 50 ns 62.5 ns 10 s 12.5 s
1.6 s 2.0 s 50 ns 62.5 ns 16 s 20 s
(c) 1996 Microchip Technology Inc.
DS30390B-J00-page 117
PIC16C7X
DS30390B-J00-page 118
(c) 1996 Microchip Technology Inc.
PIC16C7X
FFh Digital code output FBh
04h 03h 02h 01h 256LSb (full scale) 255LSb 0.5LSb 1LSb 2LSb 3LSb 4LSb 00h
Analog input voltage
ADON =0
ADON =0?
Acquire Selected Channel
GO = 0?
Yes
No
A/D Clock = RC ?
Yes
Start of A/D Conversion Delayed 1 Instruction Cycle
SLEEP Yes Instruction?
Finish Conversion GO = 0 ADIF = 1
No
Device in Yes SLEEP? Abort Conversion GO = 0 ADIF = 0
No
Finish Conversion GO = 0 ADIF = 1 Wake-up Yes From Sleep? Wait 2 TAD
No
Finish Conversion GO = 0 ADIF = 1 SLEEP Power-down A/D Wait 2 TAD
No
Stay in Sleep Power-down A/D
Wait 2 TAD
(c) 1996 Microchip Technology Inc.
DS30390B-J00-page 119
PIC16C7X
DS30390B-J00-page 120
(c) 1996 Microchip Technology Inc.
PIC16C7X
bit13
-
-
-
-
-
-
-
-
CP0
PWRTE
WDTE
F0SC1
F0SC0 bit0
Register: Address
CONFIG 2007h
bit 13-5: bit 4:
bit 3:
bit 2:
bit 1-0:
(c) 1996 Microchip Technology Inc.
DS30390B-J00-page 121
PIC16C7X
CP0 bit13
CP0
CP0 CP0 CP0 CP0
CP0 BODEN CP0 CP0 PWRTE
WDTE F0SC1 F0SC0 bit0
Register: Address
CONFIG 2007h
bit 13-7: 5-4: bit 6:
CP0:
BODEN:
bit 3:
PWRTE:
bit 2:
WDTE:
bit 1-0:
FOSC1:FOSC0:
PWRTE
PWRT
bit13
-
-
-
-
-
-
-
CP1
CP0
PWRTE WDTE F0SC1 F0SC0 bit0
Register: Address
CONFIG 2007h
bit 13-5: bit 4:
CP1:CP0:
bit 3:
PWRTE:
bit 2:
WDTE:
bit 1-0:
FOSC1:FOSC0:
DS30390B-J00-page 122
(c) 1996 Microchip Technology Inc.
PIC16C7X
CP1
CP0
CP1
CP0
CP1
CP0
-
BODEN CP1 CP0 PWRTE
WDTE
F0SC1 F0SC0
bit3 bit 13-8 5-4: CP1:CP0:
bit0
Register: CONFIG Address 2007h
bit 7: bit 6:
: BODEN:
bit 3:
PWRTE:
bit 2:
WDTE:
bit 1-0:
FOSC1:FOSC0:
OSC1 C1 XTAL OSC2 RF
(2)
To internal logic SLEEP PIC16CXX To internal logic
RF C2 Note1
(2)
Clock from ext. system Open
OSC1
PIC16CXX
OSC2
(c) 1996 Microchip Technology Inc.
DS30390B-J00-page 123
PIC16C7X
DS30390B-J00-page 124
(c) 1996 Microchip Technology Inc.
PIC16C7X
+5V
4.7k 74AS04
74AS04
PIC16CXX
CLKIN
10k XTAL 10k
20pF
20pF
VDD Rext Cext Vss OSC1
Internal clock PIC16CXX
330k
74AS04
330k
74AS04 74AS04
To Other Devices PIC16CXX
OSC2/CLKOUT Fosc/4
0.1uF XTAL
CLKIN
(c) 1996 Microchip Technology Inc.
DS30390B-J00-page 125
PIC16C7X
External Reset MCLR WDT Module VDD rise detect VDD Brown-out Reset(2) BODEN OST/PWRT OST OSC1 10-bit Ripple counter R Q Chip_Reset S WDT SLEEP Time-out Reset Power-on Reset
On-chip(1) RC OSC
PWRT 10-bit Ripple counter
Enable PWRT Enable OST
DS30390B-J00-page 126
(c) 1996 Microchip Technology Inc.
PIC16C7X
VDD BVDD Max. BVDD Min. Internal Reset 72ms
VDD BVDD Max. BVDD Min. Internal Reset <72ms 72ms
VDD BVDD Max. BVDD Min. Internal Reset 72ms
(c) 1996 Microchip Technology Inc.
DS30390B-J00-page 127
PIC16C7X
DS30390B-J00-page 128
(c) 1996 Microchip Technology Inc.
PIC16C7X
(c) 1996 Microchip Technology Inc.
DS30390B-J00-page 129
PIC16C7X
DS30390B-J00-page 130
(c) 1996 Microchip Technology Inc.
PIC16C7X
VDD MCLR
INTERNAL POR TPWRT
PWRT TIME-OUT OST TIME-OUT
TOST
INTERNAL RESET
VDD MCLR
INTERNAL POR TPWRT
PWRT TIME-OUT OST TIME-OUT
TOST
INTERNAL RESET
VDD MCLR
INTERNAL POR TPWRT
PWRT TIME-OUT OST TIME-OUT
TOST
INTERNAL RESET
(c) 1996 Microchip Technology Inc.
DS30390B-J00-page 131
PIC16C7X
VDD VDD D R R1 MCLR 10k C PIC16CXX 40k PIC16CXX MCLR 33k VDD
VDD R1 Q1
VDD
MCLR R2 40k PIC16CXX
V DD *
R1 = 0 .7 V R1+ R2
DS30390B-J00-page 132
(c) 1996 Microchip Technology Inc.
PIC16C7X
(c) 1996 Microchip Technology Inc.
DS30390B-J00 - page 133
PIC16C7X
T0IF T0IE INTF INTE
Wakeup (If in SLEEP mode)
Interrupt to CPU RBIF RBIE ADIF ADIE GIE
TMR1F TMR1E
T0IE T0IF TMR2IF TMR2IE INTE INTF RBIE RBIF ADIF ADIE PEIE PEIF GIE
Wakeup (If in SLEEP mode)
Interrupt to CPU
CCP1IF CCP1IE SSPIF SSPIE
TMR1F TMR1E TMR2IF TMR2IE CCP1IF CCP1IE CCP2IF CCP2IE ADIF ADIE TXIF TXIE RCIF RCIE SSPIF SSPIE
T0IE T0IF INTE INTF RBIE RBIF PEIE PEIF GIE
Wakeup (If in SLEEP mode)
Interrupt to CPU
DS30390B-J00 - page 134
(c) 1996 Microchip Technology Inc.
PIC16C7X
TMR1F TMR1E TMR2IF TMR2IE CCP1IF CCP1IE CCP2IF CCP2IE ADIF ADIE TXIF TXIE RCIF RCIE SSPIF SSPIE PSPIF PSPIE
T0IE T0IF INTE INTF RBIE RBIF PEIE PEIF GIE
Wakeup (If in SLEEP mode)
Interrupt to CPU
Q1 OSC1 CLKOUT 3
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
4 INT pin 1 INTF flag (INTCON<1>) GIE bit (INTCON<7>) INSTRUCTION FLOW PC Instruction fetched Instruction executed PC Inst(PC) Inst(PC-1) PC+1 Inst(PC+1) Inst(PC) PC+1 Dummy Cycle 0004h Inst(0004h) Dummy Cycle 0005h Inst(0005h) Inst(0004h) 1 5 Interrupt Latency 2
(c) 1996 Microchip Technology Inc.
DS30390B-J00 - page 135
PIC16C7X
MOVWF SWAPF CLRF MOVWF MOVF MOVWF CLRF MOVF MOVWF : : : MOVF MOVWF MOVF MOVWF SWAPF MOVWF SWAPF SWAPF
W_TEMP STATUS,W STATUS STATUS_TEMP PCLATH, W PCLATH_TEMP PCLATH FSR, W FSR_TEMP (ISR) FSR_TEMP, W FSR PCLATH_TEMP, W PCLATH STATUS_TEMP,W STATUS W_TEMP,F W_TEMP,W
; Copy W to TEMP register, could be bank one or zero ; Swap status to be saved into W ; bank 0, regardless of current bank, Clears IRP,RP1,RP0 ; Save status to bank zero STATUS_TEMP register ; Only required if using pages 1, 2 and/or 3 ; Save PCLATH into W ; Page zero, regardless of current page ; Copy FSR to W ; Copy FSR from W to FSR_TEMP
; Restore FSR ; Move W to FSR ; Restore PCLATH ; Move W into PCLATH ; Swap STATUS_TEMP register into W ; (sets bank to original state) ; Move W into STATUS register ; Swap W_TEMP ; Swap W_TEMP into W
DS30390B-J00 - page 136
(c) 1996 Microchip Technology Inc.
PIC16C7X
From TMR0 Clock Source (Figure 7-6) 0 Postscaler WDT Timer 1 M U X 8 8 - to - 1 MUX PSA To TMR0 (Figure 7-6) 0 MUX 1 PSA PS2:PS0
WDT Enable Bit
WDT Time-out
(c) 1996 Microchip Technology Inc.
DS30390B-J00 - page 137
PIC16C7X
DS30390B-J00 - page 138
(c) 1996 Microchip Technology Inc.
PIC16C7X
Q1 OSC1 CLKOUT 3 INT pin INTF flag (INTCON<1>) GIE bit (INTCON<7>) INSTRUCTION FLOW PC Instruction fetched Instruction executed PC Inst(PC) = SLEEP Inst(PC-1) PC+1 Inst(PC+1) SLEEP PC+2 PC+2 Inst(PC+2) PC+2 0004h Inst(0004h) 0005h Inst(0005h) Processor in SLEEP Interrupt Latency (Note2) TOST(2) Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Inst(PC+1)
Dummy cycle
Dummy cycle
Inst(0004h)
External Connection Signals +5V 0V VPP CLK Data I/O
To Normal Connections PIC16XX VDD VSS MCLR/VPP RB6 RB7
VDD To Normal Connections
(c) 1996 Microchip Technology Inc.
DS30390B-J00 - page 139
PIC16C7X
DS30390B-J00 - page 140
(c) 1996 Microchip Technology Inc.
PIC16C7X
13
8
7
6
0
OPCODE d f(FILE #) d = 0 for destination W d = 1 for destination f f = 7-bit file register address
Bit-oriented file register operations
13 10 9 76 f(FILE #) 0 OPCODE b(BIT #) b = 3-bit bit address f = 7-bit file register address
Literal and control operations
13 OPCODE 8 7 k (LITERAL) 0
k = 8-bit immediate value.
Literal and control operations
13 11 10 OPCODE k (LITERAL) 0
k = 8-bit immediate value.
(c) 1996 Microchip Technology Inc.
DS30390B-J00 - page 141
PIC16C7X
msb
lsb
ADDWF ANDWF CLRF CLRW COMF DECF DECFSZ INCF INCFSZ IORWF MOVF MOVWF NOP RLF RRF SUBWF SWAPF XORWF
f, d f, d f f, d f, d f, d f, d f, d f, d f, d f f, d f, d f, d f, d f, d
Add W and f AND W and f Clear f Clear W Complement f Decrement f Decrement f, Skip if 0 Increment f Increment f, Skip if 0 Inclusive OR W and f Move f Move W to f No Operation Rotate left f through carry Rotate right f through carry Subtract W from f Swap halves f Exclusive OR W and f
1 1 1 1 1 1 1 (2) 1 1 (2) 1 1 1 1 1 1 1 1 1
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0111 0101 0001 0001 1001 0011 1011 1010 1111 0100 1000 0000 0000 1101 1100 0010 1110 0110
dfff dfff 1fff 0xxx dfff dfff dfff dfff dfff dfff dfff 1fff 0xx0 dfff dfff dfff dfff dfff
ffff ffff ffff xxxx ffff ffff ffff ffff ffff ffff ffff ffff 0000 ffff ffff ffff ffff ffff
C, DC, Z Z Z Z Z Z Z Z Z
1, 2 1, 2 2 1, 2 1, 2 1, 2, 3 1, 2 1, 2, 3 1, 2 1, 2
C C C, DC, Z Z
1, 2 1, 2 1, 2 1, 2 1, 2
BCF BSF BTFSC BTFSS
f, b f, b f, b f, b
Bit Clear f Bit Set f Bit Test f, Skip if Clear Bit Test f, Skip if Set
1 1 1 (2) 1 (2)
01 01 01 01
00bb 01bb 10bb 11bb
bfff bfff bfff bfff
ffff ffff ffff ffff
1, 2 1, 2 3 3
ADDLW ANDLW CALL CLRWDT GOTO IORLW MOVLW RETFIE RETLW RETURN SLEEP SUBLW XORLW
k k k k k k k k k
Add literal to W AND literal to W Call subroutine Clear watchdog timer Go to address Inclusive OR literal to W Move literal to W Return from interrupt Return with literal in W Return from subroutine Go into standby mode Subtract W from literal Excl. OR literal to W
1 1 2 1 2 1 1 2 2 2 1 1 1
11 11 10 00 10 11 11 00 11 00 00 11 11
111x 1001 0kkk 0000 1kkk 1000 00xx 0000 01xx 0000 0000 110x 1010
kkkk kkkk kkkk 0110 kkkk kkkk kkkk 0000 kkkk 0000 0110 kkkk kkkk
kkkk kkkk kkkk 0100 kkkk kkkk kkkk 1001 kkkk 1000 0011 kkkk kkkk
C, DC, Z Z TO, PD Z
TO, PD C, DC, Z Z
DS30390B-J00 - page 142
(c) 1996 Microchip Technology Inc.
PIC16C7X
ADDLW
Add Literal to W
ANDLW
AND Literal and W
ADDWF
ADD W to f
ANDWF
AND W with f
(c) 1996 Microchip Technology Inc.
DS30390B-J00 - page 143
PIC16C7X
BCF
Bit Clear f
BTFSC
Bit Test, skip if Clear
BSF
Bit Set f
DS30390B-J00 - page 144
(c) 1996 Microchip Technology Inc.
PIC16C7X
BTFSS
Bit Test, skip if Set
CLRF
Clear f
CALL
Subroutine Call
CLRW
Clear W Register
(c) 1996 Microchip Technology Inc.
DS30390B-J00 - page 145
PIC16C7X
CLRWDT
Clear Watchdog Timer
DECF
Decrement f
COMF
Complement f
DECFSZ
Decrement f, skip if 0
DS30390B-J00 - page 146
(c) 1996 Microchip Technology Inc.
PIC16C7X
GOTO
Unconditional Branch
INCFSZ
Increment f, skip if 0
INCF
Increment f
IORLW
Inclusive OR Literal with W
(c) 1996 Microchip Technology Inc.
DS30390B-J00 - page 147
PIC16C7X
IORWF
Inclusive OR W with f
MOVF
Move f
MOVLW
Move Literal to W
MOVWF
Move W to f
DS30390B-J00 - page 148
(c) 1996 Microchip Technology Inc.
PIC16C7X
NOP
No Operation
RETFIE
Return from Interrupt
OPTION
Load Option Register
RETLW
Return Literal to W
(c) 1996 Microchip Technology Inc.
DS30390B-J00 - page 149
PIC16C7X
RETURN
Return from Subroutine
RRF
Rotate Right f through Carry
C
Register f
RLF
Rotate Left f through Carry
SLEEP
C
Register f
DS30390B-J00 - page 150
(c) 1996 Microchip Technology Inc.
PIC16C7X
SUBLW
Subtract W from Literal
SUBWF
Subtract W from f
(c) 1996 Microchip Technology Inc.
DS30390B-J00 - page 151
PIC16C7X
SWAPF
Swap Nibbles in f
XORLW
Exclusive OR literal with W
TRIS
Load TRIS Register
XORWF
Exclusive OR W with f
DS30390B-J00 - page 152
(c) 1996 Microchip Technology Inc.
PIC16C7X
(c) 1996 Microchip Technology Inc.
DS30390B-J00 - page 153
PIC16C7X
DS30390B-J00 - page 154
(c) 1996 Microchip Technology Inc.
PIC16C7X
(c) 1996 Microchip Technology Inc.
DS30390B-J00 - page 155
PIC16C7X
DS30390B-J00 - page 156
(c) 1996 Microchip Technology Inc.
PIC16C7X
(c) 1996 Microchip Technology Inc.
DS30390B-J00 - page 157
PIC16C7X
DS30390B-J00 - page 158
(c) 1996 Microchip Technology Inc.
PIC16C7X
(c) 1996 Microchip Technology Inc.
DS30390B-J00 - page 309
PIC16C7X
DS30390B-J00 - page 310
(c) 1996 Microchip Technology Inc.
PIC16C7X
(c) 1996 Microchip Technology Inc.
DS30390B-J00 - page 311
PIC16C7X
DS30390B-J00 - page 312
(c) 1996 Microchip Technology Inc.

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