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SC68C2550B
Rev. 02 -- 28 April 2005
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5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs and Motorola P interface
Product data sheet
1. General description
The SC68C2550B is a two channel Universal Asynchronous Receiver and Transmitter (UART) used for serial data communications. Its principal function is to convert parallel data into serial data and vice versa. The UART can handle serial data rates up to 5 Mbit/s. The SC68C2550B provides enhanced UART functions with 16-byte FIFOs, modem control interface, DMA mode data transfer. The DMA mode data transfer is controlled by the FIFO trigger levels and the TXRDY and RXRDY signals. On-board status registers provide the user with error indications and operational status. System interrupts and modem control features may be tailored by software to meet specific user requirements. An internal loop-back capability allows on-board diagnostics. Independent programmable baud rate generators are provided to select transmit and receive baud rates. The SC68C2550B operates at 5 V, 3.3 V and 2.5 V and the industrial temperature range, and is available in a plastic LQFP48 package.
2. Features
s s s s s s s s s s s s 2 channel UART with Motorola P interface 5 V, 3.3 V and 2.5 V operation Industrial temperature range Up to 5 Mbit/s data rate at 5 V and 3.3 V, and 3 Mbit/s at 2.5 V 16-byte transmit FIFO to reduce the bandwidth requirement of the external CPU 16-byte receive FIFO with error flags to reduce the bandwidth requirement of the external CPU Independent transmit and receive UART control Four selectable Receive FIFO interrupt trigger levels Software selectable baud rate generator Standard asynchronous error and framing bits (Start, Stop, and Parity Overrun Break) Transmit, Receive, Line Status, and Data Set interrupts independently controlled Fully programmable character formatting: x 5, 6, 7, or 8-bit characters x Even, odd, or no-parity formats x 1, 112, or 2-stop bit x Baud generation (DC to 5 Mbit/s) False start-bit detection Complete status reporting capabilities 3-state output TTL drive capabilities for bi-directional data bus and control bus
s s s
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SC68C2550B
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5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs
s Line break generation and detection s Internal diagnostic capabilities: x Loop-back controls for communications link fault isolation s Prioritized interrupt system controls s Modem control functions (CTS, RTS, DSR, DTR, RI, CD)
3. Ordering information
Table 1: Ordering information Package Name SC68C2550BIB48 LQFP48 Description plastic low profile quad flat package; 48 leads; body 7 x 7 x 1.4 mm Version SOT313-2 Type number
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Product data sheet
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SC68C2550B
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5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs
4. Block diagram
SC68C2550B
TRANSMIT FIFO REGISTER D0 to D7 R/W RESET DATA BUS AND CONTROL LOGIC TRANSMIT SHIFT REGISTER
TXA, TXB
INTERCONNECT BUS LINES AND CONTROL SIGNALS
RECEIVE FIFO REGISTER
RECEIVE SHIFT REGISTER
RXA, RXB
A0 to A3 CS
REGISTER SELECT LOGIC
DTRA, DTRB RTSA, RTSB OP2A, OP2B MODEM CONTROL LOGIC
IRQ TXRDYA, TXRDYB RXRDYA, RXRDYB
INTERRUPT CONTROL LOGIC
CLOCK AND BAUD RATE GENERATOR
CTSA, CTSB RIA, RIB CDA, CDB DSRA, DSRB
002aab334
XTAL1
XTAL2
Fig 1. Block diagram of SC68C2550B
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Product data sheet
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SC68C2550B
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5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs
5. Pinning information
5.1 Pinning
43 TXRDYA
39 DSRA
38 CTSA
40 CDA
42 VCC 41 RIA
D5 D6 D7 RXB RXA TXRDYB TXA TXB OP2B
1 2 3 4 5 6 7 8 9
37 n.c. 36 RESET 35 DTRB 34 DTRA 33 RTSA 32 OP2A 31 RXRDYA 30 IRQ 29 n.c. 28 A0 27 A1 26 A2 25 n.c. GND 24
002aab335
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48 D4
47 D3
46 D2 R/W 15
45 D1 CDB 16
SC68C2550BIB48
CS 10 A3 11 n.c. 12 XTAL1 13 XTAL2 14 GND 17 RXRDYB 18 VCC 19 DSRB 20 RIB 21 RTSB 22 CTSB 23
Fig 2. Pin configuration for LQFP48
5.2 Pin description
Table 2: Symbol A0 A1 A2 A3 CS Pin description Pin 28 27 26 11 10 Type I I I I I Description Address 0 select bit. Internal register address selection. Address 1 select bit. Internal register address selection. Address 2 select bit. Internal register address selection. Address 3. A3 is used to select Channel A or Channel B. A logic LOW selects Channel A, and a logic HIGH selects Channel B. (See Table 3.) Chip Select (active LOW). This pin enables data transfers between the user CPU and the SC68C2550B for the channel(s) addressed. Individual UART sections (A, B) are addressed by A3. See Table 3. Data bus (bi-directional). These pins are the 8-bit, 3-state data bus for transferring information to or from the controlling CPU. D0 is the least significant bit and the first data bit in a transmit or receive serial data stream. Signal and power ground. Interrupt Request. Interrupts from UART channels A-B are wire-ORed internally to function as a single IRQ interrupt. This pin transitions to a logic 0 (if enabled by the interrupt enable register) whenever a UART channel(s) requires service. Individual channel interrupt status can be determined by addressing each channel through its associated internal register, using CS and A3. An external pull-up resistor must be connected between this pin and VCC.
Rev. 02 -- 28 April 2005 4 of 35
D0 to D7
44, 45, 46, 47, 48, 1, 2, 3 17, 24 30
I/O
GND IRQ
I O
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Product data sheet
44 D0
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SC68C2550B
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5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs
Table 2: Symbol R/W
Pin description ...continued Pin 15 Type I Description A logic LOW on this pin will transfer the contents of the data bus (D[0:7]) from an external CPU to an internal register that is defined by address bits A[0:2]. A logic HIGH on this pin will load the contents of an internal register defined by address bits A[0:2] on the SC68C2550B data bus (D[0:7]) for access by an external CPU. Output 2 (user-defined). This function is associated with individual channels A and B. The state of these pins is defined by the user through the software settings of MCR[3]. OP2A/OP2B is a logic 0 when MCR[3] is set to a logic 1. OP2A/OP2B is a logic 1 when MCR[3] is set to a logic 0. The output of these two pins is HIGH after reset. Reset (active LOW). A logic 0 on this pin will reset the internal registers and all the outputs. The UART transmitter output and the receiver input will be disabled during reset time. (See Section 7.10 "SC68C2550B external reset condition" for initialization details.) Receive Ready A, B (active LOW). This function is associated with PLCC44 and LQFP48 packages only. This function provides the RX FIFO/RHR status for individual receive channels (A-B). RXRDYn is primarily intended for monitoring DMA mode 1 transfers for the receive data FIFOs. A logic 0 indicates there is a receive data to read/upload, that is, receive ready status with one or more RX characters available in the FIFO/RHR. This pin is a logic 1 when the FIFO/RHR is empty or when the programmed trigger level has not been reached. This signal can also be used for single mode transfers (DMA mode 0). Transmit Ready A, B (active LOW). This function is associated with PLCC44 and LQFP48 packages only. These outputs provide the TX FIFO/THR status for individual transmit channels (A-B). TXRDYn is primarily intended for monitoring DMA mode 1 transfers for the transmit data FIFOs. An individual channel's TXRDYA, TXRDYB buffer ready status is indicated by logic 0, that is, at lease one location is empty and available in the FIFO or THR. This pin goes to a logic 1 (DMA mode 1) when there are no more empty locations in the FIFO or THR. This signal can also be used for single mode transfers (DMA mode 0). Power supply input Crystal or external clock input. Functions as a crystal input or as an external clock input. A crystal can be connected between this pin and XTAL2 to form an internal oscillator circuit. Alternatively, an external clock can be connected to this pin to provide custom data rates. (See Section 6.5 "Programmable baud rate generator".) See Figure 3. Output of the crystal oscillator or buffered clock. (See also XTAL1.) Crystal oscillator output or buffered clock output. Should be left open if an external clock is connected to XTAL1. For extended frequency operation, this pin should be tied to VCC via a 2 k resistor. Carrier Detect (active LOW). These inputs are associated with individual UART channels A through B. A logic 0 on this pin indicates that a carrier has been detected by the modem for that channel. Clear to Send (active LOW). These inputs are associated with individual UART channels, A through B. A logic 0 on the CTS pin indicates the modem or data set is ready to accept transmit data from the SC68C2550B. Status can be tested by reading MSR[4]. This pin has no effect on the UART's transmit or receive operation. Data Set Ready (active LOW). These inputs are associated with individual UART channels, A through B. A logic 0 on this pin indicates the modem or data set is powered-on and is ready for data exchange with the UART. This pin has no effect on the UART's transmit or receive operation.
OP2A, OP2B
32, 9
O
RESET
36
I
RXRDYA, RXRDYB
31, 18
O
TXRDYA, TXRDYB
43, 6
O
VCC XTAL1
19, 42 13
I I
XTAL2
14
O
CDA, CDB CTSA, CTSB
40, 16
I
38, 23
I
DSRA, DSRB
39, 20
I
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Product data sheet
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5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs
Table 2: Symbol DTRA, DTRB
Pin description ...continued Pin 34, 35 Type O Description Data Terminal REady (active LOW). These outputs are associated with individual UART channels, A through B. A logic 0 on this pin indicates that the SC68C2550B is powered-on and ready. This pin can be controlled via the modem control register. Writing a logic 1 to MCR[0] will set the DTR output to logic 0, enabling the modem. This pin will be a logic 1 after writing a logic 0 to MCR[0], or after a reset. This pin has no effect on the UART's transmit or receive operation. Ring Indicator (active LOW). These inputs are associated with individual UART channels, A through B. A logic 0 on this pin indicates the modem has received a ringing signal from the telephone line. A logic 1 transition on this input pin will generate an interrupt. Request to Send (active LOW). These outputs are associated with individual UART channels, A through B. A logic 0 on the RTS pin indicates the transmitter has data ready and waiting to send. Writing a logic 1 in the modem control register MCR[1] will set this pin to a logic 0, indicating data is available. After a reset this pin will be set to a logic 1. This pin has no effect on the UART's transmit or receive operation. Receive data A, B. These inputs are associated with individual serial channel data to the SC68C2550B receive input circuits, A-B. The RX signal will be a logic 1 during reset, idle (no data), or when the transmitter is disabled. During the local loop-back mode, the RX input pin is disabled and TX data is connected to the UART RX input, internally. Transmit data A, B. These outputs are associated with individual serial transmit channel data from the SC68C2550B. The TX signal will be a logic 1 during reset, idle (no data), or when the transmitter is disabled. During the local loop-back mode, the TX output pin is disabled and TX data is internally connected to the UART RX input. not connected
RIA, RIB
41, 21
I
RTSA, RTSB
33, 22
O
RXA, RXB 5, 4
I
TXA, TXB 7, 8
O
n.c.
12, 25, 29, 37
-
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SC68C2550B
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5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs
6. Functional description
The SC68C2550B provides serial asynchronous receive data synchronization, parallel-to-serial and serial-to-parallel data conversions for both the transmitter and receiver sections. These functions are necessary for converting the serial data stream into parallel data that is required with digital data systems. Synchronization for the serial data stream is accomplished by adding start and stop bits to the transmit data to form a data character (character orientated protocol). Data integrity is insured by attaching a parity bit to the data character. The parity bit is checked by the receiver for any transmission bit errors. The electronic circuitry to provide all these functions is fairly complex, especially when manufactured on a single integrated silicon chip. The SC68C2550B represents such an integration with greatly enhanced features. The SC68C2550B is fabricated with an advanced CMOS process. The SC68C2550B is an upward solution that provides a dual UART capability with 16 bytes of transmit and receive FIFO memory. The SC68C2550B is designed to work with high speed modems and shared network environments that require fast data processing time. Increased performance is realized in the SC68C2550B by the transmit and receive FIFOs. This allows the external processor to handle more networking tasks within a given time. For example, the ST16C2450 without a receive FIFO, will require unloading of the RHR in 93 microseconds (this example uses a character length of 11 bits, including start/stop bits at 115.2 kbit/s). This means the external CPU will have to service the receive FIFO less than every 100 microseconds. However, with the 16-byte FIFO in the SC68C2550B, the data buffer will not require unloading/loading for 1.53 ms. This increases the service interval, giving the external CPU additional time for other applications and reducing the overall UART interrupt servicing time. In addition, the four selectable receive FIFO trigger interrupt levels is uniquely provided for maximum data throughput performance especially when operating in a multi-channel environment. The FIFO memory greatly reduces the bandwidth requirement of the external controlling CPU, increases performance, and reduces power consumption. The SC68C2550B is capable of operation up to 5 Mbit/s with a 80 MHz clock. With a crystal or external clock input of 7.3728 MHz, the user can select data rates up to 460.8 kbit/s. The rich feature set of the SC68C2550B is available through internal registers. Selectable receive FIFO trigger levels, selectable TX and RX baud rates, and modem interface controls are all standard features.
6.1 UART A-B functions
The UART provides the user with the capability to bi-directionally transfer information between an external CPU, the SC68C2550B package, and an external serial device. A logic 0 on chip select pin CS and A3 (LOW or HIGH) allows the user to configure, send data, and/or receive data via UART channels A and B. Individual channel select functions are shown in Table 3.
Table 3: CS 1 0 0
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Channel selection using CS pin A3 0 1 UART select none channel A channel B
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Product data sheet
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SC68C2550B
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5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs
6.2 Internal registers
The SC68C2550B provides two sets of internal registers (A and B) consisting of 12 registers each for monitoring and controlling the functions of each channel of the UART. These registers are shown in Table 4. The UART registers function as data holding registers (THR/RHR), interrupt status and control registers (IER/ISR), a FIFO control register (FCR), line status and control registers (LCR/LSR), modem status and control registers (MCR/MSR), programmable data rate (clock) control registers (DLL/DLM), and a user accessible scratchpad register (SPR).
Table 4: A2 0 0 0 0 1 1 1 1 0 0
[1] [2]
Internal registers decoding A1 0 0 1 1 0 0 1 1 0 0 A0 0 1 0 1 0 1 0 1 0 1 Read mode Receive Holding Register Interrupt Enable Register Interrupt Status Register Line Control Register Modem Control Register Line Status Register Modem Status Register Scratchpad Register (DLL/DLM) [2] LSB of Divisor Latch MSB of Divisor Latch LSB of Divisor Latch MSB of Divisor Latch Write mode Transmit Holding Register Interrupt Enable Register FIFO Control Register Line Control Register Modem Control Register n/a n/a Scratchpad Register
General register set (THR/RHR, IER/ISR, MCR/MSR, FCR, LSR, SPR) [1]
Baud rate register set
These registers are accessible only when LCR[7] is a logic 0. These registers are accessible only when LCR[7] is a logic 1.
6.3 FIFO operation
The 16 byte transmit and receive data FIFOs are enabled by the FIFO Control Register (FCR) bit 0. The user can set the receive trigger level via FCR[7:6], but not the transmit trigger level. The receiver FIFO section includes a time-out function to ensure data is delivered to the external CPU. An interrupt is generated whenever the Receive Holding Register (RHR) has not been read following the loading of a character or the receive trigger level has not been reached.
Table 5: 1 4 8 14 Flow control mechanism IRQ pin activation 1 4 8 14
Selected trigger level (characters)
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6.4 Hardware/software and time-out interrupts
The interrupts are enabled by IER[0-3]. Care must be taken when handling these interrupts. Following a reset, if Interrupt Enable Register (IER) bit 1 = 1, the SC68C2550B will issue a Transmit Holding Register interrupt. This interrupt must be serviced prior to continuing operations. The ISR register provides the current singular highest priority interrupt only. A condition can exist where a higher priority interrupt may mask the lower priority interrupt(s). Only after servicing the higher pending interrupt will the lower priority interrupt(s) be reflected in the status register. Servicing the interrupt without investigating further interrupt conditions can result in data errors. When two interrupt conditions have the same priority, it is important to service these interrupts correctly. Receive Data Ready and Receive Time-Out have the same interrupt priority (when enabled by IER[0]). The receiver issues an interrupt after the number of characters have reached the programmed trigger level. In this case, the SC68C2550B FIFO may hold more characters than the programmed trigger level. Following the removal of a data byte, the user should re-check LSR[0] for additional characters. A Receive Time-Out will not occur if the receive FIFO is empty. The time-out counter is reset at the center of each stop bit received or each time the receive holding register (RHR) is read. The actual time-out value is 4 character time, including data information length, start bit, parity bit, and the size of stop bit, that is, 1x, 1.5x, or 2x bit times.
6.5 Programmable baud rate generator
The SC68C2550B supports high speed modem technologies that have increased input data rates by employing data compression schemes. For example, a 33.6 kbit/s modem that employs data compression may require a 115.2 kbit/s input data rate. A 128.0 kbit/s ISDN modem that supports data compression may need an input data rate of 460.8 kbit/s. The SC68C2550B can support a standard data rate of 921.6 kbit/s. A single baud rate generator is provided for the transmitter and receiver, allowing independent TX/RX channel control. The programmable Baud Rate Generator (BRG) is capable of operating with a frequency of up to 80 MHz. To obtain maximum data rate, it is necessary to use full rail swing on the clock input. The SC68C2550B can be configured for internal or external clock operation. For internal clock oscillator operation, an industry standard microprocessor crystal is connected externally between the XTAL1 and XTAL2 pins. Alternatively, an external clock can be connected to the XTAL1 pin to clock the internal baud rate generator for standard or custom rates (see Table 6). The generator divides the input 16x clock by any divisor from 1 to (216 - 1). The SC68C2550B divides the basic external clock by 16. The basic 16x clock provides table rates to support standard and custom applications using the same system design. The rate table is configured via the DLL and DLM internal register functions. Customized baud rates can be achieved by selecting the proper divisor values for the MSB and LSB sections of baud rate generator. Programming the baud rate generator registers DLM (MSB) and DLL (LSB) provides a user capability for selecting the desired final baud rate. The example in Table 6 shows the selectable baud rate table available when using a 1.8432 MHz external clock input.
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5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs
XTAL1
XTAL2
X1 1.8432 MHz
C1 22 pF
C2 33 pF
002aab325
Fig 3. Crystal oscillator connection Table 6: Output baud rate 50 75 110 150 300 600 1200 2400 3600 4800 7200 9600 19.2 k 38.4 k 57.6 k 115.2 k Baud rate generator programming table using a 1.8432 MHz clock Output 16x clock divisor (decimal) 2304 1536 1047 768 384 192 96 48 32 24 16 12 6 3 2 1 Output 16x clock divisor (HEX) 900 600 417 300 180 C0 60 30 20 18 10 0C 06 03 02 01 DLM program value (HEX) 09 06 04 03 01 00 00 00 00 00 00 00 00 00 00 00 DLL program value (HEX) 00 00 17 00 80 C0 60 30 20 18 10 0C 06 03 02 01
6.6 DMA operation
The SC68C2550B FIFO trigger level provides additional flexibility to the user for block mode operation. LSR[6:5] provide an indication when the transmitter is empty or has an empty location(s). The user can optionally operate the transmit and receive FIFOs in the DMA mode (FCR[3]). When the transmit and receive FIFOs are enabled and the DMA mode is de-activated (DMA Mode 0), the SC68C2550B activates the interrupt output pin for each data transmit or receive operation. When DMA mode is activated (DMA Mode 1), the user takes the advantage of block mode operation by loading or unloading the FIFO in a block sequence determined by the receive trigger level and the transmit FIFO. In this mode, the SC68C2550B sets the TXRDY (or RXRDY) output pin when characters in the transmit FIFO is below 16, or the characters in the receive FIFOs are above the receive trigger level.
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6.7 Loop-back mode
The internal loop-back capability allows on-board diagnostics. In the Loop-back mode, the normal modem interface pins are disconnected and reconfigured for loop-back internally (see Figure 4). MCR[3:0] register bits are used for controlling loop-back diagnostic testing. In the Loop-back mode, the transmitter output (TX) and the receiver input (RX) are disconnected from their associated interface pins, and instead are connected together internally. The CTS, DSR, CD, and RI are disconnected from their normal modem control inputs pins, and instead are connected internally to RTS, DTR, MCR[3] (OP2) and MCR[2] (OP1). Loop-back test data is entered into the transmit holding register via the user data bus interface, D0 to D7. The transmit UART serializes the data and passes the serial data to the receive UART via the internal loop-back connection. The receive UART converts the serial data back into parallel data that is then made available at the user data interface D0 to D7. The user optionally compares the received data to the initial transmitted data for verifying error-free operation of the UART TX/RX circuits. In this mode, the receiver and transmitter interrupts are fully operational. The Modem Control Interrupts are also operational.
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5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs
SC68C2550B
TRANSMIT FIFO REGISTERS D0 to D7 R/W RESET DATA BUS AND CONTROL LOGIC MCR[4] = 1 TRANSMIT SHIFT REGISTER
TXA, TXB
INTERCONNECT BUS LINES AND CONTROL SIGNALS
RECEIVE FIFO REGISTERS
RECEIVE SHIFT REGISTER
RXA, RXB
A0 to A3 CS
REGISTER SELECT LOGIC
RTSA, RTSB
CTSA, CTSB DTRA, DTRB MODEM CONTROL LOGIC IRQ TXRDYA, TXRDYB RXRDYA, RXRDYB INTERRUPT CONTROL LOGIC CLOCK AND BAUD RATE GENERATOR
DSRA, DSRB (OP1A, OP1B)
RIA, RIB (OP2A, OP2B)
CDA, CDB
002aab336
XTAL1 XTAL2
Fig 4. Internal Loop-back mode diagram
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7. Register descriptions
Table 7 details the assigned bit functions for the SC68C2550B internal registers. The assigned bit functions are more fully defined in Section 7.1 through Section 7.10.
Table 7: A2 0 0 0 A1 0 0 0 SC68C2550B internal registers A0 0 0 1 Register Default [1] Bit 7 Set [2] XX XX 00 bit 7 bit 7 0 bit 6 bit 6 0 bit 5 bit 5 0 bit 4 bit 4 0 bit 3 bit 3 bit 2 bit 2 bit 1 bit 1 transmit holding register interrupt RCVR FIFO reset INT priority bit 0 bit 0 bit 0 receive holding register FIFOs enable INT status word length bit 0 DTR receive data ready CTS bit 0 bit 0 bit 8 RHR THR IER Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
General Register
modem receive status line interrupt status interrupt DMA mode select INT priority bit 2 parity enable XMIT FIFO reset INT priority bit 1
0
1
0
FCR
00
RCVR trigger (MSB) FIFOs enabled divisor latch enable 0 FIFO data error CD bit 7 bit 7 bit 15
RCVR trigger (LSB) FIFOs enabled
reserved 0 0
reserved 0 0
0
1
0
ISR
01
0
1
1
LCR
00
set break set parity even parity 0 0
stop bits word length bit 1 (OP1) parity error RI bit 2 bit 2 bit 10 RTS overrun error DSR bit 1 bit 1 bit 9
1 1
0 0
0 1
MCR LSR
00 60
loop back OP2 control break interrupt CTS bit 4 bit 4 bit 12 framing error CD bit 3 bit 3 bit 11
THR and THR TSR empty empty RI bit 6 bit 6 bit 14 DSR bit 5 bit 5 bit 13
1 1 0 0
[1] [2] [3]
1 1 0 0
0 1 0 1
MSR SPR DLL DLM
X0 FF XX XX
Special Register Set [3]
The value shown in represents the register's initialized HEX value; X = n/a. Accessible only when LCR[7] is logic 0. Baud rate registers accessible only when LCR[7] is logic 1.
7.1 Transmit (THR) and Receive (RHR) Holding Registers
The serial transmitter section consists of an 8-bit Transmit Hold Register (THR) and Transmit Shift Register (TSR). The status of the THR is provided in the Line Status Register (LSR). Writing to the THR transfers the contents of the data bus (D7 to D0) to the TSR and UART via the THR, providing that the THR is empty. The THR empty flag in the LSR register will be set to a logic 1 when the transmitter is empty or when data is transferred to the TSR. Note that a write operation can be performed when the THR empty flag is set (logic 0 = at least one byte in FIFO/THR, logic 1 = FIFO/THR empty). The serial receive section also contains an 8-bit Receive Holding Register (RHR) and a Receive Serial Shift Register (RSR). Receive data is removed from the SC68C2550B and receive FIFO by reading the RHR register. The receive section provides a mechanism to
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prevent false starts. On the falling edge of a start or false start bit, an internal receiver counter starts counting clocks at the 16x clock rate. After 712 clocks, the start bit time should be shifted to the center of the start bit. At this time the start bit is sampled, and if it is still a logic 0 it is validated. Evaluating the start bit in this manner prevents the receiver from assembling a false character. Receiver status codes will be posted in the LSR.
7.2 Interrupt Enable Register (IER)
The Interrupt Enable Register (IER) masks the interrupts from receiver ready, transmitter empty, line status and modem status registers. These interrupts would normally be seen on the IRQ output pin.
Table 8: Bit 7:4 3 Interrupt Enable Register bits description Symbol IER[7:4] IER[3] Description not used Modem Status Interrupt. This interrupt will be issued whenever there is a modem status change as reflected in MSR[3:0]. logic 0 = disable the modem status register interrupt (normal default condition) logic 1 = enable the modem status register interrupt 2 IER[2] Receive Line Status interrupt. This interrupt will be issued whenever a receive data error condition exists as reflected in LSR[4:1]. logic 0 = disable the receiver line status interrupt (normal default condition) logic 1 = enable the receiver line status interrupt 1 IER[1] Transmit Holding Register interrupt. In the 16C450 mode, this interrupt will be issued whenever the THR is empty, and is associated with LSR[5]. In the FIFO modes, this interrupt will be issued whenever the FIFO is empty. logic 0 = disable the Transmit Holding Register Empty (TXRDY) interrupt (normal default condition) logic 1 = enable the TXRDY (ISR level 3) interrupt 0 IER[0] Receive Holding Register. In the 68C450 mode, this interrupt will be issued when the RHR has data, or is cleared when the RHR is empty. In the FIFO mode, this interrupt will be issued when the FIFO has reached the programmed trigger level or is cleared when the FIFO drops below the trigger level. logic 0 = disable the receiver ready (ISR level 2, RXRDY) interrupt (normal default condition) logic 1 = enable the RXRDY (ISR level 2) interrupt
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7.2.1 IER versus Transmit/Receive FIFO interrupt mode operation
When the receive FIFO (FCR[0] = logic 1), and receive interrupts (IER[0] = logic 1) are enabled, the receive interrupts and register status will reflect the following:
* The receive RXRDY interrupt (Level 2 ISR interrupt) is issued to the external CPU
when the receive FIFO has reached the programmed trigger level. It will be cleared when the receive FIFO drops below the programmed trigger level.
* Receive FIFO status will also be reflected in the user accessible ISR register when
the receive FIFO trigger level is reached. Both the ISR register receive status bit and the interrupt will be cleared when the FIFO drops below the trigger level.
* The receive data ready bit (LSR[0]) is set as soon as a character is transferred from
the shift register (RSR) to the receive FIFO. It is reset when the FIFO is empty.
* When the Transmit FIFO and interrupts are enabled, an interrupt is generated when
the transmit FIFO is empty due to the unloading of the data by the TSR and UART for transmission via the transmission media. The interrupt is cleared either by reading the ISR register, or by loading the THR with new data characters.
7.2.2 IER versus Receive/Transmit FIFO polled mode operation
When FCR[0] = logic 1, resetting IER[3:0] enables the SC68C2550B in the FIFO polled mode of operation. In this mode, interrupts are not generated and the user must poll the LSR register for TX and/or RX data status. Since the receiver and transmitter have separate bits in the LSR either or both can be used in the polled mode by selecting respective transmit or receive control bit(s).
* * * * *
LSR[0] will be a logic 1 as long as there is one byte in the receive FIFO. LSR[4:1] will provide the type of receive errors, or a receive break, if encountered. LSR[5] will indicate when the transmit FIFO is empty. LSR[6] will indicate when both the transmit FIFO and transmit shift register are empty. LSR[7] will show if any FIFO data errors occurred.
7.3 FIFO Control Register (FCR)
This register is used to enable the FIFOs, clear the FIFOs, set the receive FIFO trigger levels, and select the DMA mode.
7.3.1 DMA mode
7.3.1.1 Mode 0 (FCR bit 3 = 0) Set and enable the interrupt for each single transmit or receive operation, and is similar to the 68C450 mode. Transmit Ready (TXRDY) will go to a logic 0 whenever the FIFO (THR, if FIFO is not enabled) is empty. Receive Ready (RXRDY) will go to a logic 0 whenever the Receive Holding Register (RHR) is loaded with a character. 7.3.1.2 Mode 1 (FCR bit 3 = 1) Set and enable the interrupt in a block mode operation. The transmit interrupt is set when the transmit FIFO is empty. TXRDY remains a logic 0 as long as one empty FIFO location is available. The receive interrupt is set when the receive FIFO fills to the programmed
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trigger level. However, the FIFO continues to fill regardless of the programmed level until the FIFO is full. RXRDY packages transitions LOW when the FIFO reaches the trigger level, and transitions HIGH when the FIFO empties.
7.3.2 FIFO mode
Table 9: Bit 7:6 FIFO Control Register bits description Symbol FCR[7:6] Description RCVR trigger. These bits are used to set the trigger level for the receive FIFO interrupt. logic 0 (or cleared) = normal default condition logic 1 = RX trigger level An interrupt is generated when the number of characters in the FIFO equals the programmed trigger level. However, the FIFO will continue to be loaded until it is full. Refer to Table 10. 5:4 3 FCR[5:4] FCR[3] not used; initialized to logic 0 DMA mode select logic 0 = set DMA mode `0' logic 1 = set DMA mode `1' Transmit operation in mode `0': When the SC68C2550B is in the 68C450 mode (FIFOs disabled; FCR[0] = logic 0) or in the FIFO mode (FIFOs enabled; FCR[0] = logic 1; FCR[3] = logic 0), and when there are no characters in the transmit FIFO or transmit holding register, the TXRDY pin will be a logic 0. Once active, the TXRDY pin will go to a logic 1 after the first character is loaded into the transmit holding register. Receive operation in mode `0': When the SC68C2550B is in mode `0' (FCR[0] = logic 0), or in the FIFO mode (FCR[3] = logic 0) and there is at least one character in the receive FIFO, the RXRDY pin will be a logic 0. Once active, the RXRDY pin will go to a logic 1 when there are no more characters in the receiver. Transmit operation in mode `1': When the SC68C2550B is in FIFO mode (FCR[0] = logic 1; FCR[3] = logic 1), the TXRDY pin will be a logic 1 when the transmit FIFO is completely full. It will be a logic 0 if one or more FIFO locations are empty. Receive operation in mode `1': When the SC68C2550B is in FIFO mode (FCR[0] = logic 1; FCR[3] = logic 1) and the trigger level has been reached, or a Receive Time-Out has occurred, the RXRDY pin will go to a logic 0. Once activated, it will go to a logic 1 after there are no more characters in the FIFO. 2 FCR[2] XMIT FIFO reset logic 0 = transmit FIFO not reset (normal default condition) logic 1 = clears the contents of the transmit FIFO and resets the FIFO counter logic (the transmit shift register is not cleared or altered). This bit will return to a logic 0 after clearing the FIFO. 1 FCR[1] RCVR FIFO reset logic 0 = receive FIFO not reset (normal default condition) logic 1 = clears the contents of the receive FIFO and resets the FIFO counter logic (the receive shift register is not cleared or altered). This bit will return to a logic 0 after clearing the FIFO.
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FIFO Control Register bits description ...continued Symbol FCR[0] Description FIFOs enabled logic 0 = disable the transmit and receive FIFO (normal default condition). logic 1 = enable the transmit and receive FIFO. This bit must be a `1' when other FCR bits are written to, or they will not be programmed.
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Table 9: Bit 0
Table 10: FCR[7] 0 0 1 1
RCVR trigger levels FCR[6] 0 1 0 1 RX FIFO trigger level 01 04 08 14
7.4 Interrupt Status Register (ISR)
The SC68C2550B provides four levels of prioritized interrupts to minimize external software interaction. The Interrupt Status Register (ISR) provides the user with four interrupt status bits. Performing a read cycle on the ISR will provide the user with the highest pending interrupt level to be serviced. No other interrupts are acknowledged until the pending interrupt is serviced. A lower level interrupt may be seen after servicing the higher level interrupt and re-reading the interrupt status bits. Table 11 shows the data values (bit 0 to bit 3) for the four prioritized interrupt levels and the interrupt sources associated with each of these interrupt levels.
Table 11: Priority level 1 2 2 3 4 Table 12: Bit 7:6 Interrupt source ISR[3] 0 0 1 0 0 ISR[2] 1 1 1 0 0 ISR[1] 1 0 0 1 0 ISR[0] 0 0 0 0 0 Source of the interrupt LSR (Receiver Line Status Register) RXRDY (Received Data Ready) RXRDY (Receive Data Time-out) TXRDY (Transmitter Holding Register Empty) MSR (Modem Status Register)
Interrupt Status Register bits description Symbol ISR[7:6] Description FIFOs enabled. These bits are set to a logic 0 when the FIFOs are not being used in the 68C450 mode. They are set to a logic 1 when the FIFOs are enabled in the SC68C2550B mode. logic 0 or cleared = default condition not used INT priority bits 2 to 0. These bits indicate the source for a pending interrupt at interrupt priority levels 1, 2, and 3 (see Table 11). logic 0 or cleared = default condition INT status logic 0 = an interrupt is pending and the ISR contents may be used as a pointer to the appropriate interrupt service routine logic 1 = no interrupt pending (normal default condition)
5:4 3:1
ISR[5:4] ISR[3:1]
0
ISR[0]
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7.5 Line Control Register (LCR)
The Line Control Register is used to specify the asynchronous data communication format. The word length, the number of stop bits, and the parity are selected by writing the appropriate bits in this register.
Table 13: Bit 7 Line Control Register bits description Symbol LCR[7] Description Divisor Latch enable. The internal baud rate counter latch and Enhanced Feature mode enable. logic 0 = Divisor Latch disabled (normal default condition). Logic 1 = Divisor Latch enabled. 6 LCR[6] Set break. When enabled, the Break control bit causes a break condition to be transmitted (the TX output is forced to a logic 0 state). This condition exists until disabled by setting LCR[6] to a logic 0. logic 0 = no TX break condition (normal default condition) logic 1 = forces the transmitter output (TX) to a logic 0 for alerting the remote receiver to a line break condition 5:3 2 LCR[5:3] LCR[2] programs the parity conditions (see Table 14) Stop bits. The length of stop bit is specified by this bit in conjunction with the programmed word length (see Table 15). logic 0 or cleared = default condition 1:0 LCR[1:0] Word length bits 1, 0. These two bits specify the word length to be transmitted or received (see Table 16). logic 0 or cleared = default condition Table 14: LCR[5] X X 0 0 1 Table 15: LCR[2] 0 1 1 Table 16: LCR[1] 0 0 1 1 LCR[5:3] parity selection LCR[4] X 0 1 0 1 LCR[3] 0 1 1 1 1 Parity selection no parity odd parity even parity forced parity `1' forced parity `0'
LCR[2] stop bit length Word length 5, 6, 7, 8 5 6, 7, 8 Stop bit length (bit times) 1 112 2
LCR[1:0] word length LCR[0] 0 1 0 1 Word length 5 6 7 8
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7.6 Modem Control Register (MCR)
This register controls the interface with the modem or a peripheral device.
Table 17: Bit 7:5 4 Modem Control Register bits description Symbol MCR[7:5] MCR[4] Description reserved; set to `0' Loop-back. Enable the local Loop-back mode (diagnostics). In this mode the transmitter output (TX) and the receiver input (RX), CTS, DSR, CD, and RI are disconnected from the SC68C2550B I/O pins. Internally the modem data and control pins are connected into a loop-back data configuration (see Figure 4). In this mode, the receiver and transmitter interrupts remain fully operational. The Modem Control Interrupts are also operational, but the interrupts' sources are switched to the lower four bits of the Modem Control. Interrupts continue to be controlled by the IER register. logic 0 = disable Loop-back mode (normal default condition) logic 1 = enable local Loop-back mode (diagnostics) 3 MCR[3] OP2 control logic 0 = forces OP2 output to HIGH state logic 1 = forces OP2 output to LOW state. In Loop-back mode, controls MSR[7]. 2 MCR[2] (OP1). OP1A/OP1B are not available as an external signal in the SC68C2550B. This bit is instead used in the Loop-back mode only. In the Loop-back mode, this bit is used to write the state of the modem RI interface signal. RTS logic 0 = force RTS output to a logic 1 (normal default condition) logic 1 = force RTS output to a logic 0 0 MCR[0] DTR logic 0 = force DTR output to a logic 1 (normal default condition) logic 1 = force DTR output to a logic 0
1
MCR[1]
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7.7 Line Status Register (LSR)
This register provides the status of data transfers between the SC68C2550B and the CPU.
Table 18: Bit 7 Line Status Register bits description Description FIFO data error logic 0 = no error (normal default condition) logic 1 = at least one parity error, framing error or break indication is in the current FIFO data. This bit is cleared when there are no remaining error flags associated with the remaining data in the FIFO. 6 LSR[6] THR and TSR empty. This bit is the Transmit Empty indicator. This bit is set to a logic 1 whenever the Transmit Holding Register and the Transmit Shift Register are both empty. It is reset to logic 0 whenever either the THR or TSR contains a data character. In the FIFO mode, this bit is set to `1' whenever the transmit FIFO and transmit shift register are both empty. THR empty. This bit is the Transmit Holding Register Empty indicator. This bit indicates that the UART is ready to accept a new character for transmission. In addition, this bit causes the UART to issue an interrupt to CPU when the THR interrupt enable is set. The THR bit is set to a logic 1 when a character is transferred from the Transmit Holding Register into the Transmit Shift Register. The bit is reset to a logic 0 concurrently with the loading of the Transmit Holding Register by the CPU. In the FIFO mode, this bit is set when the transmit FIFO is empty; it is cleared when at least 1 byte is written to the transmit FIFO. Break interrupt logic 0 = no break condition (normal default condition) logic 1 = the receiver received a break signal (RX was a logic 0 for one character frame time). In the FIFO mode, only one break character is loaded into the FIFO. 3 LSR[3] Framing error logic 0 = no framing error (normal default condition) logic 1 = framing error. The receive character did not have a valid stop bit(s). In the FIFO mode, this error is associated with the character at the top of the FIFO. 2 LSR[2] Parity error logic 0 = no parity error (normal default condition) logic 1 = parity error. The receive character does not have correct parity information and is suspect. In the FIFO mode, this error is associated with the character at the top of the FIFO. 1 LSR[1] Overrun error logic 0 = no overrun error (normal default condition) logic 1 = overrun error. A data overrun error occurred in the receive shift register. This happens when additional data arrives while the FIFO is full. In this case, the previous data in the shift register is overwritten. Note that under this condition, the data byte in the Receive Shift Register is not transferred into the FIFO, therefore the data in the FIFO is not corrupted by the error. 0 LSR[0] Receive data ready logic 0 = no data in Receive Holding Register or FIFO (normal default condition) logic 1 = data has been received and is saved in the Receive Holding Register or FIFO
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Symbol LSR[7]
5
LSR[5]
4
LSR[4]
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7.8 Modem Status Register (MSR)
This register provides the current state of the control interface signals from the modem, or other peripheral device to which the SC68C2550B is connected. Four bits of this register are used to indicate the changed information. These bits are set to a logic 1 whenever a control input from the modem changes state. These bits are set to a logic 0 whenever the CPU reads this register.
Table 19: Bit 7 6 5 4 3 Modem Status Register bits description Symbol MSR[7] MSR[6] MSR[5] MSR[4] MSR[3] Description CD. During normal operation, this bit is the complement of the CD input. Reading this bit in the Loop-back mode produces the state of MCR[3] (OP2). RI. During normal operation, this bit is the complement of the RI input. Reading this bit in the Loop-back mode produces the state of MCR[2] (OP1). DSR. During normal operation, this bit is the complement of the DSR input. During the Loop-back mode, this bit is equivalent to MCR[0] (DTR). CTS. During normal operation, this bit is the complement of the CTS input. During the Loop-back mode, this bit is equivalent to MCR[1] (RTS). CD
[1]
logic 0 = no CD change (normal default condition) logic 1 = the CD input to the SC68C2550B has changed state since the last time it was read. A Modem Status Interrupt will be generated. 2 MSR[2] RI
[1]
logic 0 = no RI change (normal default condition) logic 1 = the RI input to the SC68C2550B has changed from a logic 0 to a logic 1. A Modem Status Interrupt will be generated. 1 MSR[1] DSR
[1]
logic 0 = no DSR change (normal default condition) logic 1 = the DSR input to the SC68C2550B has changed state since the last time it was read. A Modem Status Interrupt will be generated. 0 MSR[0] CTS
[1]
logic 0 = no CTS change (normal default condition) logic 1 = the CTS input to the SC68C2550B has changed state since the last time it was read. A Modem Status Interrupt will be generated.
[1] Whenever any MSR bit 0 to bit 3 is set to logic 1, a Modem Status Interrupt will be generated.
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7.9 Scratchpad Register (SPR)
The SC68C2550B provides a temporary data register to store 8 bits of user information.
7.10 SC68C2550B external reset condition
Table 20: Register IER FCR ISR LCR MCR LSR MSR SPR DLL DLM Table 21: Output TXA, TXB OP2A, OP2B RTSA, RTSB DTRA, DTRB IRQ Reset state for registers Reset state IER[7:0] = 0 FCR[7:0] = 0 ISR[7:1] = 0; ISR[0] = 1 LCR[7:0] = 0 MCR[7:0] = 0 LSR[7] = 0; LSR[6:5] = 1; LSR[4:0] = 0 MSR[7:4] = input signals; MSR[3:0] = 0 SFR[7:0] = 1 DLL[7:0] = X DLM[7:0] = X Reset state for outputs Reset state logic 1 logic 1 logic 1 logic 1 3-state condition
8. Limiting values
Table 22: Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol VCC Vn Tamb Tstg Ptot(pack) Parameter supply voltage voltage at any pin operating temperature storage temperature total power dissipation per package Conditions Min GND - 0.3 -40 -65 Max 7 VCC + 0.3 +85 +150 500 Unit V V C C mW
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9. Static characteristics
Table 23: Static characteristics Tamb = -40 C to +85 C; VCC = 2.5 V, 3.3 V or 5.0 V 10 %, unless otherwise specified. Symbol VIL(CK) VIH(CK) VIL VIH VOL Parameter LOW-level clock input voltage HIGH-level clock input voltage LOW-level input voltage (except X1 clock) HIGH-level input voltage (except X1 clock) LOW-level output voltage on all outputs [1] IOL = 5 mA (data bus) IOL = 4 mA (other outputs) IOL = 2 mA (data bus) IOL = 1.6 mA (other outputs) VOH HIGH-level output voltage IOH = -5 mA (data bus) IOH = -1 mA (other outputs) IOH = -800 A (data bus) IOH = -400 A (other outputs) ILIL ICL ICC Ci
[1]
Conditions
VCC = 2.5 V Min -0.3 1.8 -0.3 1.6 1.85 1.85 Max 0.45 VCC 0.65 0.4 0.4 10 30 3.5 5
VCC = 3.3 V Min -0.3 2.4 -0.3 2.0 2.0 Max 0.6 VCC 0.8 0.4 10 30 4.5 5
VCC = 5.0 V Min -0.5 3.0 -0.5 2.2 2.4 Max 0.6 VCC 0.8 0.4 10 30 4.5 5
Unit V V V V V V V V V V V V A A mA pF
LOW-level input leakage current clock leakage supply current input capacitance
Except XTAL2, VOL = 1 V typical.
f = 5 MHz
-
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10. Dynamic characteristics
Table 24: Dynamic characteristics Tamb = -40 C to +85 C; VCC = 2.5 V, 3.3 V 10 % or 5 V 10 %, unless specified otherwise. Symbol td1 td2 td3 td4 td6 td7 td8 td9 td10 td11 td12 td13 td14 td15 td16 td17 td18 th2 th3 th4 t1w, t2w fXTAL t(RESET) tsu1 tsu2 tw1
[1] [2] [3]
Parameter R/W to chip select read cycle delay delay from CS to data data disable time write cycle delay delay from write to output delay to set interrupt from modem input delay to reset interrupt from read delay from stop to set interrupt delay from read to reset interrupt delay from start to set interrupt delay from write to transmit start delay from write to reset interrupt delay from stop to set RXRDY delay from read to reset RXRDY delay from write to set TXRDY delay from start to reset TXRDY R/W hold time from CS data hold time address hold time clock cycle period clock speed RESET pulse width address setup time data setup time CS strobe width
Conditions
VCC = 2.5 V Min 10 Max 77 15 100 100 100 1TRCLK
[1]
VCC = 3.3 V and 5 V Unit Min 10 20 25 8TRCLK
[1]
Max 26 15 33 24 24 1TRCLK
[1]
ns ns ns ns ns ns ns ns ns ns ns
25 pF load 25 pF load 25 pF load 25 pF load 25 pF load 25 pF load
20 25 -
25 pF load
8TRCLK
[1]
100 100 24TRCLK
[1]
29 100
[1]
24TRCLK ns 70 1TRCLK
[1]
10 15 15 10
[2] [3]
100 1TRCLK
[1]
10 15 15 6 200 10 16 30
ns ns ns ns
100 100 16TRCLK
[1]
75 70
[1]
16TRCLK ns 80 ns ns ns ns MHz ns ns ns ns
48 -
200 10 16 77
RCLK is an internal signal derived from Divisor Latch LSB (DLL) and Divisor Latch MSB (DLM) divisor latches. Applies to external clock; crystal oscillator max 24 MHz.
1 f XTAL = ------t 3w
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10.1 Timing diagrams
A0 to A3 tsu1 CS td1
valid address tw1 th4
valid address
td2
td4
R/W td3
D0 to D7
valid data
valid data
002aab087
Fig 5. General read timing
A0 to A3 tsu1
valid address tw1 th4
valid address
CS td1 th2 td6
R/W tsu2 th3
D0 to D7
valid data
valid data
002aab088
Fig 6. General write timing
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CS (write)(1)
active td7
RTSA, RTSB DTRA, DTRB
change of state
change of state
CDA, CDB CTSA, CTSB DSRA, DSRB td8
change of state td8
change of state
IRQ
active td9
active
active
CS (read)(2)
active
active td8
active
RIA, RIB
change of state
002aab089
(1) CS timing during a write cycle. See Figure 6. (2) CS timing during a read cycle. See Figure 5.
Fig 7. Modem input/output timing
t2w EXTERNAL CLOCK t3w
t1w
002aaa112
1 f XTAL = ------t 3w Fig 8. External clock timing
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Start bit
data bits (0 to 7) D0 D1 D2 5 data bits 6 data bits 7 data bits D3 D4 D5 D6 D7
parity bit
Stop bit
next data Start bit
RXA, RXB
td10 active td11
IRQ
CS (read)
active
16 baud rate clock
002aab090
Fig 9. Receive timing
Start bit
data bits (0 to 7) D0 D1 D2 D3 D4 D5 D6 D7
parity bit
Stop bit
next data Start bit
RXA, RXB
td15 RXRDYA, RXRDYB active data ready td16 CS (read)
active
002aab091
Fig 10. Receive ready timing in non-FIFO mode
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Start bit
data bits (0 to 7) D0 D1 D2 D3 D4 D5 D6 D7
parity bit
Stop bit
RXA, RXB
first byte that reaches the trigger level
td15 RXRDYA, RXRDYB active data ready td16 CS (read)
active
002aab092
Fig 11. Receive ready timing in FIFO mode
Start bit
data bits (0 to 7) D0 D1 D2 5 data bits 6 data bits 7 data bits active TX ready D3 D4 D5 D6 D7
parity bit
Stop bit
next data Start bit
TXA, TXB
IRQ
td12 td13
td14 active
CS (write)
active
16 baud rate clock
002aab093
Fig 12. Transmit timing
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Start bit TXA, TXB
data bits (0 to 7) D0 D1 D2 D3 D4 D5 D6 D7
parity bit
Stop bit
next data Start bit
CS (write)
active
D0 to D7
byte #1
td18
td17 TXRDYA, TXRDYB active transmitter ready transmitter not ready
002aab094
Fig 13. Transmit ready timing in non-FIFO mode
start bit
data bits (0 to 7) D0 D1 D2 D3 D4 D5 D6 D7
parity bit
stop bit
TXA, TXB
5 data bits 6 data bits 7 data bits CS (write) active td18 D0 to D7 byte #16
td17 TXRDYA, TXRDYB trigger lead
002aab337
Fig 14. Transmit ready timing in FIFO mode
9397 750 14941
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Product data sheet
Rev. 02 -- 28 April 2005
29 of 35
Philips Semiconductors
SC68C2550B
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5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs
11. Package outline
LQFP48: plastic low profile quad flat package; 48 leads; body 7 x 7 x 1.4 mm SOT313-2
c
y X
36 37
25 24 ZE
A
e
E HE
A A2
A1
(A 3) Lp L detail X
wM pin 1 index 48 1 12 ZD bp D HD wM B vM B vM A 13 bp
e
0
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.6 A1 0.20 0.05 A2 1.45 1.35 A3 0.25 bp 0.27 0.17 c 0.18 0.12 D (1) 7.1 6.9 E (1) 7.1 6.9 e 0.5 HD 9.15 8.85 HE 9.15 8.85 L 1 Lp 0.75 0.45 v 0.2 w 0.12 y 0.1 Z D (1) Z E (1) 0.95 0.55 0.95 0.55 7 o 0
o
Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT313-2 REFERENCES IEC 136E05 JEDEC MS-026 JEITA EUROPEAN PROJECTION
ISSUE DATE 00-01-19 03-02-25
Fig 15. Package outline SOT313-2 (LQFP48)
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Product data sheet
Rev. 02 -- 28 April 2005
30 of 35
Philips Semiconductors
SC68C2550B
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5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs
12. Soldering
12.1 Introduction to soldering surface mount packages
This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our Data Handbook IC26; Integrated Circuit Packages (document order number 9398 652 90011). There is no soldering method that is ideal for all surface mount IC packages. Wave soldering can still be used for certain surface mount ICs, but it is not suitable for fine pitch SMDs. In these situations reflow soldering is recommended.
12.2 Reflow soldering
Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Driven by legislation and environmental forces the worldwide use of lead-free solder pastes is increasing. Several methods exist for reflowing; for example, convection or convection/infrared heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 seconds and 200 seconds depending on heating method. Typical reflow peak temperatures range from 215 C to 270 C depending on solder paste material. The top-surface temperature of the packages should preferably be kept:
* below 225 C (SnPb process) or below 245 C (Pb-free process)
- for all BGA, HTSSON..T and SSOP..T packages - for packages with a thickness 2.5 mm - for packages with a thickness < 2.5 mm and a volume 350 mm3 so called thick/large packages.
* below 240 C (SnPb process) or below 260 C (Pb-free process) for packages with a
thickness < 2.5 mm and a volume < 350 mm3 so called small/thin packages. Moisture sensitivity precautions, as indicated on packing, must be respected at all times.
12.3 Wave soldering
Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. To overcome these problems the double-wave soldering method was specifically developed. If wave soldering is used the following conditions must be observed for optimal results:
* Use a double-wave soldering method comprising a turbulent wave with high upward
pressure followed by a smooth laminar wave.
* For packages with leads on two sides and a pitch (e):
- larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board;
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Product data sheet
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SC68C2550B
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5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs
- smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves at the downstream end.
* For packages with leads on four sides, the footprint must be placed at a 45 angle to
the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical dwell time of the leads in the wave ranges from 3 seconds to 4 seconds at 250 C or 265 C, depending on solder material applied, SnPb or Pb-free respectively. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications.
12.4 Manual soldering
Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 seconds to 5 seconds between 270 C and 320 C.
12.5 Package related soldering information
Table 25: Package [1] BGA, HTSSON..T [3], LBGA, LFBGA, SQFP, SSOP..T [3], TFBGA, VFBGA, XSON DHVQFN, HBCC, HBGA, HLQFP, HSO, HSOP, HSQFP, HSSON, HTQFP, HTSSOP, HVQFN, HVSON, SMS PLCC [5], SO, SOJ LQFP, QFP, TQFP SSOP, TSSOP, VSO, VSSOP CWQCCN..L [8], PMFP [9], WQCCN..L [8]
[1] [2]
Suitability of surface mount IC packages for wave and reflow soldering methods Soldering method Wave not suitable not suitable [4] Reflow [2] suitable suitable
suitable not not recommended [5] [6] recommended [7]
suitable suitable suitable not suitable
not suitable
For more detailed information on the BGA packages refer to the (LF)BGA Application Note (AN01026); order a copy from your Philips Semiconductors sales office. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods. These transparent plastic packages are extremely sensitive to reflow soldering conditions and must on no account be processed through more than one soldering cycle or subjected to infrared reflow soldering with peak temperature exceeding 217 C 10 C measured in the atmosphere of the reflow oven. The package body peak temperature must be kept as low as possible.
[3]
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Product data sheet
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SC68C2550B
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5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs
[4]
These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the solder cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink on the top side, the solder might be deposited on the heatsink surface. If wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. Wave soldering is suitable for LQFP, QFP and TQFP packages with a pitch (e) larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. Wave soldering is suitable for SSOP, TSSOP, VSO and VSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. Image sensor packages in principle should not be soldered. They are mounted in sockets or delivered pre-mounted on flex foil. However, the image sensor package can be mounted by the client on a flex foil by using a hot bar soldering process. The appropriate soldering profile can be provided on request. Hot bar soldering or manual soldering is suitable for PMFP packages.
[5] [6] [7] [8]
[9]
13. Abbreviations
Table 26: Acronym CPU DMA FIFO ISDN LSB MSB TTL UART Abbreviations Description Central Processing Unit Direct Memory Access First In/First Out Integrated Service Digital Network Least Significant Bit Most Significant Bit Transistor-Transistor Logic Universal Asynchronous Receiver and Transmitter
14. Revision history
Table 27: Revision history Release date 20050428 Data sheet status Product data sheet Change notice Doc. number 9397 750 14941 Supersedes SC68C2550B_1 Document ID SC68C2550B_2 Modifications:
* * *
Added `and Motorola P interface' to descriptive title on first page. Section 2 "Features" on page 1, first bullet: added `with Motorola P interface' Added Section 18 "Trademarks" on page 34. Product data sheet 9397 750 14698 -
SC68C2550B_1
20050329
9397 750 14941
(c) Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 02 -- 28 April 2005
33 of 35
Philips Semiconductors
SC68C2550B
www..com
5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs
15. Data sheet status
Level I II Data sheet status [1] Objective data Preliminary data Product status [2] [3] Development Qualification Definition This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN).
III
Product data
Production
[1] [2] [3]
Please consult the most recently issued data sheet before initiating or completing a design. The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.
16. Definitions
Short-form specification -- The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition -- Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information -- Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification.
customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes -- Philips Semiconductors reserves the right to make changes in the products - including circuits, standard cells, and/or software - described or contained herein in order to improve design and/or performance. When the product is in full production (status `Production'), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.
18. Trademarks
Notice -- All referenced brands, product names, service names and trademarks are the property of their respective owners.
17. Disclaimers
Life support -- These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors
19. Contact information
For additional information, please visit: http://www.semiconductors.philips.com For sales office addresses, send an email to: sales.addresses@www.semiconductors.philips.com
9397 750 14941
(c) Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 02 -- 28 April 2005
34 of 35
Philips Semiconductors
SC68C2550B
www..com
5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs
20. Contents
General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 Functional description . . . . . . . . . . . . . . . . . . . 7 UART A-B functions . . . . . . . . . . . . . . . . . . . . . 7 Internal registers. . . . . . . . . . . . . . . . . . . . . . . . 8 FIFO operation . . . . . . . . . . . . . . . . . . . . . . . . . 8 Hardware/software and time-out interrupts. . . . 9 Programmable baud rate generator . . . . . . . . . 9 DMA operation . . . . . . . . . . . . . . . . . . . . . . . . 10 Loop-back mode . . . . . . . . . . . . . . . . . . . . . . . 11 Register descriptions . . . . . . . . . . . . . . . . . . . 13 Transmit (THR) and Receive (RHR) Holding Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 7.2 Interrupt Enable Register (IER) . . . . . . . . . . . 14 7.2.1 IER versus Transmit/Receive FIFO interrupt mode operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 7.2.2 IER versus Receive/Transmit FIFO polled mode operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 7.3 FIFO Control Register (FCR) . . . . . . . . . . . . . 15 7.3.1 DMA mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 7.3.1.1 Mode 0 (FCR bit 3 = 0) . . . . . . . . . . . . . . . . . . 15 7.3.1.2 Mode 1 (FCR bit 3 = 1) . . . . . . . . . . . . . . . . . . 15 7.3.2 FIFO mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 7.4 Interrupt Status Register (ISR) . . . . . . . . . . . . 17 7.5 Line Control Register (LCR) . . . . . . . . . . . . . . 18 7.6 Modem Control Register (MCR) . . . . . . . . . . . 19 7.7 Line Status Register (LSR) . . . . . . . . . . . . . . . 20 7.8 Modem Status Register (MSR). . . . . . . . . . . . 21 7.9 Scratchpad Register (SPR) . . . . . . . . . . . . . . 22 7.10 SC68C2550B external reset condition . . . . . . 22 8 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 22 9 Static characteristics. . . . . . . . . . . . . . . . . . . . 23 10 Dynamic characteristics . . . . . . . . . . . . . . . . . 24 10.1 Timing diagrams . . . . . . . . . . . . . . . . . . . . . . . 25 11 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 30 12 Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 12.1 Introduction to soldering surface mount packages 31 12.2 Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 31 12.3 Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 31 12.4 Manual soldering . . . . . . . . . . . . . . . . . . . . . . 32 1 2 3 4 5 5.1 5.2 6 6.1 6.2 6.3 6.4 6.5 6.6 6.7 7 7.1 12.5 13 14 15 16 17 18 19 Package related soldering information . . . . . . Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . Revision history . . . . . . . . . . . . . . . . . . . . . . . Data sheet status. . . . . . . . . . . . . . . . . . . . . . . Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . Contact information . . . . . . . . . . . . . . . . . . . . 32 33 33 34 34 34 34 34
(c) Koninklijke Philips Electronics N.V. 2005
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Date of release: 28 April 2005 Document number: 9397 750 14941
Published in The Netherlands

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