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Dual-Band/GSM 3.6 V Integrated Power Amplifier
The MRFIC1859 is a dual-band, single supply RF Power Amplifier for GSM900/DCS1800 hand held radios. The on-chip spur free voltage generator reduces the number of external components by eliminating the need for a negative voltage supply. The device output power can be controlled open loop without the use of directional coupler and detection diode. The MRFIC1859 is General Packet Radio Service (GPRS) compatible. The device is packaged in a TQFP-32EP with exposed backside pad allowing excellent electrical and thermal performance through a solderable contact.
MRFIC1859
DUAL-BAND GSM 3.6 V IPA
SEMICONDUCTOR TECHNICAL DATA
* * * * *
Single Positive Supply Solution Input/Output External Matching High Power and Efficiency Typical 3.6 V Characteristics: Pout = 36.2 dBm, PAE = 53% for GSM Pout = 34 dBm, PAE = 43% for DCS Crosstalk Harmonic Leakage of -27 dBm Typical (GSM)
32 1
(Scale 2:1)
PLASTIC PACKAGE CASE 873E (TQFP-32EP)
ORDERING INFORMATION
Device MRFIC1859R2 Operating Temperature Range TC = -35 to 100C Package TQFP-32EP
Simplified Block Diagram
D1G B1G D2B B2B B23G D2G
InG
OutG
Negative and Positive Voltage Generator
VSS VP VSC
InD
OutD
B1D
D1D
D1B
B23D D2D
G2D
This device contains 21 active transistors.
(c) Motorola, Inc. 2000 Rev 4
MOTOROLA WIRELESS SEMICONDUCTOR SOLUTIONS - RF AND IF DEVICE DATA
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MRFIC1859
PIN CONNECTIONS
VSS 32 D2B 31 B2B 30 OutD 29 OutD Out D OutD 28 27 26 OutD 25
B23G 1 VP 2 Gnd 3 OutG 4 OutG 5 OutG 6 OutG 7 OutG 8
24 B23D 23 D2D 22 D2D 21 VSC 20 G2D 19 D1G 18 B1G 17 InG
9 M2G
10 D2G
11 D2G
12 D2G
13 D1D
14 D1B
15 B1D
16 InD
Exposed Pad (Gnd-on bottom)
MAXIMUM RATINGS
Rating Supply Voltage Symbol VD1B,D2B VD1G,D2G, D3G,D1D, D2D,D3D InG, InD OutG OutD TC Tstg RJC Value 6.0 Unit V
RF Input Power RF Output Power GSM Section DCS Section Operating Case Temperature Range Storage Temperature Range Thermal Resistance, Junction to Case
12 38 36 -35 to 100 -55 to 150 15
dBm dBm
C C C/W
NOTES: 1. Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the limits in the Recommended Operating Contitions or Electrical Characteristics tables. 2. Meets Human Body Model (HBM) 100 V and Machine Model (MM) 60 V. Additional ESD data available upon request.
RECOMMENDED OPERATING CONDITIONS
Characteristic Supply Symbol VD1B,D2B VD1G,D2G, D3G,D1D, D2D,D3D InG InD Min 2.8 Typ - Max 5.5 Unit V
Input Power GSM Input Power DCS
3.0 5.0
- -
10 12
dBm dBm
2
MOTOROLA WIRELESS SEMICONDUCTOR SOLUTIONS - RF AND IF DEVICE DATA
MRFIC1859
ELECTRICAL CHARACTERISTICS (VD1B, D2B = 3.6 V, VD1G,D2G,D3G = 3.6 V or VD1D,D2D,D3D = 3.6 V, Peak
measurement at 12.5% duty cycle, 4.6 ms period, TA = 25C, unless otherwise noted.)
Characteristic
GSM SECTION (Pin = 3.0 dBm) Frequency Range Output Power Power Added Efficiency Output Power @ Low Voltage (VD1G,D2G,D3G= 3.0 V) Harmonic Output 2fo 3fo Second Harmonic Leakage at DCS Output (Crosstalk isolation) Input Return Loss Output Power Isolation with Buffer On (Pin = 3.0 dBm, VD1B,D2B = 3.6 V, VD1G,D2G,D3G = 0 V) Output Power Isolation (Pin = 3.0 dBm, VD1B,D2B = 0 V, VD1G,D2G,D3G = 0 V) Noise Power in Rx Band 925 to 960 MHz (100 kHz measurement bandwidth) 925 to 935 MHz 935 to 960 MHz Negative Voltage (Pin = 2.0 dBm, VD1B, D2B = 3.0 V) Negative Voltage Settling time (Pin = 3.0 dBm, VD1B,D2B stepped from 0 to 3.0 V) Stability-Spurious Output (Pout = 5.0 to 35 dBm, Load VSWR = 6:1 all Phase Angle, Source VSWR = 3:1, at any phase angle Adjust VD1G,D2G,D3G for specified power) Load Mismatch Stress (Pout = 5.0 to 35 dBm, Load VSWR = 10:1 all phase angles, 5 seconds, Adjust VD1G,D2G,D3G for specified power) Positive Voltage (Pin = 3.0 dBm, VD1B = VD2B = 3.0 V) DCS SECTION (Pin = 5.0 dBm) Frequency Range Output Power Power Added Efficiency Output Power @ Low Voltage (VD1D,D2D,D3D= 3.0 V) Harmonic Output 2fo 3fo Input Return Loss Output Power Isolation with Buffer On (Pin = 5.0 dBm, VD1B,D2B = 3.6 V, VD1D,D2D,D3D = 0 V) Output Power Isolation (Pin = 5.0 dBm, VD1B,D2B = 0 V, VD1D,D2D,D3D = 0 V) Noise Power in Rx Band 1805 to 1880 MHz (100 kHz measurement bandwidth) Negative Voltage (Pin = 5.0 dBm, VD1B,D2B = 3.0 V) Negative Voltage Settling time (Pin = 5.0 dBm, VD1B,D2B stepped from 0 to 3.0 V) Stability-Spurious Output (Pout = 3.0 to 33 dBm, Load VSWR = 6:1 all Phase Angle, Source VSWR = 3:1, at any phase angle Adjust VD1D,D2D,D3D for specified power)
Symbol
Min
Typ
Max
Unit
BW Pout PAE Pout
880 35 45 33.5 - - -
- 36.2 53 34.7 -35 -60 -25 12 -8.0 -42
915 - - - -30 -45 -20 - -3.0 -
MHz dBm % dBm dBc
dBm dB dBm dBm dBm
|S11| Pon Poff NP
- - -
-90 -90 VSS TS Pspur - - - - 0.7 -
-67 -79 -4.85 2.0 -60 V s dBc
No Degradation in Output Power Before and After Test VP 6 10 - V
BW Pout PAE Pout
1710 33 35 31.5 - -
- 34 43 32.4 -40 -35 12 -8.0 -36 -85 - 0.7 -
1785 - - - -35 -30 - -2.0 - -71 -4.85 2.0 -60
MHz dBm % dBm dBc
|S11| Pon Poff NP VSS TS Pspur
- - - - - - -
dB dBm dBm dBm V s dBc
MOTOROLA WIRELESS SEMICONDUCTOR SOLUTIONS - RF AND IF DEVICE DATA
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MRFIC1859
ELECTRICAL CHARACTERISTICS (continued) (VD1B, D2B = 3.6 V, VD1G,D2G,D3G = 3.6 V or VD1D,D2D,D3D = 3.6 V, Peak
measurement at 12.5% duty cycle, 4.6 ms period, TA = 25C, unless otherwise noted.)
Characteristic
DCS SECTION (continued) (Pin = 5.0 dBm) Load Mismatch Stress (Pout = 3.0 to 33 dBm, Load VSWR = 10:1 all phase angles, 5 seconds, Adjust VD1D,D2D,D3D for specified power) Positive Voltage (Pin = 5.0 dBm, VD1B = VD2B = 3.0 V)
Symbol
Min
Typ
Max
Unit
No Degradation in Output Power Before and After Test VP 6 10 - V
PIN FUNCTION DESCRIPTION
Pin No. 1 Symbol B23G I/O I Description GSM Bias for 2nd and 3rd stage Functionality Bias pin of GSM second and third stages. Biasing circuit is made of an internal resistor connected to RF transistor gate, and in series with a current source, connected to VSS (Pin 32). An external resistor allows to tune biasing point for best gain (Class AB). To switch off GSM line-up, setting this pin (and Pin 18) to high impedance, which will apply VSS (-5.0 V) to the gates, i.e., a voltage two times lower than FET threshold voltage. A buffer amplifier is designed to produce the required negative voltage, based on RF signal amplification and rectification. Also a positive voltage is generated in the same way, with rectification and a voltage doubler. This voltage supplies an op amp in order to drive a NMOS as drain switch. Refer to application schematic, with MC33170 and MTSF3N02 (products of On Semiconductor).
2
VP
O
Positive voltage
3 4,5,6,7,8
Gnd OutG O
Ground GSM output RF output and power supply for output GSM stage. Supply voltage is provided through those five pins. An external matching network is required to provide optimum load impedance.
9 10,11,12 D2G
N.C. I GSM 2nd stage drain Power supply for GSM second stage, and inter-stage matching. Wire bonds and pins form the required inductor for optimum inter-matching tuning. Make note that decoupling capacitor on those pins needs to be placed as close as possible to the pins. Refer to application schematic for component value. Power supply for DCS first stage, and inter-staging matching. This pin associated with a printed line (80 ) forms the required inductor for a proper match. Power supply for buffer amplifier first stage, and inter-staging matching. This pin, associated with a printed line (80 ) forms the required inductor for a proper match. Same function as Pin 18 for DCS amplifier. RF input for DCS amplifier. A series inductor or line and a parallel inductor are required for a proper matching to 50 and maximum gain. See application circuit. RF input for GSM amplifier. An inductor and a capacitor are required for a proper matching to 50 and maximum gain. See application circuit. Bias pin of GSM first stage and associated buffer stage. Biasing circuit is made of an internal resistor connected to RF transistor gate, and in series with a current source, connected to VSS (Pin 32). An external resistor allows to tune biasing point for best gain (Class AB). See comments on Pin 1. Power supply for GSM first stage, and inter-stage matching. This pin, associated with a printed line (80 ) form the required inductor for a proper match. Access to DCS 2nd stage gate. A shunt capacitor connected to this pin contributes to the inter-stage matching between 1st and 2nd DCS stages. An opened drain transistor connected to this pin, with VSS as gate voltage, gives a checking signal for negative voltage generation. Used in application circuit to forbid on state to the NMOS Drain switch when VSS is not working. Prevents IC degradation when bias is not present. This pin is not used with MC33170 which has its own protection circuit.
13 14 15 16 17 18
D1D D1B B1D InD InG B1G
I I I I I I
DCS 1st stage drain Buffer 1st stage drain DCS 1st stage Bias DCS RF Input GSM RF Input GSM 1st stage Bias
19 20 21
D1G G2D VSC
I I O
GSM 1st stage drain DCS 2nd stage gate Check for Negative voltage
4
MOTOROLA WIRELESS SEMICONDUCTOR SOLUTIONS - RF AND IF DEVICE DATA
MRFIC1859
PIN FUNCTION DESCRIPTION (continued)
Pin No. 22,23 24 25,26,27, 28,29 30 31 32 Symbol D2D B23D OutD I/O I I O Description DCS 2nd stage drain DCS Bias for 2nd and 3rd stage DCS RF Output Functionality Power supply for DCS driver stage, and inter-staging matching. These pins form the required inductor for a proper match. Same as Pin 1 for DCS amplifier. RF output and power supply for output DCS stage. Supply voltage is provided through those five pins. An external matching network is required to provide optimum load impedance. Like Pins 1, 15, and 18, this is a bias pin. Pin 30 is used to bias 2nd stage of buffer amplifier. Drain supply and matching of buffer amplifier to maximize VSS and VP voltages. A buffer amplifier is designed to produce the required negative voltage, based on RF signal amplification with a two stages wide band amplifier and rectification of the resulting signal. An external zener diode is used to regulate this voltage and provide to the gates a stabilized biasing voltage. VSS is also used to switch off the unused amplifier. Refer to Bias Pins 1, 18 and 15, 24. The bottom pad of the TQFP-32EP package is used for electrical/RF grounding and thermal dissipation. The PCB pattern where it fits has to be tailored for good ground and thermal continuity (with many ground via holes).
B2B D2B VSS
I I O
Buffer 2nd state Bias Buffer 2nd stage Drain Negative Voltage
Exposed Pad
Gnd
I
Main Gnd
MOTOROLA WIRELESS SEMICONDUCTOR SOLUTIONS - RF AND IF DEVICE DATA
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MRFIC1859
Figure 1. Application Schematic
Vbat Vramp CE R8 10k MC33170* Band Select Tx EN 1 BS 2 TxEN 3 BGSM 4 BDCS 5 VDB 6 Gnd 7V bat CE VSS 13 12 Out 11 VP 10 InV 9 NinV LDO 8 14 MTSF3N02* S S S G C20 N.C. R6 10k D D D D C23 100 nF
R7 10k
C19 100 nF C16 1.0 nF
C11 3.3 pF
C18 47 pF
C2 3.9 pF
C6 1.0 pF C9 47 pF T2 47 mm
T5 1.5 mm R2** 6.8 k 1 2 3 4 5
R1 2.2 k
T6 Exposed Pad (Gnd - on bottom) 24 23 22 21 N.C. C15 12 pF C8 6.8 pF T9 11 mm R3** 5.6 k
32 31 30 29 28 27 26 25
MRFIC1859
20 19 18 17
Out GSM
C5 47 pF C4 4.7 pF
T1 6.0 mm C3 12 pF
2.5 mm T4
6 7 8 9 10 11 12 13 14 15 16
R9 1.5 k
Out DCS
L3 56 nH
C7 22 pF
1.5 mm
T3 22 mm
C10 22 pF
C17 47 pF R5 12 k L1 15 nH C21 5.6 pF In GSM
N.C. T1, T2, T3, T4 Zc = 50 T5, T6 Zc = 30 T7, T8, T9, T10 Zc = 80 Substrate FR4 Er = 4.5 C2, C3, C4 are high Q capacitors * Products of ON Semiconductor ** 1% tolerance
R4 8.2 k T8 12 mm
T7 5.5 mm
C14 47 pF
T10 4.0 mm
In DCS
C12 10 nF
C13 12 pF
C1 47 pF
C22 47 pF
L2 2.7 nH
6
MOTOROLA WIRELESS SEMICONDUCTOR SOLUTIONS - RF AND IF DEVICE DATA
MRFIC1859
GSM TYPICAL CHARACTERISTICS
Figure 2. Output Power versus Frequency
38 37.5 37 36.5 Pout (dBm) PAE (%) 36 35.5 35 34.5 34 33.5 33 880 885 890 895 900 3.0 V TA = 25C Pin = 3.0 dBm 905 910 915 3.6 V Vbat = 4.2 V 55 54 53 52 51 50 49 48 47 46 880 885 890 895 900 TA = 25C Pin = 3.0 dBm 905 910 915 3.0 V Vbat = 4.2 V 3.6 V
Figure 3. Power Added Efficiency versus Frequency
f, FREQUENCY (MHz)
f, FREQUENCEY (MHz)
Figure 4. Output Power versus Frequency
35.5 35 Pout (dBm) 34.5 34 33.5 33 880 TA = -35C 25C Pout (dBm) 36 35.5 35 34.5 880 37 36.5
Figure 5. Output Power versus Frequency
TA = -35C 25C
85C Vbat = 3.0 V Pin = 3.0 dBm 885 890 895 900 905 910 915
85C
Vbat = 3.6 V Pin = 3.0 dBm 885 890 895 900 905 910 915
f, FREQUENCY (MHz)
f, FREQUENCY (MHz)
Figure 6. Output Power versus Frequency
38 37.5 Pout (dBm) 37 36.5 36 35.5 880 85C TA = -35C 25C PAE (%) 58 56 54
Figure 7. Power Added Efficiency versus Frequency
TA = -35C
25C 52 50 85C Vbat = 3.6 V Pin = 3.0 dBm 885 890 895 900 905 910 915
Vbat = 4.2 V Pin = 3.0 dBm 885 890 895 900 905 910 915
48 46 880
f, FREQUENCY (MHz)
f, FREQUENCY (MHz)
MOTOROLA WIRELESS SEMICONDUCTOR SOLUTIONS - RF AND IF DEVICE DATA
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MRFIC1859
GSM TYPICAL CHARACTERISTICS
Figure 8. Second Harmonics versus Frequency
46 44 42 H2 (dBc) 40 38 36 34 32 30 880 885 890 895 900 Vbat = 3.6 V Pin = 3.0 dBm 905 910 915 85C TA = 25C H3 (dBc) -35C 67 66 65 64 63 62 61 60 59 58 880 885 890 895 900 85C Vbat = 3.6 V Pin = 3.0 dBm 905 910 915 25C TA = -35C
Figure 9. Third Harmonics versus Frequency
f, FREQUENCY (MHz)
f, FREQUENCEY (MHz)
Figure 10. Positive Voltage Generator Output versus Frequency
13 12 XTALK (dBm) TA = -35C Vpos (V) 11 25C 10 85C 9.0 8.0 880 Vbat = 3.6 V Pin = 3.0 dBm 885 890 895 900 905 910 915 -22 -23 -24 -25 -26 -27 -28 -29 -30 880 885 TA = -35C
Figure 11. Crosstalk versus Frequency
85C 25C Vbat = 3.6 V Pin = 3.0 dBm 890 895 900 905 910 915
f, FREQUENCY (MHz)
f, FREQUENCY (MHz)
40 35 Pout , OUTPUT POWER (dBm) 30 25 20 15 10 5.0 0 -5.0 -10 0 0.5
Figure 12. Output Power versus Vramp
TA = -35C 85C TOTAL CURRENT (A)
3.0 2.5
Figure 13. Total Current versus Vramp
TA = -35C 2.0 85C 1.5 1.0 0.5 0 f = 897.5 MHz Vbat = 3.6 V Pin = 3.0 dBm 0 0.5 1.0 Vramp (V) 1.5 2.0 2.5 25C
25C
f = 897.5 MHz Vbat = 3.6 V Pin = 3.0 dBm 1.0 Vramp (V) 1.5 2.0 2.5
8
MOTOROLA WIRELESS SEMICONDUCTOR SOLUTIONS - RF AND IF DEVICE DATA
MRFIC1859
DCS TYPICAL CHARACTERISTICS
Figure 14. Output Power versus Frequency
36 35 34 Pout (dBm) 33 32 31 30 1710 3.0 V 42 TA = 25C Pin = 5.0 dBm 1725 1740 1755 1770 1785 41 40 1710 1725 1740 1755 TA = 25C Pin = 5.0 dBm 1770 1785 Vbat = 4.2 V 3.6 V PAE (%) 44 3.0 V 43 47 46 45 3.6 V Vbat = 4.2 V
Figure 15. Power Added Efficiency versus Frequency
f, FREQUENCY (MHz)
f, FREQUENCY (MHz)
Figure 16. Output Power versus Frequency
33.5 33 32.5 Pout (dBm) 32 31.5 31 30.5 30 1710 1725 1740 1755 Vbat = 3.0 V Pin = 5.0 dBm 1770 1785 TA = -35C Pout (dBm) 25C 35 34.5 34 33.5 33 32.5 32 1710
Figure 17. Output Power versus Frequency
TA = -35C 25C 85C
85C
Vbat = 3.6 V Pin = 5.0 dBm 1725 1740 1755 1770 1785
f, FREQUENCY (MHz)
f, FREQUENCY (MHz)
Figure 18. Output Power versus Frequency
36 35.5 Pout (dBm) 35 34.5 34 33.5 1710 85C TA = -35C 25C PAE (%) 48 46 44 42 40 Vbat = 4.2 V Pin = 5.0 dBm 1725 1740 1755 1770 1785 38 36 1710
Figure 19. Power Added Efficiency versus Frequency
TA = -35C 25C 85C
Vbat = 3.6 V Pin = 5.0 dBm 1725 1740 1755 1770 1785
f, FREQUENCY (MHz)
f, FREQUENCY (MHz)
MOTOROLA WIRELESS SEMICONDUCTOR SOLUTIONS - RF AND IF DEVICE DATA
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MRFIC1859
DCS TYPICAL CHARACTERISTICS
Figure 20. Second Harmonics versus Frequency
49 47 45 H2 (dBc) 43 41 39 37 35 1710 1725 1740 1755 Vbat = 3.6 V Pin = 5.0 dBm 1770 1785 -35C TA = 25C 85C H3 (dBc) 46 43 40 25C 37 34 31 28 25 1710 1725 1740 1755 Vbat = 3.6 V Pin = 5.0 dBm 1770 1785 85C TA = -35C
Figure 21. Third Harmonics versus Frequency
f, FREQUENCY (MHz)
f, FREQUENCEY (MHz)
Figure 22. Positive Voltage Generator Output versus Frequency
12 Pout , OUTPUT POWER (dBm) 11 TA = -35C Vpos (V) 10 9.0 8.0 7.0 1710 25C 85C Vbat = 3.6 V Pin = 5.0 dBm 40 35 30 25 20 15 10 5.0 0 1725 1740 1755 1770 1785 -5.0 0 0.5
Figure 23. Output Power versus Vramp
TA = -35C
85C
25C
f = 1747.5 MHz Vbat = 3.6 V Pin = 5.0 dBm 1.0 Vramp (V) 1.5 2.0 2.5
f, FREQUENCY (MHz)
2.0 1.8 1.6 TOTAL CURRENT (A) 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 0 0.5
Figure 24. Total Current versus Vramp
TA = -35C 85C 25C
f = 1747.5 MHz Vbat = 3.6 V Pin = 5.0 dBm 1.0 Vramp (V) 1.5 2.0 2.5
10
MOTOROLA WIRELESS SEMICONDUCTOR SOLUTIONS - RF AND IF DEVICE DATA
MRFIC1859
APPLICATIONS INFORMATION
Design Philosophy The MRFIC1859 is a dual-band single supply RF integrated power amplifier designed for use in GSM900/DCS1800 handheld radios under 3.6 V operation. With matching circuit modifications, it is also applicable for use in triple band GSM900/DCS1800/PCS1900 equipment. Typical performances in GSM/DCS at 3.6 V are: GSM: 35.8 dBm with 53% PAE and, DCS: 34 dBm with 43% PAE. It features a large band (900 to 1800 MHz) internal Negative Voltage Generator based on RF rectification of the input carrier after its amplification by two dedicated buffer stages (See Simplified Block Diagram). This method eliminates spurs found on the output signal when using dc/dc converter type negative voltage generators, either on or off chip. The buffer generates also a step-up positive voltage, which can be used to drive a NMOS drain switch. External Circuit Considerations The MRFIC1859 can be tuned by changing the values and/or positions of the appropriate external components (see Figure 1: Application Schematic). While tuning the RF line-up, it is recommended to apply external negative supply in order to prevent any damage to the power amplifier stages. Poor tuning on the input may not provide enough RF power to operate the negative voltage generator properly. Input matching is a shunt-C, series-L, low pass structure for GSM and a shunt-L, series-L high pass structure for DCS. It should be optimized at the rated input power (e.g. 3.0 dBm in GSM, 5.0 dBm in DCS). Since the input lines feed both 1st stages and 1st stage buffers, input matching should be iterated with buffer and Q1 drain matching. Note that dc blocking capacitors are included on chip. First stage buffer amplifier is tuned with a short 80 microstrip line which may be replaced by a chip inductor. Second stage buffer amplifier is supplied and matched through a discrete chip inductor. Those two elements are tuned to get the maximum output from voltage generator. The overall typical buffer current (DB1 + DB2) is about 60 mA in GSM and 100 mA in DCS. However, the negative generator needs a settling time of 1.0 s (see burst mode paragraph). During this transient period of time, both stages are biased to IDSS, which is about 200 mA each. The step-up positive voltage available at Pin 2, which is approximately 10 V in each band, can be used to drive a NMOS drain switch for best performances. Q1 drains are supplied and matched through 80 printed microstrip lines that could be replaced by discrete chip inductors as well. Their lengths (or equivalent inductor values) are tuned by sliding the RF decoupling capacitors along to get the maximum gain on the first stages. Q2 drains are supplied through 60 printed microstrip lines that contribute also to the interstage matching in order to optimum drive to the final stages. The line length for Q2G and Q2D is small, so replacing it with discrete inductors is not practical. Q3 stages are fed via 50 printed microstrip lines that must handle the high supply current of that stages (2.0 Amp peak) without significant voltage drop. This line can be buried in an inner layer to save PCB space or be a discrete RF choke. Output matching is accomplished in both bands with two stages low pass networks. Easy implementation is achieved with shunt capacitors mounted along a 50 microstrip transmission line. Value and position are chosen to reach a load line of 2.0 while conjugating the device output parasitics. The networks must also properly terminate the second and third harmonic level. Use of high-Q capacitors for the first output matching capacitor circuits is recommended in order to get the best output power and efficiency performances. Note: the choice of output matching capacitor type and supplier will affect H2 and H3 level and efficiency, because of series resonant frequency. Tuning Methodology The following section gives the user some guidelines and hints to tune and optimize the MRFIC1859 operation inside their own radio PCB. First of all, one must keep in mind that negative and positive voltage generation is based on RF carrier rectification. This means that RF input signal must always be present when running the part as a standalone solution. Therefore, in order to ease the tuning phase, it is recommended to apply the negative voltage externally in order to avoid any damage to the large RF MESFET transistors. This is particularly true if one uses the complete application with MC33170 (product of On Semiconductor) as control IC to do the optimization. In that case, both negative and positive voltage should be provided externally. The RF decoupling capacitors have been selected as 47 pF for GSM band (C17, C14, C22, C9. C1, and C8) and 22 pF or 12 pF for DCS band (C10, C15, and C13). But those can be optimized depending on their size and source, for example 12 pF were used at some places for DCS to provide better decoupling of the harmonics too, thus providing some extra performance. The recommended tuning procedure consists of several steps that need to be performed in sequential order. Several iterations can be performed if appropriate. Due to low interaction between line-ups, each band can be tuned independently. * Optimize the buffer operation using D1B (T8 line) and D2B matching (L3 inductor). Simultaneously, tune GSM or DCS input matching using L1, C21 or L2, T10, respectively. Check the margin on Pin to generate VSS and VP (those voltages should still meet their specification with a 5.0 dB reduction in Pin). A small shunt capacitor can be placed on VP to maximize that voltage. * Optimize RF line up linear gain using D1G, D2G matching (T9 line) or D1D, D2D, G2D matching (T7 line, C8) for GSM or DCS line-up, respectively. The goal is to maximize and center small signal gain. Pin has to be reduced for this exercise, hence the negative voltage needs to be applied externally. A broad band measurement is helpful to visualize the frequency response. Linear gain should peak at around 40 dB for GSM and 32 dB for DCS. The input matching has to be checked again and eventually refined during this step. * Optimize output matching using T4, C3, T1, C4 and T2 for GSM or T6, C2, T5, C6, T3 for DCS, respectively. Those elements set the Pout/PAE trade-off and harmonics rejection performance.
MOTOROLA WIRELESS SEMICONDUCTOR SOLUTIONS - RF AND IF DEVICE DATA
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MRFIC1859
* Finally, one can iterate some of the above steps to fine tune RF behavior and also to find the best configuration for Cross-Talk and Harmonics content reduction. For example, D2B inductor L3 and VSS decoupling capacitor C11 have a small influence on the GSM second harmonic leaking through the DCS output. The nominal impedance seen from the IPA package pins have been measured on the demoboard (after removing the MRFIC1859) and are listed in the following table. They can be taken as a starting point for the optimization. Also this gives the equivalent lumped element if one uses a lumped element instead of microstrip line. Impedance on the different GSM I/Os: (expressed in at 900 MHz) - - - - - - InG = 16.2 + j83.5 OutG = 1.9 - j2.3 D2G = close to 0 since decoupled as short as possible D1G = 1 + j19.8 (3.5 nH) D1B = 1.2 + j28.7 (5.0 nH) D2B = infinite since 56 nH behaves as choke The NMOS is used as a ballast transistor whose drain-source resistance is controlled by Vramp. This allows to supply the PA with a voltage from 0 V (Vramp = 0 V) to Vbat (Vramp = 2.0 V) and hence to control the output power. Such a way of control provides an excellent predictability of the RF output power (since the output voltage is proportional to the drain voltage) and eliminates the need for a power or current detection loop. The band selection is achieved by setting the BS pin of the MC33170 to 0 V (GSM) or 1.0 V (DCS), hence biasing the GSM or DCS transistors through BiasGSM and BiasDCS pins. Burst Mode In order to perform burst mode measurements, the following time can be used as a guideline. Figure 25.
2.0 V CE 0V
Impedance on the different DCS I/Os: (expressed in at 1750 MHz) - - - - - - - InD = 12.5 + j36.5 OutD = 3.6 - j4.4 D2D = close to 0 since decoupled as short as possible G2D = 0.9 + j6.8 (0.64 nH) D1D = 1.1 + j20.8 (1.9 nH) D1B = 8.8 + j84.7 (7.6 nH) D2B = infinite since 56 nH behaves as choke
2.0 V TxEn (& Pin) 0V 10 s 2.0 V Vramp 0V 1.0 s
One should note that except for RFin/RFout impedance, all others should be "in theory" pure reactive shunt elements. The fact that their resistive part is not zero is linked to the finite quality factor of the equivalent inductor and also to the limited accuracy of the measurement (when close to the Smith chart border). Control Considerations The MRFIC1859 application uses drain control technique developed for our generations of GaAs IPAs. This method relies on the fact that for an RF power amplifier operating in saturation mode, the RF output power is proportional to the square of the Amplifier drain voltage: Pout (Watt) = k * VD (V) * VD (V). A dedicated control IC MC33170 has been designed to manage all those control, biasing and band selection functions. When the emitting order is sent (TxEn = High), the MC33170 activates the power supply VDbuf of the negative voltage generator NVG (VDbuf = Vbat), involving the presence of Vneg as well as a positive VP of about 9.0 V. Once Vneg detected and regulated at -5.0 V, the MC33170 enables a N-channel MOSFET to be driven.
- First the MC33170 must be awaken through CE to activate its Low Drop Out Regulator. The BS pin has also to be set according to the selected frequency band. - Then TxEn is set high which supply the buffer stages and activates the Negative and Positive Voltage Generation. TxEn signal can be used to switch the input power (using a driver or attenuator) in order to provide higher isolation for on/off burst dynamic. - Vramp (Pin 1) can be applied soon after TxEn since the internal negative voltage generator settles in less than 1.0 s. References (Motorola Application Notes) AN1599 - Power Control with the MRFIC0913 GaAs Integrated Power Amplifier and MC33169 Support IC. AN1697 - GSM900/DCS1800 Dual-Band 3.6 V Power Amplifier Solution with Open Loop Control Scheme.
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MOTOROLA WIRELESS SEMICONDUCTOR SOLUTIONS - RF AND IF DEVICE DATA
MRFIC1859
NOTES
MOTOROLA WIRELESS SEMICONDUCTOR SOLUTIONS - RF AND IF DEVICE DATA
13
MRFIC1859
NOTES
14
MOTOROLA WIRELESS SEMICONDUCTOR SOLUTIONS - RF AND IF DEVICE DATA
MRFIC1859
OUTLINE DIMENSIONS
PLASTIC PACKAGE CASE 873E-02 (TQFP-32EP) ISSUE A 0.2 C A-B D
4X
D D/2 D
24
q2
G G
q1
A A2
R1 R2
25
16
A
B
A1
S
q
L (L1)
0.25
GAGE PLANE
q3
E1 DETAIL F E1/2
E
E/2
PLATING
BASE METAL
32
9
c1 6
1 8
D1/2 D1
4X
0.2 H A-B D F H
NOTES: 1. DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 3. DATUMS A, B AND D TO BE DETERMINED AT DATUM PLANE H. 4. DIMENSIONS D1 AND E1 DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.25-MM PER SIDE. D1 AND E1 ARE MAXIMUM PLASTIC BODY SIZE DIMENSIONS INCLUDING MOLD MISMATCH. 5. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL NOT CAUSE THE LEAD WIDTH TO EXCEED THE MAXIMUM b DIMENSION BY MORE THAN 0.08-MM. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN A PROTRUSION AND ADJACENT LEAD IS 0.07-MM 6. EXACT SHAPE OF CORNERS IS OPTIONAL.
C
SEATING PLANE
4X
e/2 e
32X
0.08 C b
M
28X
0.08 J
C A-B D J
M
EXPOSED FLAG
N
DIM A A1 A2 b b1 C C1 D D1 e E E1 L L1 M N R1 R2 S
VIEW J-J
MOTOROLA WIRELESS SEMICONDUCTOR SOLUTIONS - RF AND IF DEVICE DATA
IIIII IIII IIIII IIII IIIII
(b) SECTION G-G
q q1 q2 q3
MILLIMETERS MIN MAX --- 1.13 0.039 0.089 0.95 1.05 0.17 0.27 0.17 0.23 0.09 0.2 0.09 0.16 7 BSC 5 BSC 0.5 BSC 7 BSC 5 BSC 0.45 0.75 1 REF 2.09 2.19 2.09 2.19 0.08 --- 0.08 0.2 0.2 --- 0 7 0 --- 11 13 11 13
b1
c
15
MRFIC1859
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MOTOROLA WIRELESS SEMICONDUCTOR SOLUTIONS - RF AND IF DEVICE DATA
MRFIC1859/D

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