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| Preliminary Technical Data FEATURES Low offset voltage (VOS): 50 V max Very Low Voltage Noise: 1nV/Hz max @ 100Hz High Gain (hFE): 500 min at IC = 1mA 300 min at IC = 1A Excellent Log Conformance: rBE = 0.3 Low Offset Voltage Drift: 0.1 V/C max High Gain Bandwidth Product: 200MHz Low Noise, Matched Dual Monolithic Transistor MAT12 PIN CONFIGURATION www..com Note: Substrate is connected to case on TO-78 package. Substrate is normally connected to the most negative circuit potential, but can be floated GENERAL DESCRIPTION The design of the MAT12 series of NPN dual monolithic transistors is optimized for very low noise, low drift and low rBE. Exceptional characteristics of the MAT12 include offset voltage of 50 V max and high current gain (hFE) which is maintained over a wide range of collector current. Device performance is specified over the full temperature range as well as at 25C. Input protection diodes are provided across the emitter-base junctions to prevent degradation of the device characteristics due to reverse-biased emitter current. The substrate is clamped to the most negative emitter by the parasitic isolation junction created by the protection diodes. This results in complete isolation between the transistors. The MAT12 is ideal for applications where low noise is a priority. The MAT12 can be used as an input stage to make an amplifier with noise voltage of less than 1.0 nV/Hz at 100 Hz. Other applications, such as log/antilog circuits, may use the excellent logging conformity of the MAT12. Typical bulk resistance is only 0.3 to 0.4 . The MAT12 electrical characteristics approach those of an ideal transistor when operated over a collector current range of 1A to 10 mA. Rev. PrA Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c)2010 Analog Devices, Inc. All rights reserved. MAT12 SPECIFICATIONS ELECTRICAL CHARACTERISTICS; VCB = 15V VCB = 15 V, IO = 10A, TA = 25C, unless otherwise specified. Table 1. Parameter Current Gain Symbol hFE Conditions IC = 1mA (note 1) -25CTA+85C IC = 100A -25CTA+85C IC = 10A -25CTA+85C IC = 1A -25CTA+85C 10A IC 1mA (note 2) IC = 1mA, VCB = 0 (note 3) f O= 10Hz f O= 100Hz f O= 1kHz f O= 10kHz Preliminary Technical Data w w w . D a Min 500 325 500 275 400 225 300 200 Typ 605 590 550 485 Max Unit Current Gain Match Noise Voltage Density hFE eN 0.5 2 % 1.6 0.9 0.85 0.85 2 1 1 1 nV/Hz nV/Hz nV/Hz nV/Hz Offset Voltage VOS VCB = 0, 1A IC 1mA -25CTA+85C 0 VCB VMAX (note 4) 1A IC 1mA (note 5) 1A IC 1mA (note 5), VCB=0 10 50 70 25 V uV V Offset Voltage Change vs. VCB VOS/VCB 10 Offset Voltage Change vs. IC Offset Voltage Drift VOS/IC VOS/T 5 0.08 0.03 40 25 0.3 0.3 V V/ C V/ C V -25CTA+85C -25CTA+85C, VOS trimmed to zero Breakdown Voltage Gain-Bandwidth Product Collector-Base Leakage Current BVCEO fT ICBO IC = 100mA, VCE = 10V VCB=VMAX -25CTA+85C VCC=VMAX (notes 6,7) -25CTA+85C VBE=0 (notes 6,7) -25CTA+85C 200 25 2 35 3 35 3 200 MHz pA nA pA nA pA nA Collector-Collector Leakage Current ICC 200 Collector-Emitter Leakage Current ICES 200 Rev. PrA | Page 2 of 4 Preliminary Technical Data Input Bias Current IB IC = 10A -25CTA+85C IC = 10A -25CTA+85C IC=10A (note 6) -25CTA+85C www..com MAT12 nA nA nA nA 25 45 0.6 8 Input Offset Current IOS Input Offset Current Drift IOS/T 40 90 pA/C Offset Current Change vs. VCB IOS/VCB 0 VCB VMAX (note 4) 30 70 pA/V Collector Saturation Voltage Output Capacitance Bulk Resistance Collector-Collector Capacitance VCE(SAT) COB rBE CCC IC = 1mA, IB=100A VCB=15V, IE=0 10AIC10mA (note6) VCC = 0 0.05 23 0.3 35 0.1 0.5 V pF pF Notes: 1. 2. 3. 4. 5. 6. 7. Current gain is guaranteed with Collector-Base Voltage (VCB) swept from 0 to VMAX at the indicated collector currents. Current Gain Match (hFE) defined as: hFE = (100(IB)( hFE min)/IC) Noise Voltage Density is guaranteed, but not 100% tested This is the maximum change in VOS as VCB is swept from 0V to 40V. Measured at IC=10A and guaranteed by design over the specified range of IC Guaranteed by Design ICC and ICES are verified by measurement of ICBO Rev. PrA | Page 3 of 4 MAT12 ABSOLUTE MAXIMUM RATINGS Table 2. Parameter Collector-Base Voltage (BVCBO) Collector-Emitter Voltage (BVCEO) Collector-Collector Voltage (BVCC) Emitter-Emitter Voltage (BVEE) Collector Current (IC) Emitter Current (IE) Storage Temperature Range H Packages Operating Temperature Range Junction Temperature Range RM, CP Packages Lead Temperature (Soldering, 60 sec) 1 Preliminary Technical Data THERMAL RESISTANCE Rating 40 V 40V 40V 40V 20 mA 20 mA -65C to +150C -25C to +85C -65C to +150C 300C www..com JA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. Table 3. Thermal Resistance Package Type TO-78 (H) JA TBD JC TBD Unit C/W ESD CAUTION Differential input voltage is limited to 5 V or the supply voltage, whichever is less. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. (c)2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. PR09044-0-4/10(PrA) Rev. PrA | Page 4 of 4 |
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