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Engineering Specification
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Engineering Specification 15.0 inches SXGA+ Color TFT/LCD Module Model Name:ITSX93C
Document Control Number : OEM93C-04
Note:Specification is subject to change without notice. Consequently it is better to contact to IBM before proceeding with the design of your product incorporating this module.
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Display Business Unit International Business Machines Corporation
(C) Copyright IBM Corp. 1999 All Rights reserved. August 27,1999 OEM93C-04
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Engineering Specification
i Contents
i Contents ii Record of Revision 1.0 Handling Precautions 2.0 General Description 2.1 Characteristics 2.2 Functional Block Diagram 3.0 Absolute Maximum Ratings 4.0 Optical Characteristics 5.0 Signal Interface 5.1 Connectors 5.2 Interface Signal Connector 5.3 Interface Signal Description 5.4 Interface Signal Electrical Characteristics 5.5 Signal for Lamp connector 6.0 Pixel format image 7.0 Parameter guide line for CFL Inverter 8.0 Interface Timings 8.1 Timing Characteristics 8.2 Timing Definition 9.0 Power Consumption 10.0 Power ON/OFF Sequence 11.0 Mechanical Characteristics
(C) Copyright IBM Corp. 1999 All Rights reserved. August 27,1999 OEM93C-04 2/26
Engineering Specification
ii Record of Revision
Date March 26,1999
Document Revision OEM93C-01 (Preliminary)
Page All
Summary First Edition for customer. Based on Initial Internal Spec. as of March 8,1999 Based on Mechanical Drawing as of Draft March 3,1999. Updated information as of March 23. Lamp cable length:75.5 mm To update P/N for connector. To add an explanation for UL. To update White Luminance, Optical Rise Time/Fall Time, and Power consumption. To correct Absolute Maximum Rating For Shock. To update Optical Charastaristics. To correct Signal Name of Pin #15. To update LVDS Macro AC characteristics. To update White Luminance and CFL Ignition Voltage. To add a refference data. To update Timing Characteristics. To update Timing Definition. To update Power consumption. To update DWGs. Lamp cable length:95 mm Based on Internal Spec. as of June 22,1999. Based on Mechanical Drawing as of July 5,1999. To update DWGs for EMI solution. Based on Mechanical Drawing as of August 18,1999.
April 13,1999 July 9,1999
OEM93C-02 (Preliminary) OEM93C-03
7, 10 27 4 6 8 9 11 16 18 19 20 21 23 25, 26
August 27,1999
OEM93C-04
25 , 26
(C) Copyright IBM Corp. 1999 All Rights reserved. August 27,1999 OEM93C-04 3/26
Engineering Specification
1.0 Handling Precautions
1) Since front polarizer is easily damaged, pay attention not to scratch it. 2) Be sure to turn off power supply when inserting or disconnecting from input connector. 3) Wipe off water drop immediately. Long contact with water may cause discoloration or spots. 4) When the panel surface is soiled, wipe it with absorbent cotton or other soft cloth. 5) Since the panel is made of glass, it may break or crack if dropped or bumped on hard surface. 6) Since CMOS LSI is used in this module, take care of static electricity and insure human earth when handling. 7) Do not open nor modify the Module Assembly. 8) Do not press the reflector sheet at the back of the module to any directions. 9) In case if a Module has to be put back into the packing container slot after once it was taken out from the container, do not press the center of the CFL Reflector edge. Instead, press at the far ends of the CFL Reflector edge softly. Otherwise the TFT Module may be damaged. 10) At the insertion or removal of the Signal Interface Connector, be sure not to rotate nor tilt the Interface Connector of the TFT Module. 11) After installation of the TFT Module into an enclosure ( Notebook PC Bezel, for example), do not twist nor bent the TFT Module even momentary. At designing the enclosure, it should be taken into consideration that no bending/twisting forces are applied to the TFT Module from outside. Otherwise the TFT Module may be damaged. 12)Small amount of materials having no flammability grade is used in the LCD module. The LCD module should be supplied by power complied with requirements of Limited Power Source (2.11, IEC60950 or UL1950), or be applied exemption conditions of flammability requirements (4.4.3.3, IEC60950 or UL1950) in an end product. 13)The LCD module is designed so that the CFL in it is supplied by Limited Current Circuit (2.4, IEC60950 or UL1950). Do not connect the CFL in Hazardous Voltage Circuit.
The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by IBM for any infringements of patents or other right of the third partied which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of IBM or others. The information contained herein may be changed without prior notice. It is therefore advisable to contact IBM before proceeding with the design of equipment incorporating this product.
(C) Copyright IBM Corp. 1999 All Rights reserved. August 27,1999 OEM93C-04 4/26
Engineering Specification
2.0 General Description
This specification applies to the 15.0 inches- Color TFT/LCD Module 'ITSX93C'. This module is designed for a display unit of notebook style personal computer. The screen format and electrical interface are intended to support the SXGA+(1400(H) x 1050(V)) screen. Support color is native 262K colors(RGB 6-bit data driver). All input signals are LVDS(Low Voltage Differential Signaling) interface compatible. This module does not contain an inverter card for backlight.
(C) Copyright IBM Corp. 1999 All Rights reserved. August 27,1999 OEM93C-04 5/26
Engineering Specification
2.1 Characteristics
The following items are characteristics summary on the table under 25 CHARACTERISTICS ITEMS Screen Diagonal [mm] Pixels H x V Active Area [mm] Pixel Pitch [mm] Pixel Arrangement Weight [grams] Physical Size [mm] Display Mode Support Color White Luminance [cd/m2] Design Point 1:(ICFL=3.9mA) Design Point 2:(ICFL=6.5mA) Contrast Ratio Optical Rise Time/Fall Time [msec] Nominal Input Voltage VDD [Volt] Power Consumption [Watt](VDD Line) Lamp Power Consumption [Watt] (VCFL Line) Design Point 1:(ICFL=3.9mA) Design Point 2:(ICFL=6.5mA) Typical Power Consumption [Watt] (VDD Line + VCFL Line) Design Point 1:(ICFL=3.9mA) Design Point 2:(ICFL=6.5mA) Electrical Interface Temperature Range [degree C] Operating Storage (Shipping) SPECIFICATIONS 381(15.0") 1400(x3) x 1050 304.5(H) x 228.4(V) 0.2175(per one triad) x 0.2175 R,G,B Vertical Stripe 740Typ. 318.5(W) x 241.5(H) x 7.5(D) typ. Normally White Native 262K colors(RGB 6-bit data driver) 90 Typ(center) 85 Typ(5 points average) 150 Typ(center)140 Typ(5 points average) 200 : 1 Typ. 30Typ.,50 Max. +3.3 Typ. 2.0 Typ.,2.8MAX. condition:
2.6Typ.,(W/o inverter loss) 4.0Typ.,(W/o inverter loss)
4.6Typ.5.4MAX,(W/o inverter loss) 6.0Typ.6.8MAX,(W/o inverter loss) 8 pairs LVDS(Even/Odd R/G/B Data(6bit), 3sync signals, Clock) 0 to +50 -20 to +60
(C) Copyright IBM Corp. 1999 All Rights reserved. August 27,1999 OEM93C-04 6/26
Engineering Specification
2.2 Functional Block Diagram
The following diagram shows the functional block of this 15.0 inches Color TFT/LCD Module. The first LVDS port transmits even pixels while the second LVDS port transmits odd pixels.
X-Driver Y-Driver < 8 pairs LVDS >
6bit color data for R/G/B (even/odd) DTCLK(even/odd) DSPTMG Vsync Hsync
EVEN PIXCEL ODD PIXCEL
LCD DRIVE CARD
LCD
Controller
TFT ARRAY/CELL 1400(R/G/B) x 1050
Dual LVDS RECEIVER
G/A
DC-DC Converter Ref circuit
Backlight Unit
VDD GND LCD-DRIVE Connector AMP 1318341-2 (30pin) Lamp Connector JST BHSR-02VS-1 (2pin)
(C) Copyright IBM Corp. 1999 All Rights reserved. August 27,1999 OEM93C-04 7/26
Engineering Specification
3.0 Absolute Maximum Ratings
Absolute maximum ratings of the module is as follows : Item Logic/LCD Drive Voltage Input Signal Voltage CFL Ignition Voltage CFL Current CFL Peak Inrush Current Operating Temperature Operating Relative Humidity Storage Temperature Storage Relative Humidity Vibration Shock Symbol VDD VIN Vs ICFL ICFLP TOP HOP TST HST Min -0.3 -0.3 0 8 -20 5 Max +4.0 VDD+0.3 +1,600 +7 20 +50 95 +60 95 1.5 50 10-200 18 %RH G G Hz ms Rectangle wave %RH Unit V V Vrms mAms mA Note 1 Note 1 Note 1 Note 1 Note 2 Conditions
Note 1 : Maximum Wet-Bulb should be 39 Note 2 : Duration : 50msec Max. Ta=0
and No condensation.
(C) Copyright IBM Corp. 1999 All Rights reserved. August 27,1999 OEM93C-04 8/26
Engineering Specification
4.0 Optical Characteristics
The optical characteristics are measured under stable conditions as follows under 25 Item Viewing Angle (Degrees) K:Contrast Ratio Contrast ratio Response Time (ms) Color Chromaticity (CIE) Rising Falling Red Red Green Green Blue Blue White White White Luminance (cd/ ICFL 6.5 mA ) 150Typ.(TBD) Center 140Typ.(TBD) 5 points average x y x y x y x y Horizontal K 10 Vertical K 10 Conditions (Right) (Left) (Upper) (Lower) Specification Typ. 40 40 15 30 200 30 30 0.577 0.338 0.310 0.563 0.158 0.157 0.310 0.346 Note 50Max 50Max +-0.040 +-0.030 +-0.030 +-0.030 +-0.030 +-0.040 +-0.030 +-0.030 -
:
(C) Copyright IBM Corp. 1999 All Rights reserved. August 27,1999 OEM93C-04 9/26
Engineering Specification
5.0 Signal Interface
5.1 Connectors
Physical interface is described as for the connector on module. These connectors are capable of accommodating the following signals and will be following components. Connector Name / Designation Manufacturer Type / Part Number Mating Receptacle Manufacture Mating Receptacle/Part Number For Signal Connector AMP 1318341-2 AMP 1318335-2
Connector Name / Designation Manufacturer Type / Part Number Mating Type / Part Number
For Lamp Connector JST BHSR-02VS-1 SM02B-BHSS-1
(C) Copyright IBM Corp. 1999 All Rights reserved. August 27,1999 OEM93C-04 10/26
Engineering Specification
5.2 Interface Signal Connector
Pin # 1 2 3 4 5 6 7 8 9 10 11 12 13 14
Signal Name VDD VDD VDD GND GND ReIN0ReIN0+ GND ReIN1ReIN1+ GND ReIN2ReIN2+ GND
Pin # 16 17 18 19 20 21 22 23 24 25 26 27 28 29
Signal Name ReCLKIN+ GND RoIN0RoIN0+ GND RoIN1RoIN1+ GND RoIN2RoIN2+ GND RoCLKINRoCLKIN+ GND
15 ReCLKIN30 Reserved Note: 'Reserved' pins are not allowed to connect any other line. Voltage levels of all input signals are LVDS compatible (except VDD). Refer to 5.4 " Interface Signal Electrical Characteristics", for voltage levels of all input signals.
(C) Copyright IBM Corp. 1999 All Rights reserved. August 27,1999 OEM93C-04 11/26
Engineering Specification
5.3 Interface Signal Description
The module uses a pair of LVDS receiver SN75LVDS86(Texas Instruments) compatible. LVDS is a differential signal technology for LCD interface and high speed data transfer device. Transmitter shall be SN75LVDS84/85 or compatible.
PIN # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
SIGNAL NAME VDD VDD VDD GND GND ReIN0ReIN0+ GND ReIN1ReIN1+ GND ReIN2ReIN2+ GND ReCLKINReCLKIN+ GND RoIN0RoIN0+ GND RoIN1RoIN1+ GND RoIN2RoIN2+ GND ReCLKINRoCLKIN+ GND Reserved
Description VDD (+3.3V) VDD (+3.3V) VDD (+3.3V) Ground Ground Negative LVDS differential data input (Even R0-R5, G0) Positive LVDS differential data input (Even R0-R5, G0) Ground Negative LVDS differential data input (Even G1-G5, B0-B1) Positive LVDS differential data input (Even G1-G5, B0-B1) Ground Negative LVDS differential data input (Even B2-B5, HSYNC, VSYNC, DSPTMG) Positive LVDS differential data input (Even B2-B5, HSYNC, VSYNC, DSPTMG) Ground Negative LVDS differential clock input (Even) Positive LVDS differential clock input (Even) Ground Negative LVDS differential data input (Odd R0-R5, G0) Positive LVDS differential data input (Odd R0-R5, G0) Ground Negative LVDS differential data input (Odd G1-G5, B0-B1) Positive LVDS differential data input (Odd G1-G5, B0-B1) Ground Negative LVDS differential data input (Odd B2-B5) Positive LVDS differential data input (Odd B2-B5) Ground Negative LVDS differential clock input (Odd) Positive LVDS differential clock input (Odd) Ground Reserved
Note:'Reserved' pin is not allowed to connect any other line. Output signals from any system shall be Hi-Z state when VDD is off. Input signals of odd and even clock shall be the same timing.
(C) Copyright IBM Corp. 1999 All Rights reserved. August 27,1999 OEM93C-04 12/26
Engineering Specification
Internal circuit of LVDS inputs are as follows.
Signal Input
Pin No. 6 ReIN0R
SN75LVDS86 Compatible
A0M(8)
7
ReIN0+
A0P(9)
9
ReIN1R
A1M(10)
10
ReIN1+
A1P(11)
12
ReIN2R
A2M(14)
13
ReIN2+
A2P(15)
(24)D0 (26)D1 (27)D2 (29)D3 (30)D4 (31)D5 (33)D6 (34)D7 (35)D8 (37)D9 (39)D10 (40)D11 (41)D12 (43)D13 (45)D14 (46)D15 (47)D16 (1)D17 (2)D18 (4)D19 (5)D20
Even +Red 0 Even +Red 1 Even +Red 2 Even +Red 3 Even +Red 4 Even +Red 5 Even +Green 0 Even +Green 1 Even +Green 2 Even +Green 3 Even +Green 4 Even +Green 5 Even +Blue 0 Even +Blue 1 Even +Blue 2 Even +Blue 3 Even +Blue 4 Even +Blue 5 HSYNC VSYNC DSPTMG
15
ReCLKINR
CLKINM(16) (23)CLKOUT CLKINP(17) LVDS GND(7,13,18) PLL GND(19,21) 0 ohm Jumper EVEN DTCLK
16
ReCLKIN+ LVDS GND, PLL GND
4,5,8,11,14,17,20,23,26,29 Return/GND
GND 0 ohm Jumper
I/F Connector Frame Shell (FG)
The module uses a 100ohm resistor between positive and negative data lines of each receiver input.
(C) Copyright IBM Corp. 1999 All Rights reserved. August 27,1999 OEM93C-04 13/26
Engineering Specification
Signal Input
Pin No. 18 RoIN0R
SN75LVDS86 Compatible
A0M(8)
19
RoIN0+
A0P(9)
21
RoIN1R
A1M(10)
22
RoIN1+
A1P(11)
24
RoIN2R
A2M(14)
25
RoIN2+
A2P(15)
(24)D0 (26)D1 (27)D2 (29)D3 (30)D4 (31)D5 (33)D6 (34)D7 (35)D8 (37)D9 (39)D10 (40)D11 (41)D12 (43)D13 (45)D14 (46)D15 (47)D16 (1)D17 (2)D18 (4)D19 (5)D20
Odd +Red 0 Odd +Red 1 Odd +Red 2 Odd +Red 3 Odd +Red 4 Odd +Red 5 Odd +Green 0 Odd +Green 1 Odd +Green 2 Odd +Green 3 Odd +Green 4 Odd +Green 5 Odd +Blue 0 Odd +Blue 1 Odd +Blue 2 Odd +Blue 3 Odd +Blue 4 Odd +Blue 5 NC NC NC
27
RoCLKINR
CLKINM(16) (23)CLKOUT CLKINP(17) LVDS GND(7,13,18) PLL GND(19,21) 0 ohm Jumper GND 0 ohm Jumper ODD DTCLK
28
RoCLKIN+ LVDS GND PLL GND
4,5,8,11,14,17,20,23,26,29 Return/GND
I/F Connector Frame Shell (FG)
The module uses a 100ohm resistor between positive and negative lines of each receiver input.
(C) Copyright IBM Corp. 1999 All Rights reserved. August 27,1999 OEM93C-04 14/26
Engineering Specification
SIGNAL NAME +RED 5 +RED 4 +RED 3 +RED 2 +RED 1 +RED 0 (EVEN/ODD) +GREEN 5 +GREEN 4 +GREEN 3 +GREEN 2 +GREEN 1 +GREEN 0 (EVEN/ODD) +BLUE 5 +BLUE 4 +BLUE 3 +BLUE 2 +BLUE 1 +BLUE 0 (EVEN/ODD) -DTCLK (EVEN/ODD) +DSPTMG VSYNC HSYNC VDD GND
Description (ITSX93) RED Data 5 (MSB) RED Data 4 RED Data 3 RED Data 2 RED Data 1 RED Data 0 (LSB) Red-pixel Data: Each red pixel's brightness data consists of these 6 bits pixel data. GREEN Data 5 (MSB) GREEN Data 4 GREEN Data 3 GREEN Data 2 GREEN Data 1 GREEN Data 0 (LSB) Green-pixel Data: Each green pixel's brightness data consists of these 6 bits pixel data. BLUE Data 5 (MSB) BLUE Data 4 BLUE Data 3 BLUE Data 2 BLUE Data 1 BLUE Data 0 (LSB) Blue-pixel Data: Each blue pixel's brightness data consists of these 6 bits pixel data. Data Clock: The typical frequency is 54MHz. The signal is used to strobe the pixel +data and the +DSPTMG Display Timing: When the signal is high, the pixel data shall be valid to be displayed. Vertical Sync: This signal is synchronized with -DTCLK. Both active high/low signals are acceptable. Horizontal Sync: This signal is synchronized with -DTCLK. Both active high/low signals are acceptable. +3.3V Power Supply Ground
Note: Output signals from any system shall be Hi-Z state when VDD is off.
(C) Copyright IBM Corp. 1999 All Rights reserved. August 27,1999 OEM93C-04 15/26
Engineering Specification
5.4 Interface Signal Electrical Characteristics
Input signals shall be low or Hi-Z state when VDD is off. It is recommended to refer the specifications of SN75LVDS86DGG(Texas Instruments) in detail. Signal electrical characteristics are as follows;
Parameter Vth
Condition Defferential Input High Voltage (Vcom=+1.2V) Differential Input High Voltage (Vcm=+1.2V)
Min
Max 100
unit mV
Vtl
-100
mV
LVDS Macro AC characteristics are as follows: Value 54 Typ. 800 Min 800 Min Unit MHz ps ps
Clock Frequency (T) Data Setup Time (Tsu) Data Hold Time (Thd)
T Input Clock
Input Data Tsu
Thd
5.5 Signal for Lamp Connector
Pin # 1
2
Signal Name Lamp High Voltage Lamp Low Voltage
(C) Copyright IBM Corp. 1999 All Rights reserved. August 27,1999 OEM93C-04 16/26
Engineering Specification
6.0 Pixel format image
Following figure shows the relationship of the input signals and LCD pixel format image. Even and odd pair of RGB data are sampled at a time.
Even 0 1st Line
Odd 1
Even 1398
Odd 1399
R
GB
R
GB
R
GB
R
GB
1050th Line
R
GB
R
GB
R
GB
R
GB
(C) Copyright IBM Corp. 1999 All Rights reserved. August 27,1999 OEM93C-04 17/26
Engineering Specification
7.0 Parameter guide line for CFL Inverter
PARAMETER White Luminance (Center) (5 Points average) MIN DP-1 DP-2 MAX UNITS cd/ 90 85 150 140 CONDITION (Ta=25 )
CFL current(ICFL) CFL Frequency(FCFL)
3.0 40
3.9 50
6.5 50
7.0 60
mArms KHz
(Ta=25 (Ta=25 Note 1 (Ta= 0 Note 3
) )
CFL Ignition Voltage(Vs)
1,450
-
-
-
Vrms
)
CFL Voltage (Reference)(VCFL) CFL Power consumption(PCFL)
-
675 2.6
610 4
-
Vrms W
(Ta=25 Note 2 (Ta=25 Note 2
) )
Note 1: CFL discharge frequency should be carefully determined to avoid interference between inverter and TFT LCD. Note 2: Calculated value for reference (ICFL x VCFL = PCFL). Note 3: CFL inverter should be able to give out a power that has a generating capacity of over 1,450 voltage. Lamp units need 1,450 voltage minimum for ignition. Note 4: DP-1 and DP-2 are IBM recommended Design Points. *1 All of characteristics listed are measured under the condition using the IBM Test inverter. *2 In case of using an inverter other than listed, it is recommended to check the inverter carefully. Sometimes, interfering noise stripes appear on the screen, and substandard luminance or flicker at low power may happen. *3 In designing an inverter, it is suggested to check safety circuit very carefully. Impedance of CFL, for instance, becomes more than 1 [M ohm] when CFL is damaged. *4 Generally, CFL has some amount of delay time after applying kick-off voltage. It is recommended to keep on applying kick-off voltage for 1 [Sec] until discharge. *5 CFL discharge frequency must be carefully chosen so as not to produce interfering noise stripes on the screen. *6 Reducing CFL current increases CFL discharge voltage and generally increases CFL discharge frequency. So all the parameters of an inverter should be carefully designed so as not to produce too much leakage current from high-voltage output of the inverter.
(C) Copyright IBM Corp. 1999 All Rights reserved. August 27,1999 OEM93C-04 18/26
Engineering Specification
The following chart is CFL current versus the luminance for your reference.
(C) Copyright IBM Corp. 1999 All Rights reserved. August 27,1999 OEM93C-04 19/26
Engineering Specification
8.0 Interface Timings
Basically, interface timings described here is not actual input timing of LCD module but output timing of SN75LVDS86(Texas Instruments) or equivalent.
8.1 Timing Characteristics
Signal DTCLK Item Freqency Symbol Fdck Tck +V-Sync Frame Rate Fv Tv Nv V-Active Level Tva Nva V-Back Porch V-Front Porch +DSPTMG +H-Sync V-Line Scan Rate Nvb Nvf m Fh Th Nh H-Active Level Tha Tha H-Back Porch H-Front Porch +DSPTMG +DATA Display Data Even/Odd Thb Thf Thd n 10 8 8 820 17.5 (56.25) 16.39 1059 15.78 1 7 1 MIN. TYP. 54 18.5 60 16.67 1066 46.7 3 12 1 1050 63.98 15.63 844 1.037 56 64 24 12.96 1400 1023 69.51 63 (61) 17.78 2047 MAX. 60 Unit [MHz] [ns] [Hz] [ms] [lines] [us] [lines] [lines] [lines] [lines] [kHz] [usec] [Tck] [usec] [Tck] [Tck] [Tck] [usec] [dots]
Note: 1. Tha+Thb should be less than 1024. 2. Both positive Hsync and positive Vsync polarity is recommended.
(C) Copyright IBM Corp. 1999 All Rights reserved. August 27,1999 OEM93C-04 20/26
Engineering Specification
8.2 Timing Definition
Vertical Timing
DSPTMG
Tv Tvf Tvblk Tva m Tvb
-VSYNC +VSYNC
Horizontal Timing
DSPTMG
Th Thf Thblk Tha Thd Thb
-HSYNC +HSYNC
(C) Copyright IBM Corp. 1999 All Rights reserved. August 27,1999 OEM93C-04 21/26
Engineering Specification
Tv Tva
VSYNC
Th Tha
HSYNC
Tvb Tvf 1 2 3 m
DSPTMG
Vsync,Hsync and Display Timing
Thd Tck VIDEO(EVEN) VIDEO(ODD) 0 1 2 3 n-4 n-3 n-2 n-1
DOTCLK Tck DSPTMG Tha HSYNC Thb Thd Thf
Video signal and Dot clock
(C) Copyright IBM Corp. 1999 All Rights reserved. August 27,1999 OEM93C-04 22/26
Engineering Specification
9.0 Power Consumption
Input power specifications are as follows; SYMBOL VDD PDD PARAMETER Logic/LCD Drive Voltage VDD Power Max Min 3 Typ 3.3 Max 3.6 2.8 UNITS V W CONDITION Load Capacitance 30uF MAX Pattern VDD=3.6V All Black Pattern VDD=3.3V MAX Pattern VDD=3.0V All Black Pattern VDD=3.3V
PDD
VDD Power
2
W
IDD Max IDD VDDrp
IDD Current Max IDD Current Allowable Logic/LCD Drive Ripple Voltage Allowable Logic/LCD Drive Ripple Noise 600
85
mA mA
100
mVp-p
VDDns
100
mVp-p
Note:Max Pattern:2 dot Vertical sub-pixel stripe.
(C) Copyright IBM Corp. 1999 All Rights reserved. August 27,1999 OEM93C-04 23/26
Engineering Specification
10.0 Power ON/OFF Sequence
VDD power and lamp on/off sequence is as follows. Interface signals are also shown in the chart. Signals from any system shall be Hi-Z state or low level when VDD is off.
150ms min.
VDD
10%
90%
90% 10% 10%
0V
10ms max.
0 min.
0 min.
Signals
0V
10%
10%
180ms min. (Recommended)
0 min.
Lamp On
0V
10%
10%
(C) Copyright IBM Corp. 1999 All Rights reserved. August 27,1999 OEM93C-04 24/26
Engineering Specification
11.0 Mechanical Characteristics
(C) Copyright IBM Corp. 1999 All Rights reserved. August 27,1999 OEM93C-04 25/26
Engineering Specification
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(C) Copyright IBM Corp. 1999 All Rights reserved. August 27,1999 OEM93C-04 26/26

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