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IT2002 2 to 26.5 GHz Dual-Channel, High-Power Amplifier
(Preliminary Information)
Description
The IT2002 is dual-channel broadband GaAs MMIC traveling-wave amplifier designed for applications requiring high output power. The IT2002 provides a saturated output power of 1 W per channel up to 10 GHz and greater than 28.5 dBm up to 20 GHz. Medium gain of 10 dB with flatness of +/-1dB is provided up to 26.5 GHz. DC power consumption as low as 2.7 W per channel is obtained in bias condition for best output power and good linear performance. Input and output ports are DC coupled.
Frequency range: 2 to 26.5 GHz Psat (2 to 7 GHz): 30 dBm Psat (7 to 15 GHz): 29 dBm Psat at 26.5 GHz: 25 dBm Gain with +/-1dB flatness: 10 dB DC power consumption: 2.7 W DC bias conditions: 9 V at 300 mA Full chip passivation for high reliability
VGG1 IN1 VDD1
CHANNEL 1
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Features
(Power output is per channel)
OUT1
CHANNEL 2
IN2 VGG2 VDD2
OUT2
Absolute Maximum Ratings
(per channel)
Symbol VDD1,2 VGG1,2 IDQ1,2 IG1,2 Pin Pdiss_DC Tch Tm Tst
Parameters/conditions Positive supply voltage Negative supply voltage Positive supply current Negative supply current RF input power DC power dissipation (no RF) Operating channel temperature Mounting temperature (30 s) Storage temperature
Min. -2
Max. 11 0 800 1.6 27 5 150 320 150
Units V V mA mA dBm W C C C
-65
Recommended Operating Conditions
Symbol Tb VDD1,2 V GG1,2 IDQ1,2
Parameters/conditions Operating temperature range (backside) Positive bias supply Negative bias supply DC supply drain current
Min. -40 -0.4
Typ.
Max. 85 9 -0.9 400
Units o C V V mA
-0.6 300
Electrical Characteristics
(per channel) (at 25 C) 50 ohm system VDD = +9 V Quiescent current (IDQ) = 300 mA
Symbol BW S21 S11 S22 S12 Psat
P1dB
Parameters/conditions Frequency range Small signal gain Gain flatness Input return loss Output return loss Isolation Saturated output power at 3-dB gain compression 2 - 10 GHz 2 - 20 GHz 2 - 26.5 GHz Output power at 1-dB gain compression 2 - 10 GHz 2 - 20 GHz 2 - 26.5 GHz
Min. 2 7 8 8 30 27.5 26.5 23 27 26 22.5
Typ. 10 +/-1 10 10
Max. 26.5
Units GHz dB dB dB dB dB dBm dBm dBm dBm dBm dBm
29.5 28.5 25 29 28 24.5
www.iterrac.com
This is Preliminary data sheet. See "Product Status Definitions" on Web site or catalog for product development status.
December 27, 2006 Doc. 1324 Rev. 1.0
1
iTerra Communications 2400 Geng Road, Ste. 100, Palo Alto, CA 94303 Phone (650) 424-1937, Fax (650) 424-1938
IT2002 2 to 26.5 GHz Dual-Channel, High-Power Amplifier
(Preliminary Information)
Thermal Characteristics
Symbol Rth_jb Parameters/conditions Thermal resistance junction-back side of die No RF: DC bias VDD = 9 V, IDD = 600 mA , P DC = 5.4 W Tbase = 70 C Thermal resistance junction - back side of die RF Applied: Saturated power 1 W, V D D= 9 V, Pdiss = 7 W Tbase = 70 C Rth_jb (o C/W) Tch (o C) 5 97.0 MTFF (h) >> +1E7
Rth_jb
5
105.0
>> +1E7
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Chip Layout And Pad Locations
Dimensions are in millimeters Back of chip is RF and DC ground) Chip size tolerance: 20 m Chip thickness: 4 mil with 0.4 mil tolerance
P7 P5 P2 P4
P1 P8 P6
P3
Pin Out and Pad Dimensions P1: RF input-1 (100 x 150 m) P2: RF input-2 (100 x 150 m) P3: RF output-1 and VDD1 bias (option 2) by means of bias-tee (100 x 150 m) P4: RF output-2 and VDD1 bias (option 2) by means of bias-tee (100 x150 m) P5: VDD1 positive voltage (option 1) by means of choke (150 x100 m) P6: VDD2 positive voltage (option 1) by means of choke (150 x 100 m) P7: VGG1, negative voltage (100 x 100 m) P8: VGG2, negative voltage (100 x 100m)
www.iterrac.com
This is Preliminary data sheet. See "Product Status Definitions" on Web site or catalog for product development status.
December 27, 2006 Doc. 1324 Rev. 1.0
2
iTerra Communications 2400 Geng Road, Ste. 100, Palo Alto, CA 94303 Phone (650) 424-1937, Fax (650) 424-1938
IT2002 2 to 26.5 GHz Dual-Channel, High-Power Amplifier
(Preliminary Information)
Recommended Chip Mounting for 2 to 26.5 GHz Applications
Vdd1 (option 1)
100 F
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Vgg1
RF In 1
Channel 1
RF output 1 and Vdd1 (option 2) thru bias tee
RF In 2
Channel 2
RF output 2 and Vdd2 (option 2) thru bias tee Vgg2 Vdd2 (option 1)
100 F
Note: Bypass capacitor must be large enough to isolate bias supply (>10 F)
www.iterrac.com
This is Preliminary data sheet. See "Product Status Definitions" on Web site or catalog for product development status.
December 27, 2006 Doc. 1324 Rev. 1.0
3
iTerra Communications 2400 Geng Road, Ste. 100, Palo Alto, CA 94303 Phone (650) 424-1937, Fax (650) 424-1938
IT2002 2 to 26.5 GHz Dual-Channel, High-Power Amplifier
(Preliminary Information)
Performance Data
(T = 25 C)
Measured data includes the effect of two parallel RF input/output bond www..com wires.
S21 (dB)
20.0 18.0 16.0 14.0 12.0 10.0 8.0 6.0 4.0 2.0 0.0 -2.0 -4.0 -6.0 -8.0 -10.0
Small Signal Gain, VDD1/2=9V, IDQ1/2=300mA
Input Return loss, VDD1/2=9V, IDQ1/2=300mA
10.0 5.0 0.0 -5.0 -10.0
S11 (dB)
-15.0 -20.0 -25.0 -30.0 -35.0 -40.0 -45.0 -50.0
2
4
6
8
10
12
14
16
18
20
22
24
26
28
2
4
6
8
10
12
14
16
18
20
22
24
26
28
Freq. (GHz)
Freq. (GHz)
Output Return loss, VDD1/2=9V, IDQ1/2=300mA
10.0 5.0 0.0 -5.0 -10.0
20.0 18.0 16.0 14.0 12.0 10.0 8.0 6.0 4.0 2.0 0.0 -2.0 -4.0 -6.0 -8.0 -10.0
Gain vs. Drain Bias VDD1/2, IDQ1/2=300mA
S22 (dB)
-15.0 -20.0 -25.0 -30.0 -35.0 -40.0 -45.0 -50.0 2 4 6 8 10 12 14 16 18 20 22 24 26 28
S21 (dB)
IT2002 Vdd=9V IT2002 Vdd=8V
2
4
6
8
10
12
14
16
18
20
22
24
26
28
Freq. (GHz)
Freq. (GHz)
Saturated Power, VDD1/2=9V, IDQ1/2=300mA
35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 0 2 4 6 8 10 12 14 16 18 20 22 24 26
P1dB, VDD1/2=9V, IDQ1/2=300mA
35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 0 2 4 6 8 10 12 14 16 18 20 22 24 26
Psat (dBm)
P1dB(dBm)
Freq. (GHz)
Freq. (GHz)
P1dB vs. VDD1/2, IDQ1/2=300mA
35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 0 2 4
60
Output Third Order Intercept Point, VDD1/2=9V, IDQ1/2=300mA
VDD1/2=9V
55 50 O IP3(dB m ) 45 40 35 30 25 20
P1dB(dBm)
VDD1/2=8V
6
8
10
12
14
16
18
20
22
24
26
0
2
4
6
8
10
12
14
16
18
20
22
24
26
Freq. (GHz)
Freq. (GHz)
www.iterrac.com
This is Preliminary data sheet. See "Product Status Definitions" on Web site or catalog for product development status.
December 27, 2006 Doc. 1324 Rev. 1.0
4
iTerra Communications 2400 Geng Road, Ste. 100, Palo Alto, CA 94303 Phone (650) 424-1937, Fax (650) 424-1938
IT2002 2 to 26.5 GHz Dual-Channel, High-Power Amplifier
(Preliminary Information)
Recommended Procedure for Biasing and Operation
CAUTION: LOSS OF GATE VOLTAGE (Vgg1,2) WHILE CORRESPONDING DRAIN VOLTAGE (Vdd1,2) IS PRESENT CAN DAMAGE THE AMPLIFIER. The following procedure must be considered to properly test the amplifier. The IT2002 amplifier is biased with a positive drain supply (VDD1,2 per channel) and one negative gate supply (VGG1,2 per channel) (Channel 1 and Channel 2). The recommended bias condition for the IT2002 is VDD1,2= 9.0 V, IDQ1,2 = 300 mA. To achieve this drain current level, VGG1,2 is typically biased between -0.7 V and -0.9 V. The gate voltage (VGG1/2) MUST be applied prior to the drain voltage (VDD1,2) during power up and removed after the drain voltage is removed during the power down. Drain bias VDD1,2 can be applied to the drain (P5-P6). Alternatively, the positive power supply can be applied through an external bias tee to the RF output pad (P3-P4) . CAUTION: THIS IS AN ESD SENSITIVE DEVICE Chip carrier material should be selected to have GaAs-compatible thermal coefficient of expansion and high thermal conductivity such as copper molybdenum or copper tungsten. The chip carrier should be machined, finished flat, plated with gold over nickel, and be capable of withstanding 325 C for 15 min. Die attachment for power devices should utilize gold/tin (80/20) eutectic alloy solder and should avoid a hydrogen environment for PHEMT devices. Note that the backside of the chip is gold plated and is used as RF and DC ground. These GaAs devices should be handled with care and stored in dry nitrogen environment to prevent contamination of bonding surfaces. These are ESD-sensitive devices and should be handled with caution, including the use of wrist-grounding straps. All die attach and wire/ribbon bond equipment must be well grounded to prevent static discharges through the device. Recommended wire bonding uses gold ribbon 3 mil wide and 0.5 mil thick as short as practical allowing for appropriate stress relief. The RF input and output bonds should be typically 12 mil long corresponding to a typical 2 mil gap between the chip and the substrate material. iTerra recommends 80/20 AuSn preforms be used for eutectic attachment of its high-power GaAs die. Die attachment should be performed under forming gas or dry nitrogen. All passive components should be attached prior to mounting the GaAs die. Place the chip carrier or package on a heated stage that has a temperature of 290o C controlled to +/- 5o C, with a maximum temperature of less than 300o C. Before and after placing the die on the 290o C heated stage, the die should be placed on a 150o C heated stage to minimize thermal shock. This is essential for die with dimensions greater than 1 mm. Place the AuSn preform on the carrier or package and let it melt. Using tweezers, pick up the GaAs die and scrub it several times for 5 to 15 s. After the die is positioned, remove the carrier or substrate from the heated stage. Maximum dwell time is 1 min., and typically 30 s or less.
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Application Information
Eutectic Die Attachment
www.iterrac.com
This is Preliminary data sheet. See "Product Status Definitions" on Web site or catalog for product development status.
December 27, 2006 Doc. 1324 Rev. 1.0
5
iTerra Communications 2400 Geng Road, Ste. 100, Palo Alto, CA 94303 Phone (650) 424-1937, Fax (650) 424-1938

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