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SEMICONDUCTOR TECHNICAL DATA
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MC145436A
Advance Information
Low-Power Dual Tone Multiple Frequency Receiver
The MC145436A is a low-power and improved input sensitivity version of the MC14LC5436. The MC145436A is a silicon gate CMOS LSI device containing the filter and decoder for detection of a pair of tones conforming to the DTMF standard with outputs in hexadecimal. Switched capacitor filter technology is used together with digital circuitry for the timing control and output circuits. The MC145436A provides excellent power line noise and dial tone rejection and is suitable for applications in central office equipment, PABX, and keyphone systems, remote control equipment and consumer telephony products. The MC145436A offers the following performance features: * * * * * * * * Single + 5 V Power Supply Detects All 16 Standard Digits Uses Inexpensive 3.58 MHz Crystal Provides Guard Time Controls to Improve Speech Immunity Output in 4-Bit Hexadecimal Code Built-In 60 Hz and Dial Tone Rejection Pin Compatible with SSI-204, MC145436, and MC14LC5436 Functional and Applicational Compatible with MC145436 and MC14LC5436
14 1
P SUFFIX PLASTIC DIP CASE 646
16 1
DW SUFFIX SOG PACKAGE CASE 751G
ORDERING INFORMATION
MC145436AP Plastic DIP MC145436ADW SOG Package
PIN ASSIGNMENTS PDIP
D2 D1 ENB VDD GT Xen Ain 1 2 3 4 5 6 7 14 13 12 11 10 9 8 D4 D8 DV ATB Xin Xout GND
SOG
D2 D1 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 D4 D8 DV NC ATB Xin Xout GND
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ENB VDD NC GT Xen Ain
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NC = NO CONNECTION
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This document contains information on a new product. Specifications and information herein are subject to change without notice.
REV 1 1/96
(c) Motorola, Inc. 1996 MOTOROLA
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BLOCK DIAGRAM
697 Ain 60 Hz REJECTION FILTER BS1 770 852 941 1209 BS2 1336 1477 1633 ATB Xen Xin Xout VOLTAGE REF OUTPUT REGISTER CHIP CLOCKS D4 OUTPUT DECODER ENB TIMING CIRCUIT DV PREAMP GT
D1
D2
/8
CLOCK GEN
D8
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MAXIMUM RATINGS (Voltages Referenced to GND Unless Otherwise Noted)
Rating DC Supply Voltage Input Voltage, Any Pin Except Ain Input Voltage, Ain DC Current Drain per Pin Power Dissipation Operating Temperature Range Storage Temperature Range Symbol VDD Vin Vin I PD TA Tstg Value - 0.5 to + 6.0 - 0.5 to VDD + 0.5 VDD - 10 to VDD + 0.5 10 100 - 40 to + 85 - 65 to + 150 Unit V V V mA mW C C This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid applications of any voltage higher than the maximum rated voltages to this high impedance circuit. For proper operation it is recommended that Vin and Vout be constrained to the range VSS (Vin or Vout) VDD. Reliability of operation is enhanced if unused inputs are tied to and appropriate logic voltage level (e.g., either VSS or VDD).
ELECTRICAL CHARACTERISTICS
(All Polarities Referenced to VSS = 0 V, VDD = 5.0 V 10%, TA = - 40 to + 85C, Unless Otherwise Noted) Parameter DC Supply Voltage Supply Current (fCLK = 3.58 MHz) Input Current Input Voltage Low Input Voltage High Iout Data and DV Pins: Vout = 4.5 V (Source) Iout Data and DV Pins: Vout = 0.4 V (Sink) Input Impedance Fanout Input Capacitance Ain ATB Xen, ENB GT ENB, Xin, Xen ENB, GT, Xen ENB, GT, Xen Symbol VDD IDD Iin VIL VIH IOH IOL Rin Fout Cin Min 4.5 -- -- -- -- 3.5 800 1.0 90 -- -- Typ 5 5 -- -- -- -- -- -- 100 -- 6 Max 5.5 8 450 1 1.5 -- -- -- -- 10 -- pF Unit V mA A V V A mA k
ANALOG CHARACTERISTICS (VDD = 5.0 V 10%, TA = - 40 to + 85C, Unless Otherwise Noted)
Parameter Signal Level for Detection (Ain) Twist = High Tone/Low Tone Frequency Detect Bandwidth 60 Hz Tolerance Dial Tone Tolerance (Note 1) (Dial Tone 330 + 440) Noise Tolerance (Notes 1 and 2) Power Supply Noise (Wide Band) Talk Off (Mitel Tape #CM7290) Min - 35 - 10 (1.5 + 2 Hz) -- Typ -- -- 2.5 -- -- -- -- 2 Max -2 10 3.5 0.8 0 - 12 10 -- Unit dBm dB % fO Vr ms dB dB mV p-p Hits
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-- -- -- --
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NOTES: 1. Referenced to lower amplitude tone. 2. Bandwidth limited (0 to 3.4 kHz) Gaussian Noise.
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AC CHARACTERISTICS (VDD = 5.0 V 10%, TA = - 40 to + 85C)
Characteristic Tone On Time Pause Time Detect Time Release Time Data Setup Time Data Hold Time Pulse Width DV Reset Lag Time ENB High to Output DV* ENB Low to Output High-Z* * Data out: CL = 35 pF k RL = 500 . GT For Detection For Rejection For Detection For Rejection GT = 0 GT = 1 GT = 0 GT = 1 Symbol TONEon TONEoff tdet trel tsu th tw(GT) tlag(DV) tEHDV tELDZ Min 40 -- 40 -- 22 32 28 18 7 4.2 18 -- -- -- Typ -- -- -- -- -- -- -- -- -- 4.6 -- -- 120 110 Max -- 20 -- 20 40 50 40 30 -- 5 -- 5 500 300 Unit ms ms ms ms s ms s ms ns ns
TIMING DIAGRAM
TONEon ANALOG INPUT (Ain) tdet D1, D2 D4, D8 tsu DV tlag(DV) tEHDV tELDZ th TONE BURST 1 trel HIGH-Z HIGH-Z TONEoff TONE BURST 2
tELDZ ENB
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tw(GT)
GT
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PIN DESCRIPTIONS
VDD Positive Power Supply (PDIP, SOG -- Pin 4) The digital supply pin, which is connected to the positive side of the power supply. VSS Ground (PDIP -- Pin 8, SOG -- Pin 9) Ground return pin is typically connected to the system ground. D1, D2, D4, D8 Data Output (PDIP -- Pins 2, 1, 14, 13; SOG -- Pins 2, 1, 16, 15) These digital outputs provide the hexadecimal codes corresponding to the detected digit. The digital outputs become valid after a tone pair has been detected and are cleared when a valid pause is timed. See Table 1 for hexadecimal codes.These output pins are high impedance when the enable pin is at logic 0. ENB Enable (PDIP, SOG -- Pin 3) Outputs D1, D2, D4, D8 are enabled when ENB is at a logic 1, and high impedance (disabled) when ENB is at a logic 0. GT Guard Time (PDIP -- Pin 5, SOG -- Pin 6) The guard time control input provides two sets of detected time and release time, both within the allowed ranges of tone on and tone off (see Figure 1). A longer tone detect time rejects signals too short to be considered valid. With GT = 1, talk off performance is improved, since it reduces the probability that tones simulated by speech will maintain signal conditions long enough to be accepted. In addition, a shorter release time reduces the probability that a pause simulated by an interrupt in speech will be detected as a valid pause. On the other hand, a shorter tone detect time with a long Table 1. Hexadecimal Codes
Digit 1 2 3 4 5 6 7 8 9 0 * #
release time would be appropriate for an extremely noisy environment where fast acquisition time and immunity to dropouts would be required. In general, the tone signal time generated by a telephone is 100 ms, nominal, followed by a pause of about 100 ms. A high-to-low or low-to-high transition on the GT pin resets the internal logic and the MC145436A is immediately ready to accept a new tone input. If left open, this pin is internally pulled to ground. Xen Oscillator Enable (PDIP -- Pin 6, SOG -- Pin 7) A logic 1 on Xen enables the on-chip crystal oscillator. When using alternate time base from the ATB pin, Xen should be tied to VSS. Ain Analog Input (PDIP -- Pin 7, SOG -- Pin 8) This pin accepts the analog input and is internally biased so that the input signal may be ac coupled. The input may be dc coupled so long as it does not exceed the positive supply (see Figure 2). Xin/Xout Oscillator In and Oscillator Out (PDIP -- Pins 10, 9; SOG -- Pins 11, 10) These pins connect to an internal crystal oscillator. In operation, a parallel resonant crystal is connected from X in to X out, as well as a 1 M resistor in parallel with the crystal. When using the alternate clock source from ATB, X in should be tied to VDD. ATB Alternate Time Base (PDIP -- Pin 11, SOG -- Pin 12) This pin serves as a frequency reference when more than one MC145436A is used, so that only one crystal is required for multiple MC145436As. When doing so, all ATB pins should be tied together as shown in Figure 3. When only one MC145436A is used, this pin should be left unconnected. The output frequency of ATB is 447.4 kHz. DV Data Valid (PDIP -- Pin 12, SOG -- Pin 14) DV signals a detection by going high after a valid tone pair is sensed and decoded at output pins D1, D2, D4, D8. DV remains high until a loss of the current DTMF signal occurs or until a transition in GT occurs.
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D8 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0
Output Code D4 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 D2 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 D1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0
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GUARD TIME
5 VDD
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A B
C D
Figure 1. Guard Time
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Vin
t VDD
7
VDD Vin 10 pF
u VDD
7
VDD
0.01 F Ain
10 pF
Ain
100 k
100 k
Figure 2. Analog Input (Operational Information Based on PDIP Package)
3.58 MHz
Xin 1 M ATB
Xout
VDD COL 1 Xen 697 STD DTMF (Hz) 770 852 941 1 4 7 COL 2 2 5 8 0 1336 COL 3 3 6 9 # 1477 COL 4 A B C D 1633 ROW 1 ROW 2 ROW 3 ROW 4
MC145436A VDD Xin
ATB MC145436A
Xen
*
1209
TO OTHER MC145436As
STD DTMF (Hz)
Figure 3. Multiple MC145436As
Figure 4. 4 x 4 Keyboard Matrix
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PACKAGE DIMENSIONS
P SUFFIX PLASTIC DIP CASE 646-06
NOTES: 1. LEADS WITHIN 0.13 (0.005) RADIUS OF TRUE POSITION AT SEATING PLANE AT MAXIMUM MATERIAL CONDITION. 2. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 3. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 4. ROUNDED CORNERS OPTIONAL. DIM A B C D F G H J K L M N INCHES MIN MAX 0.715 0.770 0.240 0.260 0.145 0.185 0.015 0.021 0.040 0.070 0.100 BSC 0.052 0.095 0.008 0.015 0.115 0.135 0.300 BSC 0_ 10_ 0.015 0.039 MILLIMETERS MIN MAX 18.16 19.56 6.10 6.60 3.69 4.69 0.38 0.53 1.02 1.78 2.54 BSC 1.32 2.41 0.20 0.38 2.92 3.43 7.62 BSC 0 10 _ _ 0.39 1.01
14
8
B
1 7
A F C N H G D
SEATING PLANE
L
J K M
DW SUFFIX SOG PACKAGE CASE 751G-02 -A-
16 9 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN EXCESS OF D DIMENSION AT MAXIMUM MATERIAL CONDITION. MILLIMETERS MIN MAX 10.15 10.45 7.40 7.60 2.35 2.65 0.35 0.49 0.50 0.90 1.27 BSC 0.25 0.32 0.10 0.25 0_ 7_ 10.05 10.55 0.25 0.75 INCHES MIN MAX 0.400 0.411 0.292 0.299 0.093 0.104 0.014 0.019 0.020 0.035 0.050 BSC 0.010 0.012 0.004 0.009 0_ 7 _ 0.395 0.415 0.010 0.029
-B-
1 8
8X
P 0.010 (0.25)
M
B
M
16X
D
M
J TA
S
0.010 (0.25)
B
S
F
m
R X 45_ C -T- G K
SEATING PLANE
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14X
M
DIM A B C D F G J K M P R
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Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters can and do vary in different applications. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.
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JAPAN: Nippon Motorola Ltd.; Tatsumi-SPD-JLDC, Toshikatsu Otsuki, 6F Seibu-Butsuryu-Center, 3-14-2 Tatsumi Koto-Ku, Tokyo 135, Japan. 03-3521-8315 HONG KONG: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852-26629298
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MC145436A/D MOTOROLA

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