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T35L6432A
SYNCHRONOUS BURST SRAM
FEATURES
E ast Access times: 4.5, 5, 6, 7, and 8ns F E ast clock speed: 125,100, 83, 66, and 50 MHz F E rovide high performance 3-1-1-1 access rate P E ast OE access times: 4.5, 5 and 6ns F E ingle 3.3V +10%/-5% power supply S E ommon data inputs and data outputs C E YTE WRITE ENABLE and GLOBAL WRITE B control E hree chip enables for depth expansion and T address pipelining E ddress, control, input, and output pipelined A registers Enternally self-timed WRITE CYCLE I E RITE pass-through capability W E urst control pins ( interleaved or linear burst B sequence) E igh density, high speed packages H E ow capacitive bus loading L E igh 30pF output drive capability at rated access H time E NOOZE MODE for reduced power standby S E Single cycle disable ( PentiumTM BSRAM compatible )
64K x 32 SRAM
3.3V supply, fully registered inputs and outputs, burst counter
PIN ASSIGNMENT (Top View)
ADSC ADSP BW4 BW3 BW2 BW1 GW BWE CE2 VCC VSS ADV A8 CLK CE CE2 OE A6 A7 A9
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 NC DQ17 DQ18 VCCQ VSSQ DQ19 DQ20 DQ21 DQ22 VSSQ VCCQ DQ23 DQ24 NC VCC NC VSS DQ25 DQ26 VCCQ VSSQ DQ27 DQ28 DQ29 DQ30 VSSQ VCCQ DQ31 DQ32 NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 80 79 78 77 76 75 74 73 72 71 70 69 NC DQ16 DQ15 VCCQ VSSQ DQ14 DQ13 DQ12 DQ11 VSSQ VCCQ DQ10 DQ9 VSS NC VCC ZZ DQ8 DQ7 VCCQ VSSQ DQ6 DQ5 DQ4 DQ3 VSSQ VCCQ DQ2 DQ1 NC
100-pin QFP or 100-pin TQFP
68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
MODE VSS VCC A10 A11 A12 A13 A14 A15 A0 NC NC NC NC NC A5 A4 A3 A2 A1
OPTIONS
TIMING 4.5ns access/8ns cycle 5ns access/10ns cycle 6ns access/12ns cycle 7ns access/15ns cycle 8ns access/20ns cycle Package 100-pin QFP 100-pin TQFP MARKING -4.5 -5 -6 -7 -8 Q T
GENERAL DESCRIPTION
The Taiwan Memory Technology Synchronous Burst RAM family employs: high-speed, low power CMOS design using advanced triple-layer polysilicon, double-layer metal technology. Each memory cell consists of four transistors and two high valued resistors. The T35L6432A SRAM integrates 65536 x 32 SRAM cells with advanced synchronous peripheral circuitry and a 2-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered clock input (CLK). The synchronous inputs include all addresses, all data inputs, address-pipelining P. 1 Publication Date: DEC. 1998 Revision: A
Part Number Examples
PART NO. Pkg. BURST SEQUENCE T35L6432A-5Q Q Interleaved (MODE=NC or VCC) T35L6432A-5T T Linear (MODE=GND) Taiwan Memory Technology, Inc. reserves the right to change products or specifications without notice.
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wide as controlled by the write control inputs. Individual byte write allows individual byte to be written. BW1 controls DQ1-DQ8. BW2 controls DQ9-DQ16. BW3 controls DQ17-DQ 24. BW4 controls DQ25-DQ32. BW1, BW2 , BW3, and BW4 can be active only with BWE being LOW. GW being LOW causes all bytes to be written. WRITE pass-through capability allows written data available at the output for the immediately next READ cycle. This device also incorporates pipelined enable circuit for easy depth expansion without penalizing system performance. The T35L6432A operates from a 3.3V +10%/-5% power supply. The device is ideally suited for PentiumTM, 680X0, and Power PCTM systems and for systems that are benefited from a wide synchronous data bus.
(continued) chip enable (CE), depth- expansion chip enables (CE2 and CE2),burst control inputs (ADSC ,ADSP, and ADV ), write enables (BW1, BW2 , BW3, BW4 , and BWE ), and global write (GW ). Asynchronous inputs include the output enable (OE ),Snooze enable (ZZ) and burst mode control (MODE). The data outputs (Q), enabled by OE , are also asynchronous. Addresses and chip enables are registered with either address status processor (ADSP) or address status controller (ADSC ) input pins. Subsequent burst addresses can be internally generated as controlled by the burst advance pin (ADV ). Address, data inputs, and write controls are registered on-chip to initiate self-timed WRITE cycle. WRITE cycles can be one to four bytes
GENERAL DESCRIPTION
FUNCTIONAL BLOCK DIAGRAM
A0-A15 16 ADDRESS REGISTER 16 14 16
MODE ADV CLK
A0
A1 A1'
DO D1 Q1 BINARY COUNTER & LOGIC Q0
A0'
ADSC ADSP
CLR
BWE BYTE 4 WRITE REGISTER BW4
8 BYTE 4 WRITE DRIVER
8
8 BYTE 3 WRITE REGISTER BW3 8 BYTE 2 WRITE REGISTER BW2 8 BYTE 1 WRITE REGISTER BW1 GW CE CE2 CE2 OE ENABLE REGISTER PIPELINED ENABLE BYTE 1 WRITE DRIVER BYTE 2 WRITE DRIVER BYTE 3 WRITE DRIVER
8 32 64K x 8 x 4 MEMORY ARRAY 8 SENSE AMPS 32 OUTPUT REGISTERS OUTPUT BUFFERS 32 DQ1 E E E DQ32
8
INPUT REGISTERS
4
Note: 1. The Functional Block Diagram illustrates simplified device operation. See Truth Table, pin descriptions and timing diagrams for detailed information.
Taiwan Memory Technology, Inc. reserves the right to change products or specifications without notice. P. 2 Publication Date: DEC. 1998 Revision: A
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PIN DESCRIPTIONS
QFP PINS 32-37, 44-49, 81, 82, 99, 100, SYM. TYPE DESCRIPTION A0InputAddresses: These inputs are registered and must meet the setup and A15 Synchronous hold times around the rising edge of CLK. The burst counter generates internal addresses associated with A0 and A1,during burst cycle and wait cycle. InputByte Write: A byte write is LOW for a WRITE cyle and HIGH for BW1 BW2 Synchronous a READ cycle. BW1 controls DQ1-DQ8. BW2 controls DQ9DQ16. BW3 controls DQ17-DQ24. BW4 controls DQ25-DQ32. BW3 Data I/O are high impedance if either of these inputs are LOW , BW4 conditioned by BWE being LOW. InputWrite Enable: This active LOW input gates byte write operations BWE Synchronous and must meet the setup and hold times around the rising edge of CLK. InputGlobal Write: This active LOW input allows a full 32-bit WRITE GW Synchronous to occur independent of the BWE and BWn lines and must meet the setup and hold times around the rising edge of CLK. CLK InputClock: This signal registers the addresses, data, chip enables, write Synchronous control and burst control inputs on its rising edge. All synchronous inputs must meet setup and hold times around the clock's rising edge. InputSynchronous Chip Enable: This active LOW input is used to enable CE Synchronous the device and conditions internal use of ADSP. This input is sampled only when a new external address is loaded. InputSynchronous Chip Enable: This active LOW input is used to enable CE2 Synchronous the device. This input is sampled only when a new external address is loaded. This input can be used for memory depth expansion. CE2 InputSynchronous Chip Enable: This active HIGH input is used to enable Synchronous the device. This input is sampled only when a new external address is loaded. This input can be used for memory depth expansion. Input Output enable: This active LOW asynchronous input enables the OE data output drivers. InputAddress Advance: This active LOW input is used to control the ADV Synchronous internal burst counter. A HIGH on this pin generates wait cycle (no address advance). InputAddress Status Processor: This active LOW input, along withCE ADSP Synchronous being LOW, causes a new external address to be registered and a READ cycle is initiated using the new address. InputAddress Status Controller:This active LOW input causes device to ADSC Synchronous be deselected or selected along with new external address to be registered. A READ or WRITE cycle is initiated depending upon write control inputs. P. 3 Publication Date: DEC. 1998 Revision:A
93-96
87
88
89
98
92
97
86 83
84
85
Taiwan Memory Technology, Inc. reserves the right to change products or specifications without notice.
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SYM. MODE DESCRIPTION Mode: This input selects the burst sequence. A LOW on this pin selects LINEAR BURST. A NC or HIGH on this pin selects INTERLEAVED BURST. Do not alter input state while device is operating. Input Snooze Enable: This active HIGH asynchronous input causes the device to enter a low-power standby mode in which all data in the memory arry is retained. Input/ Data Inputs/Outputs: First Byte is DQ1-DQ8. Second Byte is Output DQ9-DQ16. Third Byte is DQ17-DQ24. Fourth Byte is DQ25DQ32. Input data must meet setup and hold times around the rising edge of CLK. Supply Power Supply: 3.3V +10%/-5% Ground Ground: GND I/O Supply Output Buffer Supply: 3.3V +10%/-5% TYPE InputStatic
PIN DESCRIPTIONS (continued)
QFP PINS 31
ZZ
2,3,6-9,12,13, 18, 19,22-25,28,29,52, 53,56-59,62,63,68, 69,72-75,78,79, 15,41,65,91 17,40,67,90 4,11,20,27,54, 61,70,77 5,10,21,26,55, 60,71,76 1,14,16,30,38,39, 42,43,50,51,66,80
DQ1DQ32
VCC VSS VCCQ
VSSQ I/O Ground Output Buffer Ground: GND NC No Connect: These signals are not internally conntected.
Taiwan Memory Technology, Inc. reserves the right to change products or specifications without notice.
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INTERLEAVED BURST ADDRESS TABLE (MODE = NC/VCC)
First Address (external) A...A00 A...A01 A...A10 A...A11 Second Address (internal) A...A01 A...A00 A...A11 A...A10 Third Address (internal) A...A10 A...A11 A...A00 A...A01 Fourth Address (internal) A...A11 A...A10 A...A01 A...A00
LINEAR BURST ADDRESS TABLE (MODE = GND)
First Address (external) A...A00 A...A01 A...A10 A...A11 Second Address (internal) A...A01 A...A10 A...A11 A...A00 Third Address (internal) A...A10 A...A11 A...A00 A...A01 Fourth Address (internal) A...A11 A...A00 A...A01 A...A10
PARTIAL TRUTH TABLE FOR READ/WRITE
Function READ READ WRITE one byte WRITE all byte WRITE all byte
GW
H H H H L
BWE
H L L L X
BW1
X H L L X
BW2
X H H L X
BW3
X H H L X
BW4
X H H L X
WRITE PASS-THROUGH TRUTH TABLE
PREVIOUS CYCLE OPERATION Initiate WRITE cycle, all bytes Address= A(n-1), data= D(n-1) Initiate WRITE cycle, all bytes Address= A(n-1), data= D(n-1) Initiate WRITE cycle, all bytes Address= A(n-1), data= D(n-1) Initiate WRITE cycle, one bytes Address= A(n-1), data= D(n-1)
BWn
All L2,3 All L2,3 All L2,3 ONE L2
PRESENT CYCLE NEXT CYCLE OPERATION OPERATION CE BWn OE Initiate READ cycle L H L Read D(n) Register A(n), Q= D(n-1) No new cycle H H L No carry-over from Q = D(n-1) previous cycle No new cycle H H H No carry-over from Q = HIGH-Z previous cycle No new cycle H H L No carry-over from Q = D(n-1) for one byte previous cycle
Note: 1. Previous cycle may be any cycle(non-burst, burst, or wait). 2. BWE is LOW for individual byte WRITE. 3. GW = LOW yields the same result for all-byte WRITE operation.
Taiwan Memory Technology, Inc. reserves the right to change products or specifications without notice.
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TRUTH TABLE
ADDRESS CE CE2 CE2 USED Deselected Cycle, Power Down None H X X Deselected Cycle, Power Down None L X L Deselected Cycle, Power Down None L H X Deselected Cycle, Power Down None L X L Deselected Cycle, Power Down None L H X Snooze Cycle, Power Down None X X X READ Cycle, Begin Burst External L L H READ Cycle, Begin Burst External L L H WRITE Cycle, Begin Burst External L L H READ Cycle, Begin Burst External L L H READ Cycle, Begin Burst External L L H READ Cycle, Continue Burst Next X X X READ Cycle, Continue Burst Next X X X READ Cycle, Continue Burst Next H X X READ Cycle, Continue Burst Next H X X Next X X X WRITE Cycle, Continue Burst Next H X X WRITE Cycle, Continue Burst READ Cycle, Suspend Burst Current X X X READ Cycle, Suspend Burst Current X X X READ Cycle, Suspend Burst Current H X X READ Cycle, Suspend Burst Current H X X WRITE Cycle, Suspend Burst Current X X X WRITE Cycle, Suspend Burst Current H X X
OPERATION
ZZ ADSP ADSC ADV WRITE OE CLK DQ
L L L L L H L L L L L L L L L L L L L L L L L X L L H H X L L H H H H H X X H X H H X X H X L X X L L X X X L L L H H H H H H H H H H H H X X X X X X X X X X X L L L L L L H H H H H H X X X X X X X X L H H H H H H L L H H H H L L X X X X X X L H X L H L H L H X X L H L H X X L-H L-H L-H L-H L-H X L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H High-Z High-Z High-Z High-Z High-Z High-Z Q High-Z D Q High-Z Q High-Z Q High-Z D D
L-H Q L-H High-Z L-H Q L-H High-Z L-H D L-H D
Note: 1. X means "don't care." H means logic HIGH. L means logic LOW. WRITE = L means any one or more byte write enable signals (BW1, BW2 , BW3 or BW4 ) and BWE are LOW, or GW equals LOW. WRITE = H means all byte write signal are HIGH. 2. BW1= enables write to DQ1-DQ8. BW2 = enables write to DQ9-DQ16. BW3 = enables write to DQ17-DQ24. BW4 =enables write to DQ25-DQ32. 3. All inputs except OE must meet setup and hold times around the rising edge ( LOW to HIGH) of CLK. 4. Suspending burst generates wait cycle. 5. For a write operation following a read operation. OE must be HIGH before the input data required setup time plus High-Z time for OE and staying HIGH throughout the input data hold time. 6. This device contains circuitry that will ensure the outputs will be High-Z during power-up. 7. ADSP= LOW along with chip being selected always initiates an internal READ cycle at the L-H edge of CLK. A WRITE cycle can be performed by setting WRITE LOW for the CLK L-H edge of the subsequent wait cycle. Refer to WRITE timing diagram for clarification.
Taiwan Memory Technology, Inc. reserves the right to change products or specifications without notice.
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*Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
ABSOLUTE MAXIMUM RATINGS*
Voltage on VCC Supply Relative to VSS. ............-0.5V to +4.6V I/O Supply Voltage VccQ ........... Vss -0.5V to Vcc VIN......................................... -0.5V to Vcc +0.5V Storage Temperature (plastic)...... -55C to +150C Junction Temperature ............................... +150C Power Dissipation ........................................ 1.6W Short Circuit Output Current...................... 100mA
DC ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS
(0C Ta 70C; VCC = 3.3V +10%/-5% unless otherwise noted) DESCRIPTION CONDITIONS Input High (Logic) voltage Input Low (Logic) voltage Input Leakage Current 0V VIN VCC Output Leakage Current Output(s) disabled, 0V VOUT VCC Output High Voltage IOH = -4.0 mA Output Low Voltage IOL = 8.0 mA Supply Voltage SYM. VIH VIL ILI ILO VOH VOL Vcc MIN 2 -0.3 -2 -2 2.4 3.1 M 0.4 3.6 A X MAX VCCQ + 0.3 0.8 2 2 UNITS V V A A V V V 1, 11 1, 11 1 NOTES 1, 2 1, 2 14
DESCRIPTION CONDITIONS SYM.TYP -4.5 -5 -6 -7 -8 UNITS NOTES Power Supply mA 3, 12, 13 Device selected; all inputs VIL or Icc 200 300 270 230 190 150 Current: VIH; cycle time tKC MIN; VCC Operating = MAX; outputs open Power Supply ISB1 56 155 140 125 115 110 mA 12, 13 Device selected;ADSC ,ADSP, Current: Idle ADV , GW ,BWE VIH; all other inputsVIL orVIH; VCC = MAX; cycle time tKC MIN: outputs open CMOS Standby Device deselected; VCC = MAX; all inputs VSS + 0.2 or VCC - 0.2; all inputs static; CLK frequency =0 TTL Standby Device deselected; all inputs VIL or VIH; all inputs static; VCC = MAX;CLK frequency = 0 Clock Running Device deselected; all inputs VIL or VIH; VCC =MAX; CLK cycle time tKCMIN Taiwan Memory Technology, Inc. reserves the right to change products or specifications without notice. ISB2 0.5 5 5 5 5 5 mA 12, 13
ISB3 15
25 25 25
25
25
mA
12, 13
ISB4 30
81 81 76
66
51
mA
12, 13
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CAPACITANCE
DESCRIPTION Input Capacitance Input/ Output Capacitance(DQ) CONDITIONS TA = 25C; f = 1 MHz VCC = 3.3V SYM. CI CO TYP 3 6 MAX 4 7 UNITS NOTES pF 4 pF 4
THERMAL CONSIDERATION
DESCRIPTION Thermal Resistance - Junction to Ambient Thermal Resistance - Junction to Case CONDITIONS SYM. QFP TYP UNITS Still air, soldered on 4.25x JA 20 C/W 1.125 inch 4-layer PCB JB 1 C/W NOTES
AC ELECTRICAL CHARACTERISTICS
DESCRIPTION Clock Clock cycle time Clock HIGH time Clock LOW time Output Times Clock to output valid Clock to output invalid Clock to output in Low-Z Clock to output in High-Z OE to output valid OE to output in Low-Z OE to output in High-Z Setup Times Address -4.5 -5
(Note 5) (0CTA70C; VCC=3.3V +10%/-5%) -6 -7 -8
SYM. MIN MAX MINMAX MIN MAX MIN MAX MIN MAX UNITS NOTES
tKC tKH tKL
8 3 3 4.5
10 4 4 5 2 3 4.5 4.5 0 3 3 3 3 3 3 3 0.5 0.5 0.5 0.5 0.5 0.5 P. 8 4 5 5
12 4 4 6 2 3 5 5 0 5 3 3 3 3 3 3 0.5 0.5 0.5 0.5 0.5 0.5
15 5 5 7 2 3 6 5 0 6 3 3 3 3 3 3 0.5 0.5 0.5 0.5 0.5 0.5
20 6 6 8 2 3 6 6 0 6 3 3 3 3 3 3 0.5 0.5 0.5 0.5 0.5 0.5
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
tKQ tKQX 2 tKQLZ 2 tKQHZ tOEQ tOELZ 0 tOEHZ
6, 7 6, 7 9 6, 7 6, 7 8, 10 8, 10 8, 10 8, 10 8, 10 8, 10 8, 10 8, 10 8, 10 8, 10 8, 10 8, 10
tAS 2.5 Address Status( ADSC , ADSP ) tADSS 2.5 tAAS 2.5 Address Advance ( ADV ) Byte Write Enables ( BW1~ BW4 , BWE , GW ) Data-in Chip Enables( CE , CE2 ,CE2) Hold Times Address tWS tDS tCES 2.5 2.5 2.5
tAH 0.5 Address Status( ADSC , ADSP ) tADSH 0.5 tAAH 0.5 Address Advance ( ADV ) Byte Write Enables tWH 0.5 ( BW1~ BW4 , BWE , GW ) Data-in tDH 0.5 Chip Enables( CE , CE2 ,CE2) tCEH 0.5 Taiwan Memory Technology, Inc. reserves the right to change products or specifications without notice.
Publication Date: DEC. 1998 Revision:A
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8. A READ cycle is defined by byte write enables all HIGH or ADSP LOW along with chip enables being active for the required setup and hold times. A WRITE cycle is defined by at one byte or all byte WRITE per READ/WRITE TRUTH TABLE. 9. OE is a "don't care" when a byte write enable is sampled LOW. 10.This is a synchronous device. All synchronous inputs must meet specified setup and hold time, except for "don't care" as defined in the truth table. 11.AC I/O curves are available upon request. 12."Device Deselected means the device is in POWER-DOWN mode as defined in the truth table. "Device Selected" means the device is active. 13.Typical values are measured at 3.3V, 25C and 20ns cycle time. 14.MODE pin has an internal pull-up and exhibits an input leakage current of 10A.
AC TEST CONDITIONS
Input pulse levels Input rise and fall times Input timing reference levels Output reference levels Output load 0V to 3.0V 1.5ns 1.5V 1.5V See Figures 1 and 2
Notes: 1. All voltages referenced to VSS (GND). 2. Overshoot: VIH +3.6 V for t tKC/2. Undershoot: VIL -1.0 V for t tKC/2. 3. Icc is given with no output current. Icc increases with greater output loading and faster cycle times. 4. This parameter is sampled. 5. Test conditions as specified with the output loading as shown in Fig. 1 unless otherwise noted. 6. Output loading is specified with CL = 5 pF as in Fig. 2. 7. At any given temperature and voltage condition, tKQHZ is less than tKQLZ and tOEHZ is less than tOELZ.
OUTPUT LOADS
DQ 50 Z0 = 50 Vt = 1.5V 30 pF
Fig.1 OUTPUT LOAD EQUIVALENT 3.3V 317 DQ 351 5 pF
Fig.2 OUTPUT LOAD EQUIVALENT
Taiwan Memory Technology, Inc. reserves the right to change products or specifications without notice.
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SNOOZE MODE. When the ZZ pin becomes a logic HIGH, ISB2 is guaranteed after the setup time t ZZ is met. Any access pending when entering SNOOZE MODE is not guaranteed to successfully complete. Therefore, SNOOZE MODE must not be initiated until valid pending operations are completed.
SNOOZE MODE
SNOOZE MODE is a low current, "power down" mode in which the device is deselected and current is reduced to ISB2. The duration of SNOOZE MODE is dictated by the length of time the ZZ pin is in a HIGH state. After entering SNOOZE MODE, the clock and all other inputs are ignored. The ZZ pin (pin 64) is an asynchronous, active HIGH input that causes the device to enter
SNOOZE MODE ELECTRICAL CHARACTERISTICS
DESCRIPTION Current during SNOOZE MODE ZZ HIGH to SNOOZE MODE time SNOOZE MODE Operation Recovery Time CONDITIONS ZZ VIH SYMBOL ISB2 tZZ tRZZ 2(tKC) 2(tKC) MIN MAX 5 UNITS mA ns ns 4 4 NOTES
SNOOZE MODE WAVEFORM
CLK
CE
tRZ Z
ZZ
tZZ
I
S UPP LY
I SUPPLY I
ZZ
DO N'T CARE
Note:
1. The CE signal shown above refers to a TRUE state on all chip selects for the device. 2. All other inputs held to static CMOS levels (VIN Vss + 0.2 V or Vcc -0.2 V).
Taiwan Memory Technology, Inc. reserves the right to change products or specifications without notice.
P. 10
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READ TIMING
t KC
t
KH
t
KL
t A D SS t A DS H
t A DS S t A D SH
A DS C
t AS tAH
A DDRES S
A1 t WS t WH
A2
A3 Bur st con tin ue d wi th n ew b ase ad d re ss.
G W , BW E , B W 1- B W 4
t CE S t CE H Des ele ct cy cle.
CE ( NO T E 2)
t AAS t AAH
A DV
AD V s usp e nd s bu rs t.
OE
(NO TE 3) t KQ LZ tOE HZ t O EQ tOEL Z t KQ t KQ X t KQHZ tK QX
Q
Hi g h-Z t KQ
Q (A 1)
Q (A 2) (NOT E1)
Q(A 2+1)
Q (A 2+2)
Q(A2 + ) 3
Q(A2)
Q (A 2+1)
Q(A 3)
Bu rst wr a ps a ro und to i ts in ita l sta te. BUR S T RE A D
S in g le RE A D
DO N' T CARE UNDEFIN ED
Note: 1. Q(A2) refers to output from address A2. Q (A2 + 1) refers to output from the next internal burst address following A2. 2. CE2 and CE2 have timing identical to CE . On this diagram, when CE is LOW, CE2 is LOW and CE2 is HIGH. When CE is HIGH, CE2 is HIGH and CE2 is LOW. 3. Timing is shown assuming that the device was not enabled before entering into this sequence. OE does not cause Q to be driven until after the following clock rising edge.
Taiwan Memory Technology, Inc. reserves the right to change products or specifications without notice.
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WRITE TIMING
t KC
C LK
t KH t KL
t A DS S t A DS H
A DSP
t A D SS t A D S H A DS C exte n ds b ur s t. t A D SS t A D SH
A DS C
t AS tAH
A D D RE S S
A1
A2 BY T E W RIT E si g n als a r e ig n or ed f or f ir st cy cle w hen A DS P i n it i alte s bu r st.
A3 t WS t WH
BW E , B W 1- B W 4
t W S t WH (N OT E 5)
GW
t CE S t CE H
CE ( NO T E 2 )
t AAS tAAH
A DV
(NO TE 4) AD V su sp nd s b u rst .
OE
(NOT E 3) tDS t DH
D
Hi g h-Z
D(A1) tO E HZ
D(A2)
D(A2+1) (NOT E 1)
D(A2+1)
D(A2 +2)
D(A2+3 )
D(A3 )
D(A3+1)
D (A3+2 )
Q
BUR ST RE A D S in g le W RIT E BU RS T W RIT E E xte nd e d BU RST W RIT E
DON' T CARE UNDEFINED
Note: 1. Q(A2) refers to output from address A2. Q (A2 + 1) refers to output from the next internal burst address following A2. 2. CE2 and CE2 have timing identical to CE . On this diagram, when CE is LOW , CE2 is LOW and CE2 is HIGH. When CE is HIGH , CE2 is HIGH and CE2 is LOW. 3. OE must be HIGH before the input data setup and hold HIGH throughout the data hold time. This prevents input/output data contention for the time period to the byte write enable inputs being sampled. 4. ADV must be HIGH to permit a WRITE to the loaded address. 5. Full width WRITE can be initiated by GW LOW or GW HIGH and BWE , BW1- BW4 LOW. Taiwan Memory Technology, Inc. reserves the right to change products or specifications without notice. P. 12 Publication Date: DEC. 1998 Revision:A
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READ/WRITE TIMING
t KC
C LK
t KH t KL t A DSS t A DSH
A DSP
A DS C
tAS tAH
A D DRE S S
A1
A2
A3 t WS t WH
A4
A5
A6
BW E B W 1- B W 4
t C E S t C EH
CE (NO T E 2)
A DV
OE
t KQ t DS t DH t OELZ D(A 5 ) t KQ (N OT E1) Q(A 2 ) Si ng le W RIT E Q(A3 ) Pas s -th ough r REA D Q(A4) Q(A4+1) Q(A 4+ 2) Q(A 4+ 3) Back-to-Back W RIT Es D(A6)
D
Hig h-Z t OE HZ
D(A3)
t KQL Z
Q
H gh -Z i
Q(A1)
Back-t o -Back REA Ds
BURST REA D
DO N'T CARE UNDEFINED
Note: 1. Q(A4) refers to output from address A4. Q (A4 + 1) refers to output from the next internal burst address following A4. 2. CE2 and CE2 have timing identical to CE . On this diagram, when CE is LOW, CE2 is LOW and CE2 is HIGH. When CE is HIGH, CE2 is HIGH and CE2 is LOW. 3. The data bus (Q) remains in High-Z following a WRITE cycle unless an ADSP , ADSC or ADV cycle is performed. 4. GW is HIGH. 5. Back-to-back READs may be controlled by either ADSP or ADSC.
Taiwan Memory Technology, Inc. reserves the right to change products or specifications without notice.
P. 13
Publication Date: DEC. 1998 Revision:A
tm
TE CH
Preliminary T35L6432A
PACKAGE DIMENSIONS 100-LEAD QFP SSRAM (14 x 20 mm)
SYMBOL A A1 A2 b D E e HD' HE' L' L1' t y c
DIMENSIONS IN INCHES 0.130(MAX) 0.005 0.112O 0.004(MIN) 0.012+0.004-0.002 0.551O 0.005 0.005 0.787O 0.026O 0.006 0.008 0.677O 0.008 0.913O 0.032O 0.008 0.008 0.063O 0.006+0.004-0.002 0.004(MAX) 0C C ~12
DIMENTION IN MM 3.302(MAX) 2.845O 0.127 0.102(MIN) 0.300+0.102-0.051 14.000O 0.127 20.000O 0.127 0.650O 0.152 17.200O 0.203 23.200O 0.203 0.800O 0.203 1.600O 0.203 0.150+0.102-0.051 0.102(MAX) 0C C ~12
Taiwan Memory Technology, Inc. reserves the right to change products or specifications without notice.
P.14
Publication Date: DEC. 1998 Revision:A
tm
TE CH
Preliminary T35L6432A
PACKAGE DIMENSIONS 100-LEAD TQFP SSRAM (14 x 20 mm)
SYMBOL A A1 A2 b D E e HD' HE' L' L1' t y c
DIMENSIONS IN INCHES 0.063(MAX) 0.005 0.055O 0.002(MIN) 0.013+0.002-0.004 0.004 0.551O 0.004 0.787O 0.006 0.026O 0.004 0.630O 0.004 0.866O 0.006 0.024O 0.006 0.039O 0.002 0.006O 0.003(MAX) 0C C ~7
DIMENTION IN MM 1.600(MAX) 1.400O 0.050 0.050(MIN) 0.320+0.060-0.100 14.000O 0.100 20.000O 0.100 0.650O 0.152 16.000O 0.100 22.000O 0.100 0.600O 0.150 1.000O 0.150 0.150+0.050-0.060 0.080(MAX) 0C C ~7
Taiwan Memory Technology, Inc. reserves the right to change products or specifications without notice.
P.15
Publication Date: DEC. 1998 Revision:A

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