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LG Semicon Co.,Ltd.
Description
The GM71C4403C is the new generation dynamic RAM organized 1,048,576 words x 4 bit. GM71C4403C has realized higher density, higher performance and various functions by utilizing advanced CMOS process technology. The GM71C4403C offers Extended Data Out (EDO) Mode as a high speed access Mode. Multiplexed address inputs permit the GM71C4403C to be packaged in a standard 300mil 20(26) pin plastic SOJ , and standard 300mil 20(26) pin plastic TSOP II. The package size provides high system bit densities and is compatible with widely available automated testing and insertion equipment. System oriented features include single power supply of 5V+/-10% tolerance, direct interfacing capability with high performance logic families such as Schottky TTL.
GM71C4403C
1,048,576 WORDS x 4BIT CMOS DYNAMIC RAM
Features
* 1,048,576 Words x 4 Bit Organization * Extended Data Out Mode Capability * Single Power Supply (5V+/-10%) * Fast Access Time & Cycle Time (Unit: ns)
tRAC
GM71C4403C-60 GM71C4403C-70 GM71C4403C-80 60 70 80
tCAC
15 18 20
tRC
104 124 144
tHPC
25 30 35
* Low Power Active : 605/550/495mW (MAX) Standby : 5.5mW (CMOS level : MAX) * RAS Only Refresh, CAS before RAS Refresh, Hidden Refresh Capability * All inputs and outputs TTL Compatible *1024 Refresh Cycles/16ms
Pin Configuration
20 (26) SOJ
I/O1 I/O2 WE RAS A9
1 2 3 4 5 20 19 18 17 16
20 (26) TSOP II
VSS I/O4 I/O3 CAS OE I/O1 I/O2 WE RAS A9
1 2 3 4 5 20 19 18 17 16
VSS I/O4 I/O3 CAS OE
VSS I/O4 I/O3 CAS OE
20 19 18 17 16
1 2 3 4 5
I/O1 I/O2 WE RAS A9
A0 A1 A2 A3 VCC
6 7 8 9 10
15 14 13 12 11
A8 A7 A6 A5 A4
A0 A1 A2 A3 VCC
6 7 8 9 10
15 14 13 12 11
A8 A7 A6 A5 A4
A8 A7 A6 A5 A4
15 14 13 12 11
6 7 8 9 10
A0 A1 A2 A3 VCC
NORMAL TYPE
REVERSE TYPE
(Top View)
(Top View)
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LG Semicon
Pin Description
Pin A0-A9 A0-A9 I/O1-I/O4 RAS CAS Function Address Inputs Refresh Address Inputs Data Input / Data Output Row Address Strobe Column Address Strobe Pin WE OE VCC VSS
GM71C4403C
Function Read/Write Enable Output Enable Power (+5V) Ground
Ordering Information
Type No. GM71C4403CJ-60 GM71C4403CJ-70 GM71C4403CJ-80 GM71C4403CT-60 GM71C4403CT-70 GM71C4403CT-80 GM71C4403CR-60 GM71C4403CR-70 GM71C4403CR-80 Access Time 60ns 70ns 80ns 60ns 70ns 80ns 60ns 70ns 80ns Package 300 Mil, 20 (26) Pin Plastic SOJ 300 Mil, 20 (26) Pin Plastic TSOP II (Normal Type) 300 Mil, 20 (26) Pin Plastic TSOP II (Reverse Type)
Absolute Maximum Ratings*
Symbol TA TSTG VIN/VOUT VCC IOUT PD Parameter Ambient Temperature under Bias Storage Temperature (Plastic) Voltage on any Pin Relative to VSS Voltage on VCC Relative to VSS Short Circuit Output Current Power Dissipation Rating 0 ~ 70 -55 ~ 125 -1.0 ~ 7.0 -1.0 ~ 7.0 50 1.0 Unit C C V V mA W
*Note: Operation at or above Absolute Maximum Ratings can adversely affect device reliability.
Recommended DC Operating Conditions (All Voltage referenced to Vss, TA = 0 ~ 70C)
Symbol VCC VIH VIL 2 Parameter Supply Voltage Input High Voltage Input Low Voltage Min 4.5 2.4 -1.0 Typ 5.0 Max 5.5 6.5 0.8 Unit V V V
LG Semicon
DC Electrical Characteristics (VCC = 5V+/-10%, TA = 0 ~ 70C)
Symbol VOH VOL ICC1 Parameter
Output Level Output "H" Level Voltage (IOUT = -5mA) Output Level Output "L" Level Voltage (IOUT = 4.2mA) Operating Current Average Power Supply Operating Current (RAS, CAS, Address Cycling: tRC = tRC min) Standby Current (TTL) Power Supply Standby Current (RAS, CAS= VIH, DOUT = High-Z) RAS-Only Refresh Current Average Power Supply Current RAS-Only Refresh Mode (RAS Cycling, CAS = VIH, tRC = tRC min) Extended Data Out Page Mode Current Average Power Supply Current Extended Data Out Mode (RAS = VIL, CAS, Address Cycling: tHPC = tHPC min) Standby Current (CMOS) Power Supply Standby Current (RAS, CAS= VIH, WE, OE, Address and DIN=VIH or VIL, DOUT=High-Z) CAS-before-RAS Refresh Current (tRC = tRC min) 60ns 70ns 80ns 60ns 70ns 80ns 60ns 70ns 80ns 60ns 70ns 80ns
GM71C4403C
Min
2.4 0 -
Max Unit Note
VCC 0.4 110 100 90 2 110 100 90 130 120 110 1 mA mA 1, 3 mA 2 mA mA 1, 2 V V
ICC2
ICC3
ICC4
ICC5
ICC6
-10 -10
110 100 90 5 10 10 mA uA uA 1 mA
ICC8
Standby Current RAS = VIH CAS = VIL DOUT = Enable Input Leakage Current Any Input (0V<=VIN<=7V) Output Leakage Current (DOUT is Disabled, 0V<=VOUT<=7V)
II(L) IO(L)
Note: 1. ICC depends on output load condition when the device is selected. ICC(max) is specified at the output open condition. 2. Address can be changed once or less while RAS = VIL. 3. Address can be changed once or less while CAS = VIH.
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Capacitance (VCC = 5V+/-10%, TA = 25C)
Symbol CI1 CI2 CI/O
GM71C4403C
Parameter
Input Capacitance (Address) Input Capacitance (Clocks) Data Input/Output Capacitance (Data-In/Out)
Min
-
Max
5 7 7
Unit
U U U
Note
1 1 1, 2
Note: 1. Capacitance measured with Boonton Meter or effective capacitance measuring method. 2. CAS = VIH to disable DOUT.
AC Characteristics (VCC = 5V+/-10%, TA = 0 ~ 70C, Notes 1, 14, 15, 16)
Test Conditions Input level : VIL=0V, VIH=3.0V Input rise and fall times: 2ns Input timing reference levels: VIL=0.8V, VIH=2.4V Output timing reference levels: VOL=0.8V, VOH=2.0V Output load : 1 TTL gate + CL (100U) (Including scope and jig)
Read, Write, Read-Modify-Write and Refresh Cycles (Common Parameters)
Symbol Parameter
Random Read or Write Cycle Time RAS Precharge Time RAS Pulse Width CAS Pulse Width Row Address Set-up Time Row Address Hold Time Column Address Set-up Time Column Address Hold Time RAS to CAS Delay Time RAS to Column Address Delay Time RAS Hold Time CAS Hold Time CAS to RAS Precharge Time OE to DIN Delay Time OE Delay Time from DIN CAS Set-up Time from DIN Transition Time (Rise and Fall) Refresh Period
GM71C4403 C-60 GM71C4403 C-70 GM71C4403 C-80
Min Max Min Max Min Max 104 40 124 50 144 60 -
Unit
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms
Note
tRC tRP tRAS tCAS tASR tRAH tASC tCAH tRCD tRAD tRSH tCSH tCRP tODD tDZO tDZC tT tREF
60 10,000 70 10,000 10 10,000 0 10 0 10 20 15 15 48 10 15 0 0 2 45 30 50 16 13 10,000 0 10 0 13 20 15 18 58 10 18 0 0 2 52 35 50 16
80 10,000 15 10,000 0 10 0 15 20 15 20 68 10 20 0 0 2 60 40 50 16
19 20
8 9
22
7
4
LG Semicon
Read Cycle
Symbol Parameter
Access Time from RAS Access Time from CAS Access Time from Address Access Time from OE Read Command Setup Time Read Command Hold Time to CAS Read Command Hold Time to RAS Column Address to RAS Lead Time Column Address to CAS Lead Time Output Buffer Turn-off Time Output Buffer Turn-off Time to OE CAS to DIN Delay Time RAS to DIN Delay Time WE to DIN Delay Time OE Pulse width Output Buffer Turn-off Time to RAS Output Buffer Turn-off Time to WE Output Data Hold Time Output Data Hold Time form RAS Read Command Hold Time from
GM71C4403 C-60 GM71C4403 C-70
GM71C4403C
GM71C4403 C-80
Unit
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Note
2,3,17
3, 4, 13, 17 3, 5, 13, 17
Min Max Min Max Min Max 0 0 0 30 18 15 15 15 15 60 15 30 15 15 15 15 15 0 0 0 35 23 18 18 18 18 70 18 35 18 15 15 15 15 0 0 0 40 28 20 20 20 20 80 20 40 20 15 15 15 15
tRAC tCAC tAA tOAC tRCS tRCH tRRH tRAL tCAL tOFF tOEZ tCDD tRDD tWDD tOEP tOFR tWEZ tOH tOHR tRCHR
3,17
18 18
6,21 6
5 5 80
6,21
6
5 5 60
-
5 5 70
-
-
RAS
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Write Cycle
Symbol Parameter
Write Command Setup Time Write Command Hold Time Write Command Pulse Width Write Command to RAS Lead Time Write Command to CAS Lead Time Data-in Setup Time Data-in Hold Time
GM71C4403 C-60 GM71C4403 C-70
GM71C4403C
GM71C4403 C-80
Min Max Min Max Min Max 0 10 10 10 10 0 10 0 13 10 13 13 0 13 0 15 10 15 15 0 15 -
Unit
ns ns ns ns ns ns ns
Note
10
tWCS tWCH tWP tRWL tCWL tDS tDH
11 11
Read- Modify-Write Cycle
Symbol Parameter
Read-Modify-Write Cycle Time RAS to WE Delay Time CAS to WE Delay Time Column Address to WE Delay Time OE Hold Time from WE
GM71C4403 C-60 GM71C4403 C-70 GM71C4403 C-80
Unit
ns ns ns ns ns
Note
Min Max Min Max Min Max 133 77 32 47 15 159 90 38 55 18 183 102 42 62 20 -
tRWC tRWD tCWD tAWD tOEH
10 10 10
Refresh Cycle
Symbol Parameter
CAS Set-up Time (CAS-before-RAS Refresh Cycle) CAS Hold Time (CAS-before-RAS Refresh Cycle) RAS Precharge to CAS Hold Time CAS Precharge Time in Normal Mode
GM71C4403 C-60 GM71C4403 C-70 GM71C4403 C-80
Min Max Min Max Min Max 10 10 10 10 10 10 10 13 10 10 10 15 -
Unit
Note
tCSR tCHR tRPC tCPN
ns ns ns ns
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Extended Data Out (EDO) Mode Cycle
Symbol Parameter
EDO Mode Cycle Time EDO Mode CAS Precharge Time EDO Mode RAS Pulse Width Access Time from CAS Precharge RAS Hold Time from CAS Precharge EDO Read-Modify-Write Cycle CAS Precharge to WE Delay Time EDO Read-Modify-Write Cycle Time
GM71C4403 C-60 GM71C4403 C-70
GM71C4403C
GM71C4403 C-80
Unit
ns ns ns ns ns ns ns ns ns ns ns
Note
23
Min Max Min Max Min Max 25 10 100,000
tHPC tCP tRASP tACP tRHCP tCPW tHPRWC tCOL tCOP tRCHP tDOH
30 13 40 60 77
100,000
35 15 -
100,000
12
3,13,17
35 -
40 -
45 -
35 52 66 10 5 35 3
45 67
86
10
CAS Hold Time Referred OE CAS to OE setup Time Read Command Hold Time from CAS Precharge Output data hold time from CAS low
-
13 5 40 3
-
20 5 45 3
-
Test Mode Cycle
Symbol Parameter
Test Mode WE Setup Time Test Mode WE Hold Time
GM71C4403 C-60 GM71C4403 C-70 GM71C4403 C-80
Unit
ns ns
Note
Min Max Min Max Min Max 0 10 0 10 0 10 -
tWS tWH
Counter Test Cycle
Symbol Parameter
CAS Precharge Time in Counter Test Cycle
GM71C4403 C-60 GM71C4403 C-70 GM71C4403 C-80
Min Max Min Max Min Max 40 40 40 -
Unit
Note
tCPT
ns
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LG Semicon
Notes: 1. 2. 3. 4. 5.
6.
AC measurements assume
GM71C4403C
tT = 2ns.
Assumes that tRCD<=tRCD(max) and tRAD<=tRAD(max). If tRCD or tRAD is greater than the maximum recommended value shown in this table, tRAC exceeds the value shown. Measured with a lode circuit equivalent to 1 TTL loads and 100 pF. Assumes that tRCD>=tRCD(max) and tRAD<=tRAD(max). Assumes that tRCD<=tRCD(max) and tRAD>=tRAD(max). tOFF(max), tOEZ(max), tOFR(max) and tWEZ(max) define the time at which the output achieves the open circuit condition and is not referenced to output voltage levels. times are measured between VIH and VIL.
7. VIH(min) and VIL(max) are reference levels for measuring timing of input signals.Also transition 8. Operation with the tRCD(max) limit insures that tRAC(max) can be met tRCD(max) is specified as a
reference point only: if tRCD is greater than the specified tRCD(max) limit, then access time is controlled exclusively by tCAC. 9. Operation with the tRAD(max) limit insures that tRAC(max) can be met tRAD(max) is specified as a reference point only: if tRAD is greater than the specified tRAD(max) limit, then access time is controlled exclusively by tAA. 10. tWCS, tRWD, tCWD, and tAWD are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only if tWCS >=tWCS(min), the cycle is an early write cycle and the data out pin will remain open circuit (high impedance) throughout the entire cycle if tRWD>=tRWD(min), tCWD>=tCWD(min), tAWD>=tAWD(min) and tCPW>=tCPW(min), the cycle is a readmodify-write and the data output will contain data read from the selected cell if neither of the above sets of conditions is satisfied, the condition of the data out (at access time) is indeterminate. 11. These parameters are referenced to CAS leading edge in early write cycles and to WE leading edge in delayed write or a read modify write cycle. 12. tRASP defines RAS pulse width in extended data out mode cycles. 13. Access time is determined by the longest among tAA, tCAC and tACP. 14. An initial pause of 100us is required after power up followed by a minimum of eight initialization cycles (RAS only refresh cycle or CAS before RAS refresh cycle). If the internal refresh counter is used, a minimum of eight CAS before RAS refresh cycles is required. 15. In delayed write or read-modify-write cycles, OE must disable output buffer prior to applying data to the device. 16. Test mode operation specified in this data sheet is 2bits test function controlled by control address bit CA0. This test mode operation can be performed by WE-and-CAS-before-RAS (WCBR) refresh cycle. Refresh during test mode operation will be performed by normal read cycles or by WCBR refresh cycles. When the state of two test bits accord each other, the condition of the output data is low level. In order to end this test mode operation, perform RAS only refresh cycle or a CAS-before-RAS refresh cycle. 17. In a test mode read cycle, the value of tRAC, tAA, tCAC, tOAC and tACP is delayed for 2ns to 5ns for the specified value. These parameters should be specified in test mode cycles by adding the above value to the specified value in this data sheet.
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LG Semicon
GM71C4403C
18. Either tRCH or tRRH must be satisfied. 19. tRAS(min) = tRWD(min) + tRWL(min) + tT in Read - Modify - Write cycle. 20. tCAS(min) = tCWD(min) + tCWL(min) + tT in Read - Modify - Write cycle. 21. tOFF and tOFR are determined by the later rising edge of RAS or CAS. 22. tCSH(min) can be achieved when tRCD <= tCSH(min) - tCAS(min). 23. EDO Hi-Z control by OE or WE. OE rising edge disables data outputs. When OE goes high during CAS high, the data will not come out until next CAS access. When WE goes low during CAS high, the data will not come out until next CAS access. 24. tHPC(min) can be achieved during a series of EDO mode write cycles or EDO mode read cycles. If both write and read operation are mixed in a EDO mode RAS cycle(EDO mode mix cycle (1),(2) ) minimum value of CAS cycle (tCAS + tCP + 2tT) becomes greater than the specified tHPC(min) value.The value of CAS cycle time of mixed EDO mode is shown in EDO mode mix cycle (1) and (2).
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LG Semicon
GM71C4403C
Unit: Inches (mm)
Package Dimension
20 (26) SOJ
0.025(0.63) MIN 0.305(7.75) MAX 0.340(8.64) MAX 0.295(7.49) MIN 0.330(8.38) MIN
0.660(16.76) MIN 0.680(17.27) MAX
0.260(6.60) MIN
0.275(6.99) MAX 0.008(0.20)
0.085(2.16) MIN
0.128(3.25) MIN 0.148(3.76) MAX 0.050(1.27) TYP 0.015(0.38) MIN 0.021(0.53) MAX 0.026(0.66) MIN 0.036(0.91) MAX
20 (26) TSOP (TYPE II)
0~8 0.308(7.82) MAX 0.292(7.42) MIN
o
0.012(0.30) MIN 0.028(0.70) MAX
0.009(0.22) MAX 0.667(16.94) MIN 0.690(17.54) MAX 0.041(1.03) MIN 0.048(1.23) MAX 0.012(0.30) MIN 0.020(0.50) MAX 0.050(1.27) TYP 0.001(0.03) MIN 0.009(0.23) MAX
28
0.371(9.42) MAX
0.355(9.02) MIN

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