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CY3650 USB Development System User' Guide s
Version 2.4
June 30, 1999
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DOCUMENT HISTORY PAGE
Document Title: USB Development System User' Guide s Document Number:
REV
0.9 1.0 1.1 1.2 2.0 2.1 2.2 2.3 2.4
ECN NO.
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ISSUE DATE
ORIG. OF CHANGE
TIW JDW TEN TEN TEN TEN TEN
DESCRIPTION OF CHANGE
Preliminary Release Update switches, I/O, misc., 24pin pkg Update switches, pin list, suspend Modified to incorporate CY7C6341x and CY7C6351x Changed J1 odd pins to even and even to odd. Expanded explanation of serial buffer size Fixed Table 7, J2 Pin 30 changed from "MR_" (duplicate) to "MW_" Added TOC plus a number of changes and corrections Changed Cypress Logo to be part of file
9/27/96 11/20/96 6/17/97 7/30/97 12/16/97 2/27/98 6/30/99
CY3650 USB Development System User' Guide s
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1. Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2. Kit Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 3. Hardware Installation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 3.1. Power Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 3.2. Jumpers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 3.3. Ribbon Cable connectors J1 and J2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 3.4. PC Communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 3.5. Switch Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 4. Software Installation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 5. Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 5.1. Differences between the chip and the development board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 5.2. Firmware ROM vs. RAM operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 5.3. PC debug interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 5.4. I/O Port operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 5.5. Suspend Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 5.6. Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 5.7. USB Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 6. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 6.1. Target Chip and Connector J1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 6.2. J2 - Microcontroller Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 6.3. J3 - RS232 Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
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1. Overview
The Cypress USB Development System is a powerful tool to assist development of user hardware and firmware with emulated Cypress USB ICs. In the full development system environment (Figure 1), a PC-based interface facilitates debugging through break-traps, single stepping, and display/modification of registers and data RAM. In this mode, firmware can be implemented in on-board EPROM, or downloaded to program RAM. The RAM option provides a quick and easy method for testing firmware revisions.
PC
Wall Bug
RS-232 J2 J1
Development Board
Logic Analyzer
USB
Target System
Figure 1. Typical USB Development Environment
Stand-alone mode (Figure 2) allows portable system operation. In this case, user firmware is loaded in EPROM, and only power need be applied to produce a fully operating emulated USB chip.
Wall Bug
J2
J1
Development Board
Target System
Figure 2. Stand-alone Environment
Figure 3 shows a block diagram of the development board, illustrating the major system components and the user interfaces. The board supports a family of Cypress USB ICs, with varying amounts of on-chip EPROM, RAM, I/O,
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CY3650 USB Development System User' Guide s
etc. Consult the individual device specification for details on the IC being emulated.
CS
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Program ROM 8k x 8 Program RAM 8k x 8
Switch Options
Microcontroller
CS
Data RAM 256 x 8
Reset
S2
Serial Interface Engine
USB Transceiver Port Transceivers
USB D+ D- Port0 Port1 Port2 Port3
Power In
J13
Voltage Regulators
J6
+5V +3.3V
To/From PC
UART
Figure 3. Development Board Functional Block Diagram
2. Kit Contents
The USB Development System contains the following items: * USB development board * Wall transformer power supply ("Wall bug") * USB cable * RS-232 9-pin to 9-pin cable * 9-pin to 25-pin adapter for RS-232 cable * Quick Start User' Guide (yellow) s * This user' guide s * USB Development System Software Guide * CYASM Assembler User' Guide s * PC interface software * CYASM Assembler software * Registration Card
3. Hardware Installation
This section describes the hardware installation steps necessary for operating the development board. These include supplying power to the board, connecting to a PC, and configuring on-board switches. Refer to Figure 4 for locations of components mentioned in this document; Figure 1 shows typical connections for the system development environment.
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CY3650 USB Development System User' Guide s 3.1. Power Connection
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The development board is designed to be powered by the enclosed wall transformer. Connect the transformer to a 110V AC source, and to power jack J13 on the board. +5V and +3.3V are generated by regulators on the board. The green LED will light when power is applied.
3.2. Jumpers
Jumper JP1, at the right side of Figure 4, applies VDD (+5V) to pin 57 of connector J1. Without JP1, no connection to VDD occurs on J1. The board is shipped with the jumper installed.
U6
J13
C52
J6
U4
J12
S2
U11
U7 C51 RS3
J2
R1 U9 U10 C45 C25 D3 R5 D2 U12 RS2 J10 D1 R4 D6 D7 D4 D5
J1
JP2
D11
C53
S3
JP1
J9
RS10
U1
J7
U2
D10
D9
RS8
RP1 RS1 J8
RS6
U8
U5
(User EPROM)
U13 U3
Cypress Semiconductor
P/N MPU-80-EMU Rev B 1/12/97
RS4 RS5
U14
U15 J11
USB Conn.
Figure 4. Development Board Layout 3.3. Ribbon Cable connectors J1 and J2
The diagram above correctly depicts the location of pin 1 for both J1 and J2. However the printed wiring board shows J1 pin 1 incorrectly. Please refer to figure 4 when locating pin numbers.
3.4. PC Communication
For communicating with a PC, plug the enclosed RS-232 cable into the 9-pin connector J6 on the board. The other end of the cable should be connected to the appropriate COM port on the PC, typically COM1 or COM2, depending on the PC' configuration. A 9-pin to 25-pin adapter is provided in case the PC port uses a 25-pin connector. s
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RS7
S1
RS9
RS11
D8
CY3650 USB Development System User' Guide s
The required communication settings for the PC are: Baud Rate Data Bits Parity Stop Bits Flow Control 19200 8 None 1 None used
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It is also recommended that the UART FIFO size settings be set to the minimum values. In Windows 95 the following steps will change the FIFO settings:
* * * On the desk-top, double click on the "My Computer" Icon and then double click on the "Control Panel" Icon. Alternately, use the "start" menu and choose "Settings" and then "Control Panel". In the "Control Panel" window, double click on the "System" Icon. In the "System" window click on the "Device Manager" tab. Then scroll down through the list of devices to the serial port used for the USB Development Board, this is usually COM1 or COM2. Select the appropriate device by double clicking. This brings up a serial device window, inside you will see tabs, select the "Advanced" tab. This sub-widow contain the settings for the serial transmit and receive FIFOs. Set the receive FIFO to 1 and set the transmit FIFO to 3 if this is a valid setting, otherwise set the FIFO size to 1.
*
3.5. Switch Settings
Two 8-position DIP switches provide configuration options for the two on-board FPGAs. Table 1 and Table 2 list options for switches S1 and S3 respectively. Further information on these options is given in Section 5. Unused switches should be left in the default setting, as these may support internal test modes.
Table 1: Switch S1 Configuration
Position 1 2 3 4 5 6 7 8 Open (1) Enable Enable Enable Enable Enable Default Default Default Closed (0) Disable Disable Disable Disable Disable - - - Function USB Bus Reset Watch Dog Reset Cext (wake up) IO Port Input Only Mode Suspend on Power On Reset Required Required Required
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Table 2: Switch S3 Configuration
Position 1 2 3 4 5 6 7 8 Open (1) Program RAM Run on Reset - - - - - - Closed (0) Program ROM (U5) Halt on Reset Default Default Default Default Default Default Function User-code Source Operation at Reset Unused Unused Unused Unused Unused Unused
4. Software Installation
For information on operation of the interactive PC debug environment, refer to the USB Development System Software Guide. For information on the CYASM assembly language programming and the assembler, refer to the CYASM Assembler User' Guide. s
5. Operation
5.1. Differences between the chip and the development board
The development board is lacking some of the features that are present on the integrated circuit. Three important differences are: 1. No programmable pull-up resistors on GPIO pins 2. No programmable DAC currents on GPIO pins 3. The development board is not bus powered and therefore it is not initialized when the USB connector is first attached.
5.2. Firmware ROM vs. RAM operation
The user' program code will be executed from either a ROM (U5) or program RAM, depending on the setting of s switch S3-1 (see Table 2). The U5 ROM is a Cypress CY7C261-45, an 8k x 8 UV-erasable EPROM. Only 4k of the EPROM is currently addressable. The program RAM supports the same memory size as the EPROM. To program or erase the EPROM, refer to the data sheets for the Cypress CY7C261-45. The part can be repeatedly reprogrammed as user firmware is updated. Follow appropriate ESD precautions when handling the part. When installing U5 in the development board, note the IC orientation guide, shown on the board and in Figure 4. The following examples illustrate typical procedures for operating from either ROM or RAM. Example 1: Program ROM Operation 1. 2. 3. 4. 5. Develop assembly code; program this into the U5 Cypress CY7C261-45 EPROM. Remove power from the development board. Install U5 into the development board. Set switch S3-1 for program ROM operation (see Table 2) Apply power to the board.
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6. Switch S3-2 (see Table 2) and Switch S1-5 (see Table 1) will determine the board' operation mode at s power up reset. Switch S3-2 controls the Run on Reset mode. If enabled the program will begin executing the program from address 0 following a reset. If disabled the program will be halted at address 0, waiting for commands from the PC to run, single step, etc. Switch S1-5 controls the Suspend on Power On Reset mode. If enabled the board goes into suspend mode (see section 5.4) following a Power On Reset. It will stay suspended until there is a non-idle state on the USB bus input or an interrupt occurs. When this mode is used the Run on Reset should also be enabled. Example 2. Program RAM Operation 1. Develop assembly code; assemble and create object code file (see CYASM Assembler User' Guide; the s object file has a .rom suffix). 2. Set switch S3-1 for program RAM operation. 3. Apply power to the board, and halt microcontroller execution (use the "break" command on the PC debug software, or have switch S3-2 set to halt operation at power up reset). 4. Download the user object code file to program RAM (refer to the USB Development System Software Guide). 5. Press the reset switch S2. 6. Switch S3-2 (see Table 2) and Switch S1-5 (see Table 1) will determine the board' operation mode at s power up reset. Switch S3-2 controls the Run on Reset mode. If enabled the program will begin executing the program from address 0 following a reset. If disabled the program will be halted at address 0, waiting for commands from the PC to run, single step, etc. Switch S1-5 controls the Suspend on Power On Reset mode. If enabled the board goes into suspend mode (see section 5.4) following a Power On Reset. It will stay suspended until there is a non-idle state on the USB bus input or an interrupt occurs. When this mode is used the Run on Reset should also be enabled. Firmware will be held in program RAM until modified via the PC interface, or until power is removed from the board. Switch S3-1 can be toggled as desired between ROM and RAM operation. In RAM mode, individual bytes of the program RAM can be modified via the debug software, if desired.
5.3. PC debug interface
Refer to the USB Development System Software Guide for information on operating in the PC debug mode.
5.4. I/O Port operation
On the development board, all I/O port bits (ports P0 to P3) operate identically, and are pseudo-bidirectional. As an output, each port bit provides a strong pull-down when a ` is written to the bit. When a ` is written to the port 0' 1' bit, it functions as a weak pull-up. The pull-up strength on the board is 10 k (components RS4, RS5 for port 0, RS6, RS7 for port 1). At all times, any read from an I/O port gives the digital value of the voltage on each pin. To configure any port bit as an input, a ` must be written to that bit, and the input signal must be able to sink the pull1' up current. The I/O ports may be configured as input only by setting switch S1-4 to the open position. I/O port operation of the Cypress USB ICs differs from the operation of the development board. In the IC, writing a ` to either a port 0/1 output typically puts that bit into Current Sink mode. The value of the output current at 0' each IC pin depends on settings written to internal control registers (consult the specification for more details). On the development board the output current is not programmable. The pull-up disable function on the development board also differs from the ICs. In the IC the Port Pull-Up Registers can disable the pull-up resistor and select the interrupt polarity for each I/O port bit. On the development board the interrupt polarity is selected, but to disable the pull-up resistor it must be manually removed from the board. The port pull-up resistors are resistor packs RS4 through RS11.
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After power up or manual reset, all I/O port bits have a ` written to them, leaving them in the input/weak-pullup 1' mode. Each port is accessed by performing an I/O write or read operation to the appropriate address. All bits of the port are written or read together. Port addresses are given in the device specification.
5.5. Suspend Mode
The development board supports a suspend mode. The board will enter suspend mode following a power on reset if switch S1-5 is set to "Enable Suspend on Power On Reset", or if a one is written to the Suspend bit of the "Status & Control" Register. When suspended, the microcontroller and the timer both stop. Any USB bus activity, a reset, or an interrupt will take the board out of suspend mode. The Run button on the PC debug monitor will only start the development board if a 1 was written to the Suspend bit of the Status & Control register. The Run button will not take it out of suspend if it entered suspend following a power on reset.
5.6. Reset
Resets can be from one of these sources: * Power on reset * USB Bus reset (if enabled by switch S1-1; see Table 1) * Watchdog reset (if enabled by switch S1-2; see Table 1) * Pressing switch S2 generates a power on reset. When one of these resets occur, the following actions take place: * Program counter is reset to zero. * Internal registers are reconfigured to their reset state (see device specification). *The board will enter suspend mode following a power on reset or a reset from switch S2, if switch S1-5 is set to Enable Suspend on Power On Reset. * Operation will resume from address zero if switch S3-2 is set to Run on Reset. Otherwise, operation halts at address zero, and must be started from the PC debug monitor. The contents of both the data RAM and the program RAM are undefined at power up, and are not affected by pressing the reset button.
5.7. USB Interface
The development board supports the low-speed (1.5 Mbps) USB mode. In this mode, the low-speed peripheral has a 1.5 k pull-up to +3.3V on the D- line. Resistor R4 provides this pull-up, and is included on the board (see Figure 4). The board is shipped without a D+ pull-up at resistor R5. Refer to the USB 1.0 specification for further details on the low-speed USB mode. For details on USB transmit and receive operation with the development board, consult the specification for the emulated Cypress USB device.
6. Pin Descriptions
The development board contains three signal connectors: J1, a 60-pin header carrying target system signals; J2, a 60-pin header containing microcontroller interface signals (typically for logic analyzer connection); and J3, a 9-pin
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RS232 connector for communication with a PC. These are described in detail below.
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6.1. Target Chip and Connector J1
Please note that the square pad on the bottom side of the printed wiring may not correctly reflect the position of pin 1. Refer to the diagrams in this documentation for the correct location of J1 pin 1. Pin-outs for the 18-pin DIP and 20 / 24-pin SOIC configurations the Cypress USB IC family are given in Table 3. Note that not all chip pins are implemented on the emulation board. All other pins on connector J1 are test points, and should not be connected to any other signal.
Table 3: Target Chip Pins
Pin Name P0[7] P0[6] P0[5] P0[4] P0[3] P0[2] P0[1] P0[0] VSS VCC VPP Xi Xo Cext USB D+ USB D- P1[7] P1[6] P1[5] P1[4] P1[3] P1[2] P1[1] P1[0] 18-DIP Pin # 15 16 17 18 4 3 2 1 6 11 7 9 10 8 13 12 14 5 20-SOIC Pin # 17 18 19 20 4 3 2 1 7 12 8 10 11 9 14 13 15 6 16 5 24-SOIC Pin # 21 22 23 24 4 3 2 1 9 14 10 12 13 11 16 15 17 8 18 7 19 6 20 5 Description Port 0, Bit 7 (MSB) Port 0, Bit 6 Port 0, Bit 5 Port 0, Bit 4 Port 0, Bit 3 Port 10, Bit 2 Port 0, Bit 1 Port 0, Bit 0 (LSB) Ground Positive Supply (+5V) EPROM Supervoltage* Oscillator input* Oscillator output* External RC wake-up USB D+ USB D- Port 1, Bit 7 (24p SOIC only) Port 1, Bit 6 (24p SOIC only) Port 1, Bit 5 (24p SOIC only) Port 1, Bit 4 (24p SOIC only) Port 1, Bit 3 (SOIC only) Port 1, Bit 2 (SOIC only) Port 1, Bit 1 Port 1, Bit 0 (LSB) J1 Pin # 7 8 5 6 3 4 1 2 59,60 57** * * * 43 42 41 15 16 13 14 11 12 9 10
* Not used on development system board ** Requires jumper JP1 to connect to +5V on the development system board (see Section 3.2)
6.2. J2 - Microcontroller Signals
For debug purposes, microcontroller interface signals are available at connector J2. Table 4 gives pin functions for the signals, and Table 5 lists all signal locations on the J2 connector. Consult Figure 4 for the correct position of pin
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Table 4: J2 Pin Descriptions
NAME IA[12:0] ID[7:0] IROMS_ IRAMS_ IRAMR_ IRAMW_ DB[7:0] DA[7:0] MR_ MW_ IOW_ IOR_ SOI TRQ IRQ IRA BRA BRQ RESET MASTER RESET CLOCK VCC GND FUNCTION 13-bit address bus for program memory 8-bit Instruction Data from program memory Program ROM chip select (active low) Program RAM chip select (active low) Program RAM read enable (active low) Program RAM write enable (active low) 8-bit RAM Data bus 8-bit RAM Address bus Memory read enable for data RAM (active low) Memory write enable for data RAM (active low) I/O write enable (active low) I/O read enable (active low) Start of instruction - goes high at beginning of new instruction Test Mode Request Interrupt Request Signal Interrupt Acknowledge Bus Request Acknowledge Bus Request - When high, data and address busses are driven externally Not used Reset signal for the board (active high) 12 MHz clock signal Connection to development board' +5V s Ground
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CY3650 USB Development System User' Guide s Table 5: J2 Connector Pin-out
Pin # 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 Description IA0 IA2 IA4 IA6 IA8 IA10 IA12 IRAMS_ IRAMW_ IOR_ IRQ BRA RESET MR_ GND ID1 ID3 ID5 ID7 CLOCK DB7 DB5 DB3 DB1 DA7 DA5 DA3 DA1 VCC Pin # 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 Description IA1 IA3 IA5 IA7 IA9 IA11 GND IRAMR_ IOW_ SOI BRQ IRA TRQ MASTER RESET MW_ ID0 ID2 ID4 ID6 IROMS_ GND DB6 DB4 DB2 DB0 DA6 DA4 DA2 DA0 GND
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6.3. J3 - RS232 Connector
J3 is a 9-pin male connector for RS-232 interface to a host PC. Connections are shown in Table 6. Pins not listed are not connected .
Table 6: J3 RS-232 Connector Pin-out
Pin 2 3 6 7 Function RXD - Output data to PC TXD - Input data from PC DSR - RUN_ signal to PC debug interface RTS - input from PC (not used)
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