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S6B0718
104 SEG / 81 COM DRIVER & CONTROLLER FOR STN LCD
Feb. 2000. Ver. 2.1
Prepared by: Hyoung-Seok Lee lhs98@samsung.co.kr Contents in this document are subject to change without notice. No part of this document may be reproduced or transmitted in any form or by any means, electronic or mechanical, for any purpose, without the express written permission of LCD Driver IC Team.
104 SEG / 81 COM DRIVER & CONTROLLER FOR STN LCD
S6B0718
S6B0718 Specification Revision History Version 0.0 0.1 Original Modify syntax errors Append n-line inversion wave form to figure 11 on page 19. Modify figure 12 on page 20 Change the number of COM/SEG (85COM / 100SEG -> 81COM / 104SEG) Modify PAD location 1.1 Append PAD center coordinates to table 1, 2 on page 4, 5 Append referential instruction setup flow on page 48 to 51 Change bumped PAD size (modify figure 2 and table 1 on page 3) Change the PAD Center Coordinates of COM39 and COMS1. (modify table 2 on page 4) Change LCD power supply voltage (modify VOUT and V0 voltage on page1, 52, 53, 54, 55) Modify Set partial display duty ratio (refer to page 32) Modify N-line Inversion Register "2 to 32" -> "3 to 33" (refer to page 41) Change Consumption Current "2mA" -> "2uA", "10mA" -> " 10uA" (refer to page 47) Add Partial Duty Changing "Waiting for Discharging the LCD Power Levels (refer to figure 39) Fix the TBD Value of DC/AC Characteristics. Remove N-line Inversion function. Change the supply voltage(VDD) range (2.4 to 5.5 -> 2.4 to 3.6) Repair the COG/ILB align key coordinate. Change sales/product code to integration code (KS0718 -> S6B0718) Apr.1999 Content Date Nov.1998 Dec.1998
1.0
Mar.1999
1.2
May.1999
1.3
Jun.1999
1.4 1.4 2.0 2.0 2.1
Aug.1999 Oct. 1999 Nov. 1999 Dec. 1999 Feb. 2000
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S6B0718
104 SEG / 81 COM DRIVER & CONTROLLER FOR STN LCD
CONTENTS
INTRODUCTION ..................................................................................................................................................1 BLOCK DIAGRAM ...............................................................................................................................................2 PAD CONFIGURATION .......................................................................................................................................3 PAD CENTER COORDINATES............................................................................................................................5 PIN DESCRIPTION ..............................................................................................................................................7 POWER SUPPLY..........................................................................................................................................7 LCD DRIVER SUPPLY..................................................................................................................................7 SYSTEM CONTROL .....................................................................................................................................8 MICROPROCESSOR INTERFACE ...............................................................................................................9 LCD DRIVER OUTPUTS .............................................................................................................................11 FUNCTIONAL DESCRIPTION............................................................................................................................12 MICROPROCESSOR INTERFACE .............................................................................................................12 DISPLAY DATA RAM (DDRAM) ..................................................................................................................15 LCD DISPLAY CIRCUITS............................................................................................................................19 LCD DRIVER CIRCUIT ...............................................................................................................................21 POWER SUPPLY CIRCUITS ......................................................................................................................24 REFERECE CIRCUIT EXAMPLES..............................................................................................................29 RESET CIRCUIT .........................................................................................................................................31 INSTRUCTION DESCRIPTION...........................................................................................................................32 SPECIFICATIONS..............................................................................................................................................51 ABSOLUTE MAXIMUM RATINGS...............................................................................................................51 DC CHARACTERISTICS.............................................................................................................................52 AC CHARACTERISTICS .............................................................................................................................55 REFERENCE APPLICATIONS...........................................................................................................................59 MICROPROCESSOR INTERFACE .............................................................................................................59 CONNECTIONS BETWEEN S6B0718 AND LCD PANEL ............................................................................60
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S6B0718
104 SEG / 81 COM DRIVER & CONTROLLER FOR STN LCD
INTRODUCTION
The S6B0718 is a driver & controller LSI for graphic dot-matrix liquid crystal display systems. It contains 81 common and 104 segment driver circuits. This chip is connected directly to a microprocessor, accepts serial or 8-bit parallel display data and stores in an on-chip display data RAM of 89 x 104 bits. It provides a highly flexible display section due to 1-to-1 correspondence between on-chip display data RAM bits and LCD panel pixels. And it performs display data RAM read/write operation with no externally operating clock to minimize power consumption. In addition, because it contains power supply circuits necessary to drive liquid crystal, it is possible to make a display system with the fewest components.
FEATURES
Driver Output Circuits - 81 common outputs / 104 segment outputs Applicable Duty Ratios Programmable duty ratio - - - - - - - - - - - - - - - - - 1/9 to 1/81 Various partial display Partial window moving & data scrolling Applicable LCD bias 1/4 to 1/11 Maximum display area 81 x 104
On-chip Display Data RAM Capacity: 89 x 104 = 9,256 bits Bit data "1": a dot of display is illuminated. Bit data "0": a dot of display is not illuminated.
Microprocessor Interface 8-bit parallel bi-directional interface with 6800-series or 8080-series Serial interface (only write operation) available On-chip oscillator circuit Voltage converter (x3, x4, x5 or x6) Voltage regulator (temperature coefficient: -0.05%/C or external input) On-chip electronic contrast control function (64 steps) Voltage follower (LCD bias: 1/4 to 1/11)
On-chip Low Power Analog Circuit
Operating Voltage Range Supply voltage (VDD): 2.4 to 3.6 V LCD driving voltage (VLCD = V0 - VSS): 4.0 to 15.0 V 150 Max. (VDD = 3V, x5 boosting, V0 = 12V, internal power supply on and display OFF) 15 Max. (during power save [standby] mode) Gold bumped chip or TCP
Low power Consumption
Package Type
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104 SEG / 81 COM DRIVER & CONTROLLER FOR STN LCD
S6B0718
BLOCK DIAGRAM
SEG103 SEG102 SEG101 : : SEG2 SEG1 SEG0 COMS1 COM79 : : : COM0 COMS
VDD V0 V1 V2 V3 V4 VSS
104 SEGMENT DRIVER CIRCUITS
82 COMMON DRIVER CIRCUITS
SEGMENT CONTROLLER
COMMON CONTROLLER
HPMB
V/F CIRCUIT PAGE ADDRESS CIRCUIT V/R CIRCUIT COLUMN ADDRESS CIRCUIT DISPLAY DATA RAM 89 X 104 = 9,256 Bits LINE ADDRESS CIRCUIT DISPLAY TIMING GENERATOR CIRCUIT STATIC DRIVER MS CL SYNC M FRS FR
V0 VR INTRS VEXT REF
VOUT C1C1+ C2C2+ C3+ C4+ C5+ VCI
OSCILLATOR
V/C CIRCUIT INSTRUCTION DECODER & REGISTER
INTERNAL POWER SUPPLY
BUS HOLDER
STATUS REGISTER
MPU INTERFACE (PARALLEL & SERIAL)
Figure 1. Block Diagram
DB0 DB1 DB2 DB3 DB4 DB5 DB6(SCLK) DB7(SID) RW_WR E_RD RS CS2 CS1B PS C68 RESETB
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S6B0718
104 SEG / 81 COM DRIVER & CONTROLLER FOR STN LCD
PAD CONFIGURATION
242 243 113 112
- - - - - - - - - -
Y
- - - -
- - - -
S6B0718
(TOP VIEW, PADS UP) (0,0) X
274
- - - - - - - - - -
1 80
81
Figure 2. S6B0718 Chip Configuration
Table 1. S6B0718 Pad Dimensions Item Chip size Pad No. 1 to 80 82 to 110 115 to 240 Pad pitch 245 to 273 81 111 to 114 241 to 244 274 1 to 80 81 82 to 110 111 to 112 Bumped pad size (Max.) 113 to 114 115 to 240 241 to 242 243 to 244 245 to 273 274 Bumped pad height All pad 54 110 110 110 60 40 60 110 110 110 14 (Typ.) 112 80 40 60 110 110 110 60 40 80 m 80 60 Size X 8350 90 Y 2380 Unit
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104 SEG / 81 COM DRIVER & CONTROLLER FOR STN LCD
S6B0718
COG Align Key Coordinate
30m 30m 30m
ILB Align Key Coordinate
42m 108m 108m 42m
30m 30m 30m
(-3493.5, +488.5)
42m
(+3565, +640)
108m
108m (+3493.5, -408.5)
42m
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S6B0718
104 SEG / 81 COM DRIVER & CONTROLLER FOR STN LCD
PAD CENTER COORDINATES
Table 2. Pad Center Coordinates [Unit: m]
No.
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
Name
FRS FR TEST1 TEST2 TEST3 CL M SYNC VSS HPMB MS VDD PS C68 VSS CS1B CS2 VDD RESETB RS VSS RW_WR E_RD VDD DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 VDD VDD VDD VDD VDD VCI VCI VSS VSS VSS VSS VSS VOUT VOUT VOUT VOUT C5+ C5+
X
-3555 -3465 -3375 -3285 -3195 -3105 -3015 -2925 -2835 -2745 -2655 -2565 -2475 -2385 -2295 -2205 -2115 -2025 -1935 -1845 -1755 -1665 -1575 -1485 -1395 -1305 -1215 -1125 -1035 -945 -855 -765 -675 -585 -495 -405 -315 -225 -135 -45 45 135 225 315 405 495 585 675 765 855
Y
-1066 -1066 -1066 -1066 -1066 -1066 -1066 -1066 -1066 -1066 -1066 -1066 -1066 -1066 -1066 -1066 -1066 -1066 -1066 -1066 -1066 -1066 -1066 -1066 -1066 -1066 -1066 -1066 -1066 -1066 -1066 -1066 -1066 -1066 -1066 -1066 -1066 -1066 -1066 -1066 -1066 -1066 -1066 -1066 -1066 -1066 -1066 -1066 -1066 -1066
No.
51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100
Name
C3+ C3+ C1C1C1+ C1+ C2+ C2+ C2C2C4+ C4+ VSS REF VEXT VDD INTRS VSS V4 V4 V3 V3 V2 V2 V1 V1 V0 V0 VR VR COM39 COM38 COM37 COM36 COM35 COM34 COM33 COM32 COM31 COM30 COM29 COM28 COM27 COM26 COM25 COM24 COM23 COM22 COM21 COM20
X
945 1035 1125 1215 1305 1395 1485 1575 1665 1755 1845 1935 2025 2115 2205 2295 2385 2475 2565 2655 2745 2835 2925 3015 3105 3195 3285 3375 3465 3555 4028 4028 4028 4028 4028 4028 4028 4028 4028 4028 4028 4028 4028 4028 4028 4028 4028 4028 4028 4028
Y
-1066 -1066 -1066 -1066 -1066 -1066 -1066 -1066 -1066 -1066 -1066 -1066 -1066 -1066 -1066 -1066 -1066 -1066 -1066 -1066 -1066 -1066 -1066 -1066 -1066 -1066 -1066 -1066 -1066 -1066 -1030 -950 -890 -830 -770 -710 -650 -590 -530 -470 -410 -350 -290 -230 -170 -110 -50 10 70 130
No.
101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150
Name
COM19 COM18 COM17 COM16 COM15 COM14 COM13 COM12 COM11 COM10 DUMMY DUMMY DUMMY DUMMY COM9 COM8 COM7 COM6 COM5 COM4 COM3 COM2 COM1 COM0 COMS SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24
X
4028 4028 4028 4028 4028 4028 4028 4028 4028 4028 4028 4028 3910 3830 3750 3690 3630 3570 3510 3450 3390 3330 3270 3210 3150 3090 3030 2970 2910 2850 2790 2730 2670 2610 2550 2490 2430 2370 2310 2250 2190 2130 2070 2010 1950 1890 1830 1770 1710 1650
Y
190 250 310 370 430 490 550 610 670 730 810 890 1043 1043 1043 1043 1043 1043 1043 1043 1043 1043 1043 1043 1043 1043 1043 1043 1043 1043 1043 1043 1043 1043 1043 1043 1043 1043 1043 1043 1043 1043 1043 1043 1043 1043 1043 1043 1043 1043
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104 SEG / 81 COM DRIVER & CONTROLLER FOR STN LCD
S6B0718
Table 2. Pad Center Coordinates (Continued) [Unit: m]
No.
151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200
Name
SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 SEG38 SEG39 SEG40 SEG41 SEG42 SEG43 SEG44 SEG45 SEG46 SEG47 SEG48 SEG49 SEG50 SEG51 SEG52 SEG53 SEG54 SEG55 SEG56 SEG57 SEG58 SEG59 SEG60 SEG61 SEG62 SEG63 SEG64 SEG65 SEG66 SEG67 SEG68 SEG69 SEG70 SEG71 SEG72 SEG73 SEG74
X
1590 1530 1470 1410 1350 1290 1230 1170 1110 1050 990 930 870 810 750 690 630 570 510 450 390 330 270 210 150 90 30 -30 -90 -150 -210 -270 -330 -390 -450 -510 -570 -630 -690 -750 -810 -870 -930 -990 -1050 -1110 -1170 -1230 -1290 -1350
Y
1043 1043 1043 1043 1043 1043 1043 1043 1043 1043 1043 1043 1043 1043 1043 1043 1043 1043 1043 1043 1043 1043 1043 1043 1043 1043 1043 1043 1043 1043 1043 1043 1043 1043 1043 1043 1043 1043 1043 1043 1043 1043 1043 1043 1043 1043 1043 1043 1043 1043
No.
201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250
Name
SEG75 SEG76 SEG77 SEG78 SEG79 SEG80 SEG81 SEG82 SEG83 SEG84 SEG85 SEG86 SEG87 SEG88 SEG89 SEG90 SEG91 SEG92 SEG93 SEG94 SEG95 SEG96 SEG97 SEG98 SEG99 SEG100 SEG101 SEG102 SEG103 COM40 COM41 COM42 COM43 COM44 COM45 COM46 COM47 COM48 COM49 COM50 DUMMY DUMMY DUMMY DUMMY COM51 COM52 COM53 COM54 COM55 COM56
X
-1410 -1470 -1530 -1590 -1650 -1710 -1770 -1830 -1890 -1950 -2010 -2070 -2130 -2190 -2250 -2310 -2370 -2430 -2490 -2550 -2610 -2670 -2730 -2790 -2850 -2910 -2970 -3030 -3090 -3150 -3210 -3270 -3330 -3390 -3450 -3510 -3570 -3630 -3690 -3750 -3830 -3910 -4028 -4028 -4028 -4028 -4028 -4028 -4028 -4028
Y
1043 1043 1043 1043 1043 1043 1043 1043 1043 1043 1043 1043 1043 1043 1043 1043 1043 1043 1043 1043 1043 1043 1043 1043 1043 1043 1043 1043 1043 1043 1043 1043 1043 1043 1043 1043 1043 1043 1043 1043 1043 1043 890 810 730 670 610 550 490 430
No.
251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274
Name
COM57 COM58 COM59 COM60 COM61 COM62 COM63 COM64 COM65 COM66 COM67 COM68 COM69 COM70 COM71 COM72 COM73 COM74 COM75 COM76 COM77 COM78 COM79 COMS1
X
-4028 -4028 -4028 -4028 -4028 -4028 -4028 -4028 -4028 -4028 -4028 -4028 -4028 -4028 -4028 -4028 -4028 -4028 -4028 -4028 -4028 -4028 -4028 -4028
Y
370 310 250 190 130 70 10 -50 -110 -170 -230 -290 -350 -410 -470 -530 -590 -650 -710 -770 -830 -890 -950 -1030
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S6B0718
104 SEG / 81 COM DRIVER & CONTROLLER FOR STN LCD
PIN DESCRIPTION
POWER SUPPLY
Table 3. Power Supply Pins Name VDD VSS I/O Supply Supply Power supply Ground LCD driver supplies voltages The voltage determined by LCD pixel is impedance converted by an operational amplifier for application. Voltages should have the following relationship; V0 V1 V2 V3 V4 VSS When the internal power circuit is active, these voltages are generated as following table according to the state of LCD bias. LCD bias V2 V3 V4 V1 1/N bias (N-1) / N x V0 (N-2) / N x V0 (2/N) x V0 (1/N) x V0 NOTE: N = 4 to 11 Description
V0 V1 V2 V3 V4
I/O
LCD DRIVER SUPPLY
Table 4. LCD Driver Supply Pins Name C1C1+ C2C2+ C3+ C4+ C5+ VOUT VCI VR I/O O O O O O O O I/O I I Description Capacitor 1 negative connection pin for voltage converter Capacitor 1 positive connection pin for voltage converter Capacitor 2 negative connection pin for voltage converter Capacitor 2 positive connection pin for voltage converter Capacitor 3 positive connection pin for voltage converter Capacitor 4 positive connection pin for voltage converter Capacitor 5 positive connection pin for voltage converter Voltage converter input / output pin Voltage converter input voltage pin Voltages should have the following relationship: VDD VCI V0 V0 voltage adjustment pin It is valid only when on-chip resistors are not used (INTRS = "L") Selects the external VREF voltage via VEXT pin - REF = "L": using the external VREF - REF = "H": using the internal VREF Externally input reference voltage (VREF) for the internal voltage regulator It is valid only when REF is "L".
REF
I
VEXT
I
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104 SEG / 81 COM DRIVER & CONTROLLER FOR STN LCD
S6B0718
SYSTEM CONTROL
Table 5. System Control Pins Name I/O Description Master / slave operations select pin - MS = "H": master operation - MS = "L": slave operation The following table depends on the MS status. MS I MS H L Internal analog circuits Oscillator Enabled Disabled Power supply Enabled Disabled CL Output Input Display timing signals SYNC Output Input M Output Input
CL
I/O
Display clock input / output pin When the S6B0718 is used in master/slave mode (Multi-chip), the CL pins must be connected each other. Display sync input / output pin When the S6B0718 is used in master/slave mode (Multi-chip), the SYNC pins must be connected each other. LCD AC signals input / output pin When the S6B0718 is used in master/slave mode (Multi-chip), the M pins must be connected each other. Static driver common output pin This pin is used together with the FRS pin. Static driver segment output pin This pin is used together with the FR pin. Internal resistors select pin This pin selects the resistors for adjusting V0 voltage level. - INTRS = "H": use the internal resistors - INTRS = "L": use the external resistors VR pin and external resistive divider control V0 voltage. Power control pin of the power supplies circuit for LCD driver - HPMB = "L": high power mode - HPMB = "H": normal mode This pin is valid in master operation. Test pins Don' t use these pins.
SYNC
I/O
M
I/O
FR FRS
O O
INTRS
I
HPMB
I
TEST1 to TEST3
I
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S6B0718
104 SEG / 81 COM DRIVER & CONTROLLER FOR STN LCD
MICROPROCESSOR INTERFACE
Table 6. Microprocessor Interface Pins Name RESETB I/O I Reset the input pin When RESETB is "L", initialization is executed. Parallel/Serial data input select input PS PS I Interface Mode Parallel Serial Data/ Instruction RS RS Data Read / Write E_RD RW_WR Write only Serial Clock Description
H L
DB0 to DB7 SID(DB7)
SCLK(DB6)
*NOTE: When PS is "L", DB0 to DB5 are high impedance and E_RD and RW_WR must be fixed to either "H" or "L". C68 CS1B CS2 RS I Microprocessor interface select input pin - C68 = "H": 6800-series MPU interface - C68 = "L": 8080-series MPU interface Chip select input pins Data/instruction I/O is enabled only when CS1B is "L" and CS2 is "H". When chip select is non-active, DB0 to DB7 may be high impedance. Register select input pin - RS = "H": DB0 to DB7 are display data - RS = "L": DB0 to DB7 are control data Read / Write execution control pin C68 H RW_WR I L 8080-series /WR MPU Type 6800-series RW_WR RW Description Read/Write control input pin - RW = "H": read - RW = "L": write Write enable clock input pin The data on DB0 to DB7 are latched at the rising edge of the /WR signal.
I
I
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104 SEG / 81 COM DRIVER & CONTROLLER FOR STN LCD
S6B0718
Table 6 (Continued) Name I/O Read / Write execution control pin C68 MPU Type E_RD Description Read/Write control input pin - RW = "H": When E is "H", DB0 to DB7 are in an output status. - RW = "L": The data on DB0 to DB7 are latched at the falling edge of the E signal. Read enable clock input pin When /RD is "L", DB0 to DB7 are in an output status. Description
E_RD
I
H
6800-series
E
L
8080-series
/RD
DB0 to DB7
I/O
8-bit bi-directional data bus that is connected to the standard 8-bit microprocessor data bus. When the serial interface selected (PS = "L"); - DB0 to DB5: high impedance - DB6: serial input clock (SCLK) - DB7: serial input data (SID) When chip select is not active, DB0 to DB7 may be high impedance.
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S6B0718
104 SEG / 81 COM DRIVER & CONTROLLER FOR STN LCD
LCD DRIVER OUTPUTS
Table 7. LCD Driver Outputs Pins Name I/O Description LCD segment driver outputs The display data and the M signal control the output voltage of segment driver. Display data SEG0 to SEG103 H O H L L Power save mode M H L H L Segment driver output voltage Normal display V0 VSS V2 V3 VSS Reverse display V2 V3 V0 VSS VSS
LCD common driver outputs The internal scanning data and M signal control the output voltage of common driver. Scan data COM0 to COM79 H O H L L Power save mode COMS (COMS1) M H L H L Common driver output voltage VSS V0 V1 V4 VSS
O
Common output for the icons The output signals of two pins are same. When not used, these pins should be left open.
NOTE: DUMMY - These pins should be opened (floated).
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104 SEG / 81 COM DRIVER & CONTROLLER FOR STN LCD
S6B0718
FUNCTIONAL DESCRIPTION
MICROPROCESSOR INTERFACE
Chip Select Input There are CS1B and CS2 pins for chip selection. The S6B0718 can interface with an MPU only when CS1B is "L" and CS2 is "H". When these pins are set to any other combination, RS, E_RD, and RW_WR inputs are disabled and DB0 to DB7 are to be high impedance. And, in case of serial interface, the internal shift register and the counter are reset. Parallel / Serial Interface S6B0718 has three types of interface with an MPU, which are one serial and two parallel interface. This parallel or serial interface is determined by PS pin as shown in table 8 Table 8. Parallel / Serial Interface Mode PS H L Type Parallel Serial CS1B CS1B CS1B CS2 CS2 CS2 C68 H L *x Interface mode 6800-series MPU mode 8080-series MPU mode Serial-mode
*x: Don't care
Parallel Interface (PS = "H") The 8-bit bi-directional data bus is used in parallel interface and the type of MPU is selected by C68 as shown in Table 9. The type of data transfer is determined by signals at RS, E_RD and RW_WR as shown in table 10. Table 9. Microprocessor Selection for Parallel Interface C68 H L CS1B CS1B CS1B CS2 CS2 CS2 RS RS RS E_RD E /RD RW_WR RW /WR DB0 to DB7 DB0 to DB7 DB0 to DB7 MPU bus 6800-series 8080-series
Table 10. Parallel Data Transfer Common RS H H L L 6800-series E_RD (E) H H H H RW_WR (RW) H L H L 8080-series E_RD (/RD) L H L H RW_WR (/WR) H L H L Display data read out Display data write Register status read Writes to internal register (instruction) Description
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S6B0718
104 SEG / 81 COM DRIVER & CONTROLLER FOR STN LCD
Serial Interface (PS = "L") When the S6B0718 is active, serial data (DB7) and serial clock (DB6) inputs are enabled. And not active, the internal 8-bit shift register and the 3-bit counter are reset. Serial data can be read on the rising edge of serial clock going into DB6 and processed as 8-bit parallel data on the eighth serial clock. Serial data input is display data when RS is high and control data when RS is low. Since the clock signal (DB6) is easy to be affected by the external noise caused by the line length, the operation check on the actual machine is recommended.
CS1B
CS2
SID
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
DB7
DB6
SCLK
RS
Figure 3. Serial Interface Timing Busy Flag The Busy Flag indicates whether the S6B0718 is operating or not. When DB7 is "H" in read status operation, this device is in busy status and will accept only read status instruction. If the cycle time is correct, the microprocessor needs not to check this flag before each instruction, which improves the MPU performance.
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104 SEG / 81 COM DRIVER & CONTROLLER FOR STN LCD
S6B0718
Data Transfer The S6B0718 uses bus holder and internal data bus for Data Transfer with the MPU. When writing data from the MPU to on-chip RAM, data is automatically transferred from the bus holder to the RAM as shown in figure 4. And when reading data from on-chip RAM to the MPU, the data for the initial read cycle is stored in the bus holder (dummy read) and the MPU reads this stored data from bus holder for the next data read cycle as shown in figure 5. This means that a dummy read cycle must be inserted between each pair of address sets when a sequence of address sets is executed. Therefore, the data of the specified address cannot be output with the read display data instruction right after the address sets, but can be output at the second read of data.
MPU signals
RS
/W R
DB0 to DB7
N
D(N)
D(N+1)
D(N+2)
D(N+3)
Internal signals
/W R N D(N) D(N+1) D(N+2) D(N+3)
BUS HOLDER
COLUMN ADDRESS
N
N+1
N+2
N+3
Figure 4. Write Timing
MPU signals
RS /W R /RD DB0 to DB7 N Dummy D(N) D(N+1)
Internal signals
/W R /RD BUS HOLDER COLUMN ADDRESS N N D(N) N+1 D(N+1) N+2 D(N+2) N+3
Figure 5. Read Timing
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S6B0718
104 SEG / 81 COM DRIVER & CONTROLLER FOR STN LCD
DISPLAY DATA RAM (DDRAM)
The Display Data RAM stores pixel data for the LCD. It is 89-row by 104-column addressable array. Each pixel can be selected when the page and column addresses are specified. The 89 rows are divided into 11 pages of 8 lines and the 12th page with a single line (DB0 only). Data is read from or written to the 8 lines of each page directly through DB0 to DB7. The display data of DB0 to DB7 from the microprocessor correspond to the LCD common lines as shown in figure 6. The microprocessor can read from and write to RAM through the I/O buffer. Since the LCD controller operates independently, data can be written into RAM at the same time as data is being displayed without causing the LCD flicker.
DB0 DB1 DB2 DB3 DB4
0 1 0 1 0
0 0 1 0 0
1 0 1 1 0
------
0 1 0 0 1
COM0 COM1 COM2 COM3 COM4 LCD Display
------
Display Data RAM
Figure 6. RAM-to-LCD Data Transfer Page Address Circuit
This circuit is for providing a Page Address to Display Data RAM shown in figure 8. It incorporates 4-bit Page Address register changed by only the "Set Page" instruction. Page Address 11 (DB3, DB1 and DB0 are "H", DB2 is "L") is a special RAM area for the icons and display data DB0 is only valid. Line Address Circuit This circuit assigns DDRAM a Line Address corresponding to the first line (COM0) of the display. Therefore, by setting line address repeatedly, it is possible to realize the screen scrolling and page switching without changing the contents of on-chip RAM as shown in figure 8 & figure 9. It incorporates 7-bit Line Address register changed by only the initial display line instruction and 7-bit counter circuit. At the beginning of each LCD frame, the contents of register are copied to the line counter which is increased by CL signal and generates the Line Address for transferring the 104-bit RAM data to the display data latch circuit. However, display data of icons are not scrolled because the MPU can not access Line Address of icons.
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104 SEG / 81 COM DRIVER & CONTROLLER FOR STN LCD
S6B0718
Column Address Circuit Column address circuit has a 7-bit preset counter that provides column address to the Display Data RAM as shown in figure 8. When set Column Address MSB / LSB instruction is issued, 7-bit [Y6:Y0] is updated. And, since this address is increased by 1 each a read or write data instruction, microprocessor can access the display data continuously. However, the counter is not incremented and locked if a non-existing address above 67H. It is unlocked if a Column Address is set again by set Column Address MSB / LSB instruction. And the Column Address counter is independent of page address register. ADC Select instruction makes it possible to invert the relationship between the column address and the segment outputs. It is necessary to rewrite the display data on built-in RAM after issuing ADC Select instruction. Refer to the following figure 7. SEG output Column address [Y6:Y0] Display data LCD panel display ( ADC = 0 ) SEG 0 00H 1 SEG 1 01H 0 SEG 2 02H 1 SEG 3 03H 0 ... ... ... ... ... ... SEG 100 64H 1 SEG 101 65H 1 SEG 102 66H 0 SEG 103 67H 0
LCD panel display ( ADC = 1 )
... ...
Figure 7. The Relationship between the Column Address and the Segment Outputs
Segment Control Circuit This circuit controls the display data by the Display ON / OFF, reverse display ON / OFF and entire display ON / OFF instructions without changing the data in the display data RAM.
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Page Address
DB3 DB2 DB1 DB0
Data
DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7
Line Address 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH
Initial line register = 00H
COM Output COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15 COM16 COM17 COM18 COM19 COM20 COM21 COM22 COM23 COM24 COM25 COM26 COM27 COM28 COM29 COM30 COM31
0
0
0
0
Page 0
1/81 Duty
0
0
0
1
Page 1
0
0
1
0
Page 2
0
0
1
1
Page 3
0
1
1
1
1
0
0
0
1
0
0
1
1
0
1
0
1
0
Column Address
1
1
DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB0 00 01 02 03 04 05 67 66 65 64 63 62 SEG0 SEG1 SEG2 SEG3 SEG4 SEG5
Page7
Page8
Page9
Page10
38H 39H 3AH 3BH 3CH 3DH 3EH 3FH 40H 41H 42H 43H 44H 45H 46H 47H 48H 49H 4AH 4BH 4CH 4DH 4EH 4FH 50H 51H 52H 53H 54H 55H 56H 57H 62 63 64 65 66 67 05 04 03 02 01 00 SEG100 SEG102 SEG103 SEG101 SEG98 SEG99
1/73 Duty
COM56 COM57 COM58 COM59 COM60 COM61 COM62 COM63 COM64 COM65 COM66 COM67 COM68 COM69 COM70 COM71 COM72 COM73 COM74 COM75 COM76 COM77 COM78 COM79
Page 11
COMS
ADC=0 ADC=1
-------------
LCD Output
When Initial line address = 00H
Figure 8. Display Data RAM Map (Initial Line Address = 00H)
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104 SEG / 81 COM DRIVER & CONTROLLER FOR STN LCD
S6B0718
Page Address
DB3 DB2 DB1 DB0
Data
DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7
Line Address 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH
Initial line register = 08H
COM Output
0
0
0
0
Page 0
0
0
0
1
Page 1
0
0
1
0
Page 2
0
0
1
1
Page 3
COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15 COM16 COM17 COM18 COM19 COM20 COM21 COM22 COM23
1/81 Duty
0
1
1
1
1
0
0
0
1
0
0
1
1
0
1
0
1
0
Column Address
1
1
DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB0 00 01 02 03 04 05 67 66 65 64 63 62 SEG0 SEG1 SEG2 SEG3 SEG4 SEG5
1/73 Duty
Page 7
Page9 Page 8
Page 9
Page 10 Page11
38H 39H 3AH 3BH 3CH 3DH 3EH 3FH 40H 41H 42H 43H 44H 45H 46H 47H 48H 49H 4AH 4BH 4CH 4DH 4EH 4FH 50H 51H 52H 53H 54H 55H 56H 57H
Page 11
COM47 COM48 COM49 COM50 COM51 COM52 COM53 COM54 COM55 COM57 COM58 COM59 COM60 COM61 COM62 COM63 COM64 COM65 COM66 COM67 COM68 COM69 COM70 COM71 COM72 COM73 COM74 COM75 COM76 COM77 COM78 COM79 COMS
ADC=0 ADC=1
-------------
62 63 64 65 66 67 05 04 03 02 01 00 SEG100 SEG101 SEG102 SEG103
LCD Output
When Initial line address = 08H
Figure 9. Display Data RAM Map (Initial Line Address = 08H)
SEG98
SEG99
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LCD DISPLAY CIRCUITS
Oscillator This is completely on-chip Oscillator and its frequency is nearly independent of VDD. This Oscillator signal is used in the voltage converter and display timing generation circuit. Display Timing Generator Circuit This circuit generates some signals to be used for displaying LCD. The display clock, CL, generated by oscillation clock, generates the clock for the line counter and the signal for the display data latch. The line address of on-chip RAM is generated in synchronization with the display clock (CL) and the display data latch circuit latches the 104bit display data in synchronization with the display clock. The display data, which is read to the LCD driver, is completely independent of the access to the display data RAM from the microprocessor. The display clock generates an LCD AC signal (M) which enables the LCD driver to make a AC drive waveform, and also generates an internal common timing signal and start signal to the common driver. The frame signal or the line signal changes the M by setting internal instruction. Driving waveform and internal timing signal are shown in figure 10. In a multiple chip configuration, the slave chip requires the CL, M and SYNC signals from the master. Table 11 shows the CL, SYNC, and M status. Table 11. Master and Slave Timing Signal Status Operation mode Master Slave Oscillator ON (internal clock used) OFF (external clock used) CL Output Input SYNC Output Input M Output Input
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80
81
1
2
3
4
5
6
7
8
9
10
11
12
74
75
76
77
78
79
80
81
1
2
3
4
5
6
CL
FR
M
V0 V1 V2 V3 V4 VSS V0 V1 V2 V3 V4 VSS V0 V1 V2 V3 V4 VSS
COM0
COM1
SEGn
Figure 10. 2-frame AC Driving Waveform (Duty Ratio = 1/81)
80
81
1
2
3
4
5
6
7
8
9
10
11
12
74
75
76
77
78
79
80
81
1
2
3
4
5
6
CL
FR
M
V0 V1 V2 V3 V4 VSS V0 V1 V2 V3 V4 VSS V0 V1 V2 V3 V4 VSS
COM0
COM1
SEGn
Figure 11. N-line Inversion Driving Waveform (N = 5, Duty Ratio = 1/81)
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LCD DRIVER CIRCUIT
81-channel common driver and 104-channel segment driver configure this driver circuit. This LCD panel driver voltage depends on the combination of display data and M signal.
COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7
VDD
M
VSS V0 V1 V2
COM0
V3 V4 VSS V0 V1 V2
COM1
V3 V4 VSS V0 V1 V2
COM8 COM9 COM10 COM11 COM12 COM13 COM14
COM2
V3 V4 VSS V0 V1 V2
SEG0
V3 V4 VSS V0 V1 V2
SEG1
COM15 S E G 0 S E G 1 S E G 2 S E G 3 S E G 4
V3 V4 VSS V0 V1 V2
SEG2
V3 V4 VSS
Figure 12. Segment and Common Timing
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S6B0718
Partial Display on LCD The S6B0718 realizes the Partial Display function on LCD with low-duty driving for saving power consumption and showing the various display duty. To show the various display duty on LCD, LCD driving duty and bias are programmable via the instruction. And, built-in power supply circuits are controlled by the instruction for adjusting the LCD driving voltages
-- COMS ------------------------COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15 COM16 COM17 COM18 COM19 COM20 COM21 COM22 COM23
Figure 13. Reference Example for Partial Display (Display Duty = 25)
-- COMS -- COM0 -- COM1 -- COM2 -- COM3 -- COM4 -- COM5 -- COM6 -- COM7 -- COM8 -- COM9 -- COM10 -- COM11 -- COM12 -- COM13 -- COM14 -- COM15 -- COM16 -- COM17 -- COM18 -- COM19 -- COM20 -- COM21 -- COM22 -- COM23
Figure 14. Partial Display (Partial Display Duty = 9, Initial COM0 = 0)
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104 SEG / 81 COM DRIVER & CONTROLLER FOR STN LCD
-- COMS ------------------------COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15 COM16 COM17 COM18 COM19 COM20 COM21 COM22 COM23
Figure 15. Moving Display (Partial Display Duty = 9, Initial COM0 = 8)
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S6B0718
POWER SUPPLY CIRCUITS
The Power Supply circuits generate the voltage levels necessary to drive liquid crystal driver circuits with low-power consumption and the fewest components. There are voltage converter circuits, voltage regulator circuits, and voltage follower circuits. They are valid only in master operation and controlled by power control instruction. For details, refers to "Instruction Description". Table 12 shows the referenced combinations in using Power Supply circuits. Table 12. Recommended Power Supply Combinations User setup Only the internal power supply circuits are used Only the voltage regulator circuits and voltage follower circuits are used Only the voltage follower circuits are used Only the external power supply circuits are used Power control (VC VR VF) 111 V/C circuits ON V/R circuits ON V/F circuits ON VOUT V0 V1 to V4
Open External input External input Open
Open
Open
011
OFF
ON
ON
Open
Open
001 000
OFF OFF
OFF OFF
ON OFF
Open External input
Open External input
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Voltage Converter Circuits These circuits boost up the electric potential between VCI and Vss to 3, 4, 5 or 6 times toward positive side and boosted voltage is outputted from VOUT pin. It is possible to select the lower boosting level in any boosting circuit by "Set DC-DC Step-up" instruction. When the higher level is selected by instruction, VOUT voltage is not valid. [C1 = 1.0 to 4.7 F] Vss VOUT C5+ C3+ C1C1+ C2+ C2 C4+
+ -
+
Vss C1 VOUT C5+ C3+ VOUT = 3 x VCI
+
C1
VOUT = 4 x VCI
+ +
C1 C1
+
C1C1+
C1 C2+ C2 Vss C4+
C1
VCI
+ -
C1
VCI Vss
Figure 16. Three Times Boosting Circuit
Figure 17. Four Times Boosting Circuit
Vss VOUT C5+ C3+ C1C1+ C2+ C2 C4+
+
Vss C1 VOUT VOUT = 5 x VCI C5+
+
C1 VOUT = 6 x VCI
C1
+ +
C3+ C1 C1C1 C1+ VCI Vss C2+ C2 C1 C4+
+ -
+ +
C1 C1
+ +
C1
+ +
C1 C1
VCI Vss
Figure 18. Five Times Boosting Circuit
Figure 19. Six Times Boosting Circuit
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104 SEG / 81 COM DRIVER & CONTROLLER FOR STN LCD
S6B0718
Voltage Regulator Circuits The function of the internal Voltage Regulator circuits is to determine liquid crystal operating voltage, V0, by adjusting resistors, Ra and Rb, within the range of |V0| < |VOUT|. Because VOUT is the operating voltage of operational-amplifier circuits shown in figure 20, it is necessary to be applied internally or externally. For the Eq. 1, we determine V0 by Ra, Rb and VEV. The Ra and Rb are connected internally or externally by INTRS pin. And VEV called the voltage of electronic volume is determined by Eq. 2, where the parameter is the value selected by instruction, "Set Reference Voltage Register", within the range 0 to 63. VREF voltage at Ta= 25C is shown in Table 13. Rb V0 = (1 + ) x VEV [V] ------ (Eq. 1) Ra
(63 - ) VEV = (1 - ) x VREF [V] ------ (Eq. 2) 200 Table 13. . VREF Voltage at Ta = 25C REF 1 0 Temp. coefficient -0.05% / C External input VREF [ V ] 2.0 VEXT
VOUT
+ V EV V0 Rb VR
Ra VSS
GND
Figure 20. Internal Voltage Regulator Circuit
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104 SEG / 81 COM DRIVER & CONTROLLER FOR STN LCD
In Case of Using Internal Resistors, Ra and Rb (INTRS = "H") When INTRS pin is "H", resistor Ra is connected internally between VR pin and VSS, and Rb is connected between V0 and VR. We determine V0 by two instructions, "Regulator Resistor Select" and "Set Reference Voltage". Table 14. Internal Rb / Ra Ratio depending on 3-bit Data (R2 R1 R0) 3-bit data settings (R2 R1 R0) 000 1 + (Rb / Ra) 2.6 001 3.4 010 4.2 011 5.0 100 5.8 101 6.6 110 7.4 111 8.3
Figure 21 Shows V0 voltage measured by adjusting internal regulator register ratio (Rb / Ra) and 6-bit electronic volume registers for each temperature coefficient at Ta = 25 C.
V0 voltage [V] 15.00 14.00 12.00 10.00 8.00 6.00 4.00 2.00 0.00 0 8 16 24 32 40 48 56 63 (1, 1, 1) (1, 1, 0) (1, 0, 1) (1, 0, 0) (0, 1, 1) (0, 1, 0) (0, 0, 1) (0, 0, 0) Rb/Ra ratio
Electronic volume resistor
Figure 21. Electronic Volume Level (Temp. Coefficient = -0.05% / C)
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In Case of Using External Resistors, Ra and Rb (INTRS = "L") When INTRS pin is "L", it is necessary to connect external regulator resistor Ra between VR and VSS, and Rb between V0 and VR. Example: For the following requirements 1. LCD driver voltage, V0 = 10V 2. 6-bit reference voltage register = (1, 0, 0, 0, 0, 0) 3. Maximum current flowing Ra, Rb = 1 uA From Eq. 1 Rb 10 = (1 + ) x VEV [V] ------ (Eq. 3) Ra From Eq. 1 (63 - 32) VEV = (1 - ) x 2.0 = 1.69 [V] ------ (Eq. 4) 200 From requirement 3. 10 = 1 [uA] ------ (Eq. 5) Ra + Rb
From equations Eq. 3, 4 and 5 Ra = 1.69 [M] Rb = 8.31 [M] Table 15 Shows the Range of V0 depending on the above Requirements. Table 15. The Range of V0 Electronic volume level 0 V0 Voltage Follower Circuits VLCD voltage (V0) is resistively divided into four voltage levels (V1, V2, V3 and V4), and those output impedance are converted by the Voltage Follower for increasing drive capability. Table 16 shows the relationship between V1 to V4 level and each duty ratio. Table 16 LCD bias 1/N V1 (N-1)/N x V0 V2 (N-1)/N x V0 V3 2/N x V0 V4 1/N x V0 Remarks N = 4 to 11 8.10 ....... ....... 32 10.00 ....... ....... 63 11.83
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REFERECE CIRCUIT EXAMPLES
[C1 = 1.0 to 4.7 [F], C2 = 0.1 to 0.47 [F]]
When using internal regulator resistors When not using internal regulator resistors
V DD MS VOUT C5+ C3+ C1 C1+ C2+ C2 C4+ VR C2 C2 C2 C2 C2 V SS + + + + + V0 V1 V2 V3 V4 V SS INTRS
V DD MS VOUT C5+ C3+ C1 C1+ C2+ C2 C4+ VR + + + + + Rb V0 V1 V2 V3 V4 INTRS V SS
C1
C1 C1 C1 C1
C1
C1 C1 C1 C1 Ra
C1
C1
C2 C2 C2 C2 C2
Figure 22. When Using all LCD Power Circuits (6-Time V/C: ON, V/R: ON, V/F: ON)
When using internal regulator resistors
When not using internal regulator resistors
V DD MS
External power Supply
V DD INTRS
External power Supply
MS VOUT C5+ C3+ C1 C1+ C2+ C2 C4+ VR + + + + + Rb V0 V1 V2 V3 V4
INTRS
V SS
VOUT C5+ C3+ C1 C1+ C2+ C2 C4+ VR + + + + +
Ra C2 C2 C2 C2 C2 V SS
C2 C2 C2 C2 C2 V SS
V0 V1 V2 V3 V4
Figure 23. When Using some LCD Power Circuits (V/C: OFF, V/R: ON, V/F: ON)
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S6B0718
VDD MS INTRS VOUT C5+ C3+ C1C1+ C2+ C2C4+ VR + + + + + VSS V0 V1 V2 V3 V4
External Power Supply
Figure 24. When Using only Voltage Follower Circuit (V/C: OFF, V/R: OFF, V/F: ON)
VDD MS INTRS VOUT C5+ C3+ C1C1+ C2+ C2C4+ VR V0 V1 V2 V3 V4
External Power Supply
Figure 25. When Not Using all LCD Power Circuits (V/C: OFF, V/R: OFF, V/F: OFF)
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104 SEG / 81 COM DRIVER & CONTROLLER FOR STN LCD
RESET CIRCUIT
Setting RESETB to "L" or Reset instruction can initialize internal function. When RESETB becomes "L", following procedure is occurred. Page address: 0 Column address: 0 Modify-read: OFF Display ON / OFF: OFF Initial display line: 0 (first) Initial COM0 register: 0 (COM0) Partial display duty ratio: 1/81 Reverse display ON / OFF: OFF (normal) Entire display ON / OFF: OFF (normal) Power control register (VC, VR, VF) = (0, 0, 0) DC-DC step up: 3 times converter circuit = (0, 0) Regulator resistor select register: (R2, R1, R0) = (0, 0, 0) Reference voltage control register: (EV5, EV4, EV3, EV2, EV1, EV0) = (1, 0, 0, 0, 0, 0) LCD bias ratio: 1/10 SHL select: OFF (normal) ADC select: OFF (normal) Static indicator mode: OFF Static indicator register: (S1, S0) = (0, 0) Oscillator status: OFF Power save mode: release When RESET instruction is issued, following procedure is occurred. Page address: 0 Column address: 0 Modify-read: OFF Initial display line: 0 (First) Regulator resistor select register: (R2, R1, R0) = (0, 0, 0) Reference voltage control register (EV5, EV4, EV3, EV2, EV1, EV0) = (1, 0, 0, 0, 0, 0) Static indicator mode: OFF Static indicator register: (S1, S0) = (0, 0) Other instruction registers : Not changed While RESETB is "L" or reset instruction is executed, no instruction except read status can be accepted. Reset status appears at DB4. After DB4 becomes "L", any instruction can be accepted. RESETB must be connected to the reset pin of the MPU, and initialize the MPU and this LSI at the same time. The initialization by RESETB is essential before used.
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INSTRUCTION DESCRIPTION
Table 17. Instruction Table Instruction
Read display data Write display data Read status Set page address Set column address MSB Set column address LSB Set modify-read Reset modify-read Display ON / OFF Set initial display line register RS 1 1 0 0 0 0 0 0 0 0 0 0 Set initial COM0 register 0 Set partial display duty ratio Reverse display ON / OFF Entire display ON / OFF 0 0 0 0 0 0 0 0 0 RW 1 0 1 0 0 0 0 0 0 0 0 0 BUSY 1 0 0 1 1 1 0 x 0 x 0 x 1 1 ADC 0 0 0 1 1 0 1 S6 1 C6 1 D6 0 0 ON 1 0 0 1 1 1 0 S5 0 C5 0 D5 1 1 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
x: Don' t care Description
Read data from DDRAM Write data into DDRAM
Read data Write data RES 1 1 0 0 0 0 0 S4 0 C4 0 D4 0 0 0 P3 0 Y3 0 1 1 0 S3 0 C3 1 D3 0 0 0 P2 Y6 Y2 0 1 1 0 S2 1 C2 0 D2 1 1 0 P1 Y5 Y1 0 1 1 x S1 x C1 x D1 1 0 0 P0 Y4 Y0 0 0 D x S0 x C0 x D0 REV EON
Read the internal status Set page address Set column address MSB Set column address LSB Set modify-read mode Release modify-read mode D = 0: display OFF D = 1: display ON 2-byte instruction to specify the initial display line to realize vertical scrolling 2-byte instruction to specify the initial COM0 to realize window scrolling 2-byte instruction to set partial display duty ratio REV = 0: normal display REV = 1: reverse display EON = 0: normal display EON = 1: entire display ON
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Table 17. Instruction Table (Continued) Instruction
Power control Select DC-DC step-up Select regulator resistor Set electronic volume register Select LCD bias SHL select RS 0 0 0 0 0 0 0 RW 0 0 0 0 0 0 0 DB7 0 0 0 1 x 0 1 DB6 0 1 0 0 x 1 1 DB5 1 1 1 0 EV5 0 0 DB4 0 0 0 0 EV4 1 0 DB3 1 0 0 0 EV3 0 SHL DB2 VC 1 R2 0 EV2 B2 x DB1 VR DC1 R1 0 EV1 B1 x DB0 VF DC0 R0 1 EV0 B0 x
Description
Control power circuit operation Select the step-up of the internal voltage converter Select internal resistance ratio of the regulator resistor 2-byte instruction to specify the electronic volume register Select LCD bias COM bi-directional selection SHL = 0: normal direction SHL = 1: reverse direction SEG bi-directional selection ADC = 0: normal direction ADC = 1: reverse direction 2-byte instruction to specify the static indicator mode Start the built-in oscillator P = 0: standby mode P = 1: sleep mode Release power save mode Initialize the internal functions No operation Don't use this instruction.
ADC select Set static indicator mode Set static indicator register Oscillator ON start Set power save mode Release power save mode Reset NOP Test instruction
0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0
1 1 x 1 1 1 1 1 1
0 0 x 0 0 1 1 1 1
1 1 x 1 1 1 1 1 1
0 0 x 0 0 0 0 0 1
0 1 x 1 1 0 0 0 x
0 1 x 0 0 0 0 0 x
0 0 S1 1 0 0 1 1 x
ADC SM S0 1 P 1 0 1 x
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S6B0718
Read Display Data 8-bit data from Display Data RAM specified by the column address and page address can be read by this instruction. As the column address is incremented by 1 automatically after each this instruction, the microprocessor can continuously read data from the addressed page. A dummy read is required after loading an address into the column address register. Display Data cannot be read through the serial interface. RS 1 RW 1 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Read data
Write Display Data 8-bit data of display data from the microprocessor can be written to the RAM location specified by the column address and page address. The column address is incremented by 1 automatically so that the microprocessor can continuously write data to the addressed page. RS 1 RW 0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Write data
Set Page Address Set Column Address Data Write Column = Column +1 Yes
Set Page Address Set Column Address Dummy Data Read Column = Column +1 Data Read Column = Column +1 Yes
Data Write Continue ? No Optional Status
Data Read Continue ? No Optional Status
Figure 26. Sequence for Writing Display Data
Figure 27. Sequence for Reading Display Data
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104 SEG / 81 COM DRIVER & CONTROLLER FOR STN LCD
Read Status Indicates the internal status of the S6B0718 RS 0 RW 1 DB7 BUSY DB6 ADC DB5 ON DB4 RES DB3 0 DB2 0 DB1 0 DB0 0
Flag BUSY
Description The device is busy when internal operation or reset. Any instruction is rejected until BUSY goes Low. 0: chip is active, 1: chip is being busy. Indicates the relationship between RAM column address and segment driver. 0: reverse direction (SEG103 SEG0), 1: normal direction (SEG0 SEG103) Indicates display ON / OFF status. 0: display ON, 1: display OFF Indicates the initialization is in progress by RESETB signal. 0: chip is active, 1: chip is being reset.
ADC ON RES
Set Page Address Sets the Page Address of display data RAM from the microprocessor into the Page Address register. Any RAM data bit can be accessed when its Page Address and column address are specified. Along with the column address, the Page Address defines the address of the display RAM to write or read display data. Changing the Page Address doesn't effect to the display status. RS 0 P3 0 0 0 : 1 1 1 1 1 1 1 RW 0 P2 0 0 0 : 0 0 0 1 1 1 1 DB7 1 P1 0 0 1 : 0 1 1 0 0 1 1 DB6 0 P0 0 1 0 : 1 0 1 0 1 0 1 DB5 1 DB4 1 DB3 P3 DB2 P2 DB1 P1 DB0 P0
Selected page 0 1 2 : 9 10 11 12 13 14 15
Description
Accessible pages for displaying dot-matrix display data
Accessible page for displaying icons Not accessible page. Do not use these pages.
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104 SEG / 81 COM DRIVER & CONTROLLER FOR STN LCD
S6B0718
Set Column Address Sets the Column Address of display RAM from the microprocessor into the column address register. Along with the Column Address, the column address defines the address of the display RAM to write or read display data. When the microprocessor reads or writes display data to or from display RAM, Column Addresses are automatically incremented. Set Column Address MSB RS RW DB7 0 0 0
DB6 0
DB5 0
DB4 1
DB3 0
DB2 Y6
DB1 Y5
DB0 Y4
Set Column Address LSB RS RW DB7 0 Y6 0 0 0 : : : 1 1 1 1 : : : 1 0 Y5 0 0 0 : : : 1 1 1 1 : : : 1 0 Y4 0 0 0 : : : 0 0 0 0 : : : 1
DB6 0 Y3 0 0 0 : : : 0 0 0 1 : : : 1
DB5 0 Y2 0 0 0 : : : 1 1 1 0 : : : 1
DB4 0 Y1 0 0 1 : : : 0 1 1 0 : : : 1
DB3 Y3 Y0 0 1 0 : : : 1 0 1 0 : : : 1
DB2 Y2
DB1 Y1
DB0 Y0
Selected column address 0 1 2 : : : 101 102 103
Not accessible column Do not use these columns.
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Set Modify-Read This instruction stops the automatic increment of the column address by the read display data instruction, but the column address is still increased by the Write display data instruction. And it reduces the load of microprocessor when the data of a specific area is repeatedly changed during cursor blinking or others. This mode is canceled by the reset Modify-read instruction. RS 0 RW 0 DB7 1 DB6 1 DB5 1 DB4 0 DB3 0 DB2 0 DB1 0 DB0 0
Reset Modify-Read This instruction cancels the Modify-read mode, and makes the column address return to its initial value just before the set Modify-read instruction is started. RS 0 RW 0 DB7 1 DB6 1 DB5 1 DB4 0 DB3 1 DB2 1 DB1 1 DB0 0
Set Page Address Set Column Address (N) Set Modify-Read Dummy Read Data Read Data Process Data Write No
Change Complete ? Yes Reset Modify-Read Return Column Address (N)
Figure 28. Sequence for Cursor Display
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104 SEG / 81 COM DRIVER & CONTROLLER FOR STN LCD
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Display ON / OFF Turns the display ON or OFF RS RW DB7 1 DB6 0 DB5 1 DB4 0 DB3 1 DB2 1 DB1 1 DB0 D
0 0 D = 1: display ON D = 0: display OFF
Set Initial Display Line Register Sets the line address of display RAM to determine the initial display line using 2-byte instruction. The RAM display data is displayed at the top row (COM0) of LCD panel. The 1st Instruction RS RW 0 0
DB7 0
DB6 1
DB5 0
DB4 0
DB3 0
DB2 0
DB1 x
DB0 x
The 2nd Instruction RS RW 0 S6 0 0 : 1 1 1 : 1 0 S5 0 0 : 0 0 0 : 1
DB7 x S4 0 0 : 1 1 1 : 1
DB6 S6 S3 0 0 : 0 0 1 : 1
DB5 S5 S2 0 0 : 1 1 0 : 1
DB4 S4 S1 0 0 : 1 1 0 : 1
DB3 S3 S0 0 1 : 0 1 0 : 1
DB2 S2
DB1 S1
DB0 S0
Selected line address 0 1 : 86 87 No operation
Setting Initial Display Line Start 1st Instruction (2-byte Instruction for Mode Setting) 2nd Instruction (2-byte Instruction for Register Setting) Setting Iinitial Display Line End Figure 29. The Sequence for Setting the Initial Display Line
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Set Initial COM0 Register Sets the initial row (COM) of the LCD panel using the 2-byte instruction. By using this instruction, it is possible to realize the window moving without the change of display data. The 1st Instruction RS 0 RW 0 DB7 0 DB7 x C4 0 0 0 0 : 0 0 0 0 1 : 1 DB6 1 DB6 C6 C3 0 0 0 0 : 1 1 1 1 0 : 1 DB5 0 DB5 C5 C2 0 0 0 0 : 1 1 1 1 0 : 1 DB4 0 DB4 C4 C1 0 0 1 1 : 0 0 1 1 0 : 1 DB3 0 DB3 C3 C0 0 1 0 1 : 0 1 0 1 0 : 1 No operation DB2 1 DB2 C2 DB1 x DB1 C1 Initial COM0 COM0 COM1 COM2 COM3 : COM76 COM77 COM78 COM79 DB0 x DB0 C0
The 2nd Instruction RS RW 0 C6 0 0 0 0 : 1 1 1 1 1 : 1 0 C5 0 0 0 0 : 0 0 0 0 0 : 1
Setting Initial COM0 Start 1st Instruction (Mode Setting) 2 Instruction (Initial COM0 Setting) Setting Initial COM0 End end Figure 30. Sequence for Setting the Initial COM0
nd
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Set Partial Display Duty Ratio Sets the duty ratio within range of 9 to 81 to realize partial display by using the 2-byte instruction. The 1st Instruction RS RW 0 0
DB7 0
DB6 1
DB5 0
DB4 0
DB3 1
DB2 0
DB1 x
DB0 x
The 2nd Instruction RS RW 0 D6 0 : 0 0 0 0 0 : 1 1 1 1 1 : 1 0 D5 0 : 0 0 0 0 0 : 0 0 0 0 0 : 1
DB7 x D4 0 : 0 0 0 0 0 : 0 0 1 1 1 : 1
DB6 D6 D3 0 : 1 1 1 1 1 : 1 1 0 0 0 : 1
DB5 D5 D2 0 : 0 0 0 0 1 : 1 1 0 0 0 : 1
DB4 D4 D1 0 : 0 0 1 1 0 : 1 1 0 0 1 : 1
DB3 D3 D0 0 : 0 1 0 1 0 : 0 1 0 1 0 : 1
DB2 D2
DB1 D1
DB0 D0
Selected partial duty ratio No operation 1/9 1/10 1/11 1/12 : 1/78 1/79 1/80 1/81 No operation
Setting Partial Display Start
1st Instruction (Mode Setting) 2nd Instruction (Partial Display Duty Setting)
Setting Partial Display End
Figure 31. Sequence for Setting Partial Display
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Reverse Display ON / OFF Reverses the display status on LCD panel without rewriting the contents of the display data RAM. RS 0 REV 0 (normal) 1 (reverse) RW 0 DB7 1 DB6 0 DB5 1 DB4 0 DB3 0 DB2 1 DB1 1 DB0 REV
RAM bit data = "1" LCD pixel is illuminated LCD pixel is not illuminated
RAM bit data = "0" LCD pixel is not illuminated LCD pixel is illuminated
Entire Display ON / OFF Forces the whole LCD points to be turned on regardless of the contents of the display data RAM. At this time, the contents of the display data RAM are held. This instruction has priority over the reverse display ON / OFF instruction. RS 0 EON 0 (normal) 1 (entire) RW 0 DB7 1 DB6 0 DB5 1 DB4 0 DB3 0 DB2 1 DB1 0 DB0 EON
RAM bit data = "1" LCD pixel is illuminated LCD pixel is illuminated
RAM bit data = "0" LCD pixel is not illuminated LCD pixel is illuminated
Power Control Selects one of eight power circuit functions by using 3-bit register. An external power supply and part of internal power supply functions can be used simultaneously. RS 0 RW 0 DB7 0 DB6 0 DB5 1 DB4 0 DB3 1 DB2 VC DB1 VR DB0 VF
VC 0 1
VR
VF
Status of internal power supply circuits Internal voltage converter circuit is OFF Internal voltage converter circuit is ON
0 1 0 1
Internal voltage regulator circuit is OFF Internal voltage regulator circuit is ON Internal voltage follower circuit is OFF Internal voltage follower circuit is ON
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Select DC-DC Step-up Selects one of 4 DC-DC step-up to reduce the power consumption by this instruction. It is very useful to realize the partial display function. RS 0 RW 0 DB7 0 DB6 1 DB5 1 DB4 0 DB3 0 DB2 1 DB1 DC1 DB0 DC0
DC1 0 0 1 1
DC0 0 1 0 1
Selected DC-DC converter circuit 3 times boosting circuit 4 times boosting circuit 5 times boosting circuit 6 times boosting circuit
Regulator Resistor Select Selects resistance ratio of the internal resistor used in the internal voltage regulator. See voltage regulator section in power supply circuit. Refer to the table 15. RS 0 R2 0 0 : 1 1 RW 0 R1 0 0 : 1 1 DB7 0 R0 0 1 : 0 1 DB6 0 DB5 1 DB4 0 DB3 0 [Rb / Ra] ratio Small : : : Large DB2 R2 DB1 R1 DB0 R0
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Set Electronic Volume Register Consists of 2-byte instruction The 1st instruction sets electronic volume mode, the 2nd one updates the contents of electronic volume register. After second instruction, electronic volume mode is released. The 1st Instruction RS RW 0 0
DB7 1
DB6 0
DB5 0
DB4 0
DB3 0
DB2 0
DB1 0
DB0 1
The 2nd Instruction RS RW 0 EV5 0 0 : : 1 1 0 EV4 0 0 : : 1 1
DB7 x EV3 0 0 : : 1 1
DB6 x EV2 0 0 : : 1 1
DB5 EV5 EV1 0 0 : : 1 1
DB4 EV4 EV0 0 1 : : 0 1
DB3 EV3
DB2 EV2
DB1 EV1
DB0 EV0
Reference voltage () 0 1 : : 62 63
Setting Electronic Volume Start 1st Instruction for Mode Setting 2nd Instruction for Register Setting Setting Electronic Volume End Figure 32. Sequence for Setting the Electronic Volume
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Select LCD Bias Selects LCD Bias ratio of the voltage required for driving the LCD. RS 0 B2 0 0 0 0 1 1 1 1 RW 0 B1 0 0 1 1 0 0 1 1 DB7 0 B0 0 1 0 1 0 1 0 1 DB6 1 DB5 0 DB4 1 DB3 0 DB2 B2 DB1 B1 DB0 B0
Selected LCD bias 1/4 1/5 1/6 1/7 1/8 1/9 1/10 1/11
SHL Select COM output scanning direction is selected by this instruction which determines the LCD driver output status. RS 0 RW 0 DB7 1 DB6 1 DB5 0 DB4 0 DB3 SHL DB2 x DB1 x DB0 x
SHL = 0: normal direction (COM0 COM79) SHL = 1: reverse direction (COM79 COM0)
ADC Select Changes the relationship between RAM column address and segment driver. The direction of segment driver output pins could be reversed by software. This makes IC layout flexible in LCD module assembly. RS RW DB7 DB6 DB5 DB4 0 DB3 0 DB2 0 DB1 0 DB0 ADC
0 0 1 0 1 ADC = 0: normal direction (SEG0 SEG103) ADC = 1: reverse direction (SEG103 SEG0)
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Set Static Indicator State Consists of two bytes instruction. The first byte instruction (set Static Indicator mode) enables the second byte instruction (set Static Indicator register) to be valid. The first byte sets the Static Indicator ON / OFF. When it is on, the second byte updates the contents of Static Indicator register without issuing any other instruction and this Static Indicator state is released after setting the data of indicator register. The 1st Instruction: Set Static Indicator Mode (ON / OFF) RS RW DB7 DB6 DB5 DB4 0 0 1 SM = 0: static indicator OFF SM = 1: static indicator ON 0 1 0
DB3 1
DB2 1
DB1 0
DB0 SM
The 2nd Instruction: Set Static Indicator Register RS RW DB7 DB6 DB5 0 S1 0 0 1 1 0 x S0 0 1 0 1 x x
DB4 x
DB3 x
DB2 x
DB1 S1
DB0 S0
Status of static indicator output OFF ON (about 0.5 second blinking) ON (about 1 second blinking ) ON (always ON)
Oscillator ON Start This instruction enables the built-in oscillator circuit. RS 0 RW 0 DB7 1 DB6 0 DB5 1 DB4 0 DB3 1 DB2 0 DB1 1 DB0 1
Reset This instruction resets initial display line, column address, page address, and common output status select to their initial status, but dose not affect the contents of display data RAM. This instruction cannot initialize the LCD power supply, which is initialized by the RESETB pin. RS 0 RW 0 DB7 1 DB6 1 DB5 1 DB4 0 DB3 0 DB2 0 DB1 1 DB0 0
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Power Save The S6B0718 enters the Power Save status to reduce the power consumption to the static power consumption value and returns to the normal operation status by the following instructions. Set Power Save Mode RS RW DB7 0 0 P = 0: standby mode P = 1: sleep mode 1
DB6 0
DB5 1
DB4 0
DB3 1
DB2 0
DB1 0
DB0 P
Release Power Save Mode RS RW DB7 0 0 1
DB6 1
DB5 1
DB4 0
DB3 0
DB2 0
DB1 0
DB0 1
Set Power Save Mode
Sleep Mode Oscillator Circuits: OFF Static Driver: Disable LCD Power Supply Circuits: OFF All COM / SEG Output Level: VSS Consumption Current < 2uA
Standby Mode Oscillator Circuits: ON Static Driver: Enable LCD Power SupplyCircuits: OFF All COM / SEG Output Level: VSS Consumption Current < 15uA
Release Power Save Mode
Release Sleep Mode
Release Standby Mode
Figure 33. Power Save Routine NOP Non Operation Instruction RS 0 RW 0 DB7 1 DB6 1 DB5 1 DB4 0 DB3 0 DB2 0 DB1 1 DB0 1
Test Instruction This instruction is for testing IC. Please do not use it. RS 0 RW 0 DB7 1 DB6 1 DB5 1 DB4 1 DB3 x DB2 x DB1 x DB0 x
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Referential Instruction Setup Flow: Initializing with the Built-in Power Supply Circuits
User System Setup by External Pins
Start of Initialization
Power ON (VDD-VSS) Keeping the RESETB Pin = "L"
Waiting for Stabilizing the Power
RESETB Pin = "H"
User Application Setup by Internal Instructions [Display Duty Select] [ADC Select] [SHL Select] [COM0 Register Select]
User LCD Power Setup by Internal Instructions [Oscillator ON] [DC-DC Step-up Register Select] [Regulator Resistor Select] [Electronic Volume Register Select] [LCD Bias Register Select] [Power Control]
Waiting for Stabilizing the LCD Power Levels
End of Initialization
Figure 34. Initializing with the Built-in Power Supply Circuits
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S6B0718
Referential Instruction Setup Flow: Initializing without the Built-in Power Supply Circuits
User System Setup by External Pins
Start of Initialization
Power ON (VDD-VSS) Keeping the RESETB Pin = "L"
Waiting for Stabilizing the Power
RESETB Pin = "H"
Set Power Save
User Application Setup by Internal Instructions [Display Duty Select] [ADC Select] [SHL Select] [COM0 Register Select]
User LCD Power Setup by Internal Instructions [Oscillator ON] Regulator or Follower Register Select [Power Control]
Release Power Save
Waiting for Stabilizing the LCD Power Levels
End of Initialization
Figure 35. Initializing without the Built-in Power Supply Circuits
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Referential Instruction Setup Flow: Data Displaying
End of Initialization
Display Data RAM Addressing by Instruction [Initial Display Line] [Set Page Address] [Set Column Address]
Write Display Data by Instruction [Display Data Write]
Turn Display ON / OFF Instruction [Display ON / OFF]
End of Data Display
Figure 36. Data Displaying
Referential Instruction Setup Flow: Power OFF
Optional Status
Set Power Save by Instruction
Power OFF (VDD-VSS)
End of Power OFF
Figure 37. Power OFF
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Referential Instruction Setup Flow: Partial Duty Changing
Start of Partial changing
Set Display OFF by Internal Instruction [Display ON / OFF]
Set Standby Mode by Internal Instruction [Power Save Mode]
Set Partial Duty by Internal Instructions [Partial Display Duty Ratio Select] [Initial Display Line Register] [COM0 Register Select]
User LCD Power Setup by Internal Instructions [DC-DC Step-up Register Select] [Regulator Resistor Select] [Electronic Volume Register Select] [LCD Bias Register Select] [Power Control]
Waiting for Discharging the LCD Power Levels
Release Power Save
Waiting for Stabilizing the LCD Power Levels Write Display Data & Display ON by Internal Instruction [Display Data Write] [Display ON / OFF] End of Partial Changing
Figure 38. Partial Duty Changing
NOTE:1. Partial COM0 register setting for COM H/W half: [80 - (user duty) ] / 2
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104 SEG / 81 COM DRIVER & CONTROLLER FOR STN LCD
SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS
Table 18. Absolute Maximum Ratings Parameter Supply voltage range External reference voltage Input voltage range Operating temperature range Storage temperature range
NOTES: 1. VDD, V0, VOUT, V1 to V4, VEXT and VCI are based on VSS = 0V. 2. Voltage VOUT V0 V1 V2 V3 V4 VSS must always be satisfied. 3. If supply voltage exceeds its absolute maximum range, this LSI may be damaged permanently. It is desirable to use this LSI under electrical characteristic conditions during general operation. Otherwise, this LSI may malfunction or reduced LSI reliability may result.
Symbol VDD V0, VOUT V1, V2, V3, V4 VEXT VIN TOPR TSTR
Rating - 0.3 ~ + 7.0 + 0.3 ~ + 17.0 + 0.3 ~ V0 +0.3 ~ VDD - 0.3 ~ VDD + 0.3 - 40 ~ + 85 - 55 ~ + 125
(VSS = 0V) Unit V V V V C C
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DC CHARACTERISTICS
Table 19. DC Characteristics (VSS = 0V, VDD = 2.4~3,6V, Ta=-40~85C) Item Operating voltage (1) Operating voltage (2) High Input voltage Low Output voltage High Low VIL VOH VOL IIL IOZ RON fFR IOH = -0.5mA IOL = 0.5mA VIN = VDD or VSS VIN = VDD or VSS Ta = 25C, V0 = 8V Ta = 25C VSS 0.8VDD VSS - 1.0 - 3.0 70 2.0 85 0.2VDD VDD V 0.2VDD + 1.0 + 3.0 3.0 100 A A k Hz *3 *5 SEGn COMn *6 FR *7 *4 Symbol VDD V0 VIH Condition Min. 2.4 4.0 0.8VDD Typ. Max. 3.6 15.0 VDD V *3 Unit V V Pin used VDD *1 V0, *2
Input leakage current Output leakage current LCD driver ON resistance Frame frequency
Table 20. DC Characteristics Item Voltage converter circuit output voltage Voltage regulator circuit operating voltage Voltage follower circuit operating voltage Reference voltage Symbol VOUT Condition x3 / x4 / x5 / x6 voltage conversion (no-load ) Min. 95 Typ. 99 Max. Unit % Pin used VOUT
VOUT
6.0
-
15.0
V
VOUT
V0 VREF Ta = 25C
4.0 1.94
2.00
15.0 2.06
V V
V0 *8 *9
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Dynamic Current Consumption (1) when An External Power Supply is used. Table 21. Dynamic Current 1 (External Power) (VDD = 3.0V, Ta = 25C) Item Symbol Condition V0-Vss = 12.0V, duty = 1/81 (Display Off) IDD1 V0-Vss = 12.0V, duty = 1/81 (Display On , Checker Pattern) 15 *10 Min Typ Max 10 Unit Pin used *10
Dynamic current consumption (1)
Dynamic Current Consumption (2) when The Internal Power Supply is ON Table 22. . Dynamic Current 2 (Internal Power) Item Symbol Condition V0 - Vss = 12.0V, x5 boosting, duty = 1/81, normal mode (Display Off) IDD2 V0 - Vss = 12.0V, x5 boosting, duty = 1/81, normal mode (Display On , Checker Pattern) 300 *10 Min. Typ. (VDD = 3.0V, Ta = 25C) Max. Unit Pin used 150 *10
Dynamic current consumption (2)
Current Consumption during Power Save Mode Table 23. Power Save Mode Current (VDD = 3.0V, Ta = 25C) Item Sleep mode current Standby mode current Symbol IDDS1 IDDS2 Condition During sleep During standby Min. Typ. Max. 2 15 Unit Pin used *10 *10
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Table 24. The Relationship between Oscillation Frequency and Frame Frequency Duty ratio 1/N Item fCL Fosc
On-chip oscillator circuit is fFR x N fFR x 4 x N used (fOSC: oscillation frequency, fCL: display clock frequency, fFR: frame frequency, N = 9 to 81)
[* Remark Solves] *1. Though the wide range of operating voltages is guaranteed, a spike voltage change may affect the voltage assurance during access from the MPU. *2. In case of external power supply is applied. *3. CS1B, CS2, RS, DB0 to DB7, E_RD, RW_WR, RESETB, MS, C68, PS, INTRS, HPMB, REF, CL, M and SYNC. *4. DB0 to DB7, FR, FRS, SYNC, M and CL. *5. Applies when the DB0 to DB7, SYNC, M, and CL pins are in high impedance. *6. Resistance value when -0.1[mA] is applied during the ON status of the output pin SEGn or COMn. RON [k] = V[V] / 0.1[mA] (V : voltage change when -0.1[mA] is applied in the ON status.) *7. See Table 24 for the relationship between oscillation frequency and frame frequency. *8. The voltage regulator circuit adjusts V0 within the voltage follower operating voltage range. *9. On-chip reference voltage source of the voltage regulator circuit to adjust V0. *10. Applies to the case where the on-chip oscillation circuit is used and no access is made from the MPU. The current consumption, when the built-in power supply circuit is ON or OFF. The current flowing through voltage regulation resistors(Rb and Ra) is not included. It does not include the current of the LCD panel capacity, wiring capacity, etc.
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AC CHARACTERISTICS
Read / Write Characteristics (8080-series MP)
RS tAS80 tCY80 tPWLW, tPWLR /RD, /WR CS1B DB0 to DB7 ( Write ) DB0 to DB7 ( Read ) Figure 39. Read / Write Characteristics (8080-series MPU) Table 25 Item Address setup time Address hold time System cycle time Pulse width low for write Pulse width high for write Pulse width low for read Pulse width high for read Data setup time Data hold time Read access time Output disable time RW_WR (/WR) E_RD (/RD) DB0 to DB7 Signal RS Symbol tAS80 tAH80 tCY80 tPWLW tPWHW tPWLR tPWHR tDS80 tDH80 tACC80 tOD80 CL = 100 pF Condition (VDD = 2.4 ~ 3.6V, Ta = -40 ~ +85C) Min. Max. Unit 0 0 400 60 60 120 60 40 15 10 140 100 ns ns ns ns ns ns tACC80 tOD80 0.9VDD 0.1VDD tDS80 tPWHW, tPWHR tDH80 tAH80
NOTE: *1. The input signal rise time and fall time (tr, tf) is specified at 15 ns or less. (tr + tf) < (tCY80 - tPWLW - tPWHW ) for write, (tr + tf) < (tCY80 - tPWLR - tPWHR ) for read
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Read / Write Characteristics (6800-series Microprocessor) RS, R/W tAS68 tCY68 tEWLW, tEWLR E CS1B DB0 to DB7 ( Write ) tACC68 DB0 to DB7 ( Read ) Figure 40. Read / Write Characteristics (6800-series Microprocessor) tOD68 0.1VDD 0.9VDD tEWHW, tEWHR tDS68 tAH68
tDH68
Table 26 (VDD = 2.4 ~ 3.6V, Ta = -40 ~ +85C) Min. Max. Unit 0 0 400 60 60 120 60 40 15 CL = 100 pF 10 140 100 ns ns ns ns ns ns
Item Address setup time Address hold time System cycle time Enable width high for write Enable width low for write Enable width high for read Enable width low for read Data setup time Data hold time Read access time Output disable time
Signal RS RW E_RD (E) E_RD (E) DB0 to DB7
Symbol tAS68 tAH68 tCY68 tEWHW tEWLW tEWHR tEWLR tDS68 tDH68 tACC68 tOD68
Condition
NOTE: *1. The input signal rise time and fall time (tr, tf) is specified at 15 ns or less. (tr + tf) < (tCY68 - tEWHW - tEWLW ) for write, (tr + tf) < (tCY68 - tEWHR - tEWLR ) for read
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Serial Interface Characteristics
tCSS CS1B (CS2 = "H" ) RS tCYS DB6 ( SCLK ) 0.9VDD 0.1VDD tWLS tDSS DB7 ( SID ) Figure 41 Table 27 Item Serial clock cycle SCLK high pulse width SCLK low pulse width Address setup time Address hold time Data setup time Data hold time CS1B setup time CS1B hold time Signal DB6 (SCLK) RS DB7 (SID) CS1B Symbol tsCY tsHW tsLW tASS tAHS tDSS tDHS tCSS tCHS Condition tASS
tCHS tAHS
tWHS tDHS
(VDD = 2.4 ~ 3.6V, Ta = -40 ~ +85C) Min. Max. Unit 250 100 100 150 150 100 100 150 150 ns
ns ns ns
NOTE: *1. The input signal rise time and fall time (tr, tf) is specified at 15 ns or less.
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Reset Input Timing
tRW RESETB tR Internal status During reset Reset complete
Figure 42 Table 28 Item Reset low pulse width Reset time Signal RESETB Symbol tRW tR Condition (VDD = 2.4 ~ 3.6V, Ta = -40 ~ +85C) Min. Max. Unit 1000 1000 ns ns
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104 SEG / 81 COM DRIVER & CONTROLLER FOR STN LCD
REFERENCE APPLICATIONS
MICROPROCESSOR INTERFACE
CS1B CS2
CS1B CS2 RS E_RD RW_WR DB0 to DB7 RESETB C68 PS
6800-series MPU
RS E RW DB0 to DB7 RESETB V DD V DD
S6B0718
Figure 43. In Case of Interfacing with 6800-series (PS = "H", C68 = "H")
8080-series MPU
CS1B CS2 RS /RD /W R DB0 to DB7 RESETB V SS V DD
CS1B CS2 RS E_RD RW_WR
S6B0718
DB0 to DB7 RESETB C68 PS
Figure 44. In Case of Interfacing with 8080-series (PS = "H", C68 = "L")
MPU
CS1B CS2 RS SID SCLK RESETB OPEN VDD or VSS VSS
CS1B CS2 RS S6B0718 DB7(SID) DB6(SCLK) RESETB DB0 to DB5 C68 PS
Figure 45. In Case of Serial Interface (PS = "L", C68 = "H/L")
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104 SEG / 81 COM DRIVER & CONTROLLER FOR STN LCD
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CONNECTIONS BETWEEN S6B0718 AND LCD PANEL
Single Chip Configurations (1/81 Duty)
COMS COM79 COM40
S6B0718 (Bottom View)
SEG102 SEG1
COM39 COM0 COMS
COM51 COM0 COMS
S6B0718 (Top View)
SEG1 SEG102
COMS COM103 COM52
SEG103
SEG0
SEG0
SEG103

(R)

(R)
80 x 104 pixels
(R)
80 x 104 pixels
(R)
Figure 46. SHL = 0, ADC = 1
Figure 47. SHL = 0, ADC = 0

(R)

(R)
80 x 104 pixels
(R)
80 x 104 pixels
(R)
SEG0
COMS COM0 COM39
SEG1 SEG158
SEG159
COM40 COM79 COMS
SEG159
COM40 COM79 COMS
SEG158 SEG1
SEG0
COMS COM0 COM39
S6B0718 (Bottom View)
S6B0718 (Top View)
Figure 48. SHL = 1, ADC = 0
Figure 49. SHL = 1, ADC = 1
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104 SEG / 81 COM DRIVER & CONTROLLER FOR STN LCD
Multiple Chip Configurations (1/81 Duty)
COMS COM79 COM40
S6B0718 (Bottom View) (Master)
SEG102 SEG1
COM39 COM0 COMS
COMS COM79 COM40
S6B0718 (Bottom View) (Slave)
SEG103
COM39 COM0 COMS
SEG103
SEG0
SEG102 SEG1
SEG0

(R)
80x 208 pixels
(R)
Figure 50. SHL = 0, ADC = 1 Connect the following pins of two chips each other: - Display clock pins: CL, M, SYNC - LCD power pins: V0, V1, V2, V3, V4

(R)
80 x 208 pixels
(R)
SEG0
COMS COM0 COM39
SEG1 SEG102
SEG103
COM40 COM79 COMS
SEG0
COMS COM0 COM39
SEG1 SEG102
SEG103
COM40 COM79 COMS
S6B0718 (Bottom View) (Master)
S6B0718 (Bottom View) (Slave)
Figure 51. SHL = 1, ADC = 0 Connect the following pins of two chips each other: - Display clock pins: CL, M, SYNC - LCD power pins: V0, V1, V2, V3, V4
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