PRODUCT SPECIFICATIONS (R) Integrated Circuits Group LH28F008SCT-L85 Flash Memory 8M (1MB x 8) (Model No.: LHF08CH1) Spec No.: EL104027C Issue Date: April 24, 2000 sharp LHF08CH1 Handle this document carefully for it contains material protected by international copyright law. Any reproduction, full or in part, of this material is prohibited without the express written permission of the company. When using the products covered herein, please observe the conditions written herein and the precautions outlined in the following paragraphs. In no event shall the company be liable for any damages resulting from failure to strictly adhere to these conditions and precautions. (1) The products covered herein are designed and manufactured for the following application areas. When using the products covered herein for the equipment listed in Paragraph (2), even for the following application areas, be sure to observe the precautions given in Paragraph (2). Never use the products for the equipment listed in Paragraph (3). *Office electronics *Instrumentation and measuring equipment *Machine tools *Audiovisual equipment *Home appliance *Communication equipment other than for trunk lines (2) Those contemplating using the products covered herein for the following equipment which demands high reliability, should first contact a sales representative of the company and then accept responsibility for incorporating into the design fail-safe operation, redundancy, and other appropriate measures for ensuring reliability and safety of the equipment and the overall system. *Control and safety devices for airplanes, trains, automobiles, and other transportation equipment *Mainframe computers *Traffic control systems *Gas leak detectors and automatic cutoff devices *Rescue and security equipment *Other safety devices and safety equipment,etc. (3) Do not use the products covered herein for the following equipment which demands extremely high performance in terms of functionality, reliability, or accuracy. *Aerospace equipment *Communications equipment for trunk lines *Control equipment for the nuclear power industry *Medical equipment related to life support, etc. (4) Please direct all queries and comments regarding the interpretation of the above three Paragraphs to a sales representative of the company. Please direct all queries regarding the products covered herein to a sales representative of the company. Rev. 1.3 sharp LHF08CH1 1 CONTENTS PAGE 1.0 INTRODUCTION ................................................... 3 1.1 New Features...................................................... 3 1.2 Product Overview ................................................ 3 2.0 PRINCIPLES OF OPERATION ............................. 7 2.1 Data Protection ................................................... 7 3.0 BUS OPERATION................................................. 8 3.1 Read ................................................................... 8 3.2 Output Disable .................................................... 8 3.3 Standby ............................................................... 8 3.4 Deep Power-Down .............................................. 8 3.5 Read Identifier Codes Operation ......................... 9 3.6 Write.................................................................... 9 4.0 COMMAND DEFINITIONS .................................... 9 4.1 Read Array Command....................................... 12 4.2 Read Identifier Codes Command ...................... 12 4.3 Read Status Register Command....................... 12 4.4 Clear Status Register Command....................... 12 4.5 Block Erase Command...................................... 12 4.6 Byte Write Command ........................................ 13 4.7 Block Erase Suspend Command....................... 13 4.8 Byte Write Suspend Command ......................... 14 4.9 Set Block and Master Lock-Bit Commands ....... 14 4.10 Clear Block Lock-Bits Command..................... 15 8.0 PACKAGE AND PACKING SPECIFICATIONS ..41 7.0 ADDITIONAL INFORMATION .............................40 7.1 Ordering Information ..........................................40 6.0 ELECTRICAL SPECIFICATIONS........................25 6.1 Absolute Maximum Ratings ...............................25 6.2 Operating Conditions .........................................25 6.2.1 Capacitance .................................................25 6.2.2 AC Input/Output Test Conditions ..................26 6.2.3 DC Characteristics........................................27 6.2.4 AC Characteristics - Read-Only Operations .29 6.2.5 AC Characteristics - Write Operations..........32 6.2.6 Alternative CE#-Controlled Writes ................35 6.2.7 Reset Operations .........................................38 6.2.8 Block Erase, Byte Write and Lock-Bit Configuration Performance...........................39 PAGE 5.0 DESIGN CONSIDERATIONS ..............................23 5.1 Three-Line Output Control .................................23 5.2 RY/BY# and Block Erase, Byte Write and Lock-Bit Configuration Polling...........................................23 5.3 Power Supply Decoupling ..................................23 5.4 VPP Trace on Printed Circuit Boards ..................23 5.5 VCC, VPP, RP# Transitions.................................24 5.6 Power-Up/Down Protection................................24 5.7 Power Dissipation ..............................................24 Rev. 1.3 sharp LHF08CH1 2 LH28F008SCT-L85 8M-BIT (1MB x 8) SmartVoltage Flash MEMORY SmartVoltage Technology 2.7V(Read-Only), 3.3V or 5V VCC 3.3V, 5V or 12V VPP High-Performance Read Access Time 85ns(5V0.25V), 90ns(5V0.5V), 120ns(3.3V0.3V), 150ns(2.7V-3.6V) Operating Temperature 0C to +70C High-Density Symmetrically-Blocked Architecture Sixteen 64K-byte Erasable Blocks Low Power Management Deep Power-Down Mode Automatic Power Savings Mode Decreases ICC in Static Mode Enhanced Data Protection Features Absolute Protection with VPP=GND Flexible Block Locking Block Erase/Byte Write Lockout during Power Transitions Automated Byte Write and Block Erase Command User Interface Status Register Enhanced Automated Suspend Options Byte Write Suspend to Read Block Erase Suspend to Byte Write Block Erase Suspend to Read Extended Cycling Capability 100,000 Block Erase Cycles 1.6 Million Block Erase Cycles/Chip SRAM-Compatible Write Interface Industry-Standard Packaging 40-Lead TSOP ETOXTM* Nonvolatile Flash Technology CMOS Process (P-type silicon substrate) Not designed or rated as radiation hardened SHARP's LH28F008SCT-L85 Flash memory with SmartVoltage technology is a high-density, low-cost, nonvolatile, read/write storage solution for a wide range of applications. Its symmetrically-blocked architecture, flexible voltage and extended cycling provide for highly flexible component suitable for resident flash arrays, SIMMs and memory cards. Its enhanced suspend capabilities provide for an ideal solution for code + data storage applications. For secure code storage applications, such as networking, where code is either directly executed out of flash or downloaded to DRAM, the LH28F008SCT-L85 offers three levels of protection: absolute protection with VPP at GND, selective hardware block locking, or flexible software block locking. These alternatives give designers ultimate control of their code security needs. The LH28F008SCT-L85 is manufactured on SHARP's 0.38m ETOXTM process technology. It come in industry-standard package: the 40-lead TSOP, ideal for board constrained applications. Based on the 28F008SA architecture, the LH28F008SCT-L85 enables quick and easy upgrades for designs demanding the state-of-the-art. *ETOX is a trademark of Intel Corporation. Rev. 1.3 sharp LHF08CH1 3 1 INTRODUCTION This datasheet contains LH28F008SCT-L85 specifications. Section 1 provides a flash memory overview. Sections 2, 3, 4, and 5 describe the memory organization and functionality. Section 6 covers electrical specifications. LH28F008SCT-L85 Flash memory documentation also includes application notes and design tools which are referenced in Section 7. SmartVoltage technology provides a choice of VCC and VPP combinations, as shown in Table 1, to meet system performance and power expectations. 2.7V VCC consumes approximately one-fifth the power of 5V VCC. But, 5V VCC provides the highest read performance. VPP at 3.3V and 5V eliminates the need for a separate 12V converter, while VPP=12V maximizes block erase and byte write performance. In addition to flexible erase and program voltages, the dedicated VPP pin gives complete data protection when VPPVPPLK. Table 1. VCC and VPP Voltage Combinations Offered by SmartVoltage Technology VCC Voltage VPP Voltage 2.7V(1) 3.3V 3.3V, 5V, 12V 5V 5V, 12V NOTE: 1. Block erase, byte write and lock-bit configuration operations with VCC<3.0V are not supported. Internal VCC and VPP detection Circuitry automatically configures the device for optimized read and write operations. A Command User Interface (CUI) serves as the interface between the system processor and internal operation of the device. A valid command sequence written to the CUI initiates device automation. An internal Write State Machine (WSM) automatically executes the algorithms and timings necessary for block erase, byte write, and lock-bit configuration operations. A block erase operation erases one of the device's 64K-byte blocks typically within 0.3s (5V VCC, 12V VPP) independent of other blocks. Each block can be independently erased 100,000 times (1.6 million block erases per device). Block erase suspend mode allows system software to suspend block erase to read or write data from any other block. Writing memory data is performed in byte increments typically within 6s (5V VCC, 12V VPP). Byte write suspend mode enables the system to read data or execute code from any other flash memory array location. 1.1 New Features The LH28F008SCT-L85 SmartVoltage Flash memory maintains backwards-compatibility with SHARP's 28F008SA. Key enhancements over the 28F008SA include: *SmartVoltage Technology *Enhanced Suspend Capabilities *In-System Block Locking Both devices share a compatible pinout, status register, and software command set. These similarities enable a clean upgrade from the 28F008SA to LH28F008SCT-L85. When upgrading, it is important to note the following differences: *Because of new feature support, the two devices have different device codes. This allows for software optimization. *VPPLK has been lowered from 6.5V to 1.5V to support 3.3V and 5V block erase, byte write, and lock-bit configuration operations. The VPP voltage transitions to GND is recommended for designs that switch VPP off during read operation. *To take advantage of SmartVoltage technology, allow VPP connection to 3.3V or 5V. 1.2 Product Overview The LH28F008SCT-L85 is a high-performance 8M-bit SmartVoltage Flash memory organized as 1M-byte of 8 bits. The 1M-byte of data is arranged in sixteen 64K-byte blocks which are individually erasable, lockable, and unlockable in-system. The memory map is shown in Figure 3. Rev. 1.3 sharp LHF08CH1 4 Individual block locking uses a combination of bits, sixteen block lock-bits and a master lock-bit, to lock and unlock blocks. Block lock-bits gate block erase and byte write operations, while the master lock-bit gates block lock-bit modification. Lock-bit configuration operations (Set Block Lock-Bit, Set Master Lock-Bit, and Clear Block Lock-Bits commands) set and cleared lock-bits. The status register indicates when the WSM's block erase, byte write, or lock-bit configuration operation is finished. The RY/BY# output gives an additional indicator of WSM activity by providing both a hardware signal of status (versus software polling) and status masking (interrupt masking for background block erase, for example). Status polling using RY/BY# minimizes both CPU overhead and system power consumption. When low, RY/BY# indicates that the WSM is performing a block erase, byte write, or lock-bit configuration. RY/BY#-high indicates that the WSM is ready for a new command, block erase is suspended (and byte write is inactive), byte write is suspended, or the device is in deep power-down mode. The access time is 85ns (tAVQV) over the commercial temperature range (0C to +70C) and VCC supply voltage range of 4.75V-5.25V. At lower VCC voltages, the access times are 90ns (4.5V-5.5V), 120ns (3.0V-3.6V) and 150ns (2.7V-3.6V). The Automatic Power Savings (APS) feature substantially reduces active current when the device is in static mode (addresses not switching). In APS mode, the typical ICCR current is 1 mA at 5V VCC. When CE# and RP# pins are at VCC, the ICC CMOS standby mode is enabled. When the RP# pin is at GND, deep power-down mode is enabled which minimizes power consumption and provides write protection during reset. A reset time (tPHQV) is required from RP# switching high until outputs are valid. Likewise, the device has a wake time (tPHEL) from RP#-high until writes to the CUI are recognized. With RP# at GND, the WSM is reset and the status register is cleared. The device is available in 40-lead TSOP (Thin Small Outline Package, 1.2 mm thick). Pinout is shown in Figure 2. Rev. 1.3 sharp LHF08CH1 5 DQ0-DQ7 Output Buffer Input Buffer Output Multiplexer Identifier Register Data Register I/O Logic VCC CE# Status Register Command Register WE# OE# RP# Data Comparator A0-A19 Input Buffer Y Decoder Y Gating RY/BY# Write State Machine 16 64KByte Blocks Program/Erase Voltage Switch VPP Address Latch X Decoder VCC GND Address Counter Figure 1. Block Diagram A19 A18 A17 A16 A15 A14 A13 A12 CE# VCC VPP RP# A11 A10 A9 A8 A7 A6 A5 A4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40-LEAD TSOP STANDARD PINOUT 10mm x 20mm TOP VIEW 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 NC NC WE# OE# RY/BY# DQ7 DQ6 DQ5 DQ4 VCC GND GND DQ3 DQ2 DQ1 DQ0 A0 A1 A2 A3 Figure 2. TSOP 40-Lead Pinout Rev. 1.3 sharp LHF08CH1 6 Symbol A0-A19 DQ0-DQ7 Type INPUT INPUT/ OUTPUT CE# INPUT RP# INPUT OE# WE# INPUT INPUT RY/BY# OUTPUT VPP SUPPLY VCC SUPPLY GND NC SUPPLY Table 2. Pin Descriptions Name and Function ADDRESS INPUTS: Inputs for addresses during read and write operations. Addresses are internally latched during a write cycle. DATA INPUT/OUTPUTS: Inputs data and commands during CUI write cycles; outputs data during memory array, status register, and identifier code read cycles. Data pins float to high-impedance when the chip is deselected or outputs are disabled. Data is internally latched during a write cycle. CHIP ENABLE: Activates the device's control logic, input buffers, decoders, and sense amplifiers. CE#-high deselects the device and reduces power consumption to standby levels. RESET/DEEP POWER-DOWN: Puts the device in deep power-down mode and resets internal automation. RP#-high enables normal operation. When driven low, RP# inhibits write operations which provides data protection during power transitions. Exit from deep power-down sets the device to read array mode. RP# at VHH enables setting of the master lock-bit and enables configuration of block lock-bits when the master lock-bit is set. RP#=VHH overrides block lock-bits thereby enabling block erase and byte write operations to locked memory blocks. Block erase, byte write, or lock-bit configuration with VIH |