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SDR SDRAM E0342M21 (Ver.2.1) February 2004 (K) Japan
PRELIMINARY DATA SHEET
M2V64S50ETP
64M Single Data Rate Synchronous DRAM
DESCRIPTION
M2V64S50ETP is a 4-bank x 524,288-word x 32-bit, synchronous DRAM, with LVTTL interface. All inputs and outputs are referenced to the rising edge of CLK. The M2V64S50ETP achieve very high speed data rate up to 100MHz (-7) , 133MHz (-6), 166MHz(-5), and are suitable for digital consumer products or graphic memory in computer systems.
FEATURES
- Single 3.3v + 0.3V power supply - Max. Clock frequency -5:PC166<3-3-3> / -6:PC133<3-3-3> / -7:PC100<2-2-2> - Fully Synchronous operation referenced to clock rising edge - Single Data Rate - 4 bank operation controlled by BA0, BA1 (Bank Address) - /CAS latency- 2/3 (programmable) - Burst length- 1/2/4/8/full page (programmable) - Burst type- sequential / interleave (programmable) - Random column access - Auto precharge / All bank precharge controlled by A10 - Auto refresh and Self refresh - 4096 refresh cycles /64ms (4 banks concurrent refresh) (x32) - Address Input, Row address A0-10 / Column address A0-7 (x32) - LVTTL Interface - Package type, M2V64S50ETP: 0.5mm lead pitch 86-pin TSOP(II) (x32) -Low Power for the Self Refresh Current Low Power Version : ICC6 < 500uA (-5L, -6L, -7L)
Operating Frequencies
Max. Frequency @CL=2 * M2V64S50ETP -5/-5L M2V64S50ETP -6/-6L M2V53S50ETP -7/-7L 133MHz 100MHz 100MHz Max. Frequency @CL=3 * 166MHz 133MHz 100MHz Standard
PC166(CL3) PC133(CL3) PC100(CL2)
* CL = CAS(Read) Latency Remark: The -5L/-6L/-7L is ICC6(Self-refresh) low power version. (ICC6 < 500uA)
This Product became EOL in August, 2004.
Elpida Memory, Inc. 2003
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SDR SDRAM E0342M21 (Ver.2.1) February 2004 (K) Japan
PRELIMINARY DATA SHEET
M2V64S50ETP
64M Single Data Rate Synchronous DRAM
PIN CONFIGURATION
x32 (TOP VIEW)
VDD DQ0 VDDQ DQ1 DQ2 VSSQ DQ3 DQ4 VDDQ DQ5 DQ6 VSSQ DQ7 NC VDD DQM0 /WE /CAS /RAS /CS NC BA0 BA1 A10/AP A0 A1 A2 DQM2 VDD NC DQ16 VSSQ DQ17 DQ18 VDDQ DQ19 DQ20 VSSQ DQ21 DQ22 VDDQ DQ23 VDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 VSS DQ15 VSSQ DQ14 DQ13 VDDQ DQ12 DQ11 VSSQ DQ10 DQ9 VDDQ DQ8 NC VSS DQM1 NC NC CLK CKE A9 A8 A7 A6 A5 A4 A3 DQM3 VSS NC DQ31 VDDQ DQ30 DQ29 VSSQ DQ28 DQ27 VDDQ DQ26 DQ25 VSSQ DQ24 VSS
400mil x875mil 86pin TSOP(II)
0.5mm pin pitch
CLK CKE /CS /RAS /CAS /WE DQ0-31
: Master Clock : Clock Enable : Chip Select : Row Address Strobe : Column Address Strobe : Write Enable : Data I/O
DQM0-3 A0-10 BA0,1 VDD VDDQ VSS VSSQ
: Output Disable/ Write Mask : Address Input : Bank Address : Power Supply : Power Supply for Output : Ground : Ground for Output
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SDR SDRAM E0342M21 (Ver.2.1) February 2004 (K) Japan
PRELIMINARY DATA SHEET
M2V64S50ETP
64M Single Data Rate Synchronous DRAM
PIN FUNCTION
CLK Input Master Clock: All other inputs are referenced to the rising edge of CLK. Clock Enable: CKE controls internal clock. When CKE is low, internal clock for the following cycle is ceased. CKE is also used to select auto / self refresh. After self refresh mode is started, CKE becomes asynchronous input. Self refresh is maintained as long as CKE is low. Chip Select: When /CS is high, any command are masked except CLK, CKE and DQM Combination of /RAS, /CAS, /WE defines basic commands. A0-11 specify the Row / Column Address in conjunction with BA0,1. The Row Address is specified by A0-10(x32). The Column Address is specified by A0-7. A10 is also used to indicate precharge option. When A10 is high at a read / write command, an auto precharge is performed. When A10 is high at a precharge command, all banks are precharged. Bank Address: BA0,1 specifies one of four banks to which a command is applied. BA0,1 must be set with ACT, PRE, READ, WRITE commands. Data In and Data out are referenced to the rising edge of CLK. Din Mask / Output Disable: When DQM is high in burst write, Din for the current cycle is masked. When DQM is high in burst read, Dout is disabled at the next but one cycle. Power Supply for the memory array and peripheral circuitry. VDDQ and VSSQ are supplied to the Output Buffers only.
CKE
Input
/CS /RAS, /CAS, /WE
Input Input
A0-11
Input
BA0,1
Input
DQ0-31(x32)
Input / Output
DQM0-3(X32)
Input
VDD, VSS VDDQ, VSSQ
Power Supply Power Supply
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SDR SDRAM E0342M21 (Ver.2.1) February 2004 (K) Japan
PRELIMINARY DATA SHEET
M2V64S50ETP
64M Single Data Rate Synchronous DRAM
BLOCK DIAGRAM
DQ0-31
I/O Buffer
Memory Array Bank #0
2048 x256 x32 Cell Array
Memory Array
2048 x256 x32 Cell Array
Memory Array
2048 x256 x32 Cell Array
Memory Array
2048 x256 x32 Cell Array
Bank #1
Bank #2
Bank #3
Mode Register Control Circuitry
Address Buffer Clock Buffer
Control Signal Buffer
A0-10
BA0,1
CLK
CKE
/CS
/RAS
/CAS
/WE
DQM0-3
TYPE DESIGNATION CODE M2 V 64 S 5 0 E TP -5
These rules are only applied to the Synchronous DRAM family.
Access Item
-5 : 6ns(PC166/3-3-3) -6 : 7.5ns (PC133/3-3-3), -7 : 10ns(PC100/2-2-2), TP : TSOP (II) E: 6th gen. Reserved for Future Use 5: x32
Package Type Process Generation Function Organization Synchronous DRAM Density Interface Mitsubishi DRAM
64 : 64Mbit V : LVTTL
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SDR SDRAM E0342M21 (Ver.2.1) February 2004 (K) Japan
PRELIMINARY DATA SHEET
M2V64S50ETP
64M Single Data Rate Synchronous DRAM
BASIC FUNCTIONS
The M2V64S50ETP provides basic functions, bank (row) activate, burst read / write, bank (row) precharge, and auto / self refresh. Each command is defined by control signals of /RAS, /CAS and /WE at CLK rising edge. In addition to 3 signals, /CS ,CKE and A10 are used as chip select, refresh option, and precharge option, respectively. To know the detailed definition of commands, please see the command truth table. CLK /CS /RAS /CAS /WE CKE A10
Chip Select : L=select, H=deselect Command Command Command Refresh Option @refresh command Precharge Option @precharge or read/write command define basic commands
Activate (ACT) [/RAS =L, /CAS =/WE =H]
ACT command activates a row in an idle bank indicated by BA.
Read (READ) [/RAS =H, /CAS =L, /WE =H]
READ command starts burst read from the active bank indicated by BA. First output data appears after /CAS latency. When A10 =H at this command, the bank is deactivated after the burst read (autoprecharge, READA)
Write (WRITE) [/RAS =H, /CAS =/WE =L]
WRITE command starts burst write to the active bank indicated by BA. Total data length to be written is set by burst length. When A10 =H at this command, the bank is deactivated after the burst write (auto-precharge, WRITEA).
Precharge (PRE) [/RAS =L, /CAS =H, /WE =L]
PRE command deactivates the active bank indicated by BA. This command also terminates burst read /write operation. When A10 =H at this command, all banks are deactivated (precharge all, PREA).
Auto-Refresh (REFA) [/RAS =/CAS =L, /WE =CKE =H]
REFA command starts auto-refresh cycle. Refresh address are generated internally. After this command, the banks are precharged automatically.
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SDR SDRAM E0342M21 (Ver.2.1) February 2004 (K) Japan
PRELIMINARY DATA SHEET
M2V64S50ETP
64M Single Data Rate Synchronous DRAM
COMMAND TRUTH TABLE
COMMAND Deselect No Operation Row Address Entry & Bank Activate Single Bank Precharge Precharge All Banks Column Address Entry & Write Column Address Entry & Write with Auto-Precharge Column Address Entry & Read Column Address Entry & Read with Auto-Precharge Auto-Refresh Self-Refresh Entry Self-Refresh Exit Burst Terminate Mode Register Set MNEMONIC DESEL NOP ACT PRE PREA WRITE CKE n-1 H H H H H H CKE n X X X X X X /CS H L L L L L /RAS /CAS X H L L L H X H H H H L /WE BA0,1 X H H L L L X X V V X V A10 /AP X X V L H L A0-9, Note 11 X X V X X V
WRITEA
H
X
L
H
L
L
V
H
V
READ
H
X
L
H
L
H
V
L
V
READA REFA REFS REFSX TBST MRS
H H H L L H H
X H L H H X X
L L L H L L L
H L L X H H L
L L L X H H L
H H H X H L L
V X X X X X L
H X X X X X L
V X X X X X V 1
H=High Level, L=Low Level, V=Valid, X=Don't Care, n=CLK cycle number NOTE : A7-9=L, A0-A6 =Mode Address (x32)
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SDR SDRAM E0342M21 (Ver.2.1) February 2004 (K) Japan
PRELIMINARY DATA SHEET
M2V64S50ETP
64M Single Data Rate Synchronous DRAM
FUNCTION TRUTH TABLE (1/4)
Current State IDLE /CS H L L L L L L L ROW ACTIVE H L L L L L L L L READ H L L L /RAS X H H H L L L L X H H H H L L L L X H H H /CAS X H H L H H L L X H H L L H H L L X H H L /WE X H L X H L H L X H L H L H L H L X H L H X X X BA, CA, A10 BA, RA BA, A10 X Op-Code, Mode-Add X X X BA, CA, A10 BA, CA, A10 BA, RA BA, A10 X Op-Code, Mode-Add X X X BA, CA, A10 Address Command DESEL NOP TBST READ / WRITE ACT PRE / PREA REFA MRS DESEL NOP TBST READ / READA WRITE / WRITEA ACT PRE / PREA REFA MRS DESEL NOP TBST NOP NOP ILLEGAL*2 ILLEGAL*2 Bank Active, Latch RA NOP*4 Auto-Refresh*5 Mode Register Set*5 NOP NOP NOP Begin Read, Latch CA, Determine Auto-Precharge Begin Write, Latch CA, Determine Auto-Precharge Bank Active / ILLEGAL*2 Precharge / Precharge All ILLEGAL ILLEGAL NOP (Continue Burst to END) NOP (Continue Burst to END) Terminate Burst Action
Terminate Burst, Latch CA, READ / READA Begin New Read, Determine Auto-Precharge*3 WRITE / WRITEA ACT PRE / PREA REFA MRS Terminate Burst, Latch CA, Begin Write, Determine AutoPrecharge*3 Bank Active / ILLEGAL*2 Terminate Burst, Precharge ILLEGAL ILLEGAL
L L L L L
H L L L L
L H H L L
L H L H L
BA, CA, A10 BA, RA BA, A10 X Op-Code, Mode-Add
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SDR SDRAM E0342M21 (Ver.2.1) February 2004 (K) Japan
PRELIMINARY DATA SHEET
M2V64S50ETP
64M Single Data Rate Synchronous DRAM
FUNCTION TRUTH TABLE (2/4)
Current State WRITE /CS H L L L /RAS X H H H /CAS X H H L /WE X H L H X X X BA, CA, A10 Address Command DESEL NOP TBST READ / READA Action NOP (Continue Burst to END) NOP (Continue Burst to END) Terminate Burst Terminate Burst, Latch CA, Begin Read, Determine AutoPrecharge*3 Terminate Burst, Latch CA, Begin Write, Determine AutoPrecharge*3 Bank Active / ILLEGAL*2 Terminate Burst, Precharge ILLEGAL ILLEGAL NOP (Continue Burst to END) NOP (Continue Burst to END) ILLEGAL ILLEGAL for same Bank *6 ILLEGAL for same Bank *6 Bank Active / ILLEGAL*2 ILLEGAL*2 ILLEGAL ILLEGAL NOP (Continue Burst to END) NOP (Continue Burst to END) ILLEGAL ILLEGAL for same Bank *7 ILLEGAL for same Bank *7 Bank Active / ILLEGAL*2 ILLEGAL*2 ILLEGAL ILLEGAL
L L L L L READ with AUTO PRECHARGE H L L L L L L L L WRITE with AUTO PRECHARGE H L L L L L L L L
H L L L L X H H H H L L L L X H H H H L L L L
L H H L L X H H L L H H L L X H H L L H H L L
L H L H L X H L H L H L H L X H L H L H L H L
BA, CA, A10 BA, RA BA, A10 X Op-Code, Mode-Add X X X BA, CA, A10 BA, CA, A10 BA, RA BA, A10 X Op-Code, Mode-Add X X X BA, CA, A10 BA, CA, A10 BA, RA BA, A10 X Op-Code, Mode-Add
WRITE / WRITEA ACT PRE / PREA REFA MRS DESEL NOP TBST READ / READA WRITE / WRITEA ACT PRE / PREA REFA MRS DESEL NOP TBST READ / READA WRITE / WRITEA ACT PRE / PREA REFA MRS
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SDR SDRAM E0342M21 (Ver.2.1) February 2004 (K) Japan
PRELIMINARY DATA SHEET
M2V64S50ETP
64M Single Data Rate Synchronous DRAM
FUNCTION TRUTH TABLE (3/4)
Current State PRE - CHARGING /CS H L L L L L L L ROW ACTIVATING H L L L L L L L WRITE RECOVERING H L L L L L L L /RAS X H H H L L L L X H H H L L L L X H H H L L L L /CAS X H H L H H L L X H H L H H L L X H H L H H L L /WE X H L X H L H L X H L X H L H L X H L X H L H L X X X BA, CA, A10 BA, RA BA, A10 X Op-Code, Mode-Add X X X BA, CA, A10 BA, RA BA, A10 X Op-Code, Mode-Add X X X BA, CA, A10 BA, RA BA, A10 X Op-Code, Mode-Add Address Command DESEL NOP TBST READ / WRITE ACT PRE / PREA REFA MRS DESEL NOP TBST READ / WRITE ACT PRE / PREA REFA MRS DESEL NOP TBST READ / WRITE ACT PRE / PREA REFA MRS Action NOP (Idle after tRP) NOP (Idle after tRP) ILLEGAL*2 ILLEGAL*2 ILLEGAL*2 NOP*4 (Idle after tRP) ILLEGAL ILLEGAL NOP (Row Active after tRCD) NOP (Row Active after tRCD) ILLEGAL*2 ILLEGAL*2 ILLEGAL*2 ILLEGAL*2 ILLEGAL ILLEGAL NOP NOP ILLEGAL*2 ILLEGAL*2 ILLEGAL*2 ILLEGAL*2 ILLEGAL ILLEGAL
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SDR SDRAM E0342M21 (Ver.2.1) February 2004 (K) Japan
PRELIMINARY DATA SHEET
M2V64S50ETP
64M Single Data Rate Synchronous DRAM
FUNCTION TRUTH TABLE (4/4)
Current State REFRESHING /CS H L L L L L L L MODE REGISTER SETTING H L L L L L L L /RAS X H H H L L L L X H H H L L L L /CAS X H H L H H L L X H H L H H L L /WE X H L X H L H L X H L X H L H L X X X BA, CA, A10 BA, RA BA, A10 X Op-Code, Mode-Add X X X BA, CA, A10 BA, RA BA, A10 X Op-Code, Mode-Add Address Command DESEL NOP TBST READ / WRITE ACT PRE / PREA REFA MRS DESEL NOP TBST READ / WRITE ACT PRE / PREA REFA MRS Action NOP (Idle after tRFC) NOP (Idle after tRFC) ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL NOP (Idle after tRSC) NOP (Idle after tRSC) ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL
ABBREVIATIONS: H=High Level, L=Low Level, X=Don't Care BA=Bank Address, RA=Row Address, CA=Column Address, NOP=No Operation NOTES: 1. All entries assume that CKE was High during the preceding clock cycle and the current clock cycle. 2. ILLEGAL to bank in specified state; function may be legal in the bank indicated by BA, depending on the state of that bank. 3. Must satisfy bus contention, bus turn around, write recovery requirements. 4. NOP to bank precharging or in idle state. May precharge bank indicated by BA. 5. ILLEGAL if any bank is not idle. 6. Refer to Read with Auto-Precharge in page 16 7. Refer to Write with Auto-Precharge in page 17 ILLEGAL = Device operation and/or data-integrity are not guaranteed.
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SDR SDRAM E0342M21 (Ver.2.1) February 2004 (K) Japan
PRELIMINARY DATA SHEET
M2V64S50ETP
64M Single Data Rate Synchronous DRAM
FUNCTION TRUTH TABLE for CKE
Current State SELFREFRESH*1 CKE n-1 H L L L L L L POWER DOWN ALL BANKS IDLE*2 H L L H H H H H H H L ANY STATE other than listed above H H L L CKE n X H H H H H L X H L H L L L L L L X H L H L /CS X H L L L L X X X X X L H L L L L X X X X X /RAS /CAS X X H H H L X X X X X L X H H H L X X X X X X X H H L X X X X X X L X H H L X X X X X X /WE X X H L X X X X X X X H X H L X X X X X X X Add X X X X X X X X X X X X X X X X X X X X X X INVALID Exit Self-Refresh (Idle after tRFC) Exit Self-Refresh (Idle after tRFC) ILLEGAL ILLEGAL ILLEGAL NOP (Maintain Self-Refresh) INVALID Exit Power Down to Idle NOP (Maintain Power Down) Refer to Function Truth Table Enter Self-Refresh Enter Power Down Enter Power Down ILLEGAL ILLEGAL ILLEGAL Refer to Current State =Power Down Refer to Function Truth Table Begin CLK Suspend at Next Cycle*3 Exit CLK Suspend at Next Cycle*3 Maintain CLK Suspend Action
ABBREVIATIONS: H=High Level, L=Low Level, X=Don't Care NOTES: 1. CKE Low to High transition will re-enable CLK and other inputs asynchronously A minimum setup time must be satisfied before any command other than EXIT. 2. Self-Refresh can be entered only from the All Banks Idle State. 3. Must be legal command.
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SDR SDRAM E0342M21 (Ver.2.1) February 2004 (K) Japan
PRELIMINARY DATA SHEET
M2V64S50ETP
64M Single Data Rate Synchronous DRAM
SIMPLIFIED STATE DIAGRAM
POWER APPLIED
POWER ON
PREA
PRE CHARGE ALL
REFA ( 2 or MORE )
AUTO REFRESH
MRS
MODE REGISTER SET
MRS
SELF REFRESH
REFS
IDLE
REFSX
REFA
AUTO REFRESH
CKEL
CLK SUSPEND
ACT CKEL CKEH
CKEH
POWER DOWN
TBST WRITE
ROW ACTIVE
TBST READ
WRITE SUSPEND CKEH
CKEL
WRITEA
READA READ
CKEL
WRITE
WRITE
READ
CKEH
READ SUSPEND
WRITEA
WRITEA
READA
READA
CKEL
CKEL PRE PRE PRE
WRITEA WRITEA SUSPEND CKEH
READA
READA CKEH SUSPEND
PRE CHARGE Automatic Sequence Command Sequence
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SDR SDRAM E0342M21 (Ver.2.1) February 2004 (K) Japan
PRELIMINARY DATA SHEET
M2V64S50ETP
64M Single Data Rate Synchronous DRAM
POWER ON SEQUENCE
Before starting normal operation, the following power on sequence is necessary to prevent a SDRAM from damaged or malfunctioning. 1. Apply power and start clock. Attempt to maintain CKE high, DQM high and NOP or DESEL condition at the inputs. 2. Maintain stable power, stable clock, and NOP or DESEL input conditions for a minimum of 100us. 3. Issue precharge commands for all banks. (PRE or PREA) 4. After all banks become idle state (after tRP), issue 2 or more auto-refresh commands. 5. Issue a mode register set command to initialize the mode register. After these sequence, the SDRAM is idle state and ready for normal operation.
MODE REGISTER
Burst Length, Burst Type, /CAS Latency and Write Mode can be programmed By setting the mode register (MRS) with BA0=BA1=0. The mode register stores these data until the next MRS command, which may be issued when all banks are in idle state. After tRSC from a MRS command, the SDRAM is ready for new command. Unused bit A7-A8,A10(x32) have to be programmed to "0". CLK /CS /RAS /CAS /WE BA0,BA1 A11-A0 BA0 BA1 A11 A10 A9 0 0 0 0 WM A8 0 A7 0 A6 A5 A4 A3 A2 BT A1 A0 BL
V
LTMODE
Write Mode
0 1
Burst Write Single Write
BL 000 001 010 011 100 101 110 111 0 1
Latency Mode
CL 000 001 010 011 100 101 110 111
/CAS LATENCY R R 2 3 R R R R
Burst Length
BT=0 1 2 4 8 R R R Full Page
BT=1 1 2 4 8 R R R R
Burst Type
SEQUENTIAL INTERLEAVED
R: Reserved for Future Use
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SDR SDRAM E0342M21 (Ver.2.1) February 2004 (K) Japan
PRELIMINARY DATA SHEET
M2V64S50ETP
64M Single Data Rate Synchronous DRAM
CLK Command Address DQ CL= 3 BL= 4 /CAS Latency Burst Length Burst Type Burst Length
Read Y Q0 Q1 Q2 Q3 Write Y D0 D1 D2 D3
Initial Address BL A2 0 0 0 0 1 1 1 1 A1 0 0 1 1 0 0 1 1 0 0 1 1 A0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 4 8 0 1 2 3 4 5 6 7 0 1 2 3 0 1 1 2 3 4 5 6 7 0 1 2 3 0 1 0 2 3 4 5 6 7 0 1 2 3 0 1 Sequential 3 4 5 6 7 0 1 2 3 0 1 2 4 5 6 7 0 1 2 3 5 6 7 0 1 2 3 4
Column Addressing Interleaved 6 7 0 1 2 3 4 5 7 0 1 2 3 4 5 6 0 1 2 3 4 5 6 7 0 1 2 3 0 1 1 0 3 2 5 4 7 6 1 0 3 2 1 0 2 3 0 1 6 7 4 5 2 3 0 1 3 2 1 0 7 6 5 4 3 2 1 0 4 5 6 7 0 1 2 3 5 4 7 6 1 0 3 2 6 7 4 5 2 3 0 1 7 6 5 4 3 2 1 0
2
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SDR SDRAM E0342M21 (Ver.2.1) February 2004 (K) Japan
PRELIMINARY DATA SHEET
M2V64S50ETP
64M Single Data Rate Synchronous DRAM
OPERATIONAL DESCRIPTION
BANK ACTIVATE
One of four banks is activated by an ACT command. A bank is selected by BA0-1. A row is selected by A0-10(x32). Multiple banks can be active state concurrently by issuing multiple ACT commands. Minimum activation interval between one bank and another bank is tRRD.
PRECHARGE
An open bank is deactivated by a PRE command. A bank to be deactivated is designated by BA0-1. When multiple banks are active, a precharge all command (PREA, PRE + A10=H) deactivates all of open banks at the same time. BA0-1 are "Don't Care" in this case. Minimum delay time of an ACT command after a PRE command to the same bank is tRP.
Bank Activation and Precharge All (BL=4, CL=3)
CLK Command A0-9,11 A10 BA0-1 DQ ACT
tRRD
ACT
tRCD
READ Yb 0 01 Qb0 Qb1
PRE
tRP
ACT Xa
Xa Xa 00
Xb Xb 01
1
Xa 00
Qb2
Qb3
Precharge All
READ
A READ command can be issued to any active bank. The start address is specified by A0-7. 1st output data is available after the /CAS Latency from the READ. The consecutive data length is defined by the Burst Length. The address sequence of the burst data is defined by the Burst Type. Minimum delay time of a READ command after an ACT command to the same bank is tRCD. When A10 is high at a READ command, auto-precharge (READA) is performed. Any command (READ, WRITE, PRE, ACT,TBST) to the same bank is inhibited till the internal precharge is complete. The internal precharge starts at the BL after READA. The next ACT command can be issued after (BL + tRP) from the previous READA. In any case, tRCD+BL > tRASmin must be met.
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SDR SDRAM E0342M21 (Ver.2.1) February 2004 (K) Japan
PRELIMINARY DATA SHEET
M2V64S50ETP
64M Single Data Rate Synchronous DRAM Multi Bank Interleaving Read (CL=2, BL=4)
CLK Command A0-9,11 A10 BA0-1 DQ ACT
tRCD
READ Ya 0 00
ACT
tRCD
READ PRE
tRP
ACT Xa
Xa Xa 00
Xb Xb 01 Qa0 Qa1
Yb 0 01 Qa2 0 00 Qa3 Qb0
Xa 00 Qb1 Qb2 Qb3
Read with Auto-Precharge (CL=2, BL=4)
CLK Command A0-9,11 A10 BA0-1 DQ ACT
tRCD
READ
BL tRP
ACT Xa Xa 00 Qa0 Qa1 Qa2 Qa3
Xa Xa 00
Ya 1 00
internal precharge starts
Auto-Precharge Timing (READ, BL=4)
CLK Command DQ DQ ACT
tRCD
READ
BL
ACT Qa0 Qa1 Qa0 Qa2 Qa1 Qa3 Qa2 Qa3
CL=2 CL=3
internal precharge starts
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SDR SDRAM E0342M21 (Ver.2.1) February 2004 (K) Japan
PRELIMINARY DATA SHEET
M2V64S50ETP
64M Single Data Rate Synchronous DRAM
WRITE
A WRITE command can be issued to any active bank.The start address is specified by A0-7. 1st input data is set at the same cycle as the WRITE. The consecutive data length to be written is defined by the Burst Length. The address sequence of burst data is defined by the Burst Type. Minimum delay time of a WRITE command after an ACT command to the same bank is tRCD. From the last input data to the PRE command, the write recovery time (tWR) is required. When A10 is high at a WRITE command, auto-precharge (WRITEA) is performed. Any command (READ, WRITE, PRE, ACT, TBST) to the same bank is inhibited till the internal precharge is complete. The internal precharge starts at tWR after the last input data cycle. The next ACT command can be issued after (BL + tWR -1 +tRP) from the previous WRITEA. In any case, tRCD + BL + tWR -1 > tRASmin must be met.
Write (BL=4)
CLK Command A0-9,11 A10 BA0-1 DQ ACT
tRCD
Write
BL
PRE
tRP
ACT Xa
Xa Xa 00
Ya 0 00
tWR
0
Xa 00
Da0
Da1
Da2
Da3
Write with Auto-Precharge (BL=4)
CLK Command A0-9,11 A10 BA0-1 DQ ACT
tRCD
Write
BL tRP
ACT Xa Xa 00
tWR
Xa Xa 00
Ya 1 00 Da0 Da1 Da2 Da3 internal precharge starts
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SDR SDRAM E0342M21 (Ver.2.1) February 2004 (K) Japan
PRELIMINARY DATA SHEET
M2V64S50ETP
64M Single Data Rate Synchronous DRAM
BURST INTERRUPTION Read Interrupted by Read
Burst read operation can be interrupted by new read of any active bank. Random column access is allowed. READ to READ interval is minimum 1 CLK.
Read Interrupted by Read (CL=2, BL=4)
CLK Command A0-9,11 A10 BA0-1 DQ READ Ya 0 00 Qa0 READ READ Yb 0 00 Qa1 Yc 0 10 Qa2 Qb0 Qc0 Qc1 Qc2 Qc3
Read Interrupted by Write
Burst read operation can be interrupted by write of any active bank. Random column access is allowed. In this case, the DQ should be controlled adequately by using the DQM to prevent the bus contention. The output is disabled automatically 2 cycle after WRITE assertion.
Read Interrupted by Write (CL=2, BL=4)
CLK Command A0-9,11 A10 BA0-1 ACT Xa Xa 00 READ Ya 0 00 Write Ya 0 00
DQM DQ Qa0 Da0 Da1 Da2 Da3 by WRITE
Output disable by DQM
18
SDR SDRAM E0342M21 (Ver.2.1) February 2004 (K) Japan
PRELIMINARY DATA SHEET
M2V64S50ETP
64M Single Data Rate Synchronous DRAM
Read Interrupted by Precharge
A burst read operation can be interrupted by a precharge of the same bank . READ to PRE interval is minimum 1 CLK. A PRE command to output disable latency is equivalent to the /CAS Latency.
Read Interrupted by Precharge (BL=4)
CLK Command DQ Command READ READ Q0 PRE Q0 READ PRE Q0 Q1 PRE Q1 Q2
CL=2
DQ Command DQ
Command DQ Command
READ
PRE Q0 Q1 Q2
READ
PRE Q0 Q1
CL=3
DQ Command DQ READ PRE Q0
19
SDR SDRAM E0342M21 (Ver.2.1) February 2004 (K) Japan
PRELIMINARY DATA SHEET
M2V64S50ETP
64M Single Data Rate Synchronous DRAM
Read Interrupted by Burst Terminate
Similarly to the precharge, a burst terminate command can interrupt the burst read operation and disable the data output. The terminated bank remains active. READ to TBST interval is minimum 1 CLK. A TBST command to output disable latency is equivalent to the /CAS Latency.
Read Interrupted by Burst Terminate (BL=4)
CLK Command DQ Command READ READ Q0 TBST Q0 READ TBST Q0 Q1 TBST Q1 Q2
CL=2
DQ Command DQ
Command DQ Command
READ
TBST Q0 Q1 Q2
READ
TBST Q0 Q1
CL=3
DQ Command DQ READ TBST Q0
20
SDR SDRAM E0342M21 (Ver.2.1) February 2004 (K) Japan
PRELIMINARY DATA SHEET
M2V64S50ETP
64M Single Data Rate Synchronous DRAM
Write Interrupted by Write
Burst write operation can be interrupted by new write of any active bank. Random column access is allowed. WRITE to WRITE interval is minimum 1 CLK.
Write Interrupted by Write (BL=4)
CLK Command A0-9,11 A10 BA0-1 DQ Write Ya 0 00 Da0 Da1 Da2 Write Yb 0 00 Db0 Write Yc 0 10 Dc0 Dc1 Dc2 Dc3
Write Interrupted by Read
Burst write operation can be interrupted by read of any active bank. Random column access is allowed. WRITE to READ interval is minimum 1 CLK. The input data on DQ at the interrupting READ cycle is "Don't Care".
Write Interrupted by Read (CL=2, BL=4)
CLK Command A0-9,11 A10 BA0-1 DQ ACT Xa Xa 00 Write Ya 0 00 Da0 Da1 don't care READ Yb 0 00 Qb0 Qb1 Qb2 Qb3
21
SDR SDRAM E0342M21 (Ver.2.1) February 2004 (K) Japan
PRELIMINARY DATA SHEET
M2V64S50ETP
64M Single Data Rate Synchronous DRAM
Write Interrupted by Precharge
Burst write operation can be interrupted by precharge of the same bank. Write recovery time (tWR) is required from the last data to PRE command. During write recovery, data inputs must be masked by DQM.
Write Interrupted by Precharge (BL=4)
CLK Command A0-9,11 A10 BA0-1 DQM
tWR
ACT Xa 0 00
Write Ya 0 00
PRE
tRP
ACT Xa
0 00
0 00
DQ
Da0
Da1
Write Interrupted by Burst Terminate
Burst terminate command can terminate burst write operation. In this case, the write recovery time is not required and the bank remains active. WRITE to TBST interval is minimum 1 CLK.
Write Interrupted by Burst Terminate (BL=4)
CLK Command A0-9,11 A10 BA0-1 DQ ACT Xa 0 00 Write Ya 0 00 Da0 Da1 TBST Write Yb 0 00 Db0 Db1 Db2 Db3
22
SDR SDRAM E0342M21 (Ver.2.1) February 2004 (K) Japan
PRELIMINARY DATA SHEET
M2V64S50ETP
64M Single Data Rate Synchronous DRAM
Write with Auto-Precharge Interrupted by Write / Read to Different Bank
Burst write with auto-precharge can be interrupted by write or read to different bank. Next ACT command can be issued after (BL+tWR-1+tRP) from the WRITEA. Auto-precharge interruption by a command to the same bank is inhibited.
WRITEA Interrupted by WRITE to Different Bank (BL=4)
CLK Command A0-9,11 A10 BA0-1 DQ Write Ya 1 00 Da0 Da1 Write
BL tRP
ACT Xa
tWR
Yb 0 10 Db0 interrupted Db1 Db2 Db3 precharge
Xa 00
auto-precharge
activate
WRITEA Interrupted by READ to Different Bank (CL=2, BL=4)
CLK Command A0-9,11 A10 BA0-1 DQ Write Ya 1 00 Da0 Da1 interrupted Read
BL tRP
ACT Xa
tWR
Yb 0 10 Qb0 Qb1 precharge Qb2
Xa 00 Qb3 activate
auto-precharge
23
SDR SDRAM E0342M21 (Ver.2.1) February 2004 (K) Japan
PRELIMINARY DATA SHEET
M2V64S50ETP
64M Single Data Rate Synchronous DRAM
Read with Auto-Precharge Interrupted by Read to Different Bank
Burst read with auto-precharge can be interrupted by read to different bank. Next ACT command can be issued after (BL+tRP) from the READA. Auto-precharge interruption by a command to the same bank is inhibited.
READA Interrupted by READ to Different Bank (CL=2, BL=4)
CLK Command A0-9,11 A10 BA0-1 DQ auto-precharge Read Ya 1 00 Read
BL tRP
ACT Xa Xa 00 Qa1 Qb0 precharge Qb1 Qb2 activate Qb3
Yb 0 10 Qa0 interrupted
Full Page Burst
Full page burst length is available for only the sequential burst type. Full page burst read / write is repeated until a Precharge or a Burst Terminate command is issued. In case of the full page burst, a read / write with auto-precharge command is illegal.
24
SDR SDRAM E0342M21 (Ver.2.1) February 2004 (K) Japan
PRELIMINARY DATA SHEET
M2V64S50ETP
64M Single Data Rate Synchronous DRAM
AUTO REFRESH
Single cycle of auto-refresh is initiated with a REFA (/CS= /RAS= /CAS= L, /WE= /CKE= H) command. The refresh address is generated internally. 4096 REFA cycles within 64ms refresh 64Mbit memory cells. The auto-refresh is performed on 4 banks concurrently. Before performing an auto-refresh, all banks must be in idle state. Auto-refresh to auto-refresh interval is minimum tRFC. Any command must not be issued before tRFC from the REFA command.
Auto-Refresh
CLK /CS /RAS /CAS /WE CKE A0-11 BA0-1 minimum tRFC
NOP or DESELECT
Auto Refresh on All Banks
Auto Refresh on All Banks
25
SDR SDRAM E0342M21 (Ver.2.1) February 2004 (K) Japan
PRELIMINARY DATA SHEET
M2V64S50ETP
64M Single Data Rate Synchronous DRAM
SELF REFRESH
Self-refresh mode is entered by issuing a REFS command (/CS= /RAS= /CAS= L, /WE= H, CKE= L). Once the self-refresh is initiated, it is maintained as long as CKE is kept low. During the self-refresh mode, CKE is asynchronous and the only enabled input. All other inputs including CLK are disabled and ignored, so that power consumption due to synchronous inputs is saved. To exit the self-refresh, supplying stable CLK inputs, asserting DESEL or NOP command and then asserting CKE=H. After tRFC from the 1st CLK edge following CKE=H, all banks are in idle state and a new command can be issued, but DESEL or NOP commands must be asserted till then.
Self-Refresh
CLK
Stable CLK NOP
/CS /RAS /CAS /WE CKE A0-11 BA0-1
new command X 00
Self Refresh Entry
Self Refresh Exit
minimum tRFC for recovery
26
SDR SDRAM E0342M21 (Ver.2.1) February 2004 (K) Japan
PRELIMINARY DATA SHEET
M2V64S50ETP
64M Single Data Rate Synchronous DRAM
CLK SUSPEND and POWER DOWN
CKE controls the internal CLK at the following cycle. Figure below shows how CKE works. By negating CKE, the next internal CLK is suspended. The purpose of CLK suspend is power down, output suspend or input suspend. CKE is a synchronous input except during the self-refresh mode. CLK suspend can be performed either when the banks are active or idle. A command at the suspended cycle is ignored. ext.CLK tIH CKE tIS tIH tIS
int.CLK
Power Down by CKE
CLK CKE Command
PRE NOP NOP NOP Standby Power Down
CKE Command
ACT NOP NOP NOP
Active Power Down
DQ Suspend by CKE
CLK CKE Command
Write Read
DQ
D0
D1
D2
D3
Q0
Q1
Q2
Q3
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SDR SDRAM E0342M21 (Ver.2.1) February 2004 (K) Japan
PRELIMINARY DATA SHEET
M2V64S50ETP
64M Single Data Rate Synchronous DRAM
DQM CONTROL
DQM* is a dual functional signal defined as the data mask for writes and the output disable for reads. During writes, DQM masks input data word by word. DQM to Data In latency is 0. During reads, DQM forces output to Hi-Z word by word. DQM to output Hi-Z latency is 2. * DQM: DQ0-3 (X32)
DQM Function
CLK Command DQM0-3
Write Read
DQ
D0
D2
D3
Q0
Q1
Q3
masked by DQM=H
disabled by DQM=H
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SDR SDRAM E0342M21 (Ver.2.1) February 2004 (K) Japan
PRELIMINARY DATA SHEET
M2V64S50ETP
64M Single Data Rate Synchronous DRAM
ABSOLUTE MAXIMUM RATINGS
Symbol VDD VDDQ VI VO IO Pd Topr Tstg Parameter Supply Voltage Supply Voltage for Output Input Voltage Output Voltage Output Current Power Dissipation Operating Temperature Storage Temperature TA=25 oC Conditions with respect to VSS with respect to VSSQ with respect to VSS with respect to VSSQ Ratings -0.5 to 4.6 -0.5 to 4.6 -0.5 to VDD+0.5 -0.5 to VDD+0.5 50 1000 0 to 70 -65 to 150 Unit V V V V mA mW
oC oC
RECOMMENDED OPERATING CONDITIONS
(TA=0 to 70oC, unless otherwise noted)
Symbol VDD VSS VDDQ VSSQ VIH VIL Parameter Supply Voltage Supply Voltage Supply Voltage for Output Supply Voltage for Output High-Level Input Voltage all inputs Low-Level Input Voltage all inputs Limits Min. 3.0 0 3.0 0 2.0 -0.3 Typ. 3.3 0 3.3 0 Max. 3.6 0 3.6 0 VDD+0.3 0.8 Unit V V V V V V
CAPACITANCE
(TA=0 to 70oC, VDD = VDDQ = 3.3V+0.3V, VSS = VSSQ = 0V, unless otherwise noted)
Symbol CI(A) CI(C) CI(K) CI/O Parameter Input Capacitance,address pin Input Capacitance,control pin Input Capacitance,CLK pin Input Capacitance,I/O pin VI=1.4V f=1MHz VI=25mVrms Test Condition Limits Min. 2.0 2.0 2.0 3.0 Max. 4.0 4.0 4.0 6.0 Unit pF pF pF pF
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SDR SDRAM E0342M21 (Ver.2.1) February 2004 (K) Japan
PRELIMINARY DATA SHEET
M2V64S50ETP
64M Single Data Rate Synchronous DRAM
AVERAGE SUPPLY CURRENT from VDD
(TA=0 to 70oC, VDD = VDDQ = 3.3V+0.3V, VSS = VSSQ = 0V, Output Open, unless otherwise noted)
Symbol Icc1 Icc2P Icc2PS Icc2N Icc2NS Icc3N Icc3NS Icc4 Icc5 Parameter Operating Current (1bank) Idle Standby Current in Power Down Mode Test Conditions tCLK=min, tRC=min, BL=1 tCLK=min, CKEVIHmin, /CS>VIHmin tCLK=L, CKE>VIHmin tCLK=min, CKE>VIHmin, /CS> VIHmin tCLK=L, CKE>VIHmin tCLK=min, BL=4, gapless data tCLK=min, tRFC=min -5 / -6 / -7 Icc6 Self-Refresh Current CKE<0.2v -5L / -6L / -7L Notes 0.5 mA 6 130 140 Limits(max) -5 110 -6 100 2.0 1.0 10 5 20 10 110 120 1.0 90 100 -7 90 mA mA mA mA mA mA mA mA mA mA 1 2 2 2,3 2,4 3,5 4,5 5 Unit Note
Idle Standby Current in Normal Mode
Active Standby Current in Normal Mode Burst Operating Current Auto-Refresh Current
1. addresses are changed 3 times during tRC, only 1 bank is active & all other banks are idle 2. all banks are idle 3. input signals are changed one time during 3 x tCLK 4. input signals are stable 5. all banks are active 6. Low Power Version(-5L/-6L/-7L)
AC OPERATING CONDITIONS AND CHARACTERISTICS
(TA=0 to 70oC, VDD = VDDQ = 3.3V+0.3V, VSS = VSSQ = 0V, unless otherwise noted)
Symbol VOH(DC) VOL(DC) IOZ IL Parameter High-Level Output Voltage (DC) Low-Level Output Voltage (DC) Off-state Output Current Input Current IOH=-2mA IOL= 2mA Q floating Vo=0 to VDDQ VIH=0 to VDDQ+0.3V, other input pins=0V -10 -10 Test Conditions Limits Min. 2.4 0.4 10 10 Max. Unit V V uA uA
30
SDR SDRAM E0342M21 (Ver.2.1) February 2004 (K) Japan
PRELIMINARY DATA SHEET
M2V64S50ETP
64M Single Data Rate Synchronous DRAM
AC TIMING REQUIREMENTS
(TA=0 to 70oC, VDD = VDDQ = 3.3V+0.3V, VSS = VSSQ = 0V, unless otherwise noted) Input Pulse Levels : 0.8V to 2.0V Input Timing Measurement Level : 1.4V
Limits Symbol Parameter Min. tCLK tCH tCL tT tIS tIH tRC tRFC tRCD tRAS tRP tWR tRRD tRSC tREF CLK cycle time CLK High pulse width CLK Low pulse width Transition time of CLK Input Setup time (all inputs) Input Hold time (all inputs) Row Cycle time Refresh Cycle time Row to Column Delay Row Active time Row Precharge time Write Recovery time ACT to ACT Delay time Mode Register Set Cycle time Refresh Interval time CL=2 CL=3 7.5 7.5 2.5 2.5 1 1.5 0.8 60 66 15 45 15 15 15 10 64 120000 10 -5 Max. Min. 10 7.5 2.5 2.5 1 1.5 0.8 67.5 75 20 45 20 15 15 10 64 120000 10 -6 Max. Min. 10 10 3 3 1 2 1 70 80 20 50 20 20 20 10 64 120000 10 -7 Max. ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms Unit Note
CLK Signal tIS tCLK tIH
1.4V 1.4V AC timing is referenced to the input signal crossing through 1.4V.
31
SDR SDRAM E0342M21 (Ver.2.1) February 2004 (K) Japan
PRELIMINARY DATA SHEET
M2V64S50ETP
64M Single Data Rate Synchronous DRAM
SWITCHING CHARACTERISTICS
(TA=0 to 70oC, VDD = VDDQ = 3.3V+0.3V, VSS = VSSQ = 0V, unless otherwise noted)
Limits Symbol Parameter Min. CL=2 tAC Access Time from CLK CL=3 CL=2 tOH Output Hold Time from CLK CL=3 tOLZ Delay Time, Output Low impedance from CLK CL=2 CL=3 3 0 3 3 5.4 5.4 3 0 3 3 6 5.4 3 0 3 3 6 6 ns ns ns ns 3 5.4 3 5.4 3 6 ns ns -5 Max 5.4 Min. -6 Max 6 Min. -7 Max 6 ns Unit
tOHZ
Delay Time, Output High impedance from CLK
Note. If tr (CLK rising time) is > 1ns, (tr/2 - 0.5ns) should be added to the parameters.
Output Load Condition
Vout 50pF
CLK
1.4V
DQ tOLZ tAC tOH tOHZ
1.4V
32
SDR SDRAM E0342M21 (Ver.2.1) February 2004 (K) Japan
PRELIMINARY DATA SHEET
M2V64S50ETP
64M Single Data Rate Synchronous DRAM
TIMING CHARTS
Burst Write (Single Bank) [BL=4]
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
CLK
tRC
/CS
tRAS tRP
/RAS
tRCD tRCD
/CAS
tWR tWR
/WE CKE DQM A0-9,11 A10 BA0,1 DQ
X Y X Y
X
X
0
0
0
0
0
0
D0
D0
D0
D0
D0
D0
D0
D0
ACT#0 WRITE#0
PRE#0
ACT#0 WRITE#0
PRE#0
Italic parameter shows minimum case
33
SDR SDRAM E0342M21 (Ver.2.1) February 2004 (K) Japan
PRELIMINARY DATA SHEET
M2V64S50ETP
64M Single Data Rate Synchronous DRAM
Burst Write (Multi Bank) [BL=4]
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
CLK
tRC tRC
/CS
tRAS tRRD tRP tRCD tRCD
/RAS
tRCD
/CAS
tWR tWR
/WE CKE DQM A0-9,11 A10 BA0,1 DQ
X Y X Y X Y X
X
X
X
X
0
0
1
1
0
0
0
1
0
D0
D0
D0
D0
D1
D1
D1
D1
D0
D0
D0
D0
ACT#0 WRITE#0 ACT#1
PRE#0
ACT#0 WRITE#0 ACT#1
PRE#0
WRITEA#1 (Auto-Precharge)
Italic parameter shows minimum case
34
SDR SDRAM E0342M21 (Ver.2.1) February 2004 (K) Japan
PRELIMINARY DATA SHEET
M2V64S50ETP
64M Single Data Rate Synchronous DRAM
Burst Read (Single Bank) [CL=2,BL=4]
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
CLK
tRC
/CS
tRAS tRP tRAS
/RAS
tRCD tRCD
/CAS /WE CKE DQM A0-9,11 A10 BA0,1 DQ
X Y X Y
X
X
0
0
0
0
0
0
Q0
Q0
Q0
Q0
Q0
Q0
Q0
Q0
ACT#0
READ#0
PRE#0
ACT#0
READ#0
PRE#0
Italic parameter shows minimum case
35
SDR SDRAM E0342M21 (Ver.2.1) February 2004 (K) Japan
PRELIMINARY DATA SHEET
M2V64S50ETP
64M Single Data Rate Synchronous DRAM
Burst Read (Multi Bank) [CL=2,BL=4]
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
CLK
tRC tRC tRAS
/CS
tRRD
/RAS
tRCD tRCD tRCD
/CAS /WE CKE DQM A0-9,11 A10 BA0,1 DQ
X Y X Y X Y X
X
X
X
X
0
0
1
1
0
0
1
0
Q0
Q0
Q0
Q0
Q1
Q1
Q1
Q1
Q0
Q0
Q0
Q0
ACT#0 READA#0 ACT#1 READA#1
ACT#0
READ#0 ACT#1
PRE#0
Italic parameter shows minimum case
36
SDR SDRAM E0342M21 (Ver.2.1) February 2004 (K) Japan
PRELIMINARY DATA SHEET
M2V64S50ETP
64M Single Data Rate Synchronous DRAM
Write Interrupted by Write [BL=4]
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
CLK /CS
tRRD
/RAS
tRCD
/CAS
tWR
/WE CKE DQM A0-9,11 A10 BA0,1 DQ
X Y X Y Y Y X
X
X
X
0
0
1
0
1
0
0
1
D0
D0
D0
D0
D0
D1
D1
D1
D0
D0
D0
D0
ACT#0 WRITE#0 ACT#1
WRITE#0 interrupt same bank
WRITEA#1 interrupt other bank
WRITE#0 interrupt other bank
PRE#0 ACT#1
Italic parameter shows minimum case
37
SDR SDRAM E0342M21 (Ver.2.1) February 2004 (K) Japan
PRELIMINARY DATA SHEET
M2V64S50ETP
64M Single Data Rate Synchronous DRAM
Read Interrupted by Read [CL=2,BL=4]
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
CLK /CS
tRRD
/RAS
tRCD tRCD
/CAS /WE CKE DQM A0-9,11 A10 BA0,1 DQ
X Y X Y Y Y X
X
X
X
0
0
1
1
1
0
1
Q0
Q0
Q0
Q1
Q1
Q1
Q1
Q1
Q0
Q0
Q0
Q0
ACT#0
READ#0 ACT#1
READ#1 interrupt other bank
READA#1 interrupt same bank
READ#0 interrupt other bank
ACT#1
Italic parameter shows minimum case
38
SDR SDRAM E0342M21 (Ver.2.1) February 2004 (K) Japan
PRELIMINARY DATA SHEET
M2V64S50ETP
64M Single Data Rate Synchronous DRAM
Write Interrupted by Read, Read Interrupted by Write [CL=2,BL=4]
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
CLK /CS
tRRD
/RAS
tRCD tRCD
/CAS
tWR
/WE CKE DQM A0-9,11 A10 BA0,1 DQ
X X Y Y Y
X
X
0
1
0
1
1
1
D0
D0
Q1
Q1
D1
D1
D1
D1
ACT#0
WRITE#0 READ#1 ACT#1
WRITE#1
PRE#1
Italic parameter shows minimum case
39
SDR SDRAM E0342M21 (Ver.2.1) February 2004 (K) Japan
PRELIMINARY DATA SHEET
M2V64S50ETP
64M Single Data Rate Synchronous DRAM
Write / Read Terminated by Precharge [CL=2,BL=4]
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
CLK
tRC
/CS
tRP tRAS tRP
/RAS
tRCD tRCD
/CAS
tWR
/WE CKE DQM A0-9,11 A10 BA0,1 DQ
X Y X Y X
X
X
X
0
0
0
0
0
0
0
D0
D0
Q0
Q0
ACT#0 WRITE#0
PRE#0 Terminate
ACT#0
READ#0 PRE#0 Terminate
ACT#0
Italic parameter shows minimum case
40
SDR SDRAM E0342M21 (Ver.2.1) February 2004 (K) Japan
PRELIMINARY DATA SHEET
M2V64S50ETP
64M Single Data Rate Synchronous DRAM
Write / Read Terminated by Burst Terminate [CL=2,BL=4]
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
CLK /CS /RAS
tRCD
/CAS
tWR
/WE CKE DQM A0-9,11 A10 BA0,1 DQ
X Y Y Y
X
0
0
0
0
0
D0
D0
Q0
Q0
D0
D0
D0
D0
ACT#0 WRITE#0 TBST READ#0 TBST
WRITE#0
PRE#0
Italic parameter shows minimum case
41
SDR SDRAM E0342M21 (Ver.2.1) February 2004 (K) Japan
PRELIMINARY DATA SHEET
M2V64S50ETP
64M Single Data Rate Synchronous DRAM
Single Write Burst Read [CL=2,BL=4]
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
CLK /CS /RAS
tRCD
/CAS /WE CKE DQM A0-9,11 A10 BA0,1 DQ
X Y Y
X
0
0
0
D0
Q0
Q0
Q0
Q0
ACT#0
WRITE#0
READ#0
Italic parameter shows minimum case
42
SDR SDRAM E0342M21 (Ver.2.1) February 2004 (K) Japan
PRELIMINARY DATA SHEET
M2V64S50ETP
64M Single Data Rate Synchronous DRAM
Power-Up Sequence and Initialize
CLK
100us
/CS
tRP tRFC tRFC tRSC
/RAS /CAS /WE CKE DQM A0-9,11 A10 BA0,1 DQ
DESEL Power On PRE ALL REFA REFA REFA MRS ACT#0 MA X
0
X
0
0
Minimum 2 REFA cycles
Italic parameter shows minimum case
43
SDR SDRAM E0342M21 (Ver.2.1) February 2004 (K) Japan
PRELIMINARY DATA SHEET
M2V64S50ETP
64M Single Data Rate Synchronous DRAM
Auto Refresh
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
CLK
tRFC
/CS
tRP
/RAS
tRCD
/CAS /WE CKE DQM A0-9,11 A10 BA0,1 DQ
X Y
X
0
0
D0
D0
D0
D0
PRE ALL
REFA
ACT#0 WRITE#0
All banks must be idle before REFA is issued.
Italic parameter shows minimum case
44
SDR SDRAM E0342M21 (Ver.2.1) February 2004 (K) Japan
PRELIMINARY DATA SHEET
M2V64S50ETP
64M Single Data Rate Synchronous DRAM
Self Refresh
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
CLK
tRFC
/CS
tRP
/RAS /CAS /WE CKE DQM A0-9,11 A10 BA0,1 DQ
X
X
0
PRE ALL
Self Refresh Entry
Self Refresh Exit
ACT#0
All banks must be idle before REFS is issued.
Italic parameter shows minimum case
45
SDR SDRAM E0342M21 (Ver.2.1) February 2004 (K) Japan
PRELIMINARY DATA SHEET
M2V64S50ETP
64M Single Data Rate Synchronous DRAM
CLK Suspension [CL=2, BL=4]
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
CLK /CS /RAS
tRCD
/CAS /WE CKE DQM A0-9,11 A10 BA0,1 DQ
X Y Y
X
0
0
0
D0
D0
D0
D0
Q0
Q0
Q0
Q0
Q0
ACT#0 WRITE#0 Internal CLK suspended
READ#0
Internal CLK suspended
Italic parameter shows minimum case
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SDR SDRAM E0342M21 (Ver.2.1) February 2004 (K) Japan
PRELIMINARY DATA SHEET
M2V64S50ETP
64M Single Data Rate Synchronous DRAM
Power Down
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
CLK /CS /RAS /CAS /WE
Standby Power Down Active Power Down
CKE DQM A0-9,11 A10 BA0,1 DQ
X
X
0
PRE ALL
ACT#0
Italic parameter shows minimum case
47
SDR SDRAM E0342M21 (Ver.2.1) February 2004 (K) Japan
PRELIMINARY DATA SHEET
M2V64S50ETP
64M Single Data Rate Synchronous DRAM
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR MOS DEVICES
Exposing the MOS devices to a strong electric field can cause destruction of the gate oxide and ultimately degrade the MOS devices operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it, when once it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. MOS devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. MOS devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor MOS devices on it.
2 HANDLING OF UNUSED INPUT PINS FOR CMOS DEVICES
No connection for CMOS devices input pins can be a cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. The unused pins must be handled in accordance with the related specifications.
3 STATUS BEFORE INITIALIZATION OF MOS DEVICES
Power-on does not necessarily define initial status of MOS devices. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the MOS devices with reset function have not yet been initialized. Hence, power-on does not guarantee output pin levels, I/O settings or contents of registers. MOS devices are not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for MOS devices having reset function.
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SDR SDRAM E0342M21 (Ver.2.1) February 2004 (K) Japan
PRELIMINARY DATA SHEET
M2V64S50ETP
64M Single Data Rate Synchronous DRAM
The information in this document is subject to change without notice. Before using this document, confirm that this is the latest version.
No part of this document may be copied or reproduced in any form or by any means without the prior written consent of Elpida Memory, Inc. Elpida Memory, Inc. does not assume any liability for infringement of any intellectual property rights (including but not limited to patents, copyrights, and circuit layout licenses) of Elpida Memory, Inc. or third parties by or arising from the use of the products or information listed in this document. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of Elpida Memory, Inc. or others. Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of the customer's equipment shall be done under the full responsibility of the customer. Elpida Memory, Inc. assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. [Product applications] Elpida Memory, Inc. makes every attempt to ensure that its products are of high quality and reliability. However, users are instructed to contact Elpida Memory's sales office before using the product in aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment, medical equipment for life support, or other such application in which especially high quality and reliability is demanded or where its failure or malfunction may directly threaten human life or cause risk of bodily injury. [Product usage] Design your application so that the product is used within the ranges and conditions guaranteed by Elpida Memory, Inc., including the maximum ratings, operating supply voltage range, heat radiation characteristics, installation conditions and other related characteristics. Elpida Memory, Inc. bears no responsibility for failure or damage when the product is used beyond the guaranteed ranges and conditions. Even within the guaranteed ranges and conditions, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the equipment incorporating Elpida Memory, Inc. products does not cause bodily injury, fire or other consequential damage due to the operation of the Elpida Memory, Inc. product. [Usage environment] This product is not designed to be resistant to electromagnetic waves or radiation. This product must be used in a non-condensing environment. If you export the products or technology described in this document that are controlled by the Foreign Exchange and Foreign Trade Law of Japan, you must follow the necessary procedures in accordance with the relevant laws and regulations of Japan. Also, if you export products/technology controlled by U.S. export control regulations, or another country's export control laws or regulations, you must follow the necessary procedures in accordance with such laws or regulations. If these products/technology are sold, leased, or transferred to a third party, or a third party is granted license to use these products, that third party must be made aware that they are responsible for compliance with the relevant laws and regulations.
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