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SX8724C
ZoomingADC for sensing data acquisition
ADVANCED COMMUNICATIONS & SENSING
DATASHEET
DESCRIPTION
The SX8724C is a data acquisition system based on Semtech's low power ZoomingADCTM technology. It directly connects most types of miniature sensors with a general purpose microcontroller. With 3 differential inputs, it can adapt to multiple sensor systems. Its digital outputs are used to bias or reset the sensing elements.
FEATURES
Up to 16-bit differential data acquisition Programmable gain: (1/12 to 1000) Sensor offset compensation up to 15 times full scale of input signal 3 differential or 6 single-ended signal inputs Programmable Resolution versus Speed versus Supply current Digital outputs to bias Sensors Internal or external voltage reference Internal time base Low-power (250 uA for 16b @ 250 S/s) Fast I2C interface with external address option, no clock stretching required
APPLICATIONS
Industrial pressure sensing Industrial temperature sensing Industrial chemical sensing Barometer Compass
ORDERING INFORMATION
DEVICE SX8724CWLTDT PACKAGE MLPQ-W-16 4x4 REEL QUANTITY 1000
- Available in tape and reel only - WEEE/RoHS compliant, Pb-Free and Halogen Free.
FUNCTIONAL BLOC DIAGRAM
SX8724C
-
VBATT
VREF
+ -
+ -
AC0 AC1
AC2 AC3 AC4 AC5 AC6 AC7
SIGNAL MUX
REF MUX
+
ZoomingADC
TM
PGA
ADC
READY
MCU
CONTROL LOGIC
D0 D1 D2 D3 VPUMP VSS
GPIO
CHARGE PUMP
4MHz OSC
I2C
SCL SDA
Revision 1.01 (c) Semtech
January 2011
Page 1
www.semtech.com/products/
SX8724C
ZoomingADC for sensing data acquisition
ADVANCED COMMUNICATIONS & SENSING
DATASHEET
TABLE OF CONTENT
Section Page
ELECTRICAL SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1 2 2.1 2.1.1 2.1.2 2.1.3 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Timing Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 POR Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 I2C interface timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 I2C timing Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
CIRCUIT DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3 4 5 6 6.1 6.2 6.3 6.3.1 6.4 6.5 6.5.1 7 7.1 7.1.1 7.1.2 7.1.3 7.2 7.3 7.4 7.5 7.6 7.6.1 7.7 7.7.1 7.7.2 7.7.3 7.7.4 7.7.5 7.7.6 7.7.7 7.7.8 7.7.9 8 8.1 8.2 9 9.1 9.2 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Marking Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bloc diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VREF. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GPIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Optional Operating Mode: External Vref . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Charge Pump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RC Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Wake-up from sleep. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ZoomingADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Acquisition Chain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Programmable Gain Amplifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PGA & ADC Enabling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ZoomingADC Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input Multiplexers (AMUX and VMUX) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . First Stage Programmable Gain Amplifier (PGA1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Second Stage Programmable Gain Amplifier (PGA2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Third Stage Programmable Gain Amplifier (PGA3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PGA Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Analog-to-Digital Converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Conversion Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Over-Sampling Frequency (fs). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Over-Sampling Ratio (OSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Number of Elementary Conversions (Nelconv) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Resolution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Conversion Time & Throughput . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Continuous-Time vs. On-Request Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Output Code Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Saving Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Application hints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Reduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Gain Configuration Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I2C Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . General Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Other Slave Address Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
January 2011 Page 2
12 12 13 14 14 14 14 16 17 17 17 18 18 18 19 20 20 21 22 23 23 25 28 28 29 29 29 30 31 32 33 35 36 36 37 38 38 38
Revision 1.01 (c) Semtech
www.semtech.com/products/
SX8724C
ZoomingADC for sensing data acquisition
ADVANCED COMMUNICATIONS & SENSING
DATASHEET
TABLE OF CONTENT
Section 9.2.1 9.3 9.4 9.4.1 9.4.2 9.4.3 9.4.4 10 10.1 10.2 10.2.1 10.2.2 10.2.3 10.2.4 11 11.1 11.1.1 11.2 11.3 11.3.1 11.3.2 11.4 11.5 11.6 Address Set Externally . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I2C General Call Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I2C Register Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Writing a Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reading in a Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Writing in Several Consecutive Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reading from Several Consecutive Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Register Memory Map and Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Register Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Registers Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RC Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GPIO Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ZADC Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Mode Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Typical Performances. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input impedance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Switched Capacitor Principle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Frequency Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Linearity. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Integral Non-Linearity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Differential Non-Linearity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Gain Error and Offset Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page 39 39 40 40 40 40 41 42 42 42 43 43 44 46 47 47 48 49 50 50 54 54 57 58
FAMILY OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
12 13 Comparizon table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Comparizon by package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
14 15 16 17 18 PCB Layout Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . How to Evaluate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Package Outline Drawing: MLPQ-W16-4x4-EP1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Land Pattern Drawing: 4x4MLPQ-W16-EP1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tape and Reel Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 63 64 65 66
Revision 1.01 (c) Semtech
January 2011
Page 3
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SX8724C
ZoomingADC for sensing data acquisition
ADVANCED COMMUNICATIONS & SENSING
DATASHEET
ELECTRICAL SPECIFICATIONS
1 Absolute Maximum Ratings
Note
The Absolute Maximum Ratings, in table below, are stress ratings only. Functional operation of the device at conditions other than those indicated in the Operating Conditions sections of this specification is not implied. Exposure to the absolute maximum ratings, where different to the operating conditions, for an extended period may reduce the reliability or useful lifetime of the product.
Table 1.
Parameter Power supply
Absolute Maximum Ratings
Symbol VBATT TSTORE TBIAS VINABS TPKG ESDHBM Human Body Model ESD 2000 100 All inputs Condition Min VSS - 0.3 -55 -40 VSS - 300 Max 6.5 150 140 VBATT + 300 260 Units V C C mV C V mA
Storage temperature Temperature under bias Input voltage Peak reflow temperature ESD conditions Latchup
Revision 1.01 (c) Semtech
January 2011
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SX8724C
ZoomingADC for sensing data acquisition
ADVANCED COMMUNICATIONS & SENSING
DATASHEET
2 Operating Conditions
Unless otherwise specified: VREF,ADC = VBATT, VIN = 0V, Over-sampling frequency fS = 250 kHz, PGA3 on with Gain = 1, PGA1&PGA2 off, offsets GDOff2 = GDOff3 = 0. Power operation: normal (IbAmpAdc[1:0] = IbAmpPga[1:0] = '01'). For resolution n = 12 bits: OSR = 32 and NELCONV = 4. For resolution n = 16 bits: OSR = 256 and NELCONV = 2. Bandgap chopped at NELCONV rate. If VBATT < 4.2V, Charge Pump is forced on. If VBATT > 4.2V, Charge Pump is forced off. Table 2.
Parameter Power supply Operating temperature
.
Operating conditions limits
Symbol VBATT TOP Comment/Condition Min 2.4 -40 Typ Max 5.5 125 Unit V C
Table 3.
Parameter
Electrical Characteristics
Symbol Comment/Condition Min Typ Max Unit
CURRENT CONSUMPTION1 16 b @ 250 Sample/s ADC, fs = 125 kHz Active current, 5.5V IOP55 16 b @ 1kSample/s PGA3 + ADC, fs = 500 kHz 16 b + gain 1000 @ 1kSample/s PGA3,2,1 + ADC, fs = 500 kHz 16 b @ 250 Sample/s ADC, fs = 125 kHz Active current, 3.3V IOP33 16 b @ 1 kSample/s PGA3 + ADC, fs = 500 kHz 16 b + gain 1000 @ 1kSample/s PGA3,2,1 + ADC, fs = 500 kHz @25C Sleep current ISLEEP up to 85C @125C TIME BASE Max ADC Over-Sampling frequency ADC Over-Sampling frequency drift DIGITAL I/O Input logic high Input logic low Output logic high Output logic low SCL and SDA I/O Input logic high VIH 0.7 VBATT VIH VIL VOH VOL IOH < 4 mA IOL < 4 mA 0.4 0.7 0.3 VBATT-0.4 VBATT VBATT V V fSmax fST @25C 425 500 0.15 575 kHz % / C 250 700 1000 150 300 850 75 100 150 200 nA A 350 900 1350 A
Revision 1.01 (c) Semtech
January 2011
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SX8724C
ZoomingADC for sensing data acquisition
ADVANCED COMMUNICATIONS & SENSING
Table 3.
Parameter Input logic low Leakages currents Input leakage current VREF: Internal Bandgap Reference Absolute output voltage Variation over Temperature Total Output Noise 1. VBG VBGT VBGN VBATT > 3V VBATT > 3V, over Temperature VBATT > 3V 1.19 -1.5 1.22 ILeakIn Digital input mode, no pull-up or pull-down -100
DATASHEET
Min Typ Max 0.25 Unit VBATT
Electrical Characteristics
Symbol VIL Comment/Condition
100
nA
1.25 +1.5 1
V % mVrms
The device can be operated in either active or sleep states. The Sleep state is complete shutdown, but the active state can have a variety of different current consumptions depending on the settings. Some examples are given here: The Sleep state is the default state after power-on-reset. The chip can then be placed into an active state after a valid I2C communication is received.
Table 4.
Parameter
ZoomingADC Specifications
Symbol Condition Min Typ Max Unit
ANALOG INPUT CHARACTERISTICS Gain=1, OSR=32, VREF=5V. Note 1 Differential Input Voltage Range VIN = VINP-VINN PROGRAMMABLE GAIN AMPLIFIER Total PGA Gain PGA1 Gain PGA2 Gain PGA3 Gain Gain Settings Precision (each stage) Gain Temperature Dependance PGA2 Offset PGA3 Offset Offset Settings Precision (PGA2 or PGA3) Offset Temperature Dependance Input Impedance on PGA1 (see section 11.1, page 47) Input Impedance on PGA2,3 Output RMS Noise per over-sample Gain = 1. Note 3 Gain = 10. Note 3 Gain = 1. Note 3 PGA1. Note 4 PGA2. Note 4 PGA3. Note 4 1200 250 150 GDOFF2 GDOFF3 Step = 0.2 V/V (see Table 12, page 23) Step = 1/12 V/V (see Table 13, page 23) Note 2 -1 -63/12 -3
0.5 5
-2.42 -24.2 -2.42
+2.42 +24.2 +2.42
V mV mV
Gain=100, OSR=32, VREF=5V Gain=1000, OSR=32, VREF=5V
GDTOT GD1 GD2 GD3
Note 1 (see Table 11, page 22) (see Table 12, page 23) Step = 1/12 V/V (see Table 13, page 23) Gain 1
1/12 1 1 1/12 -3
0.5 5
1000 10 10 127/12 +3
V/V V/V V/V V/V % ppm / C
+1 +63/12 +3
V/V V/V % ppm / C k k k V V V
1350 300 200 205 340 365
Revision 1.01 (c) Semtech
January 2011
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SX8724C
ZoomingADC for sensing data acquisition
ADVANCED COMMUNICATIONS & SENSING
Table 4.
Parameter ADC STATIC PERFORMANCES Resolution (No Missing Codes) Gain Error Offset Error Integral Non-Linearity Differential Non-Linearity Power Supply Rejection Ratio DC ADC DYNAMIC PERFORMANCES Conversion Time TCONV n = 12 bits. Note 12 n = 16 bits. Note 12 n = 12 bits, fs = 250 kHz Throughput Rate (Continuous Mode) PGA Stabilization Delay ZADC ANALOG QUIESCENT CURRENT ADC Only Consumption PGA1 Consumption PGA2 Consumption PGA3 Consumption IQ VBATT = 5.5V/3.3V VBATT = 5.5V/3.3V VBATT = 5.5V/3.3V VBATT = 5.5V/3.3V 285/210 104/80 67/59 98/91 1/TCONV n = 16 bits, fs = 250 kHz Note 13 (see Table 12, page 23) 133 517 1.88 0.483 OSR INL DNL PSRR n Note 5 Note 6 Note 7 n = 16 bits. Note 8 resolution n = 12 bits. Note 9 resolution n = 16 bits. Note 9 resolution n = 12 bits. Note 10 resolution n = 16 bits. Note 10 VBATT = 5V +/- 0.3V. Note 11 VBATT = 3V +/- 0.3V. Note 11 6
0.15 1 0.6 1.5 0.5 0.5
DATASHEET
Min Typ Max Unit
ZoomingADC Specifications
Symbol Condition
16
Bits % LSB LSB LSB LSB LSB dB dB
78 72
fs cycles fs cycles kSps kSps fs cycles
A A A A
ANALOG POWER DISSIPATION : All PGAs & ADC Active Normal Power Mode 3/4 Power Reduction Mode 1/2 Power Reduction Mode 1/4 Power Reduction Mode (1) (2) (3) (4) (5) (6) (7) (8) (9) (10) (11) VBATT = 5.5V/3.3V. Note 14 VBATT = 5.5V/3.3V. Note 15 VBATT = 5.5V/3.3V. Note 16 VBATT = 5.5V/3.3V. Note 17 4.0/2.0 3.2/1.6 2.4/1.1 1.5/0.7 mW mW mW mW
Gain defined as overall PGA gain GDTOT = GD1 x GD2 x GD3. Maximum input voltage is given by: VIN,MAX = (VREF / 2) (OSR / OSR+1). Offset due to tolerance on GDoff2 or GDoff3 setting. For small intrinsic offset, use only ADC and PGA1. Measured with block connected to inputs through Amux block. Normalized input sampling frequency for input impedance is fS = 500 kHz (fS max, worst case). This figure must be multiplied by 2 for fS = 250 kHz, 4 for fS = 125 kHz. Input impedance is proportional to 1/fS. Figure independent from gain and sampling frequency. fS. The effective output noise is reduced by the over-sampling ratio Resolution is given by n = 2 log2(OSR) + log2(NELCONV). OSR can be set between 8 and 1024, in powers of 2. NELCONV can be set to 1, 2, 4 or 8. If a ramp signal is applied to the input, all digital codes appear in the resulting ADC output data. Gain error is defined as the amount of deviation between the ideal (theoretical) transfer function and the measured transfer function (with the offset error removed). Offset error is defined as the output code error for a zero volt input (ideally, output code = 0). For 1 LSB offset, NELCONV must be at least 2. INL defined as the deviation of the DC transfer curve of each individual code from the best-fit straight line. This specification holds over the full scale. DNL is defined as the difference (in LSB) between the ideal (1 LSB) and measured code transitions for successive codes. Values for Gain = 1. PSRR is defined as the amount of change in the ADC output value as the power supply voltage changes.
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(12) (13)
DATASHEET
(14) (15) (16) (17)
Conversion time is given by: TCONV = (NELCONV (OSR + 1) + 1) / fS. OSR can be set between 8 and 1024, in powers of 2. NELCONV can be set to 1, 2, 4 or 8. PGAs are reset after each writing operation to registers RegACCfg1-5, corresponding to change of configuration or input switching. The ADC should be started only some delay after a change of PGA configuration through these registers. Delay between change of configuration of PGA or input channel switching and ADC start should be equivalent to OSR (between 8 and 1024) number of cycles. This is done by writing bit Start several cycles after PGA settings modification or channel switching. This delay does not apply to conversions made without the PGAs. Nominal (maximum) bias currents in PGAs and ADC, i.e. IbAmpPga[1:0] = '11' and IbAmpAdc[1:0] = '11'. Bias currents in PGAs and ADC set to 3/4 of nominal values, i.e. IbAmpPga[1:0] = '10', IbAmpAdc[1:0] = '10'. Bias currents in PGAs and ADC set to 1/2 of nominal values, i.e. IbAmpPga[1:0] = '01', IbAmpAdc[1:0] = '01'. Bias currents in PGAs and ADC set to 1/4 of nominal values, i.e. IbAmpPga[1:0] = '00', IbAmpAdc[1:0] = '00'.
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ADVANCED COMMUNICATIONS & SENSING 2.1 Timing Characteristics
Table 5.
Parameter
DATASHEET
General timings
Symbol Comment/Condition Min Typ Max Unit
ADC INTERRUPT (READY) TIMING SPECIFICATIONS READY pulse width STARTUP TIMES Startup sequence time at POR Time to enable RC from Sleep after an I2C command (1) tSTART tRCEN 800 450 s s tIRQ Note 1 1 1/fs
The READY pulse indicates End of Conversion. This is a Positive pulse of duration equal to one cycle of the ADC sampling rate in "continuous mode".
See also Figure 17, page 33.
2.1.1 POR Waveforms
At device power-on or after a software reset
I2C com
STARTUP SEQUENCE
Self calibration
SLEEP
WAKE-UP SEQUENCE
POR
RC enabling
RC disabling
RC enabling
tPOR
tRCEN
tRCEN
RC stop
Figure 1. Power-On-Reset waveform
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2.1.2 I2C interface timings
Table 6.
Parameter I2C TIMING SPECIFICATIONS Note 1 SCL clock frequency SCL timeout ( optional mode ) Note 2 SCL Low Pulsewidth SCL High Pulsewidth Start Condition Hold Time Data Setup Time Data Hold Time Setup Time for Repeated Start Stop Condition Setup Time Bus Free Time between a STOP Condition and a START Condition Pulsewidth of Spike Suppressed Capacitive load for each bus line Noise margin at the LOW level for each connected device (including hysteresis) Noise margin at the HIGH level for each connected device (including hysteresis) (1) (2) (3) (4) (5) fSCL tSCLTO tL tH tSCH tDS tDH tRSU tPSU tBF tSUP CB VnL 0.1VBATT 0 35 4.7 4.0 0.6 250 0 Note 4 4.7 4.0 4.7 100 400 0.1VBATT 3.45 100 0 35 1.3 0.6 0.6 100 Note 3 0 0.6 0.6 1.3 100
DATASHEET
Digital interface
STANDARD-MODE Symbol Min Typ Max Min Typ Max FAST-MODE Unit
400
kHz ms s s s ns
0.9
s s s s ns
400
pF V
VnH
0.2VBATT
0.2VBATT
V
All timings specifications are referred to VILmin and VIHmax voltage levels defined for the SCL and SDA pins. The digital interface is reset if the SCL is low more than tSCLTO duration. This is the default mode at startup. The timeout can be disabled by register setting. A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system. The device internally provides a hold time of at least 300 ns for the SDA signal (referred to the VIHmin of the SCL signal) to bridge the undefined region of the falling edge of SCL. Cb = total capacitance of one bus line in pF. If mixed with Hs-mode devices, faster fall-times according to Table 6 are allowed.
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2.1.3 I2C timing Waveforms
DATASHEET
tPSU SCL tBF
tSCH
tDS 1
tDH 2-7 tL
tH 8
tDS 9
tDH tRSU
tR 1
tF
SDA
MSB
LSB tSUP
ACK
MSB tR RepStart tF
Stop
Start
Figure 2. Definition of timing for F/S-mode on the I2C-bus.
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DATASHEET
CIRCUIT DESCRIPTION
3 Pin Configuration
VPUMP SDA 13 12 11 10 9 5 AC5 6 VBATT 7 VSS 8 READY D0 D2 D3 D1 AC2 SCL 14
16 AC3 AC6 AC7 AC4 1 2 3 4
15
SX8724C (Top view)
4 Marking Information
8724C YYWW XXXXX XXXXX
nnnnn yyww xxxxx xxxxx
= Part Number = Date Code1 = Semtech Lot Number
1.Date codes and Lot numbers starting with the `E' character are used for Engineering samples
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DATASHEET
5 Pin Description
Note
The bottom pin is internally connected to VSS. It should also be connected to VSS on PCB to reduce noise and improve thermal behavior.
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
Name AC3 AC6 AC7 AC4 AC5 VBATT VSS READY D1 D3 D2 D0 SDA SCL VPUMP AC2
Type Analog Input Analog Input Analog Input Analog Input Analog Input Power Input Power Input Digital Output Digital IO + analog input Digital IO Digital IO Digital IO + analog output Digital IO Digital IO Power IO Analog Input
Function Differential sensor input in conjunction with AC2 Differential sensor input in conjunction with AC7 Differential sensor input in conjunction with AC6 Differential sensor input in conjunction with AC5 Differential sensor input in conjunction with AC4 2.4V to 5.5V power supply Chip ground Conversion complete flag. Digital output sensor drive (VBATT or VSS) VREF input in optional operating mode I2C address bit 1. Msb address bits are fuse programmed. Digital output sensor drive (VBATT or VSS) Digital output sensor drive (VBATT or VSS) Digital output sensor drive (VBATT or VSS) VREF output in optional operating mode I2C address bit 0. MSB address bits are fuse programmed. I2C data line I2C clock line. Up to 400 kHz. Charge pump output. Raises analog switch supply above VBATT if VBATT supply is too low. Recommended range for capacitor is 1nF to 10 nF. Connect the capacitor to ground. Differential sensor input in conjunction with AC3
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DATASHEET
6 General Description
The SX8724C is a complete low-power acquisition path with programmable gain, acquisition speed and resolution.
6.1 Bloc diagram
SX8724C
-
VBATT
VREF
+ -
+ -
AC0 AC1
AC2 AC3 AC4 AC5 AC6 AC7
SIGNAL MUX
REF MUX
+
ZoomingADC
TM
PGA
ADC
READY
CONTROL LOGIC
D0 D1 D2 D3 VPUMP VSS
GPIO
CHARGE PUMP
4MHz OSC
I2C
SCL SDA
Figure 3. SX8724C bloc diagram
6.2 VREF
The internally generated VREF is a trimmed bandgap reference with a nominal value of 1.22V that provides a stable voltage reference for the ZoomingADC. This reference voltage is directly connected to one of the ZoomingADC reference multiplexer inputs. The bandgap voltage stability is only guaranteed for VBATT voltages of 3V and above. As VBATT drops down to 2.4V, the bandgap voltage could reduce by up to 50mV. The bandgap has relatively weak output drive so it is recommended that if the bandgap is required as a signal input then PGA1 must be enabled with gain = 1.
6.3 GPIO
The GPIO block is a multipurpose 4 bit input/output port. In addition to digital behavior, D0 and D1 pins can be programmed as analog pins in order to be used as output (reference voltage monitoring) and input for an external
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DATASHEET
reference voltage (For further details see Figure 6, Figure 7, Figure 8 and Figure 9). Each port terminal can be individually selected as digital input or output.
RegOut[4] RegOut[0] 0 D0/VREFOUT 1 RegIn[0]
RegMode[1] Internal + Bandgap reference -
V BG
1.22V
0 1
VREF
ZoomingADC
RegMode [0]
RegOut[5] RegOut [1]
1 D1/VREFIN 0 RegIn [1]
Figure 4. GPIO bloc diagram
RegOut [6] RegOut [2] D2 RegIn [2]
RegOut [7] RegOut [3] D3 RegIn [3]
Figure 5. Digital IO bloc diagram The direction of each bit within the GPIO block (input only or input/output) can be individually set using the bits of the RegOut (address 0x40) register. If D[x]Dir = 1, both the input and output buffer are active on the corresponding GPIO block pin. If D[x]Dir= 0, the corresponding GPIO block pin is an input only and the output buffer is in high impedance. After power on reset the GPIO block pins are in input/output mode (D[x]Dir are reset to 1). The input values of GPIO block are available in RegIn (address 0x41) register (read only). Reading is always direct - there is no debounce function in the GPIO block. In case of possible noise on input signals, an external hardware filter has to be realized. The input buffer is also active when the GPIO block is defined as output and the effective value on the pin can be read back.
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DATASHEET
Data stored in the LSB bits of RegOut register are outputted at GPIO block if D[x]Dir= 1. The default values after power on reset is low (0). The digital pins are able to deliver a driving current up to 8 mA. When the bits VrefD0Out and VrefD1In in the RegMode (address 0x70) register are set to 1 the D0 and D1 pins digital behavior are automatically bypassed in order to either input or output the voltage reference signals.
6.3.1 Optional Operating Mode: External Vref
D0 and D1 are multi-functional pins with the following functions in different operating modes (see RegMode register for control settings):
0 D0/VREFOUT 1
GPIO
0 D0/VREFOUT 1
GPIO
RegMode[1] = 0 Internal + Bandgap reference -
RegMode[1] = 0 0 1
VBG
VREF
ZoomingADC
Internal + Bandgap reference -
0 1
VREF
ZoomingADC
RegMode[0] = 0
RegMode[0] = 1
1 D1/VREFIN 0
1
GPIO
D1/VREFIN
0
GPIO
Figure 6. D0 and D1 are Digital Inputs / Outputs
Figure 7. D1 is Reference Voltage Input and D0 is Digital Input / Output
0 D0/VREFOUT 1
GPIO
0 D0/VREFOUT 1
GPIO
RegMode[1] = 1 Internal + Bandgap reference -
RegMode[1] = 1 0 1
VBG
VREF
ZoomingADC
Internal + Bandgap reference -
VBG
0 1
VREF
ZoomingADC
RegMode[0] = 0
RegMode[0] = 1
1 D1/VREFIN 0
1
GPIO
D1/VREFIN
0
GPIO
Figure 8. D1 is Digital Input / Output and D0 Reference Voltage Output
Figure 9. D0 is Reference Voltage Output and D1 is Reference Voltage Input
This allows external monitoring of the internal bandgap reference or the ability to use an external reference input for the ADC, or the option to filter the internal VREF output before feeding back as VREF,ADC input. The internally generated VREF is a trimmed as ADC reference with a nominal value of 1.22V. When using an external VREF,ADC input, it may have any value between 0V and VBATT. Simply substitute the external value for 1.22 V in the ADC conversion calculations.
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ADVANCED COMMUNICATIONS & SENSING 6.4 Charge Pump
DATASHEET
This block generates a supply voltage able to power the analog switch drive levels on the chip higher than VBATT if necessary. If VBATT voltage drops below 4.2V then the block should be activated. If VBATT voltage is greater than 4.2V then VBATT may be switched straight through to the VPUMP output. If the charge pump is not activated then VPUMP = VBATT. If control input bit MultForceOff = 1 in RegMode (address 0x70) register then the charge pump is disabled and VBATT is permanently connected to VPUMP output. If control input bit MultForceOn = 1 in RegMode register then the charge pump is permanently enabled. This overrides MultForceOff bit in RegMode register. An external capacitor is required on VPUMP pin. This capacitor should be large enough to ensure that generated voltage is smooth enough to avoid affecting conversion accuracy but not so large that it gives an unacceptable settling time. A recommended value is around 2.2nF.
6.5 RC Oscillator
This block provides the master clock reference for the chip. It produces a clock at 4 MHz which is divided internally in order to generate the clock sources needed by the other blocks. The oscillator technique is a low power relaxation design and it is designed to vary as little as possible over temperature and supply voltage. This oscillator is trimmed at manufacture chip test. The RC oscillator will start up after a chip reset to allow the trimming values to be read and calibration registers and I2C address set to their default fused values. Once this has been done, the oscillator will be shut down and the chip will enter a sleep state while waiting for an I2C communication. The worst case duration from reset ( or POR ) to the sleep state is 800us.
6.5.1 Wake-up from sleep
When the device is in sleep state, the RC oscillator will start up after a communication. The start up sequence for the RC oscillator is 450us in worst case. During this time, the internal blocs using the RC can not be used: no ADC conversion can be started.
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DATASHEET
7 ZoomingADC
7.1 Overview
The ZoomingADC is a complete and versatile low-power analog front-end interface typically intended for sensing applications. In the following text the ZoomingADC will be referred as ZADC. The key features of the ZADC are: Programmable 6 to 16-bit dynamic range over-sampled ADC Flexible gain programming between 1/12 and 1000 Flexible and large range offset compensation Differential or single-ended input 2-channel differential reference inputs Power saving modes
AMUX
VSS VREF AC2 AC3 AC4 AC5 AC6 AC7
VIN Vin S
PGA1
VD1 Vin Voff PGA2
VD2 Vin Voff PGA3
VIN,ADC Vin Vref
ADC
Analog Inputs
Reference Inputs
VBATT VSS VREF VSS
VREF,ADC
VMUX
ANALOG ZOOM
Figure 10. ZADC General Functional Block Diagram The total acquisition chain consists of an input multiplexer, 3 programmable gain amplifier stages and an over sampled A/D converter. The reference voltage can be selected on two different channels. Two offset compensation amplifiers allow for a wide offset compensation range. The programmable gain and offset allow the application to zoom in on a small portion of the reference voltage defined input range.
7.1.1 Acquisition Chain
Figure 10, page 18 shows the general block diagram of the acquisition chain (AC). A control block (not shown in Figure 10) manages all communications with the I2C peripheral. The clocking is derived from the internal 4 MHz Oscillator. Analog inputs can be selected through an 8 input multiplexer, while reference input is selected between two differential channels. It should however be noted that only 7 acquisition channels (including the VREF) are available when configured as single ended since the input amplifier is always operating in differential mode with both positive and negative input selected through the multiplexer.
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DATASHEET
The core of the zooming section is made of three differential programmable amplifiers (PGA). After selection of an input and reference signals VIN and VREF,ADC combination, the input voltage is modulated and amplified through stages 1 to 3. Fine gain programming up to 1'000 V/V is possible. In addition, the last two stages provide programmable offset. Each amplifier can be bypassed if needed. The output of the cascade of PGA is directly fed to the analog-to-digital converter (ADC), which converts the signal VIN,ADC into digital. Like most ADCs intended for instrumentation or sensing applications, the ZoomingADCTM is an over-sampled converter 1. The ADC is a so-called incremental converter; with bipolar operation (the ADC accepts both positive and negative differential input voltages). In first approximation, the ADC output result relative to full-scale (FS) delivers the quantity:
OUTADC VIN , ADC FS / 2 VREF / 2
Equation 1
in two's complement (see Equation 18 and Equation 19, page 33 for details). The output code OUTADC is -FS / 2 to + FS / 2 for VIN,ADC = -VREF,ADC / 2 to + VREF,ADC / 2 respectively. As will be shown, VIN,ADC is related to input voltage VIN by the relationship:
VIN , ADC = GDTOT VIN - GDoffTOT S VREF [V ]
Equation 2
where GDTOT is the total PGA gain, GDOFFTOT is the total magnitude of PGA offset and S is the sign of the offset (see Table 9, page 21).
7.1.2 Programmable Gain Amplifiers
As seen in Figure 10, page 18, the zooming function is implemented with three programmable gain amplifiers (PGA). These are: PGA1: coarse gain tuning PGA2: medium gain and offset tuning PGA3: fine gain and offset tuning. Should be set ON for high linearity data acquisition All gain and offset settings are realized with ratios of capacitors. The user has control over each PGA activation and gain, as well as the offset of stages 2 and 3. These functions are examined hereafter.
1.
Over-sampled converters are operated with a sampling frequency fS much higher than the input signal's Nyquist rate (typically fS is 201'000 times the input signal bandwidth). The sampling frequency to throughput ratio is large (typically 10-500). These converters include digital decimation filtering. They are mainly used for high resolution, and/or low-to-medium speed applications. January 2011 Page 19
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7.1.3 PGA & ADC Enabling
DATASHEET
Depending on the application objectives, the user may enable or bypass each PGA stage. This is done according to the word Enable and the coding given in Table 7. To reduce power dissipation, the ADC can also be inactivated while idle. Table 7. ADC and PGA Enabling
Enable (RegACCfg1[3:0]) XXX0 XXX1 XX0X XX1X X0XX X1XX 0XXX 1XXX Block ADC disabled ADC enabled PGA1 disabled PGA1 enabled PGA2 disabled PGA2 enabled PGA3 disabled PGA3 enabled
7.2 ZoomingADC Registers
The system has a bank of eight 8-bit registers: six registers are used to configure the acquisition chain (RegAcCfg0 to RegAcCfg5), and two registers are used to store the output code of the analog-to-digital conversion (RegAcOutMsb & Lsb). Table 8. Periferal Registers to Configure the Acquisition Chain (AC) and to Store the Analog-to-Digital Conversion (ADC) Result
Bit position Register Name 7 RegACOutLsb RegACOutMsb RegACCfg0 Default values: RegACCfg1 Default value: RegACCfg2 Default value: RegACCfg3 Default value: RegACCfg4 Default value: RegACCfg5 Default value: Start 0, Note 2 IbAmpAdc 11, Note 7 SetFs 00, Note 10 Pga1Gain 0, Note 11 0 Busy 0, Note 16 Def 0, Note 17 SetNelconv 01, Note 3 IbAmpPga 11, Note 8 Pga2Gain 00, Note 12 Pga3Gain 0001100, Note 13 Pga3Offset 0000000, Note 15 Amux 00000, Note 18 Vmux 0, Note 19 6 5 4 3 Out[7:0] Note 1 Out[15:8] SetOsr 010, Note 4 Continuous 0, Note 5 Enable 0000, Note 9 Pga2Offset 0000, Note 14 0, Note 6 2 1 0
(r = read; w = write; rw = read & write) (1) (2) Out: (r) digital output code of the analog-to-digital converter. (MSB = Out[15]) Start: (w) setting this bit triggers a single conversion (after the current one is finished). This bit always reads back 0.
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(3) (4) (5) (6) (7) (8) (9) (10) (11) (12) (13) (14) (15) (16) (17) (18) (19)
DATASHEET
SetNelconv: (rw) sets the number of elementary conversions to 2(SetNelconv[1:0]). To compensate for offsets, the input signal is chopped between elementary conversions (1,2,4,8). SetOsr: (rw) sets the over-sampling rate (OSR) of an elementary conversion to 2(3+SetOsr[2:0]). OSR = 8, 16, 32, ..., 512, 1024. Continuous: (rw) setting this bit starts a conversion. When this bis is 1, A new conversion will automatically begin directly when the previous one is finished. Reserved IbAmpAdc: (rw) sets the bias current in the ADC to 0.25 x (1+ IbAmpAdc[1:0]) of the normal operation current (25, 50, 75 or 100% of nominal current). To be used for low-power, low-speed operation. IbAmpPga: (rw) sets the bias current in the PGAs to 0.25 x (1+IbAmpPga[1:0]) of the normal operation current (25, 50, 75 or 100% of nominal current). To be used for low-power, low-speed operation. Enable: (rw) enables the ADC modulator (bit 0) and the different stages of the PGAs (PGAi by bit i=1,2,3). PGA stages that are disabled are bypassed. SetFs: (rw) These bits set the over sampling frequency of the acquisition chain. Expressed as a fraction of the oscillator frequency, the sampling frequency is given as: 11 ' 500 kHz, 10 ' 250 kHz, 01 ' 125 kHz, 00 ' 62.5 kHz. Pga1Gain: (rw) sets the gain of the first stage: 0 ' 1, 1 ' 10. Pga2Gain: (rw) sets the gain of the second stage: 00 ' 1, 01 ' 2, 10 ' 5, 11 ' 10. Pga3Gain: (rw) sets the gain of the third stage to Pga3Gain[6:0] 1/12. Pga2Offset: (rw) sets the offset of the second stage between -1 and +1, with increments of 0.2. The MSB gives the sign (0 positive, 1 negative); amplitude is coded with the bits Pga2Offset[5:0]. Pga3Offset: (rw) sets the offset of the third stage between -5.25 and +5.25, with increments of 1/12. The MSB gives the sign (0 positive, 1 negative); amplitude is coded with the bits Pga3Offset[5:0]. Busy: (r) set to 1 if a conversion is running. Def: (w) sets all values to their defaults (PGA disabled, max speed, nominal modulator bias current, 2 elementary conversions, over-sampling rate of 32) and starts a new conversion without waiting the end of the preceding one. Amux(4:0): (rw) Amux[4] sets the mode (0 ' differential inputs, 1 ' single ended inputs with A0= common reference) Amux[3] sets the sign (0 ' straight, 1' cross) Amux[2:0] sets the channel. Vmux: (rw) sets the differential reference channel (0 ' VBATT, 1 ' VREF).
7.3 Input Multiplexers (AMUX and VMUX)
The ZoomingADC has analog inputs AC0 to AC7 and reference inputs. Let us first define the differential input voltage VIN and reference voltage VREF,ADC respectively as:
VIN = VINP -VINN
Equation 3
[V ]
VREF = VREFP - VREFN
Equation 4
[V ]
As shown in Table 9, the inputs can be configured in two ways: either as 4 differential channels (VIN1= AC1 - AC0,... , VIN4 = AC7 - AC6), or AC0 can be used as a common reference, providing 7 signal paths all referred to AC0. The control word for the analog input selection is Amux. Notice that the Amux bit 4 controls the sign of the input voltage. Table 9. Analog Input Selection
Amux (RegACCfg5[5:1]) Sign S = 1 00x00 AC1(VREF) AC0(VSS) VINP VINN Amux (RegACCfg5[5:1]) Sign S = -1 01x00 AC1(VSS) AC0(VREF) VINP VINN
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Table 9. Analog Input Selection
Amux (RegACCfg5[5:1]) Sign S = 1 00x01 00x10 00x11 10000 10001 10010 10011 10100 10101 10110 10111 AC3 AC5 AC7 AC0(VSS) AC1(VREF) AC2 AC3 AC4 AC5 AC6 AC7 AC0(VSS) AC2 AC4 AC6 VINP VINN Amux (RegACCfg5[5:1]) Sign S = -1 01x01 01x10 01x11 11000 11001 11010 11011 11100 11101 11110 11111 AC0(VSS) AC2 AC4 AC6 VINP
DATASHEET
VINN
AC3 AC5 AC7 AC0(VSS) AC1(VREF) AC2 AC3 AC4 AC5 AC6 AC7
Similarly, the reference voltage is chosen among two differential channels (VREF = VBATT-VSS, VREF = VBG-VSS or VREF = VREF,IN-VSS) as shown in Table 10. The selection bit is Vmux. The reference inputs VREFP and VREFN (common-mode) can be up to the power supply range. Table 10. Analog reference Input Selection
Vmux (RegACCfg5[0]) 0 1 1. VREFP VREF = VBATT VREF = VBG or VREF,IN1 VREFN VSS VSS
External voltage reference on D1 GPIO pin. See section 6.3 on page 14 about GPIO and "RegMode[0x70]" on page 46.
7.4 First Stage Programmable Gain Amplifier (PGA1)
The first stage can have a buffer function (unity gain) or provide a gain of 10 (see Table 11). The voltage VD1 at the output of PGA1 is:
VD1 = GD1 VIN
Equation 5
[V ]
where GD1 is the gain of PGA1 (in V/V) controlled with the Pga1Gain bit. Table 11. PGA1 gain settings
Pga1Gain bit (RegACCfg3[7]) 0 1 PGA1 gain [V/V] GD1 [V/V] 1 10
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ADVANCED COMMUNICATIONS & SENSING 7.5 Second Stage Programmable Gain Amplifier (PGA2)
DATASHEET
The second PGA has a finer gain and offset tuning capability, as shown in Table 12. The VD2 voltage at the output of PGA2 is given by:
VD 2 = GD2 VD1 - GDoff 2 S VREF
Equation 6
[V ]
where GD2 and GDOFF2 are respectively the gain and offset of PGA2 (in V/V). These are controlled with the words Pga2Gain[1:0] and Pga2Offset[3:0]. Table 12. PGA2 gain and offset settings
Pga2Gain bitfield (RegACCfg2[5:4]) 00 01 10 11 PGA2 gain [V/V] GD2 [V/V] 1 2 5 10 Pga2Offset bitfield (RegACCfg2[3:0]) 0000 0001 0010 0011 0100 0101 1000 1001 1010 1011 1100 1101 PGA2 offset GDOFF2 [V/V] 0 +0.2 +0.4 +0.6 +0.8 +1 0 -0.2 -0.4 -0.6 -0.8 -1.0
7.6 Third Stage Programmable Gain Amplifier (PGA3)
The finest gain and offset tuning is performed with the third and last PGA stage, according to the coding of Table 13. Table 13. PGA3 Gain and Offset Settings
Pga3Gain bitfield (RegACCfg3[6:0]) 0000000 0000001 ... 0000110 ... 0001100 0010000 ... 0100000 PGA3 Gain GD3 [V/V] 0 1/12 (=0.083) ... 6/12 ... 12/12 16/12 ... 32/12 Pga3Offset bitfield (RegACCfg4[6:0]) 0000000 0000001 ... 0010000 ... 0100000 ... 0111111 1000000 +16/12 ... 32/12 ... +63/12 (=+5.25) 0 PGA3 Offset GDOFF3 [V/V] 0 +1/12 (=0.083)
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Table 13. PGA3 Gain and Offset Settings
Pga3Gain bitfield (RegACCfg3[6:0]) ... 1000000 ... 1111111 PGA3 Gain GD3 [V/V] ... 64/12 ... 127/12 (=10.58) Pga3Offset bitfield (RegACCfg4[6:0]) 1000001 1000010 ... 1010000 ... 1100000 ... 1111111 PGA3 Offset GDOFF3 [V/V] -1/12 (=-0.083) -2/12 ... -16/12 ... -32/12 ... -63/12 (=-5.25)
DATASHEET
The output of PGA3 is also the input of the ADC. Thus, similarly to PGA2, we find that the voltage entering the ADC is given by:
VIN , ADC = GD3 VD 2 - GDoff 3 S VREF
Equation 7
[V ]
where GD3 and GDOFF3 are respectively the gain and offset of PGA3 (in V/V). The control words are Pga3Gain[6:0] and Pga3Offset[6:0]. To remain within the signal compliance of the PGA stages (no saturation), the condition:
VIN , VD1 , VD 2 <
Equation 8
VBATT 2
must be verified. To remain within the signal compliance of the ADC (no saturation), the condition:
V OSR - 1 VIN , ADC < REF 2 OSR
Equation 9
must be verified.
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DATASHEET
Finally, combining Equation 5 to Equation 7 for the three PGA stages, the input voltage VIN,ADC of the ADC is related to VIN by:
VIN , ADC = GDTOT VIN - GDoff TOT S VREF
Equation 10
[V ]
where the total PGA gain is defined as:
GDTOT = GD3 GD2 GD1
Equation 11
and the total PGA offset is:
GDoffTOT = GDoff 3 + GD3 GDoff 2
Equation 12
7.6.1 PGA Ranges
Figure 11 and Figure 12 illustrates the limits for the maximal conversion precision according to the common mode voltage (VCOMMON), the ADC over-sampling frequency (fs) and PGA gains. The best linearity performances can be
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obtained only below these limits, as depicted in Figure 11 if the supply voltage (VBATT) is below 4.2V and as depicted in Figure 12 if the supply voltage (VBATT) is above 4.2V.
Max gain on first active PGA
10.0 fs 62.5 or 125kHz
5.0 fs 250kHz
2.5 fs 500kHz Vcommon
VBATT-1.8V VBATT-1.2V VBATT-0.8V VBATT
Figure 11. Common mode input range on PGA for VBATT below 4.2V
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Max gain First active PGA
10.0 fs = 62.5, 125kHz or 250kHz
5.0
2.5 fs frequency 500kHz Vcommon
VBATT-2.2V VBATT-1.2V VBATT-0.8V VBATT
Figure 12. Common mode input range on PGA for VBATT above 4.2V
Max VCOMMON for gain 10 on first active PGA
5.5 V 5.0 V
4.0 V
fs 250 kHz 3.3 V
3.0 V fs 62.5 or 125kHz 2.0 V 2.4V
1.0 V
fs 500 kHz
VBATT 2.4 V 4.2 V 5.5 V
Figure 13. Common mode input range on PGA vs VBATT
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ADVANCED COMMUNICATIONS & SENSING 7.7 Analog-to-Digital Converter (ADC)
DATASHEET
The main performance characteristics of the ADC (resolution, conversion time, etc.) are determined by three programmable parameters. The setting of these parameters and the resulting performances are described later. fs : OSR : NELCONV : Over-sampling frequency Over-Sampling Ratio Number of Elementary Conversions
7.7.1 Conversion Sequence
A conversion is started each time the bit Start or the Def bit is set. As depicted in Figure 14, a complete analog-todigital conversion sequence is made of a set of NELCONV elementary incremental conversions and a final quantization step. Each elementary conversion is made of (OSR+1) over-sampling periods Ts=1/fs, i.e.:
TELCONV = (OSR + 1) / f S [s]
Equation 13
The result is the mean of the elementary conversion results. An important feature is that the elementary conversions are alternatively performed with the offset of the internal amplifiers contributing in one direction and the other to the output code. Thus, converter internal offset is eliminated if at least two elementary sequences are performed (i.e. if NELCONV >= 2). A few additional clock cycles are also required to initiate and end the conversion properly.
Init Conversion index Offset
Elementary Conversion 1 +
Elementary Conversion 2 -
Elementary Conversion NELCONV-1 +
Elementary Conversion NELCONV -
End
Conversion Result
TCONV
Figure 14. Analog-to-Digital Conversion Sequence
Note
The internal bandgap reference state may be forced High or Low, or may be set to toggle during conversion at either the same rate or half the rate of the Elementary Conversion. This may be useful to help eliminate bandgap related internal offset voltage and 1/fs noise.
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7.7.2 Over-Sampling Frequency (fs)
DATASHEET
The word SetFs[1:0] (see Table 14) is used to select the over-sampling frequency fs. The over-sampling frequency is derived from the 4MHz oscillator clock. Table 14. Sampling frequency settings
SetFs bitfield (RegACCfg2[7:6]) 00 01 10 11 Over-Sampling Frequency fs [Hz] 62.5 kHz 125 kHz 250 kHz 500 kHz
7.7.3 Over-Sampling Ratio (OSR)
The over-sampling ratio (OSR) defines the number of integration cycles per elementary conversion. Its value is set with the word SetOsr[2:0] in power of 2 steps (see Table 15) given by:
OSR = 2 3+SetOsr[2:0] [-]
Equation 14
Table 15. Over-sampling ratio settings
SetOsr[2:0] (RegACCfg[4:2]) 000 001 010 011 100 101 110 111 Over-Sampling Ratio OSR [-] 8 16 32 64 128 256 512 1024
7.7.4 Number of Elementary Conversions (Nelconv)
As mentioned previously, the whole conversion sequence is made of a set of NELCONV elementary incremental conversions. This number is set with the word SetNelconv[1:0] in power of 2 steps (see Table 16) given by:
N ELCONV = 2 SetNelconv [1:0]
Equation 15
[-]
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Table 16. Number of elementary conversion
SetOsr[2:0] (RegACCfg[4:2]) 00 01 10 11 # of Elementary Conversion NELCONV [-] 1 2 4 8
As already mentioned, NELCONV must be equal or greater than 2 to reduce internal amplifier offsets.
7.7.5 Resolution
The theoretical resolution of the ADC, without considering thermal noise, is given by:
n = 2 log2 (OSR) + log2 ( N ELCONV ) [bit]
Equation 16
16.0 Resolution - n[bits] 14.0 12.0 10.0 8.0 6.0 4.0 000 SetNelconv[1:0] 11 10 01 00
001
010
011
100
101
110
111
SetOsr[2:0]
Figure 15. Resolution vs. SetOsr[2:0] and SetNelconv[2:0] Using look-up Table 17 or the graph plotted in Figure 15, resolution can be set between 6 and 16 bits. Notice that, because of 16-bit register use for the ADC output, practical resolution is limited to 16 bits, i.e. n = 16. Even if the
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resolution is truncated to 16 bit by the output register size, it may make sense to set OSR and NELCONV to higher values in order to reduce the influence of the thermal noise in the PGA . Table 17. Resolution1 vs. SetOsr and SetNelconv settings
SetOsr control bits `000` `001` `010` `011` `100` `101` `110` `111` 1. SetNelconv control bits `00` 6 8 10 12 14 16 16 16 `01` 7 9 11 13 15 16 16 16 `10` 8 10 12 14 16 16 16 16 `11' 9 11 13 15 16 16 16 16
In shaded area, the resolution is truncated to 16 bits due to output register size RegACOut[15:0]
7.7.6 Conversion Time & Throughput
As explained in Figure 15, conversion time is given by:
TCONV = ( NELCONV (OSR+ 1) + 1) / f S [s]
Equation 17
and throughput is then simply 1/TCONV. For example, consider an over-sampling ratio of 256, 2 elementary conversions, and a sampling frequency of 500 kHz (SetOsr = "101", SetNelconv = "01" and SetFs = "00"). In this case, using Table 18, the conversion time is 515 sampling periods, or 1.03ms. This corresponds to a throughput of 971Hz in continuous-time mode. The plot of Figure 16 illustrates the classic trade-off between resolution and conversion time. Table 18. Normalized conversion time (Tconv x fs) vs. SetOsr and SetNelconv settings1
SetOsr bits OSR SetNelconv control bits NELCONV `00` 1 10 18 34 66 `01` 2 19 35 67 131 `10` 4 37 69 133 261 `11` 8 73 137 265 521
`000` `001` `010` `011`
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Table 18. Normalized conversion time (Tconv x fs) vs. SetOsr and SetNelconv settings1
SetOsr bits OSR SetNelconv control bits NELCONV `00` 1 130 258 514 1026 `01` 2 259 515 1027 2051 `10` 4 517 1029 2053 4101 `11` 8 1033 2057 4105 8201
`100` `101` `110` `111` 1.
Normalized to sampling period 1/fs
16.0 Resolution - n[bits] 14.0 12.0 10.0 8.0 6.0 4.0 10 01 00 100 1000 10000 11 10
Normalized Conversion Time - Tconv / fs [-]
Figure 16. Resolution vs. normalized1 conversion time for different SetNelconv[1:0]
1. Normalized Conversion Time - TCONV/fs
7.7.7 Continuous-Time vs. On-Request Conversion
The ADC can be operated in two distinct modes: "continuous-time" and "on-request" modes (selected using the bit Continuous).
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DATASHEET
In "continuous-time" mode, the input signal is repeatedly converted into digital. After a conversion is finished, a new one is automatically initiated. The new value is then written in the result register, and the corresponding internal trigger pulse is generated. This operation is sketched in Figure 17. The conversion time in this case is defined as TCONV.
Tconv Internal trig
Output code RegACOut[15:0]
Busy 1/fs
Ready
Figure 17. ADC "Continuous-Time" Operation In the "on-request" mode, the internal behavior of the converter is the same as in the "continuous-time" mode, but the conversion is initiated on user request (with the Start bit). As shown in Figure 18, the conversion time is also TCONV.
Tconv Internal trig
START Request
Output code RegACOut[15:0]
Busy
Ready
Figure 18. ADC "On-Request" Operation
7.7.8 Output Code Format
The ADC output code is a 16-bit word in two's complement format (see Table 19). For input voltages outside the range, the output code is saturated to the closest full-scale value (i.e. 0x7FFF or 0x8000). For resolutions smaller than 16 bits, the non-significant bits are forced to the values shown in Table 20. The output code, expressed in LSBs, corresponds to:
OUT ADC = 2 16
V IN , ADC V REF
OSR + 1 OSR
Equation 18
Recalling Equation 10, page 25, this can be rewritten as:
OUTADC = 216
VIN VREF
V GDTOT - GDoff TOT S REF VIN
Equation 19
OSR + 1 [ LSB ] OSR
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where, from Equation 11 and Equation 12, the total PGA gain and offset are respectively:
DATASHEET
GDTOT = GD3 GD2 GD1
Equation 20
and:
GDoffTOT = GDoff 3 + GD3 GDoff 2
Equation 21
Table 19. Basic ADC Relationships (example for: VREF = 5V, OSR = 512, n = 16bits)
ADC Input Voltage VIN,ADC +2.49505 V +2.49497 V ... +76.145 V 0 -76.145 V ... -2.49505 V -2.49513 V % of Full Scale (FS) +0.5 x FS ... ... ... 0 ... ... ... -0.5 x FS Output in LSBs +215-1 = 32'767 +215-2 = 32'766 ... +1 0 -1 ... -2 -1 = -32'767 -215 = -32'768
15
Hexadecimal Output Code 7FFF 7FFE ... 0001 0000 FFFF ... 8001 8000
Table 20. Last forced LSBs in conversion output register for resolution settings smaller than 16bits1
SetOsr[2:0] `000' `001' `010' `011' `100' `101' `110' `111' 1. SetNelconv = `00' 1000000000 10000000 100000 1000 10 SetNelconv = `01' 100000000 1000000 10000 100 1 SetNelconv = `10' 10000000 100000 1000 10 SetNelconv = `11' 1000000 10000 100 1 -
(n<16) (RegACOutMsb[7:0] & RegACOutLsb[7:0])
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The equivalent LSB size at the input of the PGA chain is:
DATASHEET
LSB =
OSR 1 V REF [V / V ] n 2 GDTOT OSR + 1
Equation 22
Notice that the input voltage VIN,ADC of the ADC must satisfy the condition:
VIN , ADC
1 OSR (VREFP - VREFN ) 2 OSR + 1
Equation 23
to remain within the ADC input range.
7.7.9 Power Saving Modes
During low-speed operation, the bias current in the PGAs and ADC can be programmed to save power using the control words IbAmpPga[1:0] and IbAmpAdc[1:0] (see Table 21). If the system is idle, the PGAs and ADC can even be disabled, thus, reducing power consumption to its minimum. This can considerably improve battery lifetime. Table 21. ADC & PGA power saving modes and maximum sampling frequency
IbAmpAdc [1:0] 00 01 11 00 01 11 IbAmpPga [1:0] ADC Bias Current PGA Bias Current 1/4 x IADC 1/2 x IADC IADC 1/4 x IPGA 1/2 x IPGA IPGA Max. fs [kHz] 125 250 500 125 250 500
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8 Application hints
8.1 Power Reduction
The ZoomingADC is particularly well suited for low-power applications. When very low power consumption is of primary concern, such as in battery operated systems, several parameters can be used to reduce power consumption as follows: Operate the acquisition chain with a reduced supply voltage VBATT. Disable the PGAs which are not used during analog-to-digital conversion with Enable[3:0]. Disable all PGAs and the ADC when the system is idle and no conversion is performed. Use lower bias currents in the PGAs and the ADC using the control words IbAmpPga[1:0] and IbAmpAdc[1:0]. Reduce sampling frequency. Finally, remember that power reduction is typically traded off with reduced linearity, larger noise and slower maximum sampling speed.
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ADVANCED COMMUNICATIONS & SENSING 8.2 Gain Configuration Flow
The diagram below shows the flow to set the gain of your configuration:
DATASHEET
Set gain
Gain < 10 ?
No
Gain < 100 ?
No
Enable PGA1,2&3
Yes
Yes
Enable PGA3
Enable PGA2&3
Set PGA 1 gain
Set PGA 3 gain
Set PGA 2 gain
Set PGA 2 gain
Set PGA 3 gain
Set PGA 3 gain
GAIN = PGA3
GAIN = PGA2 x PGA3
GAIN = PGA1 x PGA2 x PGA3
End
Figure 19. Gain configuration flowchart
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9 I2C Interface
The I2C interface gives access to the chip registers. It complies with the I2C protocol specifications, restricted to the slave side of the communication. The device uses a Generic Fast-Mode (400 KHz) I2C Slave Interface in accordance with the I2C bus standard. Its characteristics can be summarized as follows:
9.1 General Features
Slave only operation Fast mode operation (up to 400 kHz) Combined read and write mode support General call reset support 7-bits default slave address 0x48. Can be changed by fuse and by pinout (D0 and D1). The interface handles I2C communication at the transaction level. A read transaction is an external request to get the content of system memory location and a write transaction is an external request to write the content of a system memory location. The default I2C slave address is 0x48, 1001000 in binary. This is the standard part I2C slave address. Other addresses between 1000000 and 1001111 are available.
9.2 Other Slave Address Options
Slave address might be diffenciated (2 fuse-programmed bits + 2 LSBs given by 2 GPIO inputs): Address bit 3 and bit 2 (100XXxx ) can be changed in production by fuse. Other values are available by special request. Please contact Semtech Sales for more information. Otherwise, default value is "00". The last significant bits (100xxXX ) can be defined by the GPIO pin D0 and D1. This mode is not set by default at startup, it must be activated in a register with a command. Default value is "00".
Address bit:
65
4
3
2
1
0
100 XX XX
Fuse programmed Fixed Set externally (optional)
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9.2.1 Address Set Externally
Bit: Slave address: 65 4 3 2 1 0
DATASHEET
100 XX 01
Address bit[0] set to 1
D0 D1
GPIO
Address bit[1] set to 0
Figure 20. Example of I2C address set by external resistors The GPIO are set as ouput low at startup, so a resistor should be connected to the pad to avoid shortcut at startup. After startup, the master I2C can send a command (0x96 in RegExtAdd[0x43]) at the default I2C address to change I2C mode and set D0 and D1 as input address bits. If several SX87xx devices are connected on the same bus, the master MCU must send the command to each device simultaneousely using the default address. All SX87xx devices will receive the command at the same time. The master MCU must ensure that the command has been received by asking each slave device at their new address.
9.3 I2C General Call Reset
The device respond to the I2C general call address (0000000) if the eighth bit is '0'. The devices acknowledge the general call address and respond to commands in the second byte. If the second byte is 00000110 (06h), the device reset the internal registers and enter power-down mode.
S T A R T SDA M S B
DEVICE ADDRESS
W R I T E
REGISTER ADDRESS
S T O P
L S B
A C K
A C K
0x00
0x06
Figure 21. I2C General Call reset frame
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ADVANCED COMMUNICATIONS & SENSING 9.4 I2C Register Access
9.4.1 Writing a Register
S T A R T SDA M S B L S B A C K A C K A C K W R I T E
DATASHEET
DEVICE ADDRESS
REGISTER ADDRESS
REGISTER VALUE
S T O P
Figure 22. I2C timing diagram for writing to a register
9.4.2 Reading in a Register
R E S T A R T
S T A R T SDA M S B
DEVICE ADDRESS
W R I T E
REGISTER ADDRESS
DEVICE ADDRESS
R E A D
REGISTER VALUE (n)
S T O P
L S B
A C K
A C K
A C K
N O A C K
Figure 23. I2C timing diagram for reading from a register
9.4.3 Writing in Several Consecutive Registers
S T A R T SDA M S B
DEVICE ADDRESS
W R I T E
REGISTER ADDRESS
REGISTER VALUE (n)
REGISTER VALUE (n + x - 1)
REGISTER VALUE (n + x)
S T O P
L S B
A C K
A C K
A C K
A C K
A C K
Figure 24. I2C timing diagram for multiple writing to registers
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9.4.4 Reading from Several Consecutive Registers
DATASHEET
S T A R T SDA M S B
DEVICE ADDRESS
W R I T E
REGISTER ADDRESS
R E S T A R T
DEVICE ADDRESS
R E A D
REGISTER VALUE (n)
REGISTER VALUE (n+x)
S T O P
L S B
A C K
A C K
A C K
A C K
N O A C K
Figure 25. I2C timing diagram for multiple reading from a register
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10 Register Memory Map and Description
10.1 Register Map
Table 22 below describes the register/memory map that can be accessed through the I2C interface. It indicates the register name, register address and the register contents. Table 22. Register Map
Adress RC Register 0x30 RegRCen 1 RC oscillator control Register Bit Description
GPIO Registers 0x40 0x41 0x42 0x43 RegOut RegIn RegTimeout RegExtAdd 8 4 1 8 D0 to D3 pads data output and direction control D0 to D3 pads input data Enable/Disable I2C timeout Set address by external pin
ADC Registers 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 RegACOutLsb RegACOutMsb RegACCfg0 RegACCfg1 RegACCfg2 RegACCfg3 RegACCfg4 RegACCfg5 8 8 7 8 8 8 7 8 LSB of ADC result MSB of ADC result ADC conversion control ADC conversion control ADC conversion control ADC conversion control ADC conversion control ADC conversion control
Mode Register 0x70 RegMode 8 Chip operating mode register
10.2 Registers Descriptions
The register descriptions are presented here in ascending order of Register Address. Some registers carry several individual data fields of various sizes; from single-bit values (e.g. flags), upwards. Some data fields are spread across multiple registers. After power on reset the registers will have the values indicated in the tables "Reset" column. Please write the "Reserved" bits with their reset values.
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10.2.1 RC Register
Table 23. RegRCen[0x30]
Bit 7:1 0 Bit Name RCEn Mode r rw Reset 0000000 1 Description Reserved Enables RC oscillator. Set 0 for low power mode.
DATASHEET
10.2.2 GPIO Registers
Table 24. RegOut[0x40]
Bit 7 Bit Name D3Dir Mode rw Reset 1 Description D3 pad direction. 1 : Output 0 : Input D2 pad direction. 1 : Output 0 : Input D1 pad direction. 1 : Output 0 : Input D0 pad direction. 1 : Output 0 : Input D3 pad output value. Only valid when D3Dir=1 D2 pad output value. Only valid when D2Dir=1 D1 pad output value. Only valid when D1Dir=1 and VrefD1In=0 D0 pad output value. Only valid when D0Dir=1 and VrefD1Out=0
6
D2Dir
rw
1
5
D1Dir
rw
1
4 3 2 1 0
D0Dir D3Out D2Out D1Out D0Out
rw rw rw rw rw
1 0 0 0 0
Table 25. RegIn[0x41]
Bit 7:4 3 2 1 0 Bit Name D3In D2In D1In D0In Mode r r r r r Reset 0000 Description Reserved D3 pad value D2 pad value D1 pad value D0 pad value
Table 26. RegTimout[0x42]
Bit 7:6 5 Bit Name Timeout Mode rw w Reset 00 0 Description Reserved 0 : Disabled 1 : Enabled
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Table 26. RegTimout[0x42]
Bit 4:0 Bit Name Mode rw Reset 00000 Description Reserved
DATASHEET
Table 27. RegExtAdd[0x43]
Bit 7:0 Bit Name ExternalRd Mode rw Reset 00000000 Description Write the 0x96 value into this register to set the two LSbits of the I2C address by external (D0 and D1).
10.2.3 ZADC Registers
Table 28. RegACOutLsb[0x50]
Bit 7:0 Name Out[7:0] Mode r Reset 00000000 Description LSB of the ADC result
Table 29. RegACOutMsb[0x51]
Bit 7:0 Name Out[15:8] Mode r Reset 00000000 Description MSB of the ADC result
Table 30. RegACCfg0[0x52]
Bit 7 6:5 4:2 1 0 Name Start SetNelconv SetOsr Continuous Mode rw rw rw rw r Reset 0 01 010 0 0 Description Starts an ADC conversion Sets the number of elementary conversion to 2SetNelconv. To compensate for offset the signal is chopped between elementary conversion. Sets the ADC over-sampling rate of an elementary conversion to 23+SetOsr. Sets the continuous ADC conversion mode Reserved
Table 31. RegACCfg1[0x53]
Bit 7:6 5:4 Name IbAmpAdc IbAmpPga Mode rw rw Reset 11 11 Description Bias current selection for the ADC Bias current selection for the PGA
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Table 31. RegACCfg1[0x53]
Bit 3 2 1 0 Enable Name Mode rw rw rw rw Reset 0 0 0 0 Description PGA3 enable PGA2 enable PGA1 enable ADC enable
DATASHEET
Table 32. RegACCfg2[0x54]
Bit 7:6 5:4 3:0 Name SetFs Pga2Gain Pga2Offset Mode rw rw rw Reset 00 00 0000 Description ADC Sampling Frequency selection PGA2 gain selection PGA2 offset selection
Table 33. RegACCfg3[0x55]
Bit 7 6:0 Name Pga1Gain Pga3Gain Mode rw rw Reset 0 0001100 Description PGA1 gain selection PGA3 gain selection
Table 34. RegACCfg4[0x56]
Bit 7 6:0 Name Pga3Offset Mode rw rw Reset 0 0000000 Description Reserved PGA3 offset selection
Table 35. RegACCfg5[0x57]
Bit 7 6 5:1 0 Name Busy Def Amux Vmux Mode r rw rw rw Reset 0 0 00000 0 Description ADC activity flag Selects ADC and PGA default configuration, starts an ADC conversion Input channel configuration selector Reference channel selector 0 : VBATT 1 : VREF
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10.2.4 Mode Registers
Table 36. RegMode[0x70]
Bit 7 6 Name Mode r r Reset 1 0 Description reserved reserved VREF chopping control. Note 1 11 : Chop at NELCONV/2 rate 10 : Chop at NELCONV rate 01 : Chop state=1 00 : Chop state=0 Force charge pump On. Takes priority. Note 2 Force charge pump Off. Note 2 Enable VREF output on D0 pin Enable external VREF on D1 pin
DATASHEET
5:4
Chopper
rw
00
3 2 1 0 (1)
MultForceOn MultForceOff VrefD0Out VrefD1In
rw rw rw rw
0 1 0 0
(2)
The chop control is to allow chopping of the internal bandgap reference. This may be useful to help eliminate bandgap related internal offset voltage and 1/f noise. The bandgap chop state may be forced High or Low, or may be set to toggle during conversion at either the same rate or half the rate of the Elementary Conversion. (See Conversion Sequence in the ZoomingADC description). The internal charge pump may be forced On when VBATT supply is below 4.2V or Off when VBATT supply is above 4.2V. Enabling the charge pump increase the current consumption. If the ADC is not being run at full rate or full accuracy then it may operate sufficiently well when VBATT is less than 4.2V and internal charge pump forced Off.
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11 Typical Performances
Note
The graphs and tables provided following this note are statistical summary based on limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range and therefore outside the warranted range.
11.1 Input impedance
The PGAs of the ZoomingADC are a switched capacitor based blocks (see Switched Capacitor Principle section). This means that it does not use resistors to fix gains, but capacitors and switches. This has important implications on the nature of the input impedance of the block. Using switched capacitors is the reason why, while a conversion is done, the input impedance on the selected channel of the PGAs is inversely proportional to the sampling frequency fs and to stage gain as given in Equation 24.
Z in
1 [ ] f s (Cg gain + Cp )
Equation 24
The input impedance observed is the input impedance of the first PGA stage that is enabled or the input impedance of the ADC if all three stages are disabled. Cg multiplied by gain is the equivalent gain capacitor and Cp is the parasitic capacitor of the first enabled stage. The values for each ZoomingADC bloc are provided in Table 37: Table 37. Capacitor values
Acquisition Chain Stage PGA1 PGA2 PGA3 ADC Gain capacitor Cg 0.45 0.54 0.735 2.4 Parasitic capacitor Cp 1.04 1.2 1.53 Units pF pF pF pF
PGA1 (with a gain of 10) and PGA2 (with a gain of 10) have each a minimum input impedance of 300 kOhm at fs = 500 kHz. PGA3 (with a gain of 10) have a minimum input impedance of 250 kOhm at fs = 500 kHz. Larger input impedance can be obtained by reducing the gain and/or by reducing the over-sampling frequency fs. Therefore, with a gain of 1 and a sampling frequency of 62.5 kHz, Zin > 10.2 MOhm for PGA1. The input impedance on channels that are not selected is very high (>10MOhm).
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11.1.1 Switched Capacitor Principle
DATASHEET
Basically, a switched capacitor is a way to emulate a resistor by using a capacitor. The capacitors are much easier to realize on CMOS technologies and they show a very good matching precision.
V1 R
V2
V1
f
f
V2
Figure 26. The Switched Capacitor Principle A resistor is characterized by the current that flows through it (positive current leaves node V1):
I=
V1 -V2 [ A] R
Equation 25
One can verify that the mean current leaving node V1 with a capacitor switched at frequency f is:
I = (V1 - V 2) f C [ A]
Equation 26
Therefore as a mean value, the switched capacitor 1/(f x C) is equivalent to a resistor. It is important to consider that this is only a mean value. If the current is not integrated (low impedance source), the impedance is infinite during the whole time but the transition. What does it mean for the ZoomingADC? If the fs clock is reduced, the mean impedance is increased. By dividing the fs clock by a factor 10, the impedance is increased by a factor 10. One can reduce the capacitor that is switched by using an amplifier set to its minimal gain. In particular if PGA1 is used with gain 1, its mean impedance is 10x bigger than when it is used with gain 10.
Sensor impedence Sensor
Current integration V1 ZoomingADC (model) f f V2 C
Node Capacitance
Figure 27. The Switched Capacitor Principle One can increase the effective impedance by increasing the electrical bandwidth of the sensor node so that the switching current is absorbed through the sensor before the switching period is over. Measuring the sensor node will
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DATASHEET
show short voltage spikes at the frequency fs, but these will not influence the measurement. Whereas if the bandwidth of the node is lower, no spikes will arise, but a small offset can be generated by the integration of the charges generated by the switched capacitors, this corresponds to the mean impedance effect.
Notes:
(1) (2) (3)
One can increase the mean input impedance of the ZoomingADC by lowering the acquisition clock fs. One can increase the mean input impedance of the ZoomingADC by decreasing the gain of the first enabled amplifier. One can increase the effective input impedance of the ZoomingADC by having a source with a high electrical bandwidth (sensor electrical bandwidth much higher than fs).
11.2 Frequency Response
The incremental ADC is an over-sampled converter with two main blocks: an analog modulator and a low-pass digital filter. The main function of the digital filter is to remove the quantization noise introduced by the modulator. This filter determines the frequency response of the transfer function between the output of the ADC and the analog input VIN. Notice that the frequency axes are normalized to one elementary conversion period OSR / fs. The plots of Figure 28, page 50 also show that the frequency response changes with the number of elementary conversions NELCONV performed. In particular, notches appear for NELCONV >= 2 These notches occur at:
f
i fs NOTCH = -----------------------------------OSR N ELCONV
For
Equation 27
i = 1, 2, ... ( N ELCONV - 1 )
and are repeated every fs / OSR. Information on the location of these notches is particularly useful when specific frequencies must be filtered out by the acquisition system. This chip has no dedicated 50/60 Hz rejection filtering but some rejection can be achieved by using Equation 27 and setting the appropriate values of OSR, fs and NELCONV. Table 38. 50/60 Hz Line Rejection Examples
Rejection [Hz] fNOTCH [Hz] 61
60
fs [kHz] 125 250 500 62.5 62.5 125
OSR [-] 1024 1024 1024 1024 1024 1024
NELCONV [-] 2 4 8 8 4 8
61 61 53
50
46 46
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Normalized Magnitude [-]
Normalized Magnitude [-]
1.2 1 0.8 0.6 0.4 0.2 0 0 0.5 1 1.5 2 2.5 3 3.5 4 Nelconv = 1
1.2 1 0.8 0.6 0.4 0.2 0 0 0.5 1 1.5 2 2.5 3 3.5 4 Nelconv = 2
Normalized Frequency - f x (OSR / fs) [-] Normalized Magnitude [-]
1.2 1 0.8 0.6 0.4 0.2 0 0 0.5 1 1.5 2 2.5 3 3.5 4 Nelconv = 4
Normalized Frequency - f x (OSR / fs) [-] Normalized Magnitude [-]
1.2 1 0.8 0.6 0.4 0.2 0 0 0.5 1 1.5 2 2.5 3 3.5 4 Nelconv = 8
Normalized Frequency - f x (OSR / fs) [-]
Normalized Frequency - f x (OSR / fs) [-]
Figure 28. Frequency Response. Normalized Magnitude vs. Frequency for Different NELCONV
11.3 Linearity
11.3.1 Integral Non-Linearity
The different PGA stages have been designed to find the best compromise between the noise performance, the integral non-linearity and the power consumption. To obtain this, the first stage has the best noise performance and the third stage the best linearity performance. For large input signals (small PGA gains, i.e. up to about 50), the noise added by the PGA is very small with respect to the input signal and the second and third stage of the PGA should be used to get the best linearity. For small input signals (large gains, i.e. above 50), the noise level in the PGA is important and the first stage of the PGA should be used. The following figures show the Integral non linearity for different gain settings over the chip temperature range
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11.3.1.1 Gain 1
DATASHEET
VBATT=5V ; VREF=VBATT; PGAs disabled; OSR=1024 ; Nelconv=8 ; fs=250kHz; Resolution=16bits.
10 8 6 4 INL [LSB] INL [LSB] 2 0 -2 -4 -6 -8 -10 -2 -1.5 -1 -0.5 0 VIN [V] 0.5 1 1.5 2
INL Gain 1 @ -40C
10 8 6 4 2 0 -2 -4 -6 -8 -10 -2
INL Gain 1 @ 25C
-1.5
-1
-0.5
0 VIN [V]
0.5
1
1.5
2
Figure 29. INL -40C
10
INL Gain 1 @ 85C
Figure 30. INL 25C
10 8 6 4 INL [LSB] 2 0 -2 -4 -6 -8 -10
INL Gain 1 @ 125C
8 6 4 INL [LSB] 2 0 -2 -4 -6 -8 -10 -2 -1.5 -1 -0.5 0 VIN [V] 0.5 1 1.5 2
-2
-1.5
-1
-0.5
0 VIN [V]
0.5
1
1.5
2
Figure 31. INL 85C
11.3.1.2 Gain 10
Figure 32. INL 125C
VBATT=5V ; VREF=VBATT; ADC and PGA3 enabled ; GD3=10; OSR=1024 ; Nelconv=8 ; fs=250kHz; Resolution=16bits.
10 8 6 4 INL [LSB] INL [LSB] 2 0 -2 -4 -6 -8 -10 -0.2
INL Gain 10 @ -40C
10
INL Gain 10 @ 25C
8 6 4 2 0 -2 -4 -6 -8 -10 -0.2
-0.15
-0.1
-0.05
0 VIN [V]
0.05
0.1
0.15
0.2
-0.15
-0.1
-0.05
0 VIN [V]
0.05
0.1
0.15
0.2
Figure 33. INL -40C
Figure 34. INL 25C
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10
INL Gain 10 @ 85C
DATASHEET
10
INL Gain 10 @ 125C
8 6 4 INL [LSB] INL [LSB] 2 0 -2 -4 -6 -8 -10 -0.2
8 6 4 2 0 -2 -4 -6 -8 -10 -0.2
-0.15
-0.1
-0.05
0 VIN [V]
0.05
0.1
0.15
0.2
-0.15
-0.1
-0.05
0 VIN [V]
0.05
0.1
0.15
0.2
Figure 35. INL 85C
11.3.1.3 Gain 100
Figure 36. INL 125C
VBATT=5V ; VREF=VBATT; ADC, PGA2 and PGA3 enabled ; GD2=10; GD3=10; OSR=1024 ; Nelconv=8 ; fs=250kHz; Resolution=16bits.
50 40 30 20 INL [LSB] INL [LSB] 10 0 -10 -20 -30 -40 -50 -0.02
INL Gain 100 @ -40C
50 40 30 20 10 0 -10 -20 -30 -40 -50 -0.02
INL Gain 100 @ 25C
-0.015
-0.01
-0.005
0 VIN [V]
0.005
0.01
0.015
0.02
-0.015
-0.01
-0.005
0 VIN [V]
0.005
0.01
0.015
0.02
Figure 37. INL -40C
50 40 30 20 INL [LSB] INL [LSB] 10 0 -10 -20 -30 -40 -50 -0.02
INL Gain 100 @ 85C
Figure 38. INL 25C
50 40 30 20 10 0 -10 -20 -30 -40 -50 -0.02
INL Gain 100 @ 125C
-0.015
-0.01
-0.005
0 VIN [V]
0.005
0.01
0.015
0.02
-0.015
-0.01
-0.005
0 VIN [V]
0.005
0.01
0.015
0.02
Figure 39. INL 85C
Figure 40. INL 125C
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11.3.1.4 Gain 1000
DATASHEET
VBATT=5V ; VREF=VBATT; ADC, PGA3, PGA2, PGA1 enabled; GD1=10, GD2=10, GD3=10; OSR=1024 ; NELCONV=8 ; fs=250KHz; Resolution=16bits.
200
INL Gain 1000 @ -40C
200
INL Gain 1000 @ 25C
150 100 50 INL [LSB] INL [LSB] 0 -50 -100 -150 -200 -0.002
150 100 50 0 -50 -100 -150 -200 -0.002
-0.0015
-0.001
-0.0005
0 VIN [V]
0.0005
0.001
0.0015
0.002
-0.0015
-0.001
-0.0005
0 VIN [V]
0.0005
0.001
0.0015
0.002
Figure 41. INL -40C
200
INL Gain 1000 @ 85C
Figure 42. INL 25C
200
INL Gain 1000 @ 125C
150 100 50 INL [LSB] 0 -50 -100 -150 -200 -0.002 INL [LSB] -0.0015 -0.001 -0.0005 0 VIN [V] 0.0005 0.001 0.0015 0.002
150 100 50 0 -50 -100 -150 -200 -0.002
-0.0015
-0.001
-0.0005
0 VIN [V]
0.0005
0.001
0.0015
0.002
Figure 43. INL 85C
Figure 44. INL 125C
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11.3.2 Differential Non-Linearity
DATASHEET
The differential non-linearity is generated by the ADC. The PGA does not add differential non-linearity. Figure 45 shows the differential non-linearity.
Figure 45. Differential Non-Linearity of the ADC Converter
11.4 Noise
Ideally, a constant input voltage VIN should result in a constant output code. However, because of circuit noise, the output code may vary for a fixed input voltage. Thus, a statistical analysis on the output code of 1200 conversions for a constant input voltage was performed to derive the equivalent noise levels of PGA1, PGA2, and PGA3. The extracted rms output noise of PGA1, 2, and 3 are given in Table 39, page 56: standard output deviation and output rms noise voltage.
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Analog Inputs
VSS VREF AC2 AC3 AC4 AC5 AC6 AC7
VIN Vin S
PGA1
VN1 Vin Voff PGA2
VN2 Vin Voff PGA3
VN3
VIN,ADC Vin Vref
ADC
Reference Inputs
VBATT VSS VREF VSS
VREFN,WB
VREF,ADC
gains: offsets:
GD1
GD2 GDOFF2
GD3 GDOFF3
Figure 46. Simple Noise Model for PGAs and ADC VN1, VN2, and VN3 are the output rms noise figures of Table 39, GD1, GD2, and GD3 are the PGA gains of stages 1 to 3 respectively. VREFN,WB is the wide band noise on the reference voltage. The simple noise model of Figure 46 is used to estimate the equivalent input referred rms noise VN,IN of the acquisition chain in the model of Figure 48, page 56. This is given by the relationship:
VN , IN
2
VN 1 VN 2 VN 3 GD + GD GD + GD 1 1 2 TOT =
2
2
VREFN ,WB (GD2 GDOFF 2 + GDOFF 3 ) 1 VREFN ,WB + + 2 GD GDTOT TOT V 2 rms (OSR N ELCONV )
2 2 2
[
]
Equation 28
On the numerator of Equation 28 : 1 the first parenthesis is the PGA1 gain amplifier contribution to noise 2 the second parenthesis is the PGA2 gain amplifier contribution to noise 3 the third parenthesis is the PGA3 gain amplifier contribution to noise 4 the fourth parenthesis is PGA2 and PGA3 offset amplifiers contributions to noise 5 the last parenthesis is the contribution of the noise on the references of the ADC
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As shown in Equation 28, noise can be reduced by increasing OSR and NELCONV (increases the ADC averaging effect, but reduces noise). Table 39. PGA Noise Measurement (n = 16bits, OSR = 512, NELCONV = 2, VREF = 5V)
Parameter Output RMS noise(uV) PGA1 VN1 = 205 PGA2 VN2 = 340 PGA3 VN3 = 365
Figure 47 shows the distribution for the ADC alone (PGA1, 2, and 3 bypassed). Quantization noise is dominant in this case, and, thus, the ADC thermal noise is below 16 bits.
80 Occurences [% of total samples]
60
40
20
0 -5 -4 -3 -2 -1 0 1 2 3 4 5 Output Code Deviation From Mean Value [LSB]
Figure 47. ADC Noise (PGA1, 2 & 3 Bypassed, OSR = 512, NELCONV = 2)
Analog Inputs
VSS VREF AC2 AC3 AC4 AC5 AC6 AC7
VN,IN
VIN Vin S
PGA1
VIN,ADC Vin Voff PGA2 Vin Voff PGA3 Vin Vref
ADC
Reference Inputs
VBATT VSS VREF VSS
VREF,ADC
Figure 48. Total Input Referred Noise As an example, consider the system where: GD2 = 10 (GD1 = 1; PGA3 bypassed), OSR = 512, NELCONV = 2, VREF = 5 V. In this case, the noise contribution VN1 of PGA1 is dominant over that of PGA2. Using Equation 28, page 55, we get: VN,IN = 6.4 V (rms) at the input of the acquisition chain, or, equivalently, 0.85 LSB at the output of the ADC. Considering 0.2 V (rms) maximum signal amplitude, the signal-to-noise ratio is 90dB.
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DATASHEET
Gain error is defined as the amount of deviation between the ideal transfer function (theoretical Equation 19, page 33) and the measured transfer function (with the offset error removed). The actual gain of the different stages can vary depending on the fabrication tolerances of the different elements. Although these tolerances are specified to a maximum of 3%, they will be most of the time around 0.5%. Moreover, the tolerances between the different stages are not correlated and the probability to get the maximal error in the same direction in all stages is very low. Finally, these gain errors can be calibrated by the software at the same time with the gain errors of the sensor for instance. Figure 49 shows gain error drift vs. temperature for different PGA gains. The curves are expressed in % of Full-Scale Range (FSR) normalized to 25C. Offset error is defined as the output code error for a zero volt input (ideally, output code = 0). The offset of the ADC and the PGA1 stage are completely suppressed if NELCONV > 1. The measured offset drift vs. temperature curves for different PGA gains are depicted in Figure 50. The output offset error, expressed in LSB for 16-bit setting, is normalized to 25C. Notice that if the ADC is used alone, the output offset error is below +/-1 LSB and has no drift.
NORMALIZED TO 25C
Output Offset Er ror [LSB]
0.2
100 80 60 40 20 0 -20 -40 -50
NORMALIZED TO 25 C
1 5 20 100
Gain Error [% of FSR]
0.1 0.0 -0.1 -0.2 -0.3 -0.4 -50 -25 0 25 50 75 1 5 20 100 100
-25
0
25
50
75
100
Temperature [C]
Temperature [C]
Figure 49. Gain Error vs. Temperature for Different Gains
Figure 50. Offset Error vs. Temperature for Different Gains
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DATASHEET
Figure 51 plots the variation of current consumption with supply voltage VBATT, as well as the distribution between the 3 PGA stages and the ADC (see Table 40, page 60). The Charge Pump is forced ON for VBATT < 4.2V and forced OFF for VBATT > 4.2V.
1'100 1'000 900 800 IDD[uA] 700 600 500 400 300 200 2 2.5 3 3.5 VBATT [V] 4 4.5 5 5.5 ADC ADC+PGA1 ADC+PGA12 ADC+PGA123
Figure 51. Current Consumption vs. Supply Voltage and PGAs
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DATASHEET
As shown in Figure 52, if lower sampling frequency is used, the current consumption can be lowered by reducing the bias currents of the PGAs and the ADC with registers IbAmpPga and IbAmpAdc. (In Figure 52, IbAmpPga/Adc = '11', '10', '00' for fs = 500, 250, 62.5 kHz respectively. The Charge Pump is forced ON for VBATT < 4.2V and forced OFF for VBATT > 4.2V.
1'100 1'000 900 800 IDD [uA] 700 600 500 400 300 200 2.0 2.5 3.0 3.5 VBATT [V] 4.0 4.5 5.0 5.5 62.5Khz, Ibias = 0.25 125Khz, Ibias = 0.25 250Khz, Ibias = 0.5 500Khz, Ibias = 1
Figure 52. Current Consumption vs Temperature and ADC Sampling Frequency
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Current consumption vs. temperature is depicted in Figure 53, showing the increase between -40 and +125C.
1300 Vbatt = 2.4v 1200 1100 1000 900 800 700 600 -40 -20 0 20 40 60 80 100 120 Temperature [C] Vbatt = 3.5v Vbatt = 5.5v
Table 40. Typical Current Distribution in Acquisition Chain (n = 16 bits, fs = 250kHz)
Supply VBATT = 2.4V VBATT = 3.5V VBATT = 5.5V ADC 207 282 338 PGA1 70 82 103 PGA2 51 61 67 PGA3 78 91 98 Total 406 516 606 uA Unit
IDD [uA]
Figure 53. Current Consumption vs Temperature and Supply Voltage
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DATASHEET
FAMILY OVERVIEW
This chapter gives an overview of similar devices based on the ZoomingADC but with different features or packages. Each part is described in it's own datasheet.
12 Comparizon table
Table 41. Family comparizon table
Part number SX8723C Package Protocol D0 D1 D2 D3 Differential input channels MLPD-W-12 4x4 I2C I2C addr, Digital IO or Vref OUT I2C addr, Digital IO or Vref IN N.A. N.A. 2 SX8724C MLPQ-16 4x4 I2C I2C addr, Digital IO or Vref OUT I2C addr, Digital IO or Vref IN Digital IO Digital IO 3 SX8725C MLPD-W-12 4x4 I2C SX8723S MLPQ-16 4x4 SPI SX8724S MLPQ-16 4x4 SPI Digital IO or Vref OUT Digital IO or Vref IN N.A. N.A. 3 SX8725S MLPQ-16 4x4 SPI Digital IO or Vref OUT Digital IO or Vref IN N.A. N.A. 1
I2C add, Digital IO Digital IO or Vref or Vref OUT OUT I2C addr, Digital IO or Vref IN N.A. N.A. 1 Digital IO or Vref OUT. N.A. N.A. 2
GPIO
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SX8724C
ZoomingADC for sensing data acquisition
ADVANCED COMMUNICATIONS & SENSING
DATASHEET
13 Comparizon by package pinout
I2C versions SPI versions
VPUMP
SCLK 14
AC2
AC4 1 AC5 2 VBATT VSS READY 3 4 5
12 11 10
AC3 AC2 VPUMP
AC3 N.C. N.C. AC4 1 2 3 4
16
15
13 12 11 10 9 D0 SDO/RDY CS D1
SX8723C (Top view)
SX8723S (Top view)
9 SCL 8 SDA 7 D0
D1 6
5 AC5
6 VBATT
7 VSS SCLK 14
VPUMP
SDA
AC2
SCL
AC2
VPUMP
16 AC3 AC6 AC7 AC4 1 2 3 4 5 AC5
15
14
13 12 11 10 9 D0 D2 D3 D1 AC3 AC6 AC7 AC4 1 2 3 4
16
15
13 12 11 10 9 D0 SDO/RDY CS D1
SX8724C (Top view)
SX8724S (Top view)
6 VBATT
7 VSS
8 READY
5 AC5
6 VBATT
7 VSS
VPUMP
SCLK 14
AC2
NC NC VBATT VSS READY
1 2 3 4 5
12 11 10
AC3 AC2 VPUMP
16 AC3 N.C. N.C. N.C. 1 2
15
13 12 11 10 9 D0 SDO/RDY CS D1
SX8725C (Top view)
SX8725S (Top view) 3 4 5 N.C. 6 VBATT 7 VSS 8 READY
9 SCL 8 SDA 7 D0
D1 6
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SDI
READY
SDI 8
READY
SDI 8
SX8724C
ZoomingADC for sensing data acquisition
ADVANCED COMMUNICATIONS & SENSING
DATASHEET
MECHANICAL
14 PCB Layout Considerations
PCB layout considerations to be taken when using the SX8724C are relatively simple to get the highest performances out of the ZoomingADC. The most important to achieve good performances out the ZoomingADC is to have a good voltage reference. The SX8724C has already an internal reference that is good enough to get the best performances with a minimal amount of external components, but, in case an external reference is needed this one must be as clean as possible in order to get the desired performance. Separating the digital from the analog lines will be also a good choice to reduce the noise induced by the digital lines. It is also advised to have separated ground planes for digital and analog signals with the shortest return path, as well as making the power supply lines as wider as possible and to have good decoupling capacitors.
15 How to Evaluate
For evaluation purposes SX8724CEVK evaluation kit can be ordered. This kit connects to any PC using a USB port. The "SX87xx Evaluation Tools" software gives the user the ability to control the SX8724C registers as well as getting the raw data from the ZoomingADC and displaying it on the "Graphical User interface". For more information please look at SEMTECH web site (http://www.semtech.com).
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SX8724C
ZoomingADC for sensing data acquisition
ADVANCED COMMUNICATIONS & SENSING
DATASHEET
16 Package Outline Drawing: MLPQ-W16-4x4-EP1
DIMENSIONS MILLIMETERS DIM MIN NOM MAX
A A1 A2 b D D1 E E1 e L N aaa bbb 0.80 0.70 0.05 0.00 (0.20) 0.25 0.30 0.35 3.90 4.00 4.10 2.55 2.70 2.80 3.90 4.00 4.10 2.55 2.70 2.80 0.65 BSC 0.30 0.40 0.50 16 0.08 0.10
A
D
B
PIN 1 INDICATOR (LASER MARK)
E
A2 A aaa C A1 D1 e/2 LxN C SEATING PLANE
E/2 E1 2 1 N e bxN D/2
NOTES: 1. 2. CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES). COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS.
bbb
CAB
Figure 54. Package Outline Drawing
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SX8724C
ZoomingADC for sensing data acquisition
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17 Land Pattern Drawing: 4x4MLPQ-W16-EP1
K DIM (C) H G Z
C G H K P X Y Z
DIMENSIONS INCHES MILLIMETERS
(.156) .122 .106 .106 .026 .016 .033 .189 (3.95) 3.10 2.70 2.70 0.65 0.40 0.85 4.80
Y X P
NOTES:
1. CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES). 2. THIS LAND PATTERN IS FOR REFERENCE PURPOSES ONLY. CONSULT YOUR MANUFACTURING GROUP TO ENSURE YOUR COMPANY'S MANUFACTURING GUIDELINES ARE MET. 3. THERMAL VIAS IN THE LAND PATTERN OF THE EXPOSED PAD SHALL BE CONNECTED TO A SYSTEM GROUND PLANE. FAILURE TO DO SO MAY COMPROMISE THE THERMAL AND/OR FUNCTIONAL PERFORMANCE OF THE DEVICE. 4. SQUARE PACKAGE - DIMENSIONS APPLY IN BOTH " X " AND " Y " DIRECTIONS.
Figure 55. Land Pattern Drawing
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SX8724C
ZoomingADC for sensing data acquisition
ADVANCED COMMUNICATIONS & SENSING
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18 Tape and Reel Specification
MLP/QFN (0.70mm - 1.00mm package thickness) Single Sprocket holes Tolerances for Ao & Bo are +/- 0.20mm Tolerances for Ko is +/- 0.10mm Tolerance for Pocket Pitch is +/- 0.10mm Tolerance for Tape width is +/-0.30mm Trailer and Leader Length are minimum required length Package Orientation and Feed Direction
MLP (square)
MLP (rectangular)
Direction of Feed
Direction of Feed
Figure 56. Direction of Feed
Figure 57. User direction of feed Table 42. Tape and reel specifications
Pkg size Tape Width (W) 12 Pocket Pitch (P) 8 carrier tape (mm) Ao Bo Ko Reel Reel Size (in) 7/13 Reel Width (mm) 12.4 Trailer Length (mm) 400 Leader Length (mm) 400 QTY per Reel 1000/3000
4x4
4.35
4.35
1.10
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SX8724C
ZoomingADC for sensing data acquisition
ADVANCED COMMUNICATIONS & SENSING
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(c) Semtech 2010 All rights reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent or other industrial or intellectual property rights. Semtech assumes no responsibility or liability whatsoever for any failure or unexpected operation resulting from misuse, neglect improper installation, repair or improper handling or unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified maximum ratings or operation outside the specified range. SEMTECH PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED OR WARRANTED TO BE SUITABLE FOR USE IN LIFESUPPORT APPLICATIONS, DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF SEMTECH PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE UNDERTAKEN SOLELY AT THE CUSTOMER'S OWN RISK. Should a customer purchase or use Semtech products for any such unauthorized application, the customer shall indemnify and hold Semtech and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs damages and attorney fees which could arise. Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners.
Contact information Semtech Corporation Advanced Communications & Sensing Products
E-mail: sales@semtech.com or acsupport@semtech.com Internet: http://www.semtech.com
USA
200 Flynn Road, Camarillo, CA 93012-8790. Tel: +1 805 498 2111 Fax: +1 805 498 3804 12F, No. 89 Sec. 5, Nanking E. Road, Taipei, 105, TWN, R.O.C. Tel: +886 2 2748 3380 Fax: +886 2 2748 3390 Semtech Ltd., Units 2 & 3, Park Court, Premier Way, Abbey Park Industrial Estate, Romsey, Hampshire, SO51 9DN. Tel: +44 (0)1794 527 600 Fax: +44 (0)1794 527 601
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