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Micrel, Inc.
PRECISION1:8LVPECLFANOUT BUFFERWITH2:1RUNTPULSE ELIMINATOR INPUT MUX
Precision Edge(R) SY89837U Precision Edge(R)
SY89837U
FEATURES
Selects between two clocks, and provides 8 precision, low skew LVPECL output copies Guaranteed AC performance over temperature and supply voltage: Wide operating frequency: 1kHz to >1.5GHz * <975psin-to-outtpd * <180pstr/tf * <40psoutput-to-outputskew Unique input isolation design minimizes crosstalk Ultra-lowjitterdesign: * <1psrmsrandomjitter * <1psrmscycle-to-cyclejitter * <10pspptotaljitter(clock) * <0.7psrmsMUXcrosstalkinducedjitter UniqueinputterminationandVTpinacceptsDC-or AC-coupledinputs(CML,PECL,LVDS) 800mVLVPECLoutputswing Powersupply+2.5V5%or+3.3V10% -40Cto+85Cindustrialtemperaturerange Availablein32-pin(5mmx5mm)MLF(R) package Precision Edge(R)
DESCRIPTION
The SY89837U is a low jitter, low skew, high-speed 1:8 fanout buffer with a unique, 2:1 differential input multiplexer (MUX) optimized for clock redundant switchover applications. Unlike standard multiplexers, the SY89837U unique 2:1 runt pulse eliminator (RPE) input MUX prevents any short cycles or "runt" pulses during switchover. In addition, a unique fail-safe input protection prevents metastable conditions when the selected input clock fails to a static DC differential voltage (differential input voltage drops below 200mV). The SY89837U distributes clock frequencies from 1kHz to 1.5GHz, guaranteed, over temperature and voltage. The differential input includes Micrel's unique, 3-pin input termination architecture that allows customers to interface to any differential signal (AC- or DC-coupled) as small as 200mV without any level shifting or termination resistor networks in the signal path. The outputs are 800mV, 100k compatible LVPECL with fast rise/fall times guaranteed to be less than 200ps. The SY89837U operates from a +2.5V 5% or +3.3V 10% supply and is guaranteed over the full industrial temperature range of -40C to +85C. The SY89837U is part of Micrel's high-speed, Precision Edge(R) product line. All support documentation can be found on Micrel's web site at: www.micrel.com.
APPLICATIONS
Redundant clock distribution Fail-safeclockprotection
Precision Edge is a registered trademark of Micrel, Inc. MicroLeadFrame and MLF are registered trademarks of Amkor Technology, Inc. M9999-060410 hbwhelp@micrel.com or (408) 955-1690
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Rev.: F
Amendment: /0
Issue Date: June 2010
Micrel, Inc.
Precision Edge(R) SY89837U
TYPICAL APPLICATIONS CIRCUIT
Figure1. SimplifiedExampleIllustratingRuntPulseEliminator(RPE) CircuitWhenPrimaryClockFails
TRUTH TABLE
Inputs IN0 0 1 X X /IN0 1 0 X X IN1 X X 0 1 /IN1 X X 1 0 SEL 0 0 1 1 Outputs Q 0 1 0 1 /Q 1 0 1 0
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PACKAGE/ORDERINGINFORMATION
Ordering Information(1)
PartNumber SY89837UMI SY89837UMITR(2) SY89837UMG(3) SY89837UMGTR(2, 3) Package Type MLF-32 MLF-32 MLF-32 MLF-32 Operating Range Industrial Industrial Industrial Industrial Package Marking SY89837U SY89837U Lead Finish Sn-Pb Sn-Pb
SY89837U with Pb-Free Pb-Free bar-line indicator NiduAu SY89837U with Pb-Free Pb-Free bar-line indicator NiduAu
32-PinMLF(R)(MLF-32)
Notes: 1. Contact factory for die availability. Dice are guaranteed at TA = 25C, DC Electricals only. 2. Tape and Reel. 3. Pb-Free package is recommended for new designs.
PIN DESCRIPTION
PinNumber 1, 3, 6, 8 2, 7 31 PinName IN0, /IN0, IN1, /IN1 VT0, VT1 SEL VCC Q0 - Q7, /Q0 - /Q7 PinFunction Differential Inputs: These input pairs are the differential signal inputs to the device. These inputs accept AC- or DC-coupled signals as small as 200mV. Each pin of a pair internally terminates to aVTpinthrough50.Pleaserefertothe"InputInterfaceApplications"sectionformoredetails. Input Termination Center-Tap: Each side of the differential input pair terminates to a VT pin. The VT0andVT1pinsprovideacenter-taptoaterminationnetworkformaximuminterfaceflexibility. See the "Input Interface Applications" section for more details. This single-ended TTL/CMOS-compatible input selects the inputs to the multiplexer. This input isinternallyconnectedtoa25kpull-upresistorandwilldefaulttoalogicHIGHstateifleftopen. Positivepowersupply.Bypasswith0.1F0.01FlowESRcapacitorsasclosetothepinsas possible. Differential Outputs: These LVPECL output pairs are the outputs of the device. They are a logic function of the IN0, IN1, and SEL inputs. Please refer to the truth table for details. Unused output pairs may be left open. Ground. Ground and exposed pad to be tied together to most negative potential of chip. Power-On Reset (POR) Initialization Capacitor. When using the multiplexer with RPE capability, this pin is tied to a capacitor to VCC. The purpose is to ensure the internal RPE logic starts up in a known state. If this pin is tied to VCC, the RPE function will be disabled and the multiplexer will function as a normal multiplexer. See "Application" section for more details. The CAP pin should never be left open. Reference Voltage: These outputs bias to VCC - 1.2V. They are used for AC-coupling inputs (IN,/IN). Connect VREF_AC directly to the VT pin. Bypass with 0.01F low ESR capacitor to VCC. See "Input Interface Applications" section. Maximum sink/source current is 1.5mA.

9,19,22,32 30, 28, 26, 24, 18, 16, 14, 12, 29, 27, 25, 23, 17, 15, 13, 11 20,21 10
GND, Exposed Pad CAP
4,5
VREF-AC0 VREF-AC1
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Precision Edge(R) SY89837U
DETAILEDFUNCTIONALDESCRIPTION
RPEMUXandFail-SafeInput The SY89837U is optimized for clock switchover applications where switching from one clock to another clock without runt pulses (short cycles) is required. It features two unique circuits: RPEandFSIFunctionality The basic operation of the RPE MUX and FSI functionality is described with the following four case descriptions. All descriptions are related to the true inputs and outputs. The primary (or selected) clock is called CLK1, the secondary (or alternate) clock is called CLK2. Due to the totally 1. Runt-Pulse Eliminator (RPE) Circuit The RPE MUX provides a "glitchless" switchover between asynchronous relation of the IN and SEL signals and an two clocks and prevents any runt pulses from occurring additional internal protection against metastability, the during the switchover transition. The design of both clock number of pulses required for the operations described in inputs is identical (i.e., the switchover sequence and cases 1 through 4 can vary within certain limits. Refer to protection is symmetrical for both input pair, IN0 or IN1. Thus, "Timing Diagrams" and "Applications" section for detailed eitherinputpairmaybedefinedastheprimaryinput).Ifnot information. required, the RPE function can be permanently disabled to Case #1 Two Normal Clocks and RPE Enabled. allow the switchover between inputs to occur immediately. In this case the frequency difference between the two For more detail on how to disable the RPE function within the running clocks IN0 and IN1 must not be greater than 1.5:1. MUX, see the "Power-On Reset (POR)" section. For example, if the IN0 clock is 500MHz, the IN1 clock must be within the range of 334MHz to 750MHz. 2. Fail-Safe Input (FSI) Circuit If the SEL input changes state to select the alternate The FSI function provides protection against a selected clock, the switchover from CLK1 to CLK2 will occur in three input pair that drops below the minimum amplitude requirement.Iftheselectedinputpairdropssufficientlybelow stages: the 200mV minimum single-ended input amplitude limit (VIN), * Stage 1: The output will continue to follow CLK1 or 400mV differentially (Vdiff_IN), the output will latch to the for a limited number of pulses. last valid clock state. * Stage 2: The output will remain LOW for a limited number of pulses of CLK2. * Stage 3: The output follows CLK2.
Figure2. TimingDiagram1
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Micrel, Inc. Case #2 Input Clock Failure: Switching from a selected clock stuck HIGH to a valid clock (RPE enabled).
Precision Edge(R) SY89837U
If CLK1 fails HIGH before the RPE MUX selects CLK2 (using the SEL pin), the switchover will occur in three stages:
* Stage 1: The output will remain HIGH for a limited number of pulses of CLK2. * Stage 2: The output will switch to LOW and then remain LOW for a limited number of falling edges of CLK2. * Stage 3: The output will follow CLK2.
Note:
Figure3. TimingDiagram2(1)
1. Output shows extended clock cycle during switchover. Pulse width for both high and low of this cycle will always be greater than 50% of the CLK2 period.
Case #3 Input Clock Failure: Switching from a selected clock stuck LOW to a valid clock (RPE enabled).
If CLK1 fails LOW before the RPE MUX selects CLK2 (using the SEL pin), the switchover will occur in two stages.
* Stage 1: The output will remain LOW for a limited number of falling edges of CLK2. * Stage 2: The output will follow CLK2.
Figure4. TimingDiagram3
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Micrel, Inc. Case #4 Input Clock Failure: Switching from the selected clock input stuck in an undetermined state to a valid clock input (RPE enabled).
Precision Edge(R) SY89837U
If CLK1 fails to an undetermined state (e.g., amplitude falls below the 200mV (VIN) minimum single-ended input limit, or 400mV differentially) before the RPE MUX selects CLK2 (using the SEL pin), the switchover to the valid clock CLK2 will occur either following Case #2 or Case #3, depending upon the last valid state at the CLK1.
Figure5. TimingDiagram4
If the selected input clock fails to a floating, static, or extremely low signal swing, including 0mV, the FSI function will eliminate any metastable condition and guarantee a stable output signal. No ringing and no undetermined state will occur at the output under these conditions.
Please note that the FSI function will not prevent duty cycle distortions or runt pulses in case of a slowly deteriorating (but still toggling) input signal. Due to the FSI function, the propagation delay will depend upon rise and fall time of the input signal and on its amplitude. Refer to "Operation Characteristics" for detailed information.
POWER-ONRESET(POR)DESCRIPTION
The SY89837U includes an internal power-on reset (POR) function to ensure the RPE logic starts-up in a known logic state once the power-supply voltage is stable. An external capacitor connected between VCC and the CAP pin (pin 10) controls the delay for the power-on reset function. Calculation of the required capacitor value is based on the time the system power supply needs to power up to a minimum of 2.3V. The time constant for the internal poweron-reset must be greater than the time required for the power supply to ramp up to a minimum of 2.3V. The following term describes this relationship: tdPS(ms) C (F ) > 12(ms/F) As an example, if the time required for the system power supply to power up past 2.3V is 12ms, the required capacitor value on pin 10 would: 12ms C (F ) > 12(ms/F)
C > 1 F
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AbsoluteMaximumRatings(1)
Supply Voltage (VCC)....................................-0.5V to +4.0V Input Volage (VIN) ............................................-0.5V to VCC LVPECL Output Current (IOUT) Continuous ............................................................................. 50mA Surge ...................................................................................... 100mA Termination Current(3) Source or sink current on VT ...................................... 100mA Lead Temperature (soldering, 20 sec.) ...................... 260C Storage Temperature (TS) ........................ -65C to +150C
Operating Ratings(2)
Supply Voltage (VCC)........................... +2.375V to +2.625V ............................................................. +3.0V to +3.6V Ambient Temperature (TA) .......................... -40C to +85C Package Thermal Resistance(4) MLF(R) (JA) Stll-Air.............................................................................. 35C/W MLF(R)(JB) Junction-to-board ........................................................ 16C/W
DC ELECTRICAL CHARACTERISTICS(5)
TA = -40C to +85C; unless noted. Symbol VCC ICC Parameter Power Supply Power Supply Current DifferentialInputResistance (IN-to-/IN) Input High Voltage (IN-to-/IN) Input Low Voltage (IN-to-/IN) Input Voltage Swing (IN-to-/IN) See Figure 1a.(6) Differential Input Voltage Swing See Figure 1b. Input Resistance (IN-to-VT) Condition 2.5V nominal 3.3V nominal No load, max. VCC Min 2.375 3.0 115 45 90 1.2 0 0.2 0.4 100 50 100 Typ Max 2.625 3.6 160 55 110 VCC VCC Units V V mA V V V V mV V V
RIN
RDIFF_IN VIH
VIL
VIN
VIH-0.2
VDIFF_IN VIN_LOS VT_IN
|IN-/IN|
Input Voltage Swing when signal is lost IN-to-VT (IN-to-/IN) Output Reference Voltage (VREF-AC)
200 1.8
VREF_AC
Notes:
VCC-1.3 VCC-1.2 VCC-1.1
1. Permanent device damage may occur if ratings in the "Absolute Maximum Ratings" section are exceeded. This is a stress rating only and functional operation is not implied for conditions other than those detailed in the operational sections of this data sheet. Exposure to absolute maximum ratings conditions for extended periods may affect device reliability. 2. The data sheet limits are not guaranteed if the device is operated beyond the operating ratings. 3. Due to the limited drive capability use for input of the same package only. 4. Package thermal resistance assumes exposed pad is soldered (or equivalent) to the devices most negative potential on the PCB. yJB uses a 4-layer qJA in still air unless otherwise stated. 5. ThecircuitisdesignedtomeettheDCspecificationsshownintheabovetableafterthermalequilibriumhasbeenestablished. 6. VIN(max.)isspecifiedwhenVTisfloating.
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Precision Edge(R) SY89837U
LVPECL OUTPUTS DC ELECTRICAL CHARACTERISTICS(7)
VCC = +2.5V 5% or +3.3V 10%; RL=50toVCC-2V; TA = -40C to +85C, unless noted. Symbol VOH VOL VOUT VDIFF_OUT Parameter Condition Output HIGH Voltage Q, /Q Output LOW Voltage Q, /Q Output Voltage Swing Q, /Q Differential Output Voltage Swing Q, /Q See Figure 1a. See Figure 1b. Min VCC-1.145 VCC-1.945 500 1100 800 1600 Typ Max VCC-0.895 VCC-1.695 Units V V mV mV
LVTTL/CMOS DC ELECTRICAL CHARACTERISTICS(7)
VCC = +2.5V 5% or +3.3V 10%; RL=50toVCC-2V; TA = -40C to +85C, unless noted. Symbol VIH VIL IIH IIL Parameter Condition Input HIGH Voltage Input LOW Voltage Input HIGH Current Input LOW Current -125 -300 Min 2.0 0.8 30 Typ Max Units V V A A
Notes: 7. ThecircuitisdesignedtomeettheDCspecificationsshownintheabovetableafterthermalequilibriumhasbeenestablished.
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Precision Edge(R) SY89837U
AC ELECTRICAL CHARACTERISTICS(8)
VCC = +2.5V 5% or +3.3V 10%; TA = -40C to +85C; unless noted. Symbol fMAX tpd Parameter Condition Maximum Operating Frequency Differential Propagation Delay IN-to-Q SEL-to-Q SEL-to-Q tpd tempco tSKEW tJITTER t r, tf Differential Propagation Delay TemperatureCoefficient Output-to-output Skew Part-to-part Skew Clock Random Jitter (RJ) Crosstalk-Induced Jitter Output Rise/Fall Time (20% to 80%) RPE enabled tr, tf (IN) = 300ps (20% to 80%), Note 9 RPE enabled, see Timing Diagram. RPE disabled (VIN = VCC/2) Note10 Note 11 Note 12 Note 13 At full output swing. 70 120 Min 1.5 525 Typ 2.0 700 975 17 1000 115 20 40 200 1 0.7 180 Max Units GHz ps cycles ps fs/C ps ps psRMS psRMS ps
Notes: 8. High-frequency AC-parameters are guaranteed by design and characterization. 9. Propagation delay is a function of rise and fall time at IN. See "Operation Characteristics" for more details. 10. Output-to-output skew is measured between two different outputs under identical transitions. 11.Part-to-partskewisdefinedfortwopartswithidenticalpowersupplyvoltagesatthesametemperatureandwithnoskewoftheedgesatthe respective inputs. 12. Random jitter is measured with a K28.7 character pattern, measured at SINGLE-ENDEDANDDIFFERENTIALSWINGS
Figure1a. SimplifiedDifferentialInputSwing
Figure1b. SimplifiedLVPECLOutputSwing
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OPERATING CHARACTERISTICS
1000 900 800 700 600 500 400 300 200 100 0
Propagation Delay Variation vs. Input Rise/Fall Time
tpd (max)
1000 900 800 700
Propagation Delay Variation vs. Input Rise/Fall Time
tpd (max)
tpd (min)
600 500 400 300
tpd (min)
V IN = 200mV 0
PK
200 100 600 0 0
V IN = 400mV
PK
100 200 300 400 500 INPUT RISE/FALL TIME (ps)
100 200 300 400 500 INPUT RISE/FALL TIME (ps)
600
1000 900 800 700 600 500 400 300 200 100 0
Propagation Delay Variation vs. Input Rise/Fall Time
tpd (max)
800 750 700
Output Swing vs. Frequency
tpd (min)
650 600 550
V IN = 800mV 0
500
PK
450 600 400 0 500 1000 1500 2000 2500 3000 FREQUENCY (MHz)
100 200 300 400 500 INPUT RISE/FALL TIME (ps)
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OPERATINGCHARACTERISTICS(CONTINUED)
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INPUT AND OUTPUT STAGES
Figure2a. SimplifiedDifferentialInputStage
Figure2b. SimplifiedLVPECLOutputStage
INPUTINTERFACEAPPLICATIONS
Option: may connect V T to VCC.
Figure3a. LVPECLInterface (DC-Coupled)
Figure3b.LVPECLInterface (AC-Coupled)
Figure3c. CMLInterface (DC-Coupled)
Figure3d. CMLInterface (AC-Coupled)
Figure3e. LVDSInterface
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LVPECLOUTPUTINTERFACEAPPLICATIONS
Figure4a. ParallelThevenin-EquivalentTermination
Figure4b. ParallelTermination(3-Resistors)
RELATED PRODUCT AND SUPPORT DOCUMENTATION
PartNumber HBW Solutions Function Note New Products and Applications MLF(R) Application DataSheetLink www.amkor.com/product/notes_papers/MLFAppNote.pdf www.micrel.com/product-info/products/solutions.shtml
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32-PINMicroLeadFrame(R)(MLF-32)
PCB Thermal Consideration for 32-Pin MLF(R) Package
Package Notes: 1. PackagemeetsLevel2MoistureSensitivityClassification. 2. All parts are dry-packaged before shipment. 3. Exposed pads must be soldered to a ground for proper thermal management.
tel + 1 (408) 944-0800 fax + 1 (408) 474-1000 web http://www.micrel.com The information furnished by Micrel in this data sheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for its use. Micrelreservestherighttochangecircuitryandspecificationsatanytimewithoutnotificationtothecustomer.
Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant into thebodyor(b)supportorsustainlife,andwhosefailuretoperformcanbereasonablyexpectedtoresultinasignificantinjurytotheuser.APurchaser's use or sale of Micrel Products for use in life support appliances, devices or systems is at Purchaser's own risk and Purchaser agrees to fully indemnify Micrel for any damages resulting from such use or sale. (c) 2005 Micrel, Incorporated. M9999-060410 hbwhelp@micrel.com or (408) 955-1690
MICREL,INC. 2180FORTUNEDRIVE SANJOSE,CA 95131 USA
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