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750 MHz to 1150 MHz Quadrature Demodulator with Fractional-N PLL and VCO ADRF6801
FEATURES
IQ demodulator with integrated fractional-N PLL LO frequency range: 750 MHz to 1150 MHz Input P1dB: 12.5 dBm Input IP3: 25 dBm Noise figure (DSB): 14.3 dB Voltage conversion gain: 5.1 dB Quadrature demodulation accuracy Phase accuracy: 0.3 Amplitude accuracy: 0.05 dB Baseband demodulation: 275 MHz, 3 dB bandwidth SPI serial interface for PLL programming 40-lead, 6 mm x 6 mm LFCSP
GENERAL DESCRIPTION
The ADRF6801 is a high dynamic range IQ demodulator with integrated PLL and VCO. The fractional-N PLL/synthesizer generates a frequency in the range of 3.0 GHz to 4.6 GHz. A divide-by-4 quadrature divider divides the output frequency of the VCO down to the required local oscillator (LO) frequency to drive the mixers in quadrature. Additionally, an output buffer can be enabled that generates an fVCO/2 signal for external use. The PLL reference input is supported from 10 MHz to 160 MHz. The phase detector output controls a charge pump whose output is integrated in an off-chip loop filter. The loop filter output is then applied to an integrated VCO. The IQ demodulator mixes the differential RF input with the complex LO derived from the quadrature divider. The differential I and Q output paths have excellent quadrature accuracy and can handle baseband signaling or complex IF up to 120 MHz. The ADRF6801 is fabricated using an advanced silicon-germanium BiCMOS process. It is available in a 40-lead, exposed-paddle, RoHS-compliant, 6 mm x 6 mm LFCSP package. Performance is specified over the -40C to +85C temperature range.
APPLICATIONS
QAM/QPSK RF/IF demodulators Cellular W-CDMA/CDMA/CDMA2000 Microwave point-to-(multi)point radios Broadband wireless and WiMAX
FUNCTIONAL BLOCK DIAGRAM
GND
35
VCCLO VCCLO
34 17
LOSEL
36
IBBP
33
IBBN GND
32 31 30 GND 29 VCCBB
BUFFER CTRL LON 37
BUFFER
ADRF6801
LOP 38 FRACTION MODULUS REG SPI INTERFACE THIRD-ORDER FRACTIONAL INTERPOLATOR N COUNTER x2 REFIN 6 GND /2
7
28 GND 27 VCCRF
GND 11 DATA 12 CLK 13 LE 14 GND 15
INTEGER REG
BUFFER
MUX
DIVIDER /1 OR /2 QUAD /2
26 RFIN
PRESCALER /2
VCO CORE
25 GNDRF 24 GND
MUX
TEMP SENSOR 3.3V LDO
- PHASE + FREQUENCY DETECTOR
/4 MUXOUT 8
1 2 10 16
CHARGE PUMP 250A, 500A (DEFAULT), 750A, 1000A
3 4 5
23 GND 22 VCCBB
2.5V LDO
9 39
VCO LDO
40 18 19 20
21 GND
09576-001
VCC1
DECL3
VCC2
GND
CPOUT GND RSET
DECL2
VTUNE
DECL1
QBBP QBBN GND
Figure 1.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
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ADRF6801 TABLE OF CONTENTS
Features .............................................................................................. 1 Applications....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 Timing Characteristics ................................................................ 5 Absolute Maximum Ratings............................................................ 6 ESD Caution.................................................................................. 6 Pin Configuration and Function Descriptions............................. 7 Typical Performance Characteristics ............................................. 9 Synthesizer/PLL .......................................................................... 12 Complementary Cumulative Distribution Functions (CCDF) ....................................................................................................... 13 Circuit Description......................................................................... 14 LO Quadrature Drive................................................................. 14 V-to-I Converter......................................................................... 14 Mixers .......................................................................................... 14 Emitter Follower Buffers ........................................................... 14 Bias Circuitry .............................................................................. 14 Register Structure....................................................................... 14 Applications Information .............................................................. 21 Basic Connections...................................................................... 21 Supply Connections ................................................................... 21 Synthesizer Connections ........................................................... 21 I/Q Output Connections ........................................................... 22 RF Input Connections ............................................................... 22 Charge Pump/VTUNE Connections ...................................... 22 LO Select Interface ..................................................................... 22 External LO Interface ................................................................ 22 Setting the Frequency of the PLL ............................................. 22 Register Programming............................................................... 22 EVM Measurements .................................................................. 23 Evaluation Board Layout and Thermal Grounding................... 24 ADRF6801 Software .................................................................. 28 Characterization Setups................................................................. 30 Outline Dimensions ....................................................................... 34 Ordering Guide .......................................................................... 34
REVISION HISTORY
1/11--Revision 0: Initial Version
Rev. 0 | Page 2 of 36
ADRF6801 SPECIFICATIONS
VS = 5 V; ambient temperature (TA) = 25C; fREF = 26 MHz, fLO = 900 MHz, fBB = 4.5 MHz, RLOAD = 450 differential, all register and PLL settings use the recommended values shown in the Register Structure section, unless otherwise noted. Table 1.
Parameter RF INPUT AT 900 MHz Internal LO Frequency Range Input Return Loss Input P1dB Second-Order Input Intercept (IIP2) Third-Order Input Intercept (IIP3) Noise Figure LO-to-RF Leakage I/Q BASEBAND OUTPUTS Voltage Conversion Gain Demodulation Bandwidth Quadrature Phase Error I/Q Amplitude Imbalance Output DC Offset (Differential) Output Common-Mode Voltage Gain Flatness Maximum Output Swing Maximum Output Current LO INPUT/OUTPUT Output Level Input Level Input Impedance VCO Operating Frequency SYNTHESIZER SPECIFICATIONS Test Conditions/Comments RFIN pins With VCO amplitude = 63 (R6 [DB15 to DB10]) With VCO amplitude = 24 (R6 [DB15 to DB10]) Measured at 900 MHz -5 dBm each tone -5 dBm each tone Double sideband from RF to either I or Q output With a -10 dBm interferer 5 MHz away At 1xLO frequency, 50 termination at the RF port IBBP, IBBN, QBBP, QBBN pins 450 differential load across IBBP, IBBN (or QBBP, QBBN) 1 V p-p signal 3 dB bandwidth Min 750 750 <-20 12.5 >65 25 14.3 18.9 -75 5.1 275 0.3 0.05 5 VPOS - 2.4 0.2 4 2.4 12 -2.5 0 50 3000 3000 4500 4600 Typ Max 1125 1150 Unit MHz MHz dB dBm dBm dBm dB dB dBm dB MHz Degrees dB mV V dB p-p V p-p V p-p mA p-p dBm dBm MHz MHz
Channel Spacing PLL Bandwidth SPURS Reference Spurs
Any 5 MHz (<100 MHz) Differential 450 load Differential 200 load Each pin LOP, LON Into a differential 50 load, LO buffer enabled (LO frequency = 900 MHz, output frequency = 1800 MHz) Externally applied 2xLO, PLL disabled Externally applied 2xLO, PLL disabled With VCO amplitude = 63 (R6 [DB15 to DB10]) With VCO amplitude = 24 (R6 [DB15 to DB10]) All synthesizer specifications measured with recommended settings provided in Figure 33 through Figure 39 fPFD = 26 MHz; modulus = 2047 Can be adjusted with off-chip loop filter component values and RSET fLO = 900 MHz, fREF = 26 MHz, fPFD = 26 MHz, measured at BB outputs with fBB = 50 MHz fREF = 26 MHz, fPFD = 26 MHz fPFD/2 fPFD x 2 fPFD x 3
25 130
kHz kHz
-91.6 -107.8 -89.1 -94.2
dBc dBc dBc dBc
Rev. 0 | Page 3 of 36
ADRF6801
Parameter PHASE NOISE (USING 130 kHz LOOP FILTER) Test Conditions/Comments fLO = 900 MHz, fREF = 26 MHz, fPFD = 26 MHz, measured at BB outputs with fBB = 50 MHz 1 kHz offset 10 kHz offset 100 kHz offset 500 kHz offset 1 MHz offset 5 MHz offset 10 MHz offset 1 kHz to 10 MHz integration bandwidth fLO = 900 MHz, fREF = 26 MHz, fPFD = 26 MHz, measured at BB outputs with fBB = 50 MHz 1 kHz offset 10 kHz offset 100 kHz offset 500 kHz offset 1 MHz offset 5 MHz offset 10 MHz offset Measured with fREF = 26 MHz, fPFD = 26 MHz Measured with fREF = 104 MHz, fPFD = 26 MHz REFIN, MUXOUT pins Usable range VOL (lock detect output selected) VOH (lock detect output selected) Min Typ Max Unit
Integrated Phase Noise PHASE NOISE (USING 2.5 kHz LOOP FILTER)
-99.5 -107.8 -106.6 -126.7 -131.7 -143.5 -150.5 0.16
dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz rms
PLL FIGURE OF MERIT (FOM) Phase Detector Frequency REFERENCE CHARACTERISTICS REFIN Input Frequency REFIN Input Capacitance MUXOUT Output Level REFOUT Duty Cycle CHARGE PUMP Pump Current Output Compliance Range LOGIC INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IINH/IINL Input Capacitance, CIN POWER SUPPLIES Voltage Range (5 V) Supply Current (5 V)
20 10
-71.3 -88.3 -114.1 -129.5 -138.6 -150.2 -150.3 -215.4 -220.9 26
40 160
dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz/Hz dBc/Hz/Hz MHz MHz pF V V % A V V V A pF V mA mA mA mA
4 0.25 2.7 50 500 1 CLK, DATA, LE pins 1.4 0 0.1 5 VCC1, VCC2, VCCLO, VCCBB, VCCRF pins 4.75 Normal Rx mode, internal LO Rx mode, internal LO with LO buffer enabled Rx mode, using external LO input (internal VCO, PLL shut down) Power-down mode 5 262 288 157 20 5.25 3.3 0.7 2.8
Supply Current (5 V)
Rev. 0 | Page 4 of 36
ADRF6801
TIMING CHARACTERISTICS
VS = 5 V, unless otherwise noted. Table 2.
Parameter t1 t2 t3 t4 t5 t6 t7 Limit at TMIN to TMAX (B Version) 20 10 10 25 25 10 20 Unit ns min ns min ns min ns min ns min ns min ns min Test Conditions/Comments LE setup time DATA to CLK setup time DATA to CLK hold time CLK high duration CLK low duration CLK to LE setup time LE pulse width
Timing Diagram
t4
CLOCK
t5
t2
DATA DB23 (MSB) DB22
t3
DB2 DB1 (CONTROL BIT C2) DB0 (LSB) (CONTROL BIT C1)
t7
LE
t1
LE
t6
09576-002
Figure 2. Timing Diagram
Rev. 0 | Page 5 of 36
ADRF6801 ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter Supply Voltage, VCC1, VCC2, VCCLO, VCCBB, and VCCRF (VS1) Digital I/O, CLK, DATA, and LE RFIN JA (Exposed Paddle Soldered Down) Maximum Junction Temperature Operating Temperature Range Storage Temperature Range Rating -0.5 V to +5.5 V -0.3 V to +3.6 V 16 dBm 30C/W 150C -40C to +85C -65C to +150C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ESD CAUTION
Rev. 0 | Page 6 of 36
ADRF6801 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
34 VCCLO 39 VTUNE 36 LOSEL 40 DECL1 33 IBBP 32 IBBN 35 GND 37 LON 38 LOP 31 GND
VCO LDO
BUFFER CTRL
VCC1 1
30 GND
DECL3 2 SCALE CPOUT 3 PHASE DETECTOR AND CHARGE PUMP
29 VCCBB
28 GND BLEED DIV CTRL 27 VCCRF
GND 4
RSET 5 x2 REFIN 6 /2 GND 7 ENABLE MUXOUT 8 /4 MUX 6 CURRENT CAL/SET 6 VCO BAND VCO 3000MHz TO 4600MHz MUX DIV /1 OR /2 QUADRATURE /2
26 RFIN
25 GNDRF
PROGRAMABLE DIVIDER
PRESCALER /2
24 GND
23 GND
DECL2 9 2.5V LDO VCC2 10 FRACTION MODULUS SERIAL PORT INTEGER THIRD-ORDER SDM
22 VCCBB
21 GND
DATA 12
LE 14
VCCLO 17
CLK 13
QBBP 18
GND 11
GND 15
GND 16
QBBN 19
GND 20
Figure 3. Pin Configuration
Table 4. Pin Function Descriptions
Pin No. 1 2 3 4, 7, 11, 15, 16, 20, 21, 23, 24, 28, 30, 31, 35 Mnemonic VCC1 DECL3 CPOUT GND Description The 5 V Power Supply Pin for VCO and PLL (VCC1). Decoupling Node for the 3.3 V LDO. Connect a 0.1 F capacitor between this pin and ground. Charge Pump Output Pin. Connect this pin to VTUNE through the loop filter. Connect these pins to a low impedance ground plane.
Rev. 0 | Page 7 of 36
08817-003
ADRF6801
Pin No. 5 Mnemonic RSET Description Charge Pump Current. The nominal charge pump current can be set to 250 A, 500 A, 750 A, or 1 mA using DB10 and DB11 of Register 4 and by setting DB18 to 0 (internal reference current). In this mode, no external RSET is required. If DB18 is set to 1, the four nominal charge pump currents (INOMINAL) can be externally tweaked according to the following equation where the resulting value is in units of ohms.
6 8 9 10 12 13 14
REFIN MUXOUT DECL2 VCC2 DATA CLK LE
17, 34 18, 19 22, 29 25 26 27 32, 33 36
VCCLO QBBP, QBBN VCCBB GNDRF RFIN VCCRF IBBN, IBBP LOSEL
37, 38
LON, LOP
39 40
VTUNE DECL1 EP
217 .4 x I CP RSET = - 37 .8 I NOMINAL Reference Input. Nominal input level is 1 V p-p. Input range is 10 MHz to 160 MHz. Multiplexer Output. This output can be programmed to provide the reference output signal or the lock detect signal. The output is selected by programming the appropriate register. Decoupling Node for 2.5 V LDO. Connect a 0.1 F capacitor between this pin and ground. The 5 V power supply pin for the 2.5 V LDO. Serial Data Input. The serial data is loaded MSB first with the three LSBs being the control bits. Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is latched into the 24-bit shift register on the CLK rising edge. Maximum clock frequency is 20 MHz. Load Enable. When the LE input pin goes high, the data stored in the shift registers is loaded into one of the six registers, the relevant latch being selected by the first three control bits of the 24-bit word. The 5 V Power Supply for the LO Path Blocks. Demodulator Q-Channel Differential Baseband Outputs; Differential Output Impedance of 24 . The 5 V Power Supply for the Baseband Output Section of the Demodulator Blocks. Ground Return for RF Input Balun. Single-Ended, Ground Referenced 50 , RF Input. The 5 V Power Supply for the RF Input Section of the Demodulator Blocks. Demodulator I-Channel Differential Baseband Outputs; Differential Output Impedance of 24 . LO Select. Connect this pin to ground for the simplest operation and to completely control the LO path and input/output direction from the register SPI programming. For additional control without register reprogramming, this input pin can determine whether the LOP and LON pins operate as inputs or outputs. LOP and LON become inputs if the LOSEL pin is set low, the LDRV bit of Register 5 is set low, and the LXL bit of Register 5 is set high. The externally applied LO drive must be at 2xLO frequency (and the LDIV bit of Register 5 (DB5) set low). LON and LOP become outputs when LOSEL is high or if the LDRV bit of Register 5 (DB3) is set high and the LXL bit of Register 5 (DB4) is set low. The output frequency is 2xLO frequency (and the LDIV bit of Register 5 (DB5) must be set high). This pin should not be left floating. Local Oscillator Input/Output. When these pins are used as output pins, a differential frequency divided version of the internal VCO is available on these pins. When the internal LO generation is disabled, an external MxLO frequency signal can be applied to these pins (where M corresponds to the LO path divider setting). (Differential Input/Output Impedance of 50 ) VCO Control Voltage Input. This pin is driven by the output of the loop filter. The nominal input voltage range on this pin is 1.0 V to 2.8 V. Connect a 10 F capacitor between this pin and ground as close to the device as possible because this pin serves as the VCO supply and loop filter reference. Exposed Paddle. The exposed paddle should be soldered to a low impedance ground plane.
Rev. 0 | Page 8 of 36
ADRF6801 TYPICAL PERFORMANCE CHARACTERISTICS
VS = 5 V, TA = 25C, unless otherwise noted. LO = 750 MHz to 1150 MHz.
CONVERSION GAIN (dB) AND INPUT P1dB (dBm) 16 14 12 10 8 6 4 55 2 0 750 50 750 GAIN
INPUT IP2 (dBm)
80
IP1dB
75
TA = +85C TA = +25C TA = -40C
70 TA = +85C TA = +25C TA = -40C I CHANNEL Q CHANNEL
65
60
09576-004
800
850
900
950
1000
1050
1100
1150
800
850
900
950
1000
1050
1100
1150
LO FREQUENCY (MHz)
LO FREQUENCY (MHz)
Figure 4. Conversion Gain and Input P1dB vs. LO Frequency
35 33 31 29 TA = +85C TA = +25C TA = -40C 20 19 18
Figure 7. Input IP2 vs. LO Frequency
NOISE FIGURE (dB)
17 16 15 14 13 12 11
INPUT IP3 (dBm)
TA = +85C TA = +25C TA = -40C
27 25 23 21 19 17
09576-005
800
850
900
950
1000
1050
1100
1150
800
850
900
950
1000
1050
1100
1150
LO FREQUENCY (MHz)
LO FREQUENCY (MHz)
Figure 5. Input IP3 vs. LO Frequency
1.0 5
Figure 8. Noise Figure vs. LO Frequency
IQ QUADRATURE PHASE ERROR (Degrees)
0.8 0.6 TA = +85C TA = +25C TA = -40C
4 3 2 1 0 -1 -2 -3 -4
09576-009
IQ GAIN MISMATCH (dB)
TA = +85C TA = +25C TA = -40C
0.4 0.2 0 -0.2 -0.4 -0.6 -0.8
800
850
900
950
1000
1050
1100
1150
09576-006
-1.0 750
-5 750
800
850
900
950
1000
1050
1100
1150
LO FREQUENCY (MHz)
LO FREQUENCY (MHz)
Figure 6. IQ Gain Mismatch vs. LO Frequency
Figure 9. IQ Quadrature Phase Error vs. LO Frequency
Rev. 0 | Page 9 of 36
09576-008
15 750
10 750
09576-007
ADRF6801
-50 -55 1 0
NORMALIZED BASEBAND FREQUENCY RESPONSE (dB)
LO-TO-RF FEEDTHROUGH (dBm)
-60 -65 -70 -75 -80 -85 -90 750
-1 -2 -3 -4 -5 -6 -7 1 10 100 BASEBAND FREQUENCY (MHz)
800
850
900
950
1000
1050
1100
1150
LO FREQUENCY (MHz)
Figure 10. LO-to-RF Feedthrough vs. LO Frequency, LO Output Turned Off
-35
LO-TO-BB FEEDTHROUGH (dBV rms)
09576-010
Figure 13. Normalized Baseband Frequency Response vs. Baseband Frequency
80
IIP2
INPUT P1dB (dBm), INPUT IP2 (dBm), AND INPUT IP3 (dBm)
-40 -45 -50 -55 -60 -65 -70 -75 750
70 60 50 40 30 20 10 0
TA = +85C TA = +25C TA = -40C I CHANNEL Q CHANNEL IIP3
IP1dB
09576-011
800
850
900
950
1000
1050
1100
1150
5
10
15
20
25
30
35
40
45
50
LO FREQUENCY (MHz)
BASEBAND FREQUENCY (MHz)
Figure 11. LO-to-BB Feedthrough vs. LO Frequency, LO Output Turned Off
-30 -35
Figure 14. Input P1dB, Input IP2, and Input IP3 vs. Baseband Frequency
34 32 30
RF-TO-BB FEEDTHROUGH (dBc)
-40
28 NOISE FIGURE (dB) 26 24 22 20 18 16 14 12
09576-012
-45 -50 -55 -60 -65 -70 750
800
850
900
950
1000
1050
1100
1150
-30
-25
-20
-15
-10
-5
0
5
RF FREQUENCY (MHz)
INPUT BLOCKER POWER (dBm)
Figure 12. RF-to-BB Feedthrough vs. RF Frequency
Figure 15. Noise Figure vs. Input Blocker Level, fLO = 900 MHz (RF Blocker 5 MHz Offset)
Rev. 0 | Page 10 of 36
09576-015
10 -35
09576-014
09576-013
ADRF6801
0 -5
2.0 1.9 1.8
RF INPUT RETURN LOSS (dB)
-10 -15 -20 -25 -30 -35 -40 750
VPTAT VOLTAGE (V)
09576-016
1.7 1.6 1.5 1.4 1.3 1.2 -40
800
850
900
950
1000
1050
1100
1150
-15
10
35
60
85
RF FREQUENCY (MHz)
TEMPERATURE (C)
Figure 16. RF Input Return Loss vs. RF Frequency
0 -2
Figure 19. VPTAT vs. Temperature
3.5 TA = +85C TA = +25C TA = -40C
3.0
LOP, LON DIFFERENTIAL OUTPUT RETURN LOSS (dB)
-4
VTUNE VOLTAGE (V)
-6 -8 -10 12 -14 -16 1500
2.5
2.0
1.5
1.0
09576-017
1600
1700
1800
1900
2000
2100
2200
2300
800
850
900
950
1000
1050
1100
1150
LOP, LON OUTPUT FREQUENCY (MHz)
LO FREQUENCY (MHz)
Figure 17. LO Output Return Loss vs. LO Output Frequency, LO Output Enabled (1500 MHz to 2300 MHz), Measured through TC1-1-13 Balun
400 380 360 340 TA = +85C TA = +25C TA = -40C
Figure 20. VTUNE vs. LO Frequency
CURRENT (mA)
320 300 280 260 240 220
09576-018
200 750
800
850
900
950
1000
1050
1100
1150
LO FREQUENCY (MHz)
Figure 18. 5 V Supply Currents vs. LO Frequency, LO Output Enabled
Rev. 0 | Page 11 of 36
09576-020
0.5 750
09576-019
ADRF6801
SYNTHESIZER/PLL
VS = 5 V. See the Register Structure section for recommended settings used. External loop filter bandwidths of ~130 kHz and 2.5 kHz used (see plots within this section for annotations), fREF = fPFD = 26 MHz, measured at BB output, fBB = 50 MHz, unless otherwise noted.
-40 TA = +85C TA = +25C TA = -40C
1.0 0.9 TA = +85C TA = +25C TA = -40C
INTEGRATED PHASE NOISE (rms)
09576-021
-60 PHASE NOISE (dBc/Hz)
0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1
-80 130kHz LOOP FILTER BANDWIDTH
-100
-120 2.5kHz LOOP FILTER BANDWIDTH -140
1k
10k
100k 1M OFFSET FREQUENCY (Hz)
10M
800
850
900
950
1000
1050
1100
1150
LO FREQUENCY (MHz)
Figure 21. Phase Noise vs. Offset Frequency, fLO = 900 MHz, Shown for Loop Filter Bandwidths of 2.5 kHz and 130 kHz
-70 -75 TA = +85C TA = +25C TA = -40C 1 x PFD FREQUENCY 3 x PFD FREQUENCY 0.5 x PFD FREQUENCY
Figure 24. Integrated Phase Noise vs. LO Frequency (Spurs Omitted), Using Loop Filter Bandwidth of 130 kHz
-50 1kHz OFFSET -70
PHASE NOISE (dBc/Hz)
PLL REFERENCE SPURS (dBc)
-80 -85 -90 -95 -100 -105 -110 750
10kHz OFFSET 1kHz OFFSET
-90
-110 10kHz OFFSET -130 5MHz OFFSET
130kHz LOOP FILTER BANDWIDTH 2.5kHz LOOP FILTER BANDWIDTH TA = +85C TA = +25C TA = -40C
-150 5MHz OFFSET 800 850 900 950 1000 1050 LO FREQUENCY (MHz) 1100 1150
09576-025 09576-026
800
850
900
950
1000
1050
1100
1150
LO FREQUENCY (MHz)
Figure 22. PLL Reference Spurs vs. LO Frequency, Using Loop Filter Bandwidth of 130 kHz
-70 -75 PLL REFERENCE SPURS (dBc) -80 -85 -90 -95 -100 -105 -110 750 TA = +85C TA = +25C TA = -40C 2 x PFD FREQUENCY 4 x PFD FREQUENCY
09576-022
-170 750
Figure 25. Phase Noise vs. LO Frequency (1 kHz, 10 kHz, and 5 MHz Offsets), Shown for Loop Filter Bandwidths of 2.5 kHz and 130 kHz
-90
-100
PHASE NOISE (dBc/Hz)
100kHz OFFSET
-110 100kHz OFFSET 1MHz OFFSET -130
-120
-140 1MHz OFFSET -150 130kHz LOOP FILTER BANDWIDTH 2.5kHz LOOP FILTER BANDWIDTH TA = +85C TA = +25C TA = -40C 1050 1100 1150
800
850
900
950
1000
1050
1100
1150
09576-023
-160 750
800
850
900
950
1000
LO FREQUENCY (MHz)
LO FREQUENCY (MHz)
Figure 23. PLL Reference Spurs vs. LO Frequency, Using Loop Filter Bandwidth of 130 kHz
Figure 26. Phase Noise vs. LO Frequency (100 kHz and 1 MHz Offsets), Shown for Loop Filter Bandwidths of 2.5 kHz and 130 kHz
Rev. 0 | Page 12 of 36
09576-024
-160
0 750
ADRF6801
COMPLEMENTARY CUMULATIVE DISTRIBUTION FUNCTIONS (CCDF)
VS = 5 V, fLO = 900 MHz, fBB = 4.5 MHz.
CUMULATIVE DISTRIBUTION PERCENTAGE (%)
90 80 70 60 50 40 30 20 10
09576-027
CUMULATIVE DISTRIBUTION PERCENTAGE (%)
100
100 90 80 70 60 50 40 30 20 10
09576-030
09576-132
09576-131
GAIN TA = +85C TA = +25C TA = -40C IP1dB
TA = +85C TA = +25C TA = -40C I CHANNEL Q CHANNEL
0 0 2 4 6 8 10 12 14 16 18 GAIN (dB) AND INPUT P1dB (dBm)
0 60 62 64 66 68 70 72 74 76 78 80 INPUT IP2 (dBm)
Figure 27. Gain and Input P1dB
CUMULATIVE DISTRIBUTION PERCENTAGE (%)
CUMULATIVE DISTRIBUTION PERCENTAGE (%)
Figure 30. Input IP2
100 90 80 70 60 50 40 30 20 10 0 4 6 8 10 12 14 16 18 20 22 24 NOISE FIGURE (dB) TA = +85C TA = +25C TA = -40C
100 90 80 70 60 50 40 30 20 10 17 19 21 23 25 27 29 31 33 35
09576-028
TA = +85C TA = +25C TA = -40C I CHANNEL Q CHANNEL
0 15
INPUT IP3 (dBm)
Figure 28. Input IP3
CUMULATIVE DISTRIBUTION PERCENTAGE (%)
100 90 80 70 60 50 40 30 20 10 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5
09576-029
Figure 31. Noise Figure
CUMULATIVE DISTRIBUTION PERCENTAGE (%)
100 90 80 70 60 50 40 30 20 10 0 -5 -4 -3 -2 -1 0 1 2 3 4 5 TA = +85C TA = +25C TA = -40C
TA = +85C TA = +25C TA = -40C
0 -0.5
IQ GAIN MISMATCH (dB)
IQ QUADRATURE PHASE ERROR (Degrees)
Figure 29. IQ Gain Mismatch
Figure 32. IQ Quadrature Phase Error
Rev. 0 | Page 13 of 36
ADRF6801 CIRCUIT DESCRIPTION
The ADRF6801 integrates a high performance IQ demodulator with a state-of-the-art fractional-N PLL. The PLL also integrates a low noise VCO. The SPI port allows the user to control the fractional-N PLL functions, the demodulator LO divider functions, and optimization functions, as well as allowing for an externally applied LO. The ADRF6801 uses a high performance mixer core that results in an exceptional input IP3 and input P1dB, with a very low output noise floor for excellent dynamic range.
BIAS CIRCUITRY
There are several band gap reference circuits and three low dropout regulators (LDOs) in the ADRF6801 that generate the reference currents and voltages used by different sections. The first of the LDOs is the 2.5 V LDO, which is always active and provides the 2.5 V supply rail used by the internal digital logic blocks. The 2.5 V LDO output is connected to DECL2 (Pin 9) for the user to provide external decoupling. The second LDO is the VCO LDO, which acts as the positive supply rail for the internal VCO. The VCO LDO output is connected to DECL2 (Pin 40) for the user to provide external decoupling. The VCO LDO can be powered down by setting Register 6, DB18 = 0, which allows the user to save power when not using the VCO. The third LDO is the 3.3 V LDO, which acts as the 3.3 V positive supply rail for the reference input, phase frequency detector, and charge pump circuitry. The 3.3 V LDO output is connected to DECL3 (Pin 2) for the user to provide external decoupling. The 3.3 V LDO can be powered down by setting Register 6, DB19 = 0, which allows the user to save power when not using the VCO. The demodulator also has a bias circuit that supplies bias current for the mixer V-to-I stage, which then sets the bias for the mixer core. The demodulator bias cell can also be shut down by setting Register 5, DB7 = 0.
LO QUADRATURE DRIVE
A signal at 2x the desired mixer LO frequency is delivered to a divide-by-2 quadrature phase splitter followed by limiting amplifiers which then drive the I and Q mixers, respectively.
V-TO-I CONVERTER
The RF input signal is applied to an on-chip balun which then provides both a ground referenced, 50 single-ended input impedance and a differential voltage output to a V-to-I converter that converts the differential voltages to differential output currents. These currents are then applied to the emitters of the Gilbert cell mixers.
MIXERS
The ADRF6801 has two double-balanced mixers: one for the in-phase channel (I channel) and one for the quadrature channel (Q channel). These mixers are based on the Gilbert cell design of four cross-connected transistors. The output currents from the two mixers are summed together in the resistive loads that then feed into the subsequent emitter follower buffers.
REGISTER STRUCTURE
The ADRF6801 provides access to its many programmable features through a 3-wire SPI control interface that is used to program the seven internal registers. The minimum delay and hold times are shown in the timing diagram (see Figure 2). The SPI provides digital control of the internal PLL/VCO as well as several other features related to the demodulator core, on-chip referencing, and available system monitoring functions. The MUXOUT pin provides a convenient, single-pin monitor output signal that can be used to deliver a PLL lock-detect signal or an internal voltage proportional to the local junction temperature. Note that internal calibration for the PLL must run when the ADRF6801 is initialized at a given frequency. This calibration is run automatically whenever Register 0, Register 1, or Register 2 is programmed. Because the other registers affect PLL performance, Register 0, Register 1, and Register 2 must always be programmed last. For ease of use, starting the initial programming with Register 7 and then programming the registers in descending order, ending with Register 0, is recommended. Once the PLL and other settings are programmed, the user can change the PLL frequency simply by programming Register 0, Register 1, or Register 2 as necessary.
EMITTER FOLLOWER BUFFERS
The output emitter followers drive the differential I and Q signals off chip. The output impedance is set by on-chip 12 series resistors that yield a 24 differential output impedance for each baseband port. The fixed output impedance forms a voltage divider with the load impedance that reduces the effective gain. For example, a 500 differential load has ~0.5 dB lower effective gain than with a high (10 k) differential load impedance. The common-mode dc output levels of the emitter followers are set from VCCBB via the voltage drop across the mixer load resistors, the VBE of the output emitter follower, and the voltage drop across the 12 series resistor.
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ADRF6801
DIVIDE MODE DB23 0 DB22 0 DB21 0 DB20 0 DB19 0 DB18 0 DB17 0 DB16 0 DB15 0 DB14 0 DB13 0 DB12 0 DB11 0 DB10 DM INTEGER DIVIDE RATIO DB9 DB8 ID6 ID5 DB7 ID4 DB6 ID3 DB5 ID2 DB4 ID1 DB3 ID0 CONTROL BITS DB2 C3(0) DB1 C2(0) DB0 C1(0)
DM 0 1
DIVIDE MODE FRACTIONAL (DEFAULT) INTEGER
ID6 0 0 0 0 ... ... 0 ... ... 1 1 1 1 1
ID5 0 0 0 0 ... ... 1 ... ... 1 1 1 1 1
ID4 1 1 1 1 ... ... 1 ... ... 1 1 1 1 1
ID3 0 0 0 1 ... ... 1 ... ... 0 1 1 1 1
ID2 1 1 1 0 ... ... 0 ... ... 1 0 0 0 0
ID1 0 1 1 0 ... ... 0 ... ... 1 0 0 1 1
ID0 1 0 1 0 ... ... 0 ... ... 1 0 1 0 1
DIVIDE RATIO 21 (INTEGER MODE ONLY) 22 (INTEGER MODE ONLY) 23 (INTEGER MODE ONLY) 24 ... ... 56 (DEFAULT) ... ... 119 120 (INTEGER MODE ONLY) 121 (INTEGER MODE ONLY)
09576-031
122 (INTEGER MODE ONLY) 123 (INTEGER MODE ONLY)
Figure 33. Integer Divide Control Register (R0)
Register 0--Integer Divide Control
With R0[2:0] set to 000, the on-chip integer divide control register is programmed as shown in Figure 33. The internal VCO frequency (fVCO) equation is (1) fVCO = fPFD x (INT + (FRAC/MOD)) x 2 where: fVCO is the output frequency of the internal VCO. INT is the preset integer divide ratio value (21 to 123 for integer mode, 24 to 119 for fractional mode). MOD is the preset fractional modulus (1 to 2047). FRAC is the preset fractional divider ratio value (0 to MOD - 1).
The integer divide ratio sets the INT value in Equation 1. The INT, FRAC, and MOD values make it possible to generate output frequencies that are spaced by fractions of the PFD frequency. Note that the demodulator LO frequency is given by fLO = fVCO/4.
Divide Mode
Divide mode determines whether fractional mode or integer mode is used. In integer mode, the VCO output frequency, fVCO, is calculated by fVCO = fPFD x (INT) x 2 (2)
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ADRF6801
Register 1--Modulus Divide Control
With R1[2:0] set to 001, the on-chip modulus divide control register is programmed as shown in Figure 34. The MOD value is the preset fractional modulus ranging from 1 to 2047.
MODULUS DIVIDE RATIO DB23 DB22 0 0 DB21 0 DB20 0 DB19 0 DB18 0 DB17 0 DB16 0 DB15 0 DB14 0 DB13 MD10 DB12 MD9 DB11 MD8 DB10 MD7 DB9 MD6 DB8 MD5 DB7 MD4 DB6 MD3 DB5 MD2 DB4 MD1 DB3 MD0 CONTROL BITS DB2 C3(0) DB1 C2(0) DB0 C1(1)
MD10 0 0 ... ... 1 ... ... 1
MD9 0 0 ... ... 1 ... ... 1
MD8 0 0 ... ... 0 ... ... 1
MD7 0 0 ... ... 0 ... ... 1
MD6 0 0 ... ... 0 ... ... 1
MD5 0 0 ... ... 0 ... ... 1
MD4 0 0 ... ... 0 ... ... 1
MD3 0 0 ... ... 0 ... ... 1
MD2 0 0 ... ... 0 ... ... 1
MD1 0 1 ... ... 0 ... ... 1
MD0 1 0 ... ... 0 ... ... 1
MODULUS VALUE 1 2 ... ... 1536 (DEFAULT) ... ... 2047
09576-032
Figure 34. Modulus Divide Control Register (R1)
Register 2--Fractional Divide Control
With R2[2:0] set to 010, the on-chip fractional divide control register is programmed as shown in Figure 35. The FRAC value is the preset fractional modulus ranging from 0 to MOD - 1.
FRACTIONAL DIVIDE RATIO DB23 0 DB22 0 DB21 0 DB20 0 DB19 0 DB18 0 DB17 0 DB16 0 DB15 0 DB14 0 DB13 FD10 DB12 FD9 DB11 FD8 DB10 FD7 DB9 FD6 DB8 FD5 DB7 FD4 DB6 FD3 DB5 FD2 DB4 FD1 DB3 FD0 CONTROL BITS DB2 C3(0) DB1 C2(1) DB0 C1(0)
FD10 0 0 ... ... 0 ... ...
FD9 0 0 ... ... 1 ... ...
FD8 0 0 ... ... 1 ... ...
FD7 0 0 ... ... 0 ... ...
FD6 0 0 ... ... 0 ... ...
FD5 0 0 ... ... 0 ... ...
FD4 0 0 ... ... 0 ... ...
FD3 0 0 ... ... 0 ... ...
FD2 0 0 ... ... 0 ... ...
FD1 0 0 ... ... 0 ... ...
FD0 0 1 ... ... 0 ... ...
FRACTIONAL VALUE 0 1 ... ... 768 (DEFAULT) ... ... 09576-033
FRACTIONAL VALUE MUST BE LESS THAN MODULUS
Figure 35. Fractional Divide Control Register (R2)
Register 3--- Modulator Dither Control
With R3[2:0] set to 011, the on-chip - modulator dither control register is programmed as shown in Figure 36. The dither restart value can be programmed from 0 to 217 to 1, though a value of 1 is typically recommended.
DB23 0 DITHER MAGNITUDE DB22 DB21 DITH1 DITH0 DITHER DITHER RESTART VALUE ENABLE DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DEN DV16 DV15 DV14 DV13 DV12 DV11 DV10 DV9 DV8 DV7 DV6 DV5 CONTROL BITS DB7 DB6 DB5 DV4 DV3 DV2 DB4 DB3 DB2 DB1 DB0 DV1 DV0 C3(0) C2(1) C1(1)
DEN 0 1 DITH1 0 0 1 1 DITH0 0 1 0 1
DITHER ENABLE DISABLE ENABLE (DEFAULT, RECOMMENDED)
DITHER MAGNITUDE 15 (DEFAULT) 7 3 1 (RECOMMENDED)
DV16 DV15 DV14 DV13 DV12 DV11 DV10 DV9 0 ... ... 1 0 ... ... 1 0 ... ... 1 0 ... ... 1 0 ... ... 1 0 ... ... 1 0 ... ... 1 0 ... ... 1
DV8 0 ... ... 1
DV7 0 ... ... 1
DV6 0 ... ... 1
DV5 0 ... ... 1
DV4 0 ... ... 1
DV3 0 ... ... 1
DV2 0 ... ... 1
DV1 0 ... ... 1
DV0 1 ... ... 1
DITHER RESTART VALUE 0x00001 (DEFAULT) ... ... 0x1FFFF
Figure 36. - Modulator Dither Control Register (R3)
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ADRF6801
Register 4--Charge Pump, PFD, and Reference Path Control
With R4[2:0] set to 100, the on-chip charge pump, PFD, and reference path control register is programmed as shown in Figure 37. The charge pump current is controlled by the base charge pump current (ICP, BASE) and the value of the charge pump current multiplier (ICP, MULT). The base charge pump current can be set using an internal or external resistor (according to Bit DB18 of Register 4). When using an external resistor, the value of ICP, BASE can be varied according to
217 . 4 x I CP , BASE R SET [ ] = - 37 . 8 250
and the divided-down VCO signal. This phase offset is used to linearize the PFD-CP transfer function and can improve fractional spurs. The magnitude of the phase offset is determined by
[deg] = 22 . 5 PFD , OFS I CP , MULT
Finally, the phase offset can be either positive or negative depending on the value of the DB17 bit in Register 4. The reference frequency applied to the PFD can be manipulated using the internal reference path source. The external reference frequency applied can be internally scaled in frequency by 2x, 1x, 0.5x, or 0.25x. This allows a broader range of reference frequency selections while keeping the reference frequency applied to the PFD within an acceptable range. The ADRF6801 also provides a MUXOUT pin that can be programmed to output a selection of several internal signals. The default mode provides a lock-detect output that allows users to verify when the PLL has locked to the target frequency. In addition, several other internal signals can be routed to the MUXOUT pin as described in Figure 37.
The actual charge pump current can be programmed to be a multiple (1, 2, 3, or 4) of the charge pump base current. The multiplying value (ICP, MULT) is equal to 1 plus the value of the DB11 and DB10 bits in Register 4. The PFD phase offset multiplier (PFD, OFS), which is set by Bit DB16 to Bit DB12 of Register 4, causes the PLL to lock with a nominally fixed phase offset between the PFD reference signal
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ADRF6801
OUPUT MUX SOURCE DB23 RMS2 DB22 RMS1 DB21 RMS0 INPUT REF PATH SOURCE DB20 RS1 DB19 RS0 CHARGE PUMP REF DB18 CPM PDF PHASE OFFSET POLARITY DB17 CPBD DB16 CPB4 PFD PHASE OFFSET MULTIPLIER VALUE DB15 DB14 DB13 DB12 CPB0 CHARGE PUMP CURRENT MULTIPLIER DB11 CPP1 DB10 CPP0 CP CNTL SRC DB9 CPS CHARGE PUMP CONTROL DB8 CPC1 DB7 CPC0 PFD EDGE SENSITIVITY DB6 PE1 DB5 PE0 PFD ANTIBACKLASH DELAY DB4 PAB1 DB3 PAB0 CONTROL BITS DB2 C3(1) DB1 C2(0) DB0 C1(0)
CPB3 CPB2 CPB1
PAB1 PAB0 PFD ANTIBACKLASH DELAY 0 0 1 1 0 1 0 1 0ns (DEFAULT, RECOMMENDED) 0.5ns 0.75ns 0.9ns
PE0 0 1 PE1 0 1
REFERENCE PATH EDGE SENSITIVITY FALLING EDGE (RECOMMENDED) RISING EDGE (DEFAULT)
DIVIDER PATH EDGE SENSITIVITY FALLING EDGE (RECOMMENDED) RISING EDGE (DEFAULT)
CHARGE PUMP CPC1 CPC0 CONTROL BOTH ON 0 0 PUMP DOWN 0 1 PUMP UP 1 0 TRISTATE (DEFAULT) 1 1 CPS 0 1 CHARGE PUMP CONTROL SOURCE CONTROL BASED ON STATE OF DB7/DB8 (CP CONTROL) CONTROL FROM PFD (DEFAULT)
CHARGE PUMP CPP1 CPP0 CURRENT MULTIPLIER 0 0 1 1 CPB4 CPB3 CPB2 CPB1 CPB0 0 0 ... 0 ... 0 ... 1 CPBD 0 1 CPM 0 1 RS1 0 0 1 1 RS0 0 1 0 1 0 0 ... 0 ... 1 ... 1 0 0 ... 1 ... 0 ... 1 0 0 ... 1 ... 1 ... 1 0 1 ... 0 ... 0 ... 1 0 1 0 1 1 2 (DEFAULT, RECOMMENDED) 3 4
PFD PHASE OFFSET MULTIPLIER 0 x 22.5/ICP, MULT 1 x 22.5/ICP, MULT ... 6 x 22.5/ICP, MULT (RECOMMENDED) ... 10 x 22.5/ICP, MULT (DEFAULT) ... 31 x 22.5/ICP, MULT
PFD PHASE OFFSET POLARITY NEGATIVE POSITIVE (DEFAULT, RECOMMENDED)
CHARGE PUMP CURRENT REFERENCE SOURCE INTERNAL (DEFAULT) EXTERNAL
INPUT REFERENCE PATH SOURCE 2 x REFERENCE INPUT REFERENCE INPUT (DEFAULT) 0.5 x REFERENCE INPUT 0.25 x REFERENCE INPUT
RMS2 RMS1 RMS0 OUTPUT MUX SOURCE 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 LOCK DETECT (DEFAULT) VPTAT BUFFERED VERSION OF REFERENCE INPUT BUFFERED VERSION OF 0.5 x REFERENCE INPUT BUFFERED VERSION OF 2 x REFERENCE INPUT TRISTATE BUFFERED VERSION OF 0.25 x FREF RESERVED (DO NOT USE)
Figure 37. Charge Pump, PFD, and Reference Path Control Register (R4)
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ADRF6801
Register 5--LO Path and Demodulator Control
Register 5 controls whether the LOIP and LOIN pins act as an input or output, whether the divider before the polyphase divider is in divide-by-1 or divide-by-2, and whether the demodulator bias circuitry is enabled as detailed in Figure 38.
LO LO OUTPUT IN/OUT DRIVER CONTROL BITS CTRL ENABLE DB4 DB3 DB2 DB1 DB0
DEMOD BIAS ENABLE
LO FIRST DIVIDER
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DB7 DMBE
DB6 0
DB5 LDIV
LXL
LDRV C3(1) C2(0) C1(1)
LO OUTPUT DRIVER LDRV ENABLE 0 1 DRIVER OFF (DEFAULT) DRIVER ON
LXL LO IN/OUT CONTROL 0 1 LO OUTPUT (DEFAULT) LO INPUT
LDIV 0 1
DIVIDE RATIO /1 / 2 (DEFAULT, NECESSARY FOR VCO USE)
DMBE 0 1
DEMOD BIAS ENABLE DISABLE ENABLE (DEFAULT)
09576-036
Figure 38. LO Path and Demodulator Control Register (R5)
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ADRF6801
Register 6--VCO Control and Enables
With R6[2:0] set to 110, the VCO control and enables register is programmed as shown in Figure 39. VCO band selection is normally selected based on BANDCAL calibration; however, the VCO band can be selected directly using Register 6. The VCO BS SRC determines whether the BANDCAL calibration determines the optimum VCO tuning band or if the external SPI interface is used to select the VCO tuning band based on the value of the VCO band select.
CHARGE 3.3V VCO PUMP LDO VCO LDO VCO ENABLE ENABLE ENABLE ENABLE SWITCH DB23 DB22 DB21 0 0 0 DB20 CPEN DB19 L3EN DB18 LVEN
The VCO amplitude can be controlled through Register 6. The VCO amplitude setting can be controlled between 0 and 31 decimal, with a default value of 24. The internal VCO can be disabled using Register 6. The internal VCO LDO can be disabled if an external clean 3.0 V supply is available. The internal charge pump can be disabled through Register 6. Normally, the charge pump is enabled.
VCO AMPLITUDE
VCO BS CSR
VCO BAND SELECT
CONTROL BITS
DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 VCO EN VCO SW VC5 VC4 VC3 VC2 VC1 VC0 VBSRC VBS5 VBS4 VBS3 VBS2 VBS1 VBS0 C3(1) C2(1) C1(0)
VBS5 VBS4 VBS3 VBS2 VBS1 VBS0 VCO BAND SELECT FROM SPI 0 ... 1 ... 1 0 ... 0 ... 1 0 ... 0 ... 1 0 ... 0 ... 1 0 ... 0 ... 1 0 ... 0 ... 1 0 ... 32 (DEFAULT) ... 63
VBSRC VCO BAND CAL AND SW SOURCE CONTROL 0 1 VC5 0 ... 0 ... 1 ... 1 VCO SW 0 1 VC4 0 ... 0 ... 0 ... 1 VC3 0 ... 1 ... 1 ... 1 BAND CAL (DEFAULT) SPI VC2 0 ... 0 ... 1 ... 1 VC1 0 ... 0 ... 1 ... 1 VC0 0 ... 0 ... 1 ... 1 VCO AMPLITUDE 0 ... 8 (DEFAULT) ... 47 ... 63 (RECOMMENDED)
VCO SWITCH CONTROL FROM SPI REGULAR (DEFAULT) BAND CAL
VCO EN 0 1
VCO ENABLE DISABLE ENABLE (DEFAULT)
LVEN 0 1
VCO LDO ENABLE DISABLE ENABLE (DEFAULT)
L3EN 3.3V LDO ENABLE 0 1 DISABLE ENABLE (DEFAULT)
CPEN CHARGE PUMP ENABLE 0 1 DISABLE ENABLE (DEFAULT)
09576-037
Figure 39. VCO Control and Enables (R6)
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ADRF6801 APPLICATIONS INFORMATION
BASIC CONNECTIONS
The basic circuit connections for a typical ADRF6801 application are shown in Figure 40.
SYNTHESIZER CONNECTIONS
The ADRF6801 includes an on-board VCO and PLL for LO synthesis. An external reference must be applied for the PLL to operate. A 1 V p-p nominal external reference must be applied to Pin 6 through an ac coupling capacitor. The reference is compared to an internally divided version of the VCO output frequency to create a charge pump error current to control and lock the VCO. The charge pump output current is filtered and converted to a control voltage through the external loop filter that is then applied to the VTUNE pin (Pin 39). ADIsimPLLTM can be a helpful tool when designing the external charge pump loop filter. The typical Kv of the VCO, the charge pump output current magnitude, and PFD frequency should all be considered when designing the loop filter. The charge pump current magnitude can be set internally or with an external RSET resistor connected to Pin 5 and ground, along with the internal digital settings applied to the PLL (see the Register 4--Charge Pump, PFD, and Reference Path Control section for more details).
+5V CHARGE PUMP LOOP FILTER IF I-OUTPUT BALUN
SUPPLY CONNECTIONS
The ADRF6801 has several supply connections and on-board regulated reference voltages that should be bypassed to ground using low inductance bypass capacitors located in close proximity to the supply and reference pins of the ADRF6801. Specifically Pin 1, Pin 2, Pin 9, Pin 10, Pin 17, Pin 22, Pin 27, Pin 29, Pin 34, and Pin 40 should be bypassed to ground using individual bypass capacitors. Pin 40 is the decoupling pin for the on-board VCO LDO, and for best phase noise performance, several bypass capacitors ranging from 100 pF to 10 F may help to improve phase noise performance. For additional details on bypassing the supply nodes, see the evaluation board schematic in Figure 42.
IF I-OUTPUT
40
DECL1
39
VTUNE
38
LOP
37
LON
36
LOSEL
35
GND
34
VCCLO
33
IBBP
32
IBBN
31
GND
+5V
GND 30 VCCBB 29 GND 28 VCCRF 27 RFIN 26 GNDRF 25 GND 24 GND 23 VCCBB 22 GND 21
+5V
1 VCC1 2 DECL3 3 CPOUT 4 OPEN R2 5 6 7 GND RSET REFIN GND
+5V RF INPUT
ADRF6801
EXTERNAL REFERENCE
MONITOR OUTPUT
8 MUXOUT 9 DECL2
+5V
10 VCC2
VCCLO QBBP DATA GND GND GND QBBN GND CLK LE
+5V
11
12
13
14
15
16
17
18
19
20
SPI CONTROL
IF Q-OUTPUT BALUN +5V
IF Q-OUTPUT
Figure 40. Basic Connections
Rev. 0 | Page 21 of 36
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ADRF6801
I/Q OUTPUT CONNECTIONS
The ADRF6801 has I and Q baseband outputs. Each output stage consists of emitter follower output transistors with a low differential impedance of 24 and can source up to 12 mA p-p differentially. A Mini-Circuits TCM9-1+ balun is used to transform a single-ended 50 load impedance into a nominal 450 differential impedance.
SETTING THE FREQUENCY OF THE PLL
The frequency of the VCO/PLL, once locked, is governed by the values programmed into the PLL registers, as follows: fPLL = fPFD x 2 x (INT + FRAC/MOD) where: fPLL is the frequency at the VCO when the loop is locked. fPFD is the frequency at the input of the phase frequency detector. INT is the integer divide ratio programmed into Register 0. MOD is the modulus divide ratio programmed into Register 1. FRAC is the fractional value programmed into Register 2. The practical lower limit of the reference input frequency is determined by the combination of the desired fPLL and the maximum programmable integer divide ratio of 119 and reference input frequency multiplier of 2. For a maximum fPLL of 4600 MHz, fREF > ~fPLL/(119 x 2 x 2), or 9.7 MHz. A lock detect signal is available as one of the selectable outputs through the MUXOUT pin, with logic high signifying that the loop is locked. When the internal VCO is used, the actual LO frequency is fLO = fPLL/4
RF INPUT CONNECTIONS
The ADRF6801 is to be driven single-ended and can be either dc coupled or ac coupled. There is an on-chip ground referenced balun that converts the applied single-ended signal to a differential signal that is then input to the RF V-to-I converter.
CHARGE PUMP/VTUNE CONNECTIONS
The ADRF6801 uses a loop filter to create the VTUNE voltage for the internal VCO. The loop filter in its simplest form is an integrating capacitor. It converts the current mode error signal coming out of the CPOUT pin into a voltage to control the VCO via the VTUNE voltage. The stock filter on the evaluation board has a bandwidth of 130 kHz. The loop filter contains seven components, four capacitors, and three resistors. Changing the values of these components changes the bandwidth of the loop filter. Note that to obtain the approximately 2.5 kHz loop bandwidth, the user can change the values of the following components on the evaluation board to as follows: C14 = 0.1 F, R10 = 68 , C15 = 4.7 F, R9 = 270 , C13 = 47 nF, R60 = 0 , C4 = open.
REGISTER PROGRAMMING
Because Register 6 controls the powering of the VCO and charge pump, it must be programmed once before programming the PLL frequency (Register 0, Register 1, and Register 2). The registers should be programmed starting with the highest register (Register 7) first and then sequentially down to Register 0 last. When Register 0, Register 1, or Register 2 is programmed, an internal VCO calibration is initiated that must execute when the other registers are set. Therefore, the order must be Register 7, Register 6, Register 5, Register 4, Register 3, Register 2, Register 1, and then Register 0. Whenever Register 0, Register 1, or Register 2 is written to, it initializes the VCO calibration (even if the value in these registers does not change). After the device has been powered up and the registers configured for the desired mode of operation, only Register 0, Register 1, or Register 2 must be programmed to change the LO frequency. If none of the register values is changing from their defaults, there is no need to program them.
LO SELECT INTERFACE
The ADRF6801 has the option of either monitoring a scaled version of the internally generated LO (LOSEL pin driven high at 3.3 V) or providing an external LO source (LOSEL pin driven low to ground, the LDRV bit in Register 5 set low, and the LXL bit in Register 5 set high). See the Pin Configuration and Function Descriptions section for full operation details.
EXTERNAL LO INTERFACE
The ADRF6801 provides the option to use an external signal source for the LO into the IQ demodulating mixer core. It is important to note that the applied LO signal is divided down by either 2 or 4 depending on the LO path divider bit, LDIV, in Register 5, prior to the actual IQ demodulating mixer core. The divider is determined by the register settings in the LO path and mixer control register (see the Register 5--LO Path and Demodulator Control section). The LO input pins (Pin 37 and Pin 38) present a broadband differential 50 input impedance. The LOP and LON input pins must be ac-coupled. This is achieved on the evaluation board via a Mini-Circuits TC1-1-13+ balun with a 1:1 impedance ratio. When not in use, the LOP and LON pins can be left unconnected.
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ADRF6801
EVM MEASUREMENTS
EVM is a measure used to quantify the performance of a digital radio transmitter or receiver. A signal received by a receiver has all constellation points at their ideal locations; however, various imperfections in the implementation (such as magnitude imbalance, noise floor, and phase imbalance) cause the actual constellation points to deviate from their ideal locations. In general, a demodulator exhibits three distinct EVM limitations vs. received input signal power. As signal power increases, the distortion components increase. At large enough signal levels, where the distortion components due to the harmonic nonlinearities in the device are falling in-band, EVM degrades as signal levels increase. At medium signal levels, where the demodulator behaves in a linear manner and the signal is well above any notable noise contributions, the EVM has a tendency to reach an optimal level determined dominantly by either quadrature accuracy and I/Q gain match of the demodulator or the precision of the test equipment. As signal levels decrease, such that the noise is the major contribution, the EVM performance vs. the signal level exhibits a decibel-for-decibel degradation with decreasing signal level. At lower signal levels, where noise proves to be the dominant limitation, the decibel EVM proves to be directly proportional to the SNR. The basic test setup to test EVM for the ADRF6801 consisted of an Agilent E4438C, which was used as a signal source. The 900 MHz modulated signal was driven single ended into the RFIN SMA connector of the ADRF6801 evaluation board. The IQ baseband outputs were taken differentially into two AD8130 difference amplifiers to convert the differential signals into singleended signals. A Hewlett Packard 89410A VSA was used to sample and calculate the EVM of the signal. The ADRF6801 IQ baseband output pins were presented with a 450 differential load impedance. The ADRF6801 shows excellent EVM performance for 16 QAM. Figure 41 shows the EVM of the ADRF6801 being better than -40 dB over a RF input range of about +35 dB for the 16 QAM modulated signal at a 10 MHz symbol rate. The pulse shaping filter's roll-off (alpha) was set to 0.35.
0 -5 -10 -15
EVM (dB)
-20 -25 -30 -35 -40
09576-042
-45 -65
-55
-45
-35
-25
-15
-5
5
15
INPUT POWER (dBm)
Figure 41. EVM vs. Input Power, EVM Measurements at fRF = 900 MHz; fIF = 0 MHz (that is, Direct Down Conversion); 16 QAM; Symbol Rate = 10 MHz
Rev. 0 | Page 23 of 36
ADRF6801 EVALUATION BOARD LAYOUT AND THERMAL GROUNDING
An evaluation board is available for testing the ADRF6801. The evaluation board schematic is shown in Figure 42. Table 5 provides the component values and suggestions for modifying the component values for the various modes of operation.
VCC VCC_SENSE OSC_3P3V OUTPUT_EN LO_EXTERN
1 3 5 7 9 J1
2 4 VCC 6 8 10 3P3V_SENSE 2P5V_LDO VCO_LDO LO_EXTERN VTUNE R59 OPEN R38 0 C14 22pF R37 0 R11 OPEN R10 3k C15 2.7nF 0 LO C8 100pF C7 0.1F R45 0 4 C13 6.8pF C4 22pF 52 R46 T1 3 1 0 10k R56 R33 10k R6 0 VCC_LO VCC_LO R55
VCC_RF S1 R29 0
VCC_BB R32 0
VCC_LO R31 0
VCC4 R13 0 VCC_SENSE
C28 10F VCC OPEN IBBP R3 R4 0 OPEN R41 P2 3 2 1 T2 4
VCC
CP
R9
10k
R60
10k
R40 IOUT_SE 0
R5 0
5 OPEN IBBN R39
VCO_LDO R15 0
R1 0 C1 100pF
R12 0
1nF C6
1nF C5 R27 0 C30 0.1F
3P3V1 C2 10F
3P3V_SENSE VCC4 R7 VCC4 0 C9 0.1F C10 100pF C11 0.1F
R49 OPEN VCO_LDO
40 DECL1
39 VTUNE
38 LOP
37 LON
36 LOSEL
35 GND
34 VCCLO
33 IBBP
32 IBBN
31 GND C26 100pF GND 30 VCCBB 29 GND 28 VCCRF 27 R28 R26 0 C24 100pF VCC_RF C27 0.1F VCC_RF
VCC_BB
1 VCC1 R8
2 DECL3 0 C12 100pF 3 CPOUT 4 OPEN 5 C31 R2 6 REFIN R14 49.9 1nF 7 GND 8 MUXOUT R16 REFOUT 0 VCCLO DATA GND GND GND QBBP QBBN 10 VCC2 CLK 2P5V_LDO LE 9 DECL2 RSET GND
C25 0.1F
ADRF6801
RFIN 26 0 GNDRF 25 GND 24 GND 23 R25 VCCBB 22 GND 21 GND C22 100pF 0 C23 0.1F VCC_BB
RFIN
REFIN
VCC_BB1
OPEN R23 R47 R21 0 3 0 R44 OPEN 2 1 R22 0 C29 0.1F R20 S2 R54 R53 0 VCC 10k OPEN 5 OPEN
R18 0 C16 100pF
QBBP
2P5V C3 10F C17 0.1F
11
12
13
14
15
16
17
18
19
20
DATA LE
T3 4
R43 QOUT_SE 0
R58 OPEN
VCC VCC2
R17 0 C19 0.1F C18 100pF
C33 OPEN
R51 OPEN CLK
C34 OPEN
R52 OPEN
P3
R48 0
R30 0 C32 OPEN R50 OPEN
R57 0
QBBN R42
R35 0 R19 OPEN
0
R34 LEGEND NET NAME TEST POINT SMA INPUT/OUTPUT VTUNE R36 0 DIG_GND GND GND1 P1 GND2 1 6 2 7 3 8 4 9 5 C21 100pF R24 0 C20 0.1F OUTPUT_EN OPEN VCC_LO VCC_LO1
09576-044
Figure 42. Evaluation Board Schematic
Rev. 0 | Page 24 of 36
ADRF6801
The package for the ADRF6801 features an exposed paddle on the underside that should be well soldered to an exposed opening in the solder mask on the evaluation board. Figure 43 illustrates the dimensions used in the layout of the ADRF6801 footprint on the ADRF6801 evaluation board (1 mil. = 0.0254 mm). Note the use of nine via holes on the exposed paddle. These ground vias should be connected to all other ground layers on the evaluation board to maximize heat dissipation from the device package. Under these conditions, the thermal impedance of the ADRF6801 was measured to be approximately 30C/W in still air.
0.012
0.050
0.035
0.168
Figure 44. ADRF6801 Evaluation Board Top Layer
0.025
0.177 0.232
Figure 43. Evaluation Board Layout Dimensions for the ADRF6801 Package
09576-043
0.020
Figure 45. ADRF6801 Evaluation Board Bottom Layer
Table 5. Evaluation Board Configuration Options
Component VCC, VCC2, VCC4, VCO_LDO, VCC_LO, VCC_LO1, VCC_RF, VCC_BB1, 3P3V1, 2P5V, CLK, DATA, LE, CP, DIG_GND, GND, GND1, GND2 Function Power supply, ground and other test points. Connect a 5 V supply to VCC. Default Condition VCC, VCC2, VCC4, VCC_LO, VCC_RF, VCC_BB1, VCC_LO1, VCO_LDO, 3P3V1, 2P5V = Components Corporation TP-104-01-02, CP, LE, CLK, DATA = Components Corporation TP-104-01-06, GND, GND1, GND2, DIG_GND = Components Corporation TP-104-01-00 R1, R6, R7, R8 = 0 (0402), R13, R15, R17 = 0 (0402), R18, R24, R25, R26, R27 = 0 (0402), R29, R31, R32 = 0 (0402), R36 = 0 (0402), R49 = open (0402)
R1, R6, R7, R8, R13, R15, R17, R18, R24, R25, R26, R27, R29, R31, R32, R36, R49
Power supply decoupling. Shorts or power supply decoupling resistors.
Rev. 0 | Page 25 of 36
09576-047
09576-046
ADRF6801
Component C1, C2, C3, C7, C8, C9, C10, C11, C12, C16, C17, C18, C19, C20, C21, C22, C23, C24, C25, C26, C27, C28 Function The capacitors provide the required decoupling of the supply-related pins. Default Condition C1, C8, C10, C12 = 100 pF (0402), C16, C18, C21, C22 = 100 pF (0402), C24, C26 = 100 pF (0402), C7, C9, C11 = 0.1 F (0402), C17, C19, C20, C23 = 0.1 F (0402), C25, C27 = 0.1 F (0402), C3, C2 = 10 F (0603), C28 = 10 F (3216) C5, C6 = 1 nF (0603), T1 = TC1-1-13+ Mini-Circuits R14 = 49.9 (0402), R16 = 0 (0402), R58 = open (0402), C31 = 1 nF (0603)
T1, C5, C6
R16, R14, R58, C31
R2, R9, R10, R11, R12, R37, R38, R59, R60, C4, C14, C15, C13
R3, R4, R5, R21, R22, R23, R39, R40, R41, R42, R43, R44, R45, R46, R47, R48, C29, C30, T2, T3, P2, P3
R28 R30, R35, R50, R51, R52, R57, C32, C33, C34, P1
R33, R55, R56, S1
External LO path. The T1 transformer provides single-ended-to-differential conversion. C5 and C6 provide the necessary ac coupling. REFIN input path. R14 provides a broadband 50 termination followed by C31, which provides the ac coupling into REFIN. R16 provides an external connectivity to the MUXOUT feature described in Register 4. R58 provides option for connectivity to the P1-6 line of a 9-pin D-sub connector for dc measurements. Loop filter component options. A variety of loop filter topologies is supported using component placements C4, C13, C14, C15, R9, R10, and R60. R38 and R59 provide connectivity options to numerous test points for engineering evaluation purposes. R2 provides resistor programmability of the charge pump current (see Register 4 description). R37 connects the charge pump output to the loop filter. R12 references the loop filter to the VCO_LDO. Default values on board provide a loop filter bandwidth of roughly 130 kHz using a 26 MHz PFD frequency. IF I/Q output paths. The T2 and T3 baluns provide a 9:1 impedance transformation; therefore, with a 50 load on the single-ended IOUT/QOUT side, the center tap side of the balun presents a differential 450 to the ADRF6806. The center taps of the baluns are ac grounded through C29 and C30. The baluns create a differential-to-single-ended conversion for ease of testing and use, but an option to have straight differential outputs is achieved via populating R3, R39, R23, and R42 with 0 resistors and removing R4, R5, R21, and R22. P2 and P3 are differential measurement test points (not to be used as jumpers). RF input interface. R28 provides the single-ended RF input path to the on-chip RF input balun. Serial port interface. A 9-pin D-sub connector (P1) is provided for connecting to a host PC or control hardware. Optional RC filters can be installed on the CLK, DATA, and LE lines to filter the PC signals through R50 to R52 and C32 to C34. CLK, DATA, and LE signals can be observed via test points for debug purposes. R58 provides a connection to the MUXOUT for sensing lock detect through the P1 connector. LO select interface. The LOSEL pin, in combination with the LDRV and LXL bits in Register 5, controls whether the LOP and LON pins operate as inputs or outputs. A detailed description of how the LOSEL pin, LDRV bit, and the LXL bit work together to control the LOP and LON pins is found in Table 4 under the LOSEL pin description. Using the S1 switch, the user can pull LOSEL to a logic high (VCC/2) or a logic low (ground). Resistors R55 and R56 form a resistor divider to provide a logic high of VCC/2. LO select can also be controlled through Pin 9 of J1. The 0 jumper, R33, must be installed to control LOSEL via J1.
Rev. 0 | Page 26 of 36
R12, R37, R38 = 0 (0402), R59 = open (0402), R9, R60 = 10 k (0402), R10 = 3 k (0402), R2, R11 = open (0402), C13 = 6.8 pF (0402), C4, C14 = 22 pF (0402), C15 = 2.7 nF (1206)
R4, R5, R21, R22, = 0 (0402), R40, R43, R45, R46 = 0 (0402), R47, R48 = 0 (0402), R3, R23, R39, R41, R42, R44 = open (0402), C29, C30, = 0.1 F (0402), T2, T3 = TCM9-1+ Mini-Circuits, P2, P3 = Samtec SSW-102-01-G-S
R28 = 0 (0402) R30, R35, R57 = 0 (0402), R50, R51, R52 = open (0402), C32, C33, C34 = open (0402), P1 = Tyco Electronics 5747840-3
R33 = 0 (0402), R55, R56 = 10 k (0402), S1 = Samtec TSW-103-08-G-S
ADRF6801
Component J1 Function Engineering test points and external control. J1 is a 10-pin connector connected to various important points on the evaluation board that the user can measure or force voltages upon. Provides ground connection for Pin 16. Default Condition J1 = Molex Connector Corp. 10-89-7102
R19, R20, R34, R53, R54, S2
R20, R53 = 0 (0402), R34, R54 = open (0402), R19 = open, S2 = open
Rev. 0 | Page 27 of 36
ADRF6801
ADRF6801 SOFTWARE
The ADRF6801 evaluation board can be controlled from PCs using a USB adapter board, which is also available from Analog Devices, Inc. The USB adapter evaluation documentation and ordering information can be found on the EVAL-ADF4XXXZ-USB product page. The basic user interfaces are shown in Figure 46 and Figure 47. The software allows the user to configure the ADRF6801 for various modes of operation. The internal synthesizer is controlled by clicking on any of the numeric values listed in RF Section. Attempting to program Ref Input Frequency, PFD Frequency, VCO Frequency (2xLO), LO Frequency, or other values in RF Section launches the Synth Form window shown in Figure 47. Using Synth Form, the user can specify values for Local Oscillator Frequency (MHz) and External Reference Frequency (MHz). The user can also enable the LO output buffer and divider options from this menu. After setting the desired values, it is important to click Upload all registers for the new setting to take effect.
Figure 46. Evaluation Board Software Main Window
Rev. 0 | Page 28 of 36
09576-048
ADRF6801
Figure 47. Evaluation Board Software Synth Form Window
Rev. 0 | Page 29 of 36
09576-049
ADRF6801 CHARACTERIZATION SETUPS
Figure 48 to Figure 50 show the general characterization bench setups used extensively for the ADRF6801. The setup shown in Figure 48 was used to do the bulk of the testing. An automated Agilent VEE program was used to control the equipment over the IEEE bus. This setup was used to measure gain, input P1dB, output P1dB, input IP2, input IP3, IQ gain mismatch, IQ quadrature accuracy, and supply current. The evaluation board was used to perform the characterization with a Mini-Circuits TCM9-1+ balun on each of the I and Q outputs. When using the TCM9-1+ balun below 5 MHz (the specified 1 dB low frequency corner of the balun), distortion performance degrades; however, this is not the ADRF6801 degrading, merely the low frequency corner of the balun introducing distortion effects. Through this balun, the 9-to-1 impedance transformation effectively presented a 450 differential load at each of the I and Q channels. The losses of the output baluns were de-embedded from all measurements. To do phase noise and reference spur measurements, the setup shown in Figure 50 was used. Phase noise was measured at the baseband output (I or Q) at a baseband carrier frequency of 50 MHz. The baseband carrier of 50 MHz was chosen to allow phase noise measurements to be taken at frequencies of up to 20 MHz offset from the carrier. The noise figure was measured using the setup shown in Figure 49 at a baseband frequency of 10 MHz.
Rev. 0 | Page 30 of 36
ADRF6801
IEEE
R&S SMA100 SIGNAL GENERATOR
IEEE RF1
3dB
R&S SMT03 SIGNAL GENERATOR
AGILENT 11636A POWER DIVIDER (USED AS COMBINER)
3dB
MINI-CIRCUITS ZHL-42W AMPLIFIER (SUPPLIED WITH +15V dc FOR OPERATION)
REF
IEEE
RF2
3dB 3dB
R&S SMT03 SIGNAL GENERATOR
RF
IEEE CH A CH B HP 8508A VECTOR VOLTMETER I CH AGILENT MXA SPECTRUM ANALYZER 6dB IEEE IEEE AGILENT 34980A MULTIFUNCTION SWITCH (WITH 34950 AND 2x 34921 MODULES) 3dB 6dB RF Q CH RF SWITCH MATRIX
IEEE
IEEE
AGILENT DMM (FOR ISUPPLY MEAS.)
ADRF6801
10-PIN CONNECTION (+5V VPOS, DC MEASURE) EVALUATION BOARD
AGILENT E3631A POWER SUPPLY 9-PIN D-SUB CONNECTION (VCO AND PLL PROGRAMMING)
6dB
IEEE IEEE
REF
IEEE
IEEE
09576-050
Figure 48. General Characterization Setup
Rev. 0 | Page 31 of 36
ADRF6801
IEEE
AGILENT 8665B LOW NOISE SYN SIGNAL GENERATOR REF
RF1
AGILENT 346B NOISE SOURCE
3dB
RF
IEEE
10MHz LOW-PASS FILTER
RF SWITCH MATRIX
AGILENT N8974A NOISE FIGURE ANALYZER AGILENT DMM (FOR ISUPPLY MEAS.)
I CH
RF
Q CH
6dB E IEEE
3dB
6dB
IEEE
AGILENT 34980A MULTIFUNCTION SWITCH (WITH 34950 AND 2x 34921 MODULES)
ADRF6801
10-PIN CONNECTION (+5V VPOS1, DC MEASURE) EVALUATION BOARD
AGILENT E3631A POWER SUPPLY
IEEE
6dB
9-PIN D-SUB CONNECTION (VCO AND PLL PROGRAMMING)
REF
IEEE
IEEE
09576-051
Figure 49. Noise Figure Characterization Setup
Rev. 0 | Page 32 of 36
ADRF6801
IEEE
R&S SMA100 SIGNAL GENERATOR
IEEE RF1 R&S SMA100 SIGNAL GENERATOR
REF
IEEE
100MHz LOW-PASS FILTER
3dB AGILENT E5052 SIGNAL SOURCE ANALYZER RF
IEEE
RF SWITCH MATRIX
AGILENT MXA SPECTRUM ANALYZER AGILENT DMM (FOR ISUPPLY MEAS.)
I CH
RF
Q CH
6dB E IEEE
3dB
6dB
IEEE
AGILENT 34980A MULTIFUNCTION SWITCH (WITH 34950 AND 2x 34921 MODULES)
ADRF6801
10-PIN CONNECTION (+5V VPOS1, DC MEASURE) EVALUATION BOARD
AGILENT E3631A POWER SUPPLY
IEEE
6dB
I E IEEE
9-PIN D-SUB CONNECTION (VCO AND PLL PROGRAMMING)
REF
IEEE
IEEE
IEEE
09576-052
Figure 50. Phase Noise Characterization Setup
Rev. 0 | Page 33 of 36
ADRF6801 OUTLINE DIMENSIONS
6.00 BSC SQ 0.60 MAX
31 30 40 1
0.60 MAX PIN 1 INDICATOR
PIN 1 INDICATOR
TOP VIEW
5.75 BSC SQ
0.50 BSC 0.50 0.40 0.30
EXPOSED PAD
(BOT TOM VIEW)
4.25 4.10 SQ 3.95
10
21 20
11
0.25 MIN 4.50 REF
12 MAX
0.80 MAX 0.65 TYP 0.05 MAX 0.02 NOM
1.00 0.85 0.80
COMPLIANT TO JEDEC STANDARDS MO-220-VJJD-2
Figure 51. 40-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 6 mm x 6 mm Body, Very Thin Quad (CP-40-1) Dimensions shown in millimeters
ORDERING GUIDE
Model 1 ADRF6801ACPZ-R7 ADRF6801-EVALZ
1
072108-A
SEATING PLANE
0.30 0.23 0.18
0.20 REF
COPLANARITY 0.08
FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET.
Temperature Range -40C to +85C
Package Description 40-Lead Lead Frame Chip Scale Package [LFCSP_VQ] Evaluation Board
Package Option CP-40-1
Ordering Quantity 750
Z = RoHS Compliant Part.
Rev. 0 | Page 34 of 36
ADRF6801 NOTES
Rev. 0 | Page 35 of 36
ADRF6801 NOTES
(c)2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D09576-0-1/11(0)
Rev. 0 | Page 36 of 36

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