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September 2006 rev 0.4
2.5V or 3.3V, 200MHz, 14 Output Zero Delay Buffer
General Features
* * * * * * * * * * * * * * Output frequency range: 8.3MHz to 200MHz Input frequency range: 4.2MHz to 125MHz 2.5V or 3.3V operation Split 2.5V/3.3V outputs 14 Clock outputs: Drive up to 28 clock lines 1 Feedback clock output 2 LVCMOS reference clock inputs 150pS max output-output skew PLL bypass mode `SpreadTrak' Output enable/disable Industrial temperature range: -40C to +85C 52 Pin 1.0 mm TQFP Package RoHS Compliance
PCS5I9775
provides 14 outputs partitioned in 3 banks of 5, 5, and 4 outputs. Bank A and Bank B divide the VCO output by 4 or 8 while Bank C divides by 8 or 12 per SEL(A:C) settings, see Functional Table. These dividers allow output to input ratios of 6:1, 4:1, 3:1, 2:1, 3:2, 4:3, 1:1, and 2:3. Each LVCMOS compatible output can drive 50 series or parallel terminated transmission lines. For series terminated transmission lines, each output can drive one or two traces giving the device an effective fanout of 1:28. The PLL is ensured stable, given that the VCO is configured to run between 200MHz and 500MHz. This allows a wide range of output frequencies from 8.3MHz to 200MHz. For normal operation, the external feedback input, FB_IN, is connected to the feedback output, FB_OUT. The internal VCO is running at multiples of the input reference clock set by the feedback divider, see Frequency Table. When PLL_EN is LOW, PLL is bypassed and the reference clock directly feeds the output dividers. This mode is fully static and the minimum input clock frequency specification does not apply.
Functional Description
The PCS5I9775 is a low-voltage high-performance 200MHz PLL-based zero delay buffer designed for high-speed clock distribution applications. The PCS5I9775 features two reference clock inputs and
Block Diagram
.
VCO_SEL (1, 0) PLL_EN TCLK_SEL TCLK0 TCLK1 FB_IN SELA /2//4 CLK STOP /2
PLL 200500MHZ
/2//4 /4
CLK STOP
QA0 QA1 QA2 QA3 QA4 QB0 QB1 QB2 QB3 QB4
SELB
/4//6 SELC CLK_STP#
CLK STOP
QC0 QC1 QC2 QC3 FB_OUT
/4//6//8//12 FB_SEL(1.0) MR#/OE
PulseCore Semiconductor Corporation 1715 S. Bascom Ave Suite 200, Campbell, CA 95008 * Tel: 408-879-9077 * Fax: 408-879-9018 www.pulsecoresemi.com
Notice: The information in this document is subject to change without notice.
September 2006 rev 0.4
Pin Configuration
PCS5I9775
VCO_SEL
VDDQC
VDDQC
VDDQB
QC1
QC2
QC3
VSS
VSS
QC0
VSS
VSS MR#/OE CLK_STP# SELB SELC PLL_EN SELA TCLK_SEL TCLK0 TCLK1 VCO_SEL1 VDD AVDD
1 2 3 4 5 6 7 8 9 10 11 12 13
52 51 50 49 48 47 46 45 44 43 42 41 40
NC
QB0
39 38 37 36 35 34 33 32 31 30 29 28 27
VSS QB1 VDDQB QB2 VSS QB3 VDDQB QB4 FB_IN VSS FB_OUT VDDFB NC
PCS5I9775
14 15 16 17 18 19 20 21 22 23 24 25 26
QA3
QA2
QA1
QA4
FB_SEL0
FB_SEL1
VSS
AVSS
VDDQA
VDDQA
VSS
QA0
2.5V or 3.3V, 200MHz, 14 Output Zero Delay Buffer
Notice: The information in this document is subject to change without notice.
VDDQA
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Pin
9 10 16, 18, 21, 23, 25 32, 34, 36, 38, 40 44, 46, 48, 50 29 31 2 3 6 8 11, 52 7, 4, 5 20, 14 17, 22, 26 33, 37, 41 45, 49 28 13 12 15 1, 19, 24, 30, 35, 39, 43, 47, 51 27, 42
PCS5I9775
I/O
I, PD I, PU O O O O I, PU I, PU I, PU I, PU I, PD I, PD I, PD I, PD Supply Supply Supply Supply Supply Supply Supply
Pin Description1 Name
TCLK0 TCLK1 QA(4:0) QB(4:0) QC(3:0) FB_OUT FB_IN MR#/OE CLK_STP# PLL_EN TCLK_SEL VCO_SEL(1,0) SEL(A:C) FB_SEL(1,0) VDDQA VDDQB VDDQC VDDFB AVDD VDD AVSS
Type
LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS VDD VDD VDD VDD VDD VDD Ground
Description
LVCMOS/LVTTL reference clock input LVCMOS/LVTTL reference clock input Clock output bank A Clock output bank B Clock output bank C Feedback clock output. Connect to FB_IN for normal operation. Feedback clock input. Connect to FB_OUT for normal operation. This input should be at the same voltage rail as input reference clock. See Table 1. Output enable/disable input. See Table 2. Clock stop enable/disable input. See Table 2. PLL enable/disable input. See Table 2. Reference select input. See Table 2. VCO divider select input. See Tables 2, 3 and 4. Frequency select input, Bank (A:C). See Table 3. Feedback dividers select inputs. See Table 4. 2.5V or 3.3V Power supply for bank A output clocks2,3 2.5V or 3.3V Power supply for bank B output clocks
2,3
2.5V or 3.3V Power supply for bank C output clocks2,3 2.5V or 3.3V Power supply for feedback output clock2,3 2.5V or 3.3V Power supply for PLL2,3 2.5V or 3.3V Power supply for core and inputs2,3 Analog Ground
VSS
Supply
Ground
Common Ground
NC
No Connection
Notes: 1. PU = Internal pull-up, PD = Internal pull-down 2. A 0.1F bypass capacitor should be placed as close as possible to each positive power pin (<0.2"). If these bypass capacitors are not close to the pins their high frequency filtering characteristics will be cancelled by the lead inductance of the traces. 3. AVDD and VDD pins must be connected to a power supply level that is at least equal or higher than that of VDDQA, VDDQB, VDDQC, and VDDFB power supply pins.
2.5V or 3.3V, 200MHz, 14 Output Zero Delay Buffer
Notice: The information in this document is subject to change without notice.
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September 2006 rev 0.4
`SpreadTrak'
Many systems being designed now utilize a technology called Spread Spectrum Frequency Timing Generation. PCS5I9975A is designed so as not to filter off the Spread Spectrum feature of the Reference Input, assuming it exists.
PCS5I9775
When a zero delay buffer is not designed to pass the Spread Spectrum feature through, the result is a significant amount of tracking skew which may cause problems in the systems requiring synchronization.
Table 1. Frequency Table Feedback Output Divider
/8 /12 /16 /24 /32 /48 /4 /6 /8 /12
VCO
Input Clock * 8 Input Clock * 12 Input Clock * 16 Input Clock * 24 Input Clock * 32 Input Clock * 48 Input Clock * 4 Input Clock * 6 Input Clock * 8 Input Clock * 12
Input Frequency Range (AVDD = 3.3V)
25MHz to 62.5MHz 16.6MHz to 41.6MHz 12.5MHz to 31.25MHz 8.3MHz to 20.8MHz 6.25MHz to 15.625MHz 4.2MHz to 10.4MHz 50MHz to 125MHz 33.3MHz to 83.3MHz 25MHz to 62.5MHz 16.6MHz to 41.6MHz
Input Frequency Range (AVDD = 2.5V)
25MHz to 50MHz 16.6MHz to 33.3MHz 12.5MHz to 25MHz 8.3MHz to 16.6MHz 6.25MHz to 12.5MHz 4.2 MHz to 8.3MHz 50MHz to 100MHz 33.3MHz to 66.6MHz 25MHz to 50MHz 16.6MHz to 33.3MHz
Table 2. Function Table (Configuration controls) Control
TCLK_SEL VCO_SEL0 VCO_SEL1 PLL_EN
Default
0 0 0 1 TCLK0
0
TCLK1 VCO/2 (mid input frequency range) Gated by VCO_SEL0 Bypass mode, PLL disabled. The input clock connects to the output dividers Outputs disabled (three-state) and reset of the device. During reset/output disable the PLL feedback loop is open and the VCO running at its minimum frequency. The device is reset by the internal power-on reset (POR) circuitry during power-up. QA, QB, and QC outputs disabled in LOW state. FB_OUT is not affected by CLK_STP.
1
VCO/4 (low input frequency range) VCO (high input frequency range) PLL enabled. The VCO output connects to the output dividers
MR/OE
1
Outputs enabled
CLK_STP
1
Outputs enabled
2.5V or 3.3V, 200MHz, 14 Output Zero Delay Buffer
Notice: The information in this document is subject to change without notice.
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Table 3. Function Table (Bank A, B, and C) VCO_SEL1
0 0 0 0 1 1
PCS5I9775
VCO_SEL0
0 0 1 1 x x
SELA
0 1 0 1 0 1
QA(4:0)
/4 /8 /8 /16 /2 /4
SELB
0 1 0 1 0 1
QB(4:0)
/4 /8 /8 /16 /2 /4
SELC
0 1 0 1 0 1
QC(3:0)
/8 /12 /16 /24 /4 /6
Table 4. Function Table (FB_OUT) VCO_SEL1
0 0 0 0 0 0 0 0 1 1 1 1
VCO_SEL0
0 0 0 0 1 1 1 1 x x x x
FB_SEL1
0 0 1 1 0 0 1 1 0 0 1 1
FB_SEL0
0 1 0 1 0 1 0 1 0 1 0 1
FB_OUT
/8 /16 /12 /24 /16 /32 /24 /48 /4 /8 /6 /12
Absolute Maximum Conditions Parameter
VDD VDD VIN VOUT VTT LU RPS TS TA TJ OJC OJA ESDH FIT
Description
DC Supply Voltage DC Operating Voltage DC Input Voltage DC Output Voltage Output termination Voltage Latch Up Immunity Power Supply Ripple Temperature, Storage Temperature, Operating Ambient Temperature, Junction Dissipation, Junction to Case Dissipation, Junction to Ambient ESD Protection (Human Body Model) Failure in Time
Condition
Functional Relative to VSS Relative to VSS Functional Ripple Frequency < 100kHz Non Functional Functional Functional Functional Functional Manufacturing test
Min
-0.3 2.375 -0.3 -0.3 200 -65 -40
Max
5.5 3.465 VDD+ 0.3 VDD+ 0.3 VDD /2 150 +150 +85 150 23 55 10
Unit
V V V V V mA mVp-p C C C C/W C/W Volts ppm
2000
2.5V or 3.3V, 200MHz, 14 Output Zero Delay Buffer
Notice: The information in this document is subject to change without notice.
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September 2006 rev 0.4
DC Electrical Specifications (VDD= 3.3V 5%, TA = -40C to +85C) Parameter
VIL VIH VOL VOH IIL IIH IDDA IDDQ IDD CIN ZOUT
PCS5I9775
Description
Input Voltage, Low Input Voltage, High Output Voltage, Low4 Output Voltage, High4 Input Current, Low5 Input Current, High
5
Condition
LVCMOS LVCMOS IOL= 24 mA IOL= 12 mA IOH= -24 mA VIL= VSS VIL= VDD AVDD only All VDD pins except AVDD Outputs loaded @ 100MHz Outputs loaded @ 200MHz
Min
2.0
Typ
Max
0.8 VDD+0.3 0.55 0.30
Unit
V V V V A A mA mA mA pF
2.4
-100 100 5 10 1 225 290 4
PLL Supply Current Quiescent Supply Current Dynamic Supply Current Input Pin Capacitance Output Impedance
12
15
18
DC Electrical Specifications (VDD= 2.5V 5%, TA = -40C to +85C) Parameter
VIL VIH VOL VOH IIL IIH IDDA IDDQ IDD CIN ZOUT
Description
Input Voltage, Low Input Voltage, High Output Voltage, Low
5 4 4
Condition
LVCMOS LVCMOS IOL= 15 mA IOH= -15 mA VIL= VSS VIL= VDD AVDD only All VDD pins except AVDD Outputs loaded @ 100MHz Outputs loaded @ 200MHz
Min.
1.7 1.8
Typ.
Max
0.7 VDD+0.3 0.6 -100 100
Unit
V V V V A A mA mA mA pF
Output Voltage, High Input Current, Low Input Current, High5 PLL Supply Current
5
10 1
Quiescent Supply Current Dynamic Supply Current Input Pin Capacitance Output Impedance
135 160 4 14 18 22
Notes: 4. Driving one 50 parallel terminated transmission line to a termination voltage of VTT. Alternatively, each output drives up to two 50 series terminated transmission lines. 5. Inputs have pull-up or pull-down resistors that affect the input current.
2.5V or 3.3V, 200MHz, 14 Output Zero Delay Buffer
Notice: The information in this document is subject to change without notice.
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September 2006 rev 0.4
AC Electrical Specifications6 (VDD= 2.5V 5%, TA = -40C to +85C) Parameter
fVCO
PCS5I9775
Description
VCO Frequency
Condition
/4 Feedback /6 Feedback /8 Feedback /12 Feedback
Min
200 50 33.3 25 16.7 12.5 8.3 6.3 4.2 0 25 100 50 33.3 25 16.7 12.5 8.3 45 0.1 -100
Typ
Max
400 100 66.6 50 33.3 25 16.7 12.5 8.3 200 75 1.0 200 100 66.6 50 33.3 25 16.7 55 1.0 100 150 150 225 10 10
Unit
MHz
fin
Input Frequency
/16 Feedback /24 Feedback /32 Feedback /48 Feedback Bypass mode (PLL_EN = 0)
MHz
frefDC tr, tf
Input Duty Cycle TCLK Input Rise/Fall Time 0.7V to 1.7V /2 Output /4 Output /6 Output
% nS
fMAX
Maximum Output Frequency
/8 Output /12 Output /16 Output /24 Output
MHz
DC tr, tf t() tsk(O) tsk(B) tPLZ, HZ tPZL, ZH BW tJIT(CC) tJIT(PER) tJIT() tLOCK
Output Duty Cycle Output Rise/Fall times Propagation Delay (static phase offset) Output-to-Output Skew Bank-to-Bank Skew Output Disable Time Output Enable Time PLL Closed Loop Bandwidth (-3 dB) Cycle-to-Cycle Jitter Period Jitter I/O Phase Jitter Maximum PLL Lock Time VCO_SEL = 0 VCO_SEL = 1 Same frequency Multiple frequencies 0.7V to 1.8V TCLK to FB_IN, does not include jitter Skew within Bank Banks at same frequency Banks at different frequency
% nS pS pS pS nS nS MHz
0.5 - 1.0 1.0 - 2.0 150 300 100 150 1
pS pS pS mS
Note: 6. AC characteristics apply for parallel output termination of 50 to VTT. Parameters are guaranteed by characterization and are not 100% tested.
2.5V or 3.3V, 200MHz, 14 Output Zero Delay Buffer
Notice: The information in this document is subject to change without notice.
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September 2006 rev 0.4
AC Electrical Specifications 6 (VDD= 3.3V 5%, TA = -40C to +85C) Parameter Description Condition
fVCO VCO Frequency /4 Feedback /6 Feedback /8 Feedback /12 Feedback fin Input Frequency /16 Feedback /24 Feedback /32 Feedback /48 Feedback Bypass mode (PLL_EN = 0) frefDC tr, tf Input Duty Cycle TCLK Input Rise/Fall Time 0.8V to 2.0V /2 Output /4 Output /6 Output fMAX Maximum Output Frequency /8 Output /12 Output /16 Output /24 Output DC tr, tf t() tsk(O) Output Duty Cycle Output Rise/Fall times Propagation Delay (static phase offset) Output-to-Output Skew 0.8V to 2.4V TCLK to FB_IN, same VDD, does not include jitter Skew within Bank Banks at same voltage, same frequency Banks at same voltage, different frequency Banks at different voltage
PCS5I9775
Min
200 50 33.3 25 16.7 12.5 8.3 6.3 4.2 0 25 100 50 33.3 25 16.7 12.5 8.3 45 0.1 -100
Typ
Max
500 125 83.3 62.5 41.6 31.3 20.8 15.6 10.4 200 75 1.0 200 125 83.3 62.5 41.6 31.3 20.8 55 1.0 100 150 150 225 250 10 10
Unit
MHz
MHz
% nS
MHz
% nS pS pS
tsk(B)
Bank-to-Bank Skew
pS
tPLZ, HZ tPZL, ZH BW tJIT(CC) tJIT(PER) tJIT() tLOCK
Output Disable Time Output Enable Time PLL Closed Loop Bandwidth (-3dB) Cycle-to-Cycle Jitter Period Jitter I/O Phase Jitter Maximum PLL Lock Time I/O at same VDD VCO_SEL = 0 VCO_SEL = 1 Same frequency Multiple frequencies 0.5 - 1.0 1.0 - 2.0
nS nS MHz
150 300 100 150 1
pS pS pS mS
2.5V or 3.3V, 200MHz, 14 Output Zero Delay Buffer
Notice: The information in this document is subject to change without notice.
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PCS5I9775
Figure 1. AC Test Reference for VDD = 3.3V / 2.5V
Figure 2. Propagation Delay t(), Static Phase Offset
Figure 3. Output Duty Cycle (DC)
Figure 4. Output-to-Output Skew, tsk(O)
2.5V or 3.3V, 200MHz, 14 Output Zero Delay Buffer
Notice: The information in this document is subject to change without notice.
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September 2006 rev 0.4
Package Information 52-lead TQFP Package
PCS5I9775
SECTION A-A
Dimensions Symbol
A A1 A2 D D1 E E1 L L1 T T1 b b1 R0 a e
Inches Min Max
.... 0.0020 0.0374 0.4646 0.3898 0.4646 0.3898 0.0177 0.0035 0.0038 0.0102 0.0106 0.0031 0 0.0472 0.0059 0.0413 0.4803 0.3976 0.4803 0.3976 0.0295 0.0079 0.0062 0.0150 0.0130 0.0079 7
Millimeters Min Max
... 0.05 0.95 11.8 9.9 11.8 9.9 0.45 0.09 0.097 0.26 0.27 0.08 0 1.2 0.15 1.05 12.2 10.1 12.2 10.1 0.75 0.2 0.157 0.38 0.33 0.2 7
0.03937 REF
1.00 REF
0.0256 BASE
0.65 BASE
2.5V or 3.3V, 200MHz, 14 Output Zero Delay Buffer
Notice: The information in this document is subject to change without notice.
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September 2006 rev 0.4
Ordering Information Part Number
PCS5P9775G-52-ET PCS5P9775G-52-ER PCS5I9775G-52-ET PCS5I9775G-52-ER
PCS5I9775
Marking
PCS5P9775G PCS5P9775G PCS5I9775G PCS5I9775G
Package Type
52-pin TQFP, Tray, Green 52-pin TQFP - Tape and Reel, Green 52-pin TQFP, Tray, Green 52-pin TQFP - Tape and Reel, Green
Operating Range
Commercial Commercial Industrial Industrial
Device Ordering Information
PCS5I9775G-52-ET
R = Tape & Reel, T = Tube or Tray O = SOT S = SOIC T = TSSOP A = SSOP V = TVSOP B = BGA Q = QFN DEVICE PIN COUNT U = MSOP E = TQFP L = LQFP U = MSOP P = PDIP D = QSOP X = SC-70
G = GREEN PACKAGE, LEAD FREE, and RoHS
PART NUMBER X= Automotive I= Industrial P or n/c = Commercial (-40C to +125C) (-40C to +85C) (0C to +70C) 1 = Reserved 2 = Non PLL based 3 = EMI Reduction 4 = DDR support products 5 = STD Zero Delay Buffer 6 = Power Management 7 = Power Management 8 = Power Management 9 = Hi Performance 0 = Reserved
PulseCore Semiconductor Mixed Signal Product
Licensed under US patent #5,488,627, #6,646,463 and #5,631,920.
2.5V or 3.3V, 200MHz, 14 Output Zero Delay Buffer
Notice: The information in this document is subject to change without notice.
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September 2006 rev 0.4
PCS5I9775
PulseCore Semiconductor Corporation 1715 S. Bascom Ave Suite 200 Campbell, CA 95008 Tel: 408-879-9077 Fax: 408-879-9018 www.pulsecoresemi.com
Copyright (c) PulseCore Semiconductor All Rights Reserved Preliminary Information Part Number: PCS5I9775 Document Version: 0.4
Note: This product utilizes US Patent # 6,646,463 Impedance Emulator Patent issued to PulseCore Semiconductor, dated 11-11-2003
(c) Copyright 2006 PulseCore Semiconductor Corporation. All rights reserved. Our logo and name are trademarks or registered trademarks of PulseCore Semiconductor. All other brand and product names may be the trademarks of their respective companies. PulseCore reserves the right to make changes to this document and its products at any time without notice. PulseCore assumes no responsibility for any errors that may appear in this document. The data contained herein represents PulseCore's best data and/or estimates at the time of issuance. PulseCore reserves the right to change or correct this data at any time, without notice. If the product described herein is under development, significant changes to these specifications are possible. The information in this product data sheet is intended to be general descriptive information for potential customers and users, and is not intended to operate as, or provide, any guarantee or warrantee to any user or customer. PulseCore does not assume any responsibility or liability arising out of the application or use of any product described herein, and disclaims any express or implied warranties related to the sale and/or use of PulseCore products including liability or warranties related to fitness for a particular purpose, merchantability, or infringement of any intellectual property rights, except as express agreed to in PulseCore's Terms and Conditions of Sale (which are available from PulseCore). All sales of PulseCore products are made exclusively according to PulseCore's Terms and Conditions of Sale. The purchase of products from PulseCore does not convey a license under any patent rights, copyrights; mask works rights, trademarks, or any other intellectual property rights of PulseCore or third parties. PulseCore does not authorize its products for use as critical components in life-supporting systems where a malfunction or failure may reasonably be expected to result in significant injury to the user, and the inclusion of PulseCore products in such life-supporting systems implies that the manufacturer assumes all risk of such use and agrees to indemnify PulseCore against all claims arising from such use.
2.5V or 3.3V, 200MHz, 14 Output Zero Delay Buffer
Notice: The information in this document is subject to change without notice.
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