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M48T37Y M48T37V
5.0 or 3.3 V, 256 Kbit (32 Kbit x 8) TIMEKEEPER(R) SRAM
Features

Integrated ultra low power SRAM, real-time clock, power-fail control circuit, and battery Frequency test output for real-time clock software calibration Automatic power-fail chip deselect and WRITE protection Watchdog timer WRITE protect voltage (VPFD = Power-fail deselect voltage): - M48T37Y: VCC = 4.5 to 5.5 V 4.2 V VPFD 4.5 V - M48T37V: VCC = 3.0 to 3.6 V 2.7 V VPFD 3.0 V Packaging includes a 44-lead SOIC and SNAPHAT(R) top (to be ordered separately) SOIC package provides direct connection for a SNAPHAT(R) top which contains the battery and crystal Microprocessor power-on reset (valid even during battery backup mode) Programmable alarm output active in the battery backup mode Battery low flag RoHS compliant - Lead-free second level interconnect
SNAPHAT(R) (SH) Battery/crystal
44 1

SOH44 (MH) 44-pin SOIC

August 2010
Doc ID 7019 Rev 9
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www.st.com 1
Contents
M48T37Y, M48T37V
Contents
1 2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Operation modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.1 2.2 2.3 READ mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 WRITE mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Data retention mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3
Clock operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 Reading the clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Setting the clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Stopping and starting the oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Setting the alarm clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Calibrating the clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Programmable interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Battery low flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Initial power-on defaults . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 VCC noise and negative going transients . . . . . . . . . . . . . . . . . . . . . . . . . 18
4 5 6 7 8 9
Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Environmental information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
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M48T37Y, M48T37V
List of tables
List of tables
Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 READ mode AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 WRITE mode AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Alarm repeat modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Default values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Operating and AC measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Power down/up AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Power down/up trip points DC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 SOH44 - 44-lead plastic small outline, 4-socket SNAPHAT(R), package mechanical data . 24 SH - 4-pin SNAPHAT(R) housing for 48 mAh battery & crystal, package mechanical data . 25 SH - 4-pin SNAPHAT(R) housing for 120 mAh battery & crystal, package mechanical data 26 Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 SNAPHAT(R) battery table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
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List of figures
M48T37Y, M48T37V
List of figures
Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 SOIC connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 READ mode AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 WRITE enable controlled, WRITE AC waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Chip enable controlled, WRITE AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Alarm interrupt reset waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Backup mode alarm waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Supply voltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Crystal accuracy across temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Clock calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 AC testing load circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Power down/up mode AC waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 SOH44 - 44-lead plastic small outline, 4-socket SNAPHAT(R) outline. . . . . . . . . . . . . . . . . 24 SH - 4-pin SNAPHAT(R) housing for 48 mAh battery & crystal, pack. outline . . . . . . . . . . . 25 SH - 4-pin SNAPHAT(R) housing for 120 mAh battery & crystal, pack. outline . . . . . . . . . . 26 Recycling symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
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M48T37Y, M48T37V
Description
1
Description
The M48T37Y/V TIMEKEEPER(R) RAM is a 32 Kb x 8 non-volatile static RAM and real-time clock. The monolithic chip is available in a special package which provides a highly integrated battery-backed memory and real-time clock solution. The 44-lead, 330 mil SOIC package provides sockets with gold-plated contacts at both ends for direct connection to a separate SNAPHAT housing containing the battery and crystal. The unique design allows the SNAPHAT(R) battery/crystal package to be mounted on top of the SOIC package after the completion of the surface mount process. Insertion of the SNAPHAT housing after reflow prevents potential battery and crystal damage due to the high temperatures required for device surface-mounting. The SNAPHAT housing is keyed to prevent reverse insertion. The SOIC and battery packages are shipped separately in plastic anti-static tubes or in tape & reel form. For the 44-lead SOIC, the battery/crystal package (e.g., SNAPHAT) part number is "M4T28-BR12SH" or "M4T32-BR12SH".
Caution:
Do not place the SNAPHAT battery/crystal top in conductive foam, as this will drain the lithium button-cell battery. Figure 1. Logic diagram
VCC 15 A0-A14 W E G WDI 8 DQ0-DQ7 RST IRQ/FT
M48T37Y M48T37V
VSS
AI02172
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Description Table 1.
A0-A14 DQ0-DQ7 RST IRQ/FT WDI E G W VCC VSS NC
M48T37Y, M48T37V Signal names
Address inputs Data inputs / outputs Reset output (open drain) Interrupt / frequency test output (open drain) Watchdog input Chip enable Output enable WRITE enable Supply voltage Ground Not connected internally
Figure 2.
SOIC connections
NC RST NC NC A14 A12 A7 A6 A5 A4 A3 NC NC WDI A2 A1 A0 DQ0 DQ1 DQ2 NC VSS 44 1 2 43 3 42 4 41 40 5 39 6 38 7 8 37 36 9 35 10 11 M48T37Y 34 12 M48T37V 33 32 13 31 14 30 15 29 16 28 17 27 18 26 19 25 20 21 24 23 22 VCC NC NC NC IRQ/FT W A13 A8 A9 A11 G NC NC A10 E NC DQ7 DQ6 DQ5 DQ4 DQ3 NC
AI02174
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M48T37Y, M48T37V Figure 3. Block diagram
IRQ/FT WDI
Description
OSCILLATOR AND CLOCK CHAIN 32,768 Hz CRYSTAL POWER 16 x 8 BiPORT SRAM ARRAY
A0-A14
LITHIUM CELL VOLTAGE SENSE AND SWITCHING CIRCUITRY VPFD
32,752 x 8 SRAM ARRAY
DQ0-DQ7
E W G
VCC
RST
VSS
AI03253
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Operation modes
M48T37Y, M48T37V
2
Operation modes
As Figure 3 on page 7 shows, the static memory array and the quartz controlled clock oscillator of the M48T37Y/V are integrated on one silicon chip. The memory locations that provide user accessible BYTEWIDETM clock information are in the bytes with addresses 7FF1 and 7FF9h-7FFFh (located in Table 5 on page 13). The clock locations contain the century, year, month, date, day, hour, minute, and second in 24-hour BCD format. Corrections for 28, 29 (leap year - valid until the year 2100), 30, and 31 day months are made automatically. Byte 7FF8h is the clock control register. This byte controls user access to the clock information and also stores the clock calibration setting. Byte 7FF7h contains the watchdog timer setting. The watchdog timer redirects an out-ofcontrol microprocessor and provides a reset or interrupt to it. Bytes 7FF2h-7FF5h are reserved for clock alarm programming. These bytes can be used to set the alarm. This will generate an active low signal on the IRQ/FT pin when the alarm bytes match the date, hours, minutes, and seconds of the clock. The eight clock bytes are not the actual clock counters themselves; they are memory locations consisting of BiPORTTM READ/WRITE memory cells. The M48T37Y/V includes a clock control circuit which updates the clock bytes with current information once per second. The information can be accessed by the user in the same manner as any other location in the static memory array. The M48T37Y/V also has its own power-fail detect circuit. The control circuitry constantly monitors the single VCC supply for an out of tolerance condition. When VCC is out of tolerance, the circuit write protects the SRAM, providing a high degree of data security in the midst of unpredictable system operation brought on by low VCC. As VCC falls below the battery backup switchover voltage (VSO), the control circuitry connects the battery which maintains data and clock operation until valid power returns. Table 2.
Mode Deselect WRITE READ READ Deselect Deselect VSO to VPFD (min) VSO(1)
(1)
Operating modes
VCC 4.5 to 5.5 V or 3.0 to 3.6 V E VIH VIL VIL VIL X X G X X VIL VIH X X W X VIL VIH VIH X X DQ0-DQ7 High Z DIN DOUT High Z High Z High Z Power Standby Active Active Active CMOS standby Battery backup mode
1. See Table on page 23 for details.
Note:
X = VIH or VIL; VSO = Battery backup switchover voltage.
2.1
READ mode
The M48T37Y/V is in the READ mode whenever WRITE enable (W) is high and chip enable (E) is low. The unique address specified by the 15 address inputs defines which one of the 32,752 bytes of data is to be accessed. Valid data will be available at the data I/O pins within address access time (tAVQV) after the last address input signal is stable, providing that the E and output enable (G) access times are also satisfied. If the E and G access times are not
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M48T37Y, M48T37V
Operation modes
met, valid data will be available after the latter of the chip enable access time (tELQV) or output enable access time (tGLQV). The state of the eight three-state data I/O signals is controlled by E and G. If the outputs are activated before tAVQV, the data lines will be driven to an indeterminate state until tAVQV. If the address inputs are changed while E and G remain active, output data will remain valid for output data hold time (tAXQX) but will be indeterminate until the next address access. Figure 4. READ mode AC waveforms
tAVAV A0-A14 tAVQV tELQV E tELQX tGLQV G tGLQX DQ0-DQ7 VALID
AI00925
VALID tAXQX tEHQZ
tGHQZ
Note:
WRITE enable (W) = high. Table 3. READ mode AC characteristics
M48T37Y Symbol Parameter(1) Min tAVAV tAVQV tELQV tGLQV tELQX(2) tGLQX(2) tEHQZ(2) tGHQZ(2) tAXQX READ cycle time Address valid to output valid Chip enable low to output valid Output enable low to output valid Chip enable low to output transition Output enable low to output transition Chip enable high to output Hi-Z Output enable high to output Hi-Z Address transition to output transition 10 5 5 25 25 10 70 70 70 35 10 5 50 40 -70 Max Min 100 100 100 50 M48T37V -100 Max ns ns ns ns ns ns ns ns ns Unit
1. Valid for ambient operating temperature: TA = 0 to 70 C or -40 to 85 C; VCC = 4.5 to 5.5 V or 3.0 to 3.6 V (except where noted). 2. CL = 5 pF.
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Operation modes
M48T37Y, M48T37V
2.2
WRITE mode
The M48T37Y/V is in the WRITE mode whenever W and E are low. The start of a WRITE is referenced from the latter occurring falling edge of W or E. A WRITE is terminated by the earlier rising edge of W or E. The addresses must be held valid throughout the cycle. E or W must return high for a minimum of tEHAX from chip enable or tWHAX from WRITE enable prior to the initiation of another READ or WRITE cycle. Data-in must be valid tDVWH prior to the end of WRITE and remain valid for tWHDX afterward. G should be kept high during WRITE cycles to avoid bus contention; however, if the output bus has been activated by a low on E and G, a low on W will disable the outputs tWLQZ after W falls. Figure 5. WRITE enable controlled, WRITE AC waveform
tAVAV A0-A14 VALID tAVWH tAVEL E tWLWH tAVWL W tWLQZ tWHDX DQ0-DQ7 DATA INPUT tDVWH
AI00926
tWHAX
tWHQX
Figure 6.
Chip enable controlled, WRITE AC waveforms
tAVAV
A0-A14
VALID tAVEH tAVEL tELEH tEHAX
E tAVWL W tEHDX DQ0-DQ7 DATA INPUT tDVEH
AI00927
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M48T37Y, M48T37V Table 4. WRITE mode AC characteristics
M48T37Y Symbol Parameter(1) Min tAVAV tAVWL tAVEL tWLWH tELEH tWHAX tEHAX tDVWH tDVEH tWHDX tEHDX tWLQZ(2)(3) tAVWH tAVEH tWHQX
(2)(3)
Operation modes
M48T37V -100 Unit
-70 Max
Min 100 0 0 80 80 10 10 50 50 5 5
Max ns ns ns ns ns ns ns ns ns ns ns 50 ns ns ns ns
WRITE cycle time Address valid to WRITE enable low Address valid to chip enable low WRITE enable pulse width Chip enable low to chip enable high WRITE enable high to address transition Chip enable high to address transition Input valid to WRITE enable high Input valid to chip enable high WRITE enable high to input transition Chip enable high to input transition WRITE enable low to output Hi-Z Address valid to WRITE enable high Address valid to chip enable high WRITE enable high to output transition
70 0 0 50 55 0 0 30 30 5 5 25 60 60 5
80 80 10
1. Valid for ambient operating temperature: TA = 0 to 70 C or -40 to 85 C; VCC = 4.5 to 5.5 V or 3.0 to 3.6 V (except where noted). 2. CL = 5 pF. 3. If E goes low simultaneously with W going low, the outputs remain in the high impedance state.
2.3
Data retention mode
With valid VCC applied, the M48T37Y/V operates as a conventional BYTEWIDETM static RAM. Should the supply voltage decay, the RAM will automatically power-fail deselect, write protecting itself when VCC falls within the VPFD (max), VPFD (min) window. All outputs become high impedance, and all inputs are treated as "Don't care."
Note:
A power failure during a WRITE cycle may corrupt data at the currently addressed location, but does not jeopardize the rest of the RAM's content. At voltages below VPFD (min), the user can be assured the memory will be in a write protected state, provided the VCC fall time is not less than tF. The M48T37Y/V may respond to transient noise spikes on VCC that reach into the deselect window during the time the device is sampling VCC. Therefore, decoupling of the power supply lines is recommended. When VCC drops below VSO, the control circuit switches power to the internal battery which preserves data and powers the clock. The internal button cell will maintain data in the M48T37Y/V for an accumulated period of at least 7 years at room temperature when VCC is less than VSO. As system power returns and VCC rises above VSO, the battery is disconnected and the power supply is switched to external VCC. Normal RAM operation can resume tREC after VCC reaches VPFD (max). For more information on battery storage life refer to the application note AN1012.
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Clock operations
M48T37Y, M48T37V
3
3.1
Clock operations
Reading the clock
Updates to the TIMEKEEPER(R) registers should be halted before clock data is read to prevent reading data in transition. The BiPORTTM TIMEKEEPER cells in the RAM array are only data registers and not the actual clock counters, so updating the registers can be halted without disturbing the clock itself. Updating is halted when a '1' is written to the READ bit, D6 in the control register 7FF8h. As long as a '1' remains in that position, updating is halted. After a halt is issued, the registers reflect the count; that is, the day, date, and the time that were current at the moment the halt command was issued. All of the TIMEKEEPER registers are updated simultaneously. A halt will not interrupt an update in progress. Updating will resume within a second after the bit is reset to a '0.'
3.2
Setting the clock
Bit D7 of the control register (7FF8h) is the WRITE bit. Setting the WRITE bit to a '1,' like the READ bit, halts updates to the TIMEKEEPER registers. The user can then load them with the correct day, date, and time data in 24-hour BCD format (see Table 5 on page 13). Resetting the WRITE bit to a '0' then transfers the values of all time registers (7FF1h, 7FF9h-7FFFh) to the actual TIMEKEEPER counters and allows normal operation to resume. After the WRITE bit is reset, the next clock update will occur in approximately one second.
Note:
Upon power-up following a power failure, both the WRITE bit and the READ bit will be reset to '0.'
3.3
Stopping and starting the oscillator
The oscillator may be stopped at any time. If the device is going to spend a significant amount of time on the shelf, the oscillator can be turned off to minimize current drain on the battery. The STOP bit is the MSB of the seconds register. Setting it to a '1' stops the oscillator. When reset to a '0,' the M48T37Y/V oscillator starts within one second.
Note:
It is not necessary to set the WRITE bit when setting or resetting the FREQUENCY TEST bit (FT) or the STOP bit (ST).
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M48T37Y, M48T37V Table 5.
Address D7 7FFFh 7FFEh 7FFDh 7FFCh 7FFBh 7FFAh 7FF9h 7FF8h 7FF7h 7FF6h 7FF5h 7FF4h 7FF3h 7FF2h 7FF1h 7FF0h WDF 0 0 0 0 0 ST W WDS AFE RPT4 RPT3 RPT2 RPT1 R BMB4 0 0 0 D6 D5 D4 D3 D2 D1 Year 10 M Month Date: Day of month 0 0 Day of week Hours Minutes Seconds Calibration BMB2 BMB1 BMB0 0 0 0 RB1 0 RB0 0 D0 10 years 0 0 FT 0 0
Clock operations Register map
Data Function/range BCD format Year Month Date Day Hours Min Sec Control Watchdog Interrupts Alarm date Alarm hour Alarm min Alarm sec Century Z Flags 01-31 00-23 00-59 00-59 00-99 00-99 01-12 01-31 01-7 00-23 00-59 00-59
10 date 0
10 hours 10 minutes 10 seconds S BMB3 ABE
AIarm 10 date AIarm 10 hours
Alarm date Alarm hours Alarm minutes Alarm seconds 100 year
Alarm 10 minutes Alarm 10 seconds 1000 year AF Z BL Z
Z
Z
Keys: S = Sign bit FT = Frequency test bit R = READ bit W = WRITE bit ST = Stop bit 0 = Must be set to '0' BL = Battery low flag (read only) BMB0-BMB4 = Watchdog multiplier bits AFE = Alarm flag enable flag RB0-RB1 = Watchdog resolution bits WDS = Watchdog steering bit ABE = Alarm in battery backup mode enable bit RPT1-RPT4 = Alarm repeat mode bits WDF = Watchdog flag (read only) AF = Alarm flag (read only) Z = '0' and are read only
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Clock operations
M48T37Y, M48T37V
3.4
Setting the alarm clock
Registers 7FF5h-7FF2h contain the alarm settings. The alarm can be configured to go off at a predetermined time on a specific day of the month or repeat every day, hour, minute, or second. It can also be programmed to go off while the M48T37Y/V is in the battery backup mode of operation to serve as a system wake-up call. RPT1-RPT4 put the alarm in the repeat mode of operation. Table 6 shows the possible configurations. Codes not listed in the table default to the once per second mode to quickly alert the user of an incorrect alarm setting.
Note:
User must transition address (or toggle chip enable) to see flag bit change. When the clock information matches the alarm clock settings based on the match criteria defined by RPT1-RPT4, AF is set. If AFE is also set, the alarm condition activates the IRQ/FT pin. To disable alarm, write '0' to the alarm date registers and RPT1-4. The alarm flag and the IRQ/FT output are cleared by a READ to the flags register as shown in Figure 7. A subsequent READ of the flags register is necessary to see that the value of the alarm flag has been reset to '0.' The IRQ/FT pin can also be activated in the battery backup mode. The IRQ/FT will go low if an alarm occurs and both the alarm in battery backup mode enable (ABE) and the AFE are set. The ABE and AFE bits are reset during power-up, therefore an alarm generated during power-up will only set AF. The user can read the flag register at system boot-up to determine if an alarm was generated while the M48T37Y/V was in the deselect mode during power-up. Figure 8 illustrates the backup mode alarm timing. Figure 7. Alarm interrupt reset waveform
ADDRESS 7FF0h 15ns Min
A0-A14
ACTIVE FLAG BIT
IRQ/FT
AI01677B
Table 6.
RPT4 1 1 1 1 0
Alarm repeat modes
RPT3 1 1 1 0 0 RPT2 1 1 0 0 0 RPT1 1 0 0 0 0 Alarm activated Once per second Once per minute Once per hour Once per day Once per month
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M48T37Y, M48T37V Figure 8.
VCC VPFD (max) VPFD (min) VSO
Clock operations Backup mode alarm waveforms
tREC
ABE, AFE bit in Interrupt Register
AF bit in Flags Register
IRQ/FT HIGH-Z HIGH-Z
AI03254B
3.5
Calibrating the clock
The M48T37Y/V is driven by a quartz controlled oscillator with a nominal frequency of 32,768 Hz. The devices are tested not to exceed 35 ppm (parts per million) oscillator frequency error at 25 C, which equates to about 1.53 minutes per month. With the calibration bits properly set, the accuracy of each M48T37Y/V improves to better than +1/-2 ppm at 25 C. The oscillation rate of any crystal changes with temperature (see Figure 10 on page 19). Most clock chips compensate for crystal frequency and temperature shift error with cumbersome trim capacitors. The M48T37Y/V design, however, employs periodic counter correction. The calibration circuit adds or subtracts counts from the oscillator divider circuit at the divide by 256 stage, as shown in Figure 11 on page 19. The number of times pulses are blanked (subtracted, negative calibration) or split (added, positive calibration) depends upon the value loaded into the five-bit calibration byte found in the control register. Adding counts speeds the clock up, subtracting counts slows the clock down. The calibration byte occupies the five lower order bits (D4-D0) in the control register 7FF8h. These bits can be set to represent any value between 0 and 31 in binary form. Bit D5 is the sign bit; '1' indicates positive calibration, '0' indicates negative calibration. Calibration occurs within a 64 minute cycle. The first 62 minutes in the cycle may, once per minute, have one second either shortened by 128 or lengthened by 256 oscillator cycles. If a binary '1' is loaded into the register, only the first 2 minutes in the 64 minute cycle will be modified; if a binary 6 is loaded, the first 12 will be affected, and so on. Therefore, each calibration step has the effect of adding 512 or subtracting 256 oscillator cycles for every 125, 829, 120 (64 minutes x 60 seconds/minute x 32,768 cycles/second) actual oscillator cycles, that is +4.068 or -2.034 ppm of adjustment per calibration step in the calibration register. Assuming that the oscillator is in fact running at exactly 32,768 Hz, each of the 31 increments in the calibration byte would represent +10.7 or -5.35 seconds per month which corresponds to a total range of +5.5 or -2.75 minutes per month.
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Clock operations
M48T37Y, M48T37V
Two methods are available for ascertaining how much calibration a given M48T37Y/V may require. The first involves simply setting the clock, letting it run for a month and comparing it to a known accurate reference (like WWW broadcasts). While that may seem crude, it allows the designer to give the end user the ability to calibrate his clock as his environment may require, even after the final product is packaged in a non-user serviceable enclosure. All the designer has to do is provide a simple utility that accesses the calibration byte. The second approach is better suited to a manufacturing environment, and involves the use of the IRQ/FT pin. The pin will toggle at 512 Hz when the stop bit (ST, D7 of 7FF9h) is '0' the frequency test bit (FT, D6 of 7FFCh) is '1,' the alarm flag enable bit (AFE, D7 of 7FF6h) is '0,' and the watchdog steering bit (WDS, D7 of 7FF7h) is '1' or the watchdog register is reset (7FF7h=0). Any deviation from 512 Hz indicates the degree and direction of oscillator frequency shift at the test temperature. For example, a reading of 512.01024 Hz would indicate a +20 ppm oscillator frequency error, requiring a -10(WR001010) to be loaded into the calibration byte for correction. Note: Setting or changing the calibration byte does not affect the frequency test output frequency. The IRQ/FT pin is an open drain output which requires a pull-up resistor for proper operation. A 500-10 k resistor is recommended in order to control the rise time. The FT bit is cleared on power-down. For more information on calibration, see the application note AN934, "TIMEKEEPER calibration."
3.6
Watchdog timer
The watchdog timer can be used to detect an out-of-control microprocessor. The user programs the watchdog timer by setting the desired amount of time-out into the eight-bit watchdog register, address 7FF7h. The five bits (BMB4-BMB0) that store a binary multiplier and the two lower order bits (RB1-RB0) select the resolution, where 00 = 1/16 second, 01 = 1/4 second, 10 = 1 second, and 11 = 4 seconds. The amount of time-out is then determined to be the multiplication of the five-bit multiplier value with the resolution. (For example: writing 00001110 in the watchdog register = 3x1, or 3 seconds).
Note:
Accuracy of timer is within the selected resolution. If the processor does not reset the timer within the specified period, the M48T37Y/V sets the watchdog flag (WDF) and generates a watchdog interrupt or a microprocessor reset. WDF is reset by reading the flags register (Address 7FF0h).
Note:
User must transition address (or toggle chip enable) to see flag bit change. Reset will not occur unless the addresses are stable at the flag location for at least 15 ns while the device is in the READ mode as shown in Figure 9 on page 19. The most significant bit of the watchdog register is the watchdog steering bit. When set to a '0,' the watchdog will activate the IRQ/FT pin when timed-out. When WDS is set to a '1,' the watchdog will output a negative pulse on the RST pin for a duration of tREC. The watchdog register, the FT bit, AFE bit, and ABE bit will reset to a '0' at the end of a watchdog time-out when the WDS bit is set to a '1.' The watchdog timer resets when the microprocessor performs a re-write of the watchdog register or an edge transition (low to high / high to low) on the WDI pin occurs. The timeout period then starts over.
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Clock operations
The watchdog timer is disabled by writing a value of 00000000 to the eight bits in the watchdog register. Should the watchdog timer time out, a value of 00h needs to be written to the watchdog register in order to clear the IRQ/FT pin. The watchdog function is automatically disabled upon power-down and the watchdog register is cleared. If the watchdog function is set to output to the IRQ/FT pin and the frequency test function is activated, the watchdog or alarm function prevails and the frequency test function is denied. The WDI pin should be connected to VSS if not used.
3.7
Power-on reset
The M48T37Y/V continuously monitors VCC. When VCC falls to the power fail detect trip point, the RST pulls low (open drain) and remains low on power-up for tREC after VCC passes VPFD. RST is valid for all VCC conditions. The RST pin is an open drain output and an appropriate resistor to VCC should be chosen to control rise time (see Figure 13 on page 22).
3.8
Programmable interrupts
The M48T37Y/V provides two programmable interrupts: an alarm and a watchdog. When an interrupt condition occurs, the M48T37Y/V sets the appropriate flag bit in the flag register 7FF0h. The interrupt enable bits (AFE and ABE) in 7FF6h and the watchdog steering (WDS) bit in 7FF7h allow the interrupt to activate the IRQ/FT pin. The alarm flag and the IRQ/FT output are cleared by a READ to the flags register. An interrupt condition reset will not occur unless the addresses are stable at the flag location for at least 15 ns while the device is in the READ mode as shown in Figure 7 on page 14. The IRQ/FT pin is an open drain output and requires a pull-up resistor (10 k recommended) to VCC. The pin remains in the high impedance state unless an interrupt occurs or the frequency test mode is enabled.
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Clock operations
M48T37Y, M48T37V
3.9
Battery low flag
The M48T37Y/V automatically performs periodic battery voltage monitoring upon power-up. The battery low flag (BL), bit D4 of the flags register 7FF0h, will be asserted high if the SNAPHAT(R) battery is found to be less than approximately 2.5 V. The BL flag will remain active until completion of battery replacement and subsequent battery low monitoring tests during the next power-up sequence. If a battery low is generated during a power-up sequence, this indicates the battery voltage is below 2.5 V (approximately), which may be insufficient to maintain data integrity. Data should be considered suspect and verified as correct. A fresh battery should be installed. The SNAPHAT top may be replaced while VCC is applied to the device.
Note:
This will cause the clock to lose time during the interval the battery/crystal is removed. Battery monitoring is a useful technique only when performed periodically. The M48T37Y/V only monitors the battery when a nominal VCC is applied to the device. Thus applications which require extensive durations in the battery back-up mode should be powered-up periodically (at least once every few months) in order for this technique to be beneficial. Additionally, if a battery low is indicated, data integrity should be verified upon power-up via a checksum or other technique.
3.10
Initial power-on defaults
Upon application of power to the device, the following register bits are set to a '0' state: WDS; BMB0-BMB4; RB0-RB1; AFE; ABE; W; R; and FT (see Table 7). Table 7. Default values
Condition Initial power-up (Battery attach for SNAPHAT(R))(2) Subsequent power-up / RESET(3) Power-down
(4)
W 0 0 0
R 0 0 0
FT 0 0 0
AFE 0 0 1
ABE 0 0 1
Watchdog register(1) 0 0 0
1. WDS, BMB0-BMB4, RBO, RB1. 2. State of other control bits undefined. 3. State of other control bits remains unchanged. 4. Assuming these bits set to '1' prior to power-down.
3.11
VCC noise and negative going transients
ICC transients, including those produced by output switching, can produce voltage fluctuations, resulting in spikes on the VCC bus. These transients can be reduced if capacitors are used to store energy which stabilizes the VCC bus. The energy stored in the bypass capacitors will be released as low going spikes are generated or energy will be absorbed when overshoots occur. A ceramic bypass capacitor value of 0.1 F (as shown in Figure 9) is recommended in order to provide the needed filtering. In addition to transients that are caused by normal SRAM operation, power cycling can generate negative voltage spikes on VCC that drive it to values below VSS by as much as
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Clock operations
one volt. These negative spikes can cause data corruption in the SRAM while in battery backup mode. To protect from these voltage spikes, it is recommended to connect a Schottky diode from VCC to VSS (cathode connected to VCC, anode to VSS). Schottky diode 1N5817 is recommended for through hole and MBRS120T3 is recommended for surface mount. Figure 9. Supply voltage protection
VCC VCC
0.1F
DEVICE
VSS
AI02169
Figure 10. Crystal accuracy across temperature
Frequency (ppm) 20 0 -20 -40 -60 -80 -100 -120 -140 -160 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80
AI00999
F = -0.038 ppm (T - T )2 10% 0 F C2 T0 = 25 C
Temperature C
Figure 11. Clock calibration
NORMAL
POSITIVE CALIBRATION
NEGATIVE CALIBRATION
AI00594B
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Maximum ratings
M48T37Y, M48T37V
4
Maximum ratings
Stressing the device above the rating listed in the absolute maximum ratings table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 8.
Symbol TA TSTG TSLD(1) VIO VCC IO PD
Absolute maximum ratings
Parameter Ambient operating temperature Storage temperature (VCC off, oscillator off) Lead solder temperature for 10 seconds Input or output voltages M48T37Y M48T37V M48T37Y M48T37V Grade 1 Grade 6 SNAPHAT(R) SOH44 Value 0 to 70 -40 to 85 -40 to 85 -55 to 150 260 -0.3 to 7 -0.3 to 4.6 -0.3 to 7 -0.3 to 4.6 10 1 Unit C C C C C V V V V mA W
Supply voltage Output current Power dissipation
1. For SOH44 package, lead-free (Pb-free) lead finish: reflow at peak temperature of 260 C (the time above 255 C must not exceed 30 seconds).
Caution: Caution:
Negative undershoots below -0.3 V are not allowed on any pin while in the battery backup mode. Do NOT wave solder SOIC to avoid damaging SNAPHAT(R) sockets.
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DC and AC parameters
5
DC and AC parameters
This section summarizes the operating and measurement conditions, as well as the DC and AC characteristics of the device. The parameters in the following DC and AC characteristic tables are derived from tests performed under the measurement conditions listed in the relevant tables. Designers should check that the operating conditions in their projects match the measurement conditions when using the quoted parameters. Table 9. Operating and AC measurement conditions
Parameter Supply voltage (VCC) Ambient operating temperature (TA) Load capacitance (CL) Input rise and fall times Input pulse voltages Input and output timing ref. voltages Grade 1 Grade 6 M48T37Y 4.5 to 5.5 0 to 70 -40 to 85 100 10 0 to 3 1.5 M48T37V 3.0 to 3.6 0 to 70 -40 to 85 50 10 0 to 3 1.5 Unit V C C pF ns V V
Note:
Output Hi-Z is defined as the point where data is no longer driven. Figure 12. AC testing load circuit
DEVICE UNDER TEST
645
(1) CL = 100pF
1.75V
CL includes JIG capacitance
AI02325
1. 50 pF for M48T37V.
Note:
Excluding open-drain output pins Table 10.
Symbol CIN CIO
(3)
Capacitance
Parameter(1)(2) Input capacitance Input / output capacitance Min Max 10 10 Unit pF pF
1. Effective capacitance measured with power supply at 5 V. Sampled only, not 100% tested. 2. At 25 C, f = 1 MHz. 3. Outputs deselected.
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DC and AC parameters Table 11. DC characteristics
M48T37Y Symbol Parameter Test condition(1) Min ILI(2) ILO
(3)
M48T37Y, M48T37V
M48T37V -100 Unit Max 1 1 33 2 2 -0.3 2.2 0.8 VCC + 0.3 0.4 0.4 2.4 A A mA mA mA V V V V V
-70 Max 1 1 50 3 3 -0.3 2.2 0.8 VCC + 0.3 0.4 0.4 2.4 Min
Input leakage current Output leakage current Supply current Supply current (standby) TTL Supply current (standby) CMOS Input low voltage Input high voltage Output low voltage (standard)
0 V VIN VCC 0 V VOUT VCC Outputs open E = VIH E = VCC - 0.2 V
ICC ICC1 ICC2 VIL VIH VOL VOH
IOL = 2.1 mA IOL = 10 mA IOH = -1 mA
Output low voltage (open drain) Output high voltage
1. Valid for ambient operating temperature: TA = 0 to 70 C or -40 to 85 C; VCC = 4.5 to 5.5 V or 3.0 to 3.6 V (except where noted). 2. WDI internally pulled down to VSS through a 100 k resistor. 3. Outputs deselected.
Figure 13. Power down/up mode AC waveforms
VCC VPFD (max) VPFD (min) VSO tF tFB tDR tREC RST tRB tR
INPUTS
VALID
DON'T CARE
VALID
HIGH-Z OUTPUTS VALID VALID
AI03078
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DC and AC parameters
Table 12.
Symbol tF(2) tFB(3) tR tRB tREC
(4)
Power down/up AC characteristics
Parameter(1) VPFD (max) to VPFD (min) VCC fall time VPFD (min) to VSS VCC fall time VPFD (min) to VPFD (max) VCC rise time VSS to VPFD (min) VCC rise time VPFD (max) to RST high Min 300 10 10 1 40 200 Max Unit s s s s ms
1. Valid for ambient operating temperature: TA = 0 to 70 C or -40 to 85 C; VCC = 4.5 to 5.5 V or 3.0 to 3.6 V (except where noted). 2. VPFD (max) to VPFD (min) fall time of less than tF may result in deselection/write protection not occurring until 200 s after VCC passes VPFD (min). 3. VPFD (min) to VSS fall time of less than tFB may cause corruption of RAM data 4. tREC (min) = 20 ms for industrial temperature range - grade 6 device.
Table 13.
Symbol VPFD
Power down/up trip points DC characteristics
Parameter(1) M48T37Y Power-fail deselect voltage M48T37V M48T37Y Battery backup switchover voltage M48T37V Grade 1 Expected data retention time Grade 6 5 10(3) 2.7 2.9 VBAT VPFD -100 mV 7 3.0 V V V Years Years Min 4.2 Typ 4.4 Max 4.5 Unit V
VSO tDR(2)
1. Valid for ambient operating temperature: TA = 0 to 70 C or -40 to 85 C; VCC = 4.5 to 5.5 V or 3.0 to 3.6 V (except where noted). 2. At 25 C, VCC = 0 V. 3. Using larger M4T32-BR12SH6 SNAPHAT(R) top (recommended for industrial temperature range - grade 6 device).
Note:
All voltages referenced to VSS.
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Package mechanical data
M48T37Y, M48T37V
6
Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK(R) packages, depending on their level of environmental compliance. ECOPACK(R) specifications, grade definitions and product status are available at: www.st.com. ECOPACK(R) is an ST trademark. Figure 14. SOH44 - 44-lead plastic small outline, 4-socket SNAPHAT(R) outline
A2 B e A C eB CP
D
N
E
H A1 L
SOH-A
1
Note:
Drawing is not to scale. Table 14. SOH44 - 44-lead plastic small outline, 4-socket SNAPHAT(R), package mechanical data
mm Symbol Typ A A1 A2 B C D E e eB H L a N CP 0.81 0.05 2.34 0.36 0.15 17.71 8.23 - 3.20 11.51 0.41 0 44 0.10 Min Max 3.05 0.36 2.69 0.46 0.32 18.49 8.89 - 3.61 12.70 1.27 8 0.032 0.002 0.092 0.014 0.006 0.697 0.324 - 0.126 0.453 0.016 0 44 0.004 Typ Min Max 0.120 0.014 0.106 0.018 0.012 0.728 0.350 - 0.142 0.500 0.050 8 inches
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Package mechanical data
Figure 15. SH - 4-pin SNAPHAT(R) housing for 48 mAh battery & crystal, pack. outline
A1
A2 A A3
eA D
B eB
L
E
SHTK-A
Note:
Drawing is not to scale. Table 15. SH - 4-pin SNAPHAT(R) housing for 48 mAh battery & crystal, package mechanical data
mm Symbol Typ A A1 A2 A3 B D E eA eB L 0.46 21.21 14.22 15.55 3.20 2.03 6.73 6.48 Min Max 9.78 7.24 6.99 0.38 0.56 21.84 14.99 15.95 3.61 2.29 0.018 0.835 0.560 0.612 0.126 0.080 0.265 0.255 Typ Min Max 0.385 0.285 0.275 0.015 0.022 0.860 0.590 0.628 0.142 0.090 inches
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Package mechanical data
M48T37Y, M48T37V
Figure 16. SH - 4-pin SNAPHAT(R) housing for 120 mAh battery & crystal, pack. outline
A1
A2 A A3
eA D
B eB
L
E
SHTK-A
Note:
Drawing is not to scale. Table 16. SH - 4-pin SNAPHAT(R) housing for 120 mAh battery & crystal, package mechanical data
mm Symbol Typ A A1 A2 A3 B D E eA eB L 0.46 21.21 17.27 15.55 3.20 2.03 8.00 7.24 Min Max 10.54 8.51 8.00 0.38 0.56 21.84 18.03 15.95 3.61 2.29 0.018 0.835 0.680 0.612 0.126 0.080 0.315 0.285 Typ Min Max 0.415 .0335 0.315 0.015 0.022 0.860 .0710 0.628 0.142 0.090 inches
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Part numbering
7
Part numbering
Table 17.
Example: Device type M48T Supply voltage and write protect voltage 37Y = VCC = 4.5 to 5.5 V; VPFD = 4.2 to 4.5 V 37V = VCC = 3.0 to 3.6 V; VPFD = 2.7 to 3.0 V Speed -70 = 70 ns (37Y) -10 = 100 ns (37V) Package MH(1) = SOH44 Temperature range 1 = 0 to 70 C 6 = -40 to 85 C(2) Shipping method blank = tubes (not for new design - use E) E = ECOPACK(R) package, tubes F = ECOPACK(R) package, tape & reel TR = tape & reel (not for new design - use F)
1. The SOIC package (SOH44) requires the SNAPHAT(R) battery package which is ordered separately under the part number "M4TXX-BR12SH" in plastic tube or "M4TXX-BR12SHTR" in tape & reel form (see Table ). 2. Not recommended for new design. Contact ST sales office for availability.
Ordering information scheme
M48T 37Y -70 MH 1 E
Caution:
Do not place the SNAPHAT battery package "M4TXX-BR12SH" in conductive foam as it will drain the lithium button-cell battery. For other options, or for more information on any aspect of this device, please contact the ST sales office nearest you. Table 18. SNAPHAT(R) battery table
Description Lithium battery (48 mAh) SNAPHAT(R) Lithium battery (120 mAh) SNAPHAT(R) Package SH SH
Part number M4T28-BR12SH M4T32-BR12SH
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Environmental information
M48T37Y, M48T37V
8
Environmental information
Figure 17. Recycling symbols
This product contains a non-rechargeable lithium (lithium carbon monofluoride chemistry) button cell battery fully encapsulated in the final product. Recycle or dispose of batteries in accordance with the battery manufacturer's instructions and local/national disposal and recycling regulations. Please refer to the following web site address for additional information regarding compliance statements and waste recycling. Go to www.st.com/rtc, then select "Lithium Battery Recycling" from "Related Topics".
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Revision history
9
Revision history
Table 19.
Date Dec-1999 07-Feb-2000 11-Jul-2000 19-Jun-2001 06-Aug-2001 15-Jan-2002 20-May-2002 31-Mar-2003 01-Apr-2004 08-Feb-2006 03-Aug-2007 24-Mar-2009 02-Aug-2010
Document revision history
Revision 1 2 2.1 3 3.1 3.2 3.3 4 5 6 7 8 9 First issue From preliminary data to datasheet; battery low flag paragraph changed; 100 ns speed class identifier changed (Table , 4) tFB changed (Table ); watchdog timer paragraph changed Reformatted; added temp./voltage info. to tables (Table 10, 11, , 4, , ) Fix text for setting the alarm clock (Figure 7) Fix footnote numbering (Table ) Modify reflow time and temperature footnote (Table 8) v2.2 template applied; data retention condition updated (Table ) Reformatted; updated with lead-free package information (Table 8, ) New template; updated lead-free text; fixed DC characteristics (Table 8, 11, ) Reformatted; added lead-free second level interconnect information to cover page and Section 6: Package mechanical data. Updated Table 8; Section 6: Package mechanical data; added Section 8: Environmental information; minor reformatting. Updated Features, Section 4, Table 17; reformatted document; minor textual changes. Changes
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M48T37Y, M48T37V
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