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| PJDLLLC70 Very Low Capacitance Diode Array This diode array is configured to protect up to two high speed data transmission lines, used in Low Voltage Differential Signal (LVDS) ports. Acting as a line terminator, minimizes overshoot and undershoot conditions due to bus impedance as well as protect against over-voltage events as electrostatic discharges. The line-line concept minimizes the problems to customers to re-route PCB lines, simplifying the design. SOT563 Package 6 5 4 1 2 SPECIFICATION FEATURES Maximum Capacitance of 1.2pF at 0Vdc 1MHz Line-to-Ground Maximum Leakage Current of 1A @ VRWM Industry Standard SMT Package SOT563 IEC61000-4-2 Full Compliance; 15kV Air, 8kV Contact* 100% Tin Matte finish (LEAD-FREE PRODUCT) 3 Line1 +VREF Line2 6 5 4 APPLICATIONS USB 2.0 and Firewire Port Protection HDMI Version 1.3 DVI 1 2 3 Line1 Gnd Line2 Note: pins 1and 6 (Line1) as well as pins 3 and 4 (Line2) must be connected externally, as the drawing attached below. MARKING : 70 I/O Line 1 GND I/O Line 2 1 6 2 5 +VREF 3 4 Line-line concept ease the PCB design, directly placing the device over the data lines, opening only the contact points. VREF is fixed by the operating voltage, referenced to the ground. MAXIMUM RATINGS Tj = 25C Unless otherwise noted Rating Peak Pulse Current (8/20s Waveform) Rectifier Repetitive Peak Reverse Voltage Operating Junction Temperature Range Storage Temperature Range Soldering Temperature, t max = 10s Symbol I PPM VRRM TJ Tstg TL Value 12 70 -55 to +125 -55 to +150 260 Units A V C C C Note: ESD Testing requires to connect a TVS between +VREF and GND, if there is no +VREF Bias connected. 7/23/2009 Page 1 www.panjit.com PJDLLLC70 ELECTRICAL CHARACTERISTICS Parameter Reverse Stand-Off Voltage Reverse Breakdown Voltage Reverse Leakage Current Diode Surge Forward Voltage (8/20s) Diode Surge Forward Voltage (8/20s) Diode Surge Forward Voltage (8/20s) Off State Capacitance Symbol V RWM VBR IR VFC VFC VFC CT I BR = 50A VR = 70V I pp = 1 A I pp = 5 A I pp = 12 A 0 Vdc Bias f = 1MHz Between I/O Line and GND 0 Vdc Bias f = 1MHz Between I/O lines Tj = 25C unless otherwise noted Conditions Min Typical Max 70 85 1 2 7 13 1.0 1.0 Units V V A V V V pF pF 7/23/2009 Page.2 www.panjit.com PJDLLLC70 PACKAGE DIMENSIONS - SOT563 APPLICATION EXAMPLE (USB2.0 port) 4 and 3 pins connected together through the same Data line D+ D+ Vbus+ (5V or 3.3V) D6 and 1 pins connected together through the same Data line D- 7/23/2009 Page.3 www.panjit.com |
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