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| CY8CMBR2044 Capacitive Button Controllers Capacitive Button Controllers Features Overview The CY8CMBR2044 incorporates several innovative features to save time, money, and can quickly enable a capacitive touch sensing UI in your next design. It does not require any software tools or coding because system configuration is done using hardware. These features enable a broader audience of designers to implement capacitive buttons without learning new tool sets and developing code. In addition, this device is enabled with Cypress's revolutionary SmartSense auto tuning algorithm. SmartSense ends the need to manually tune the UI during development as well as the required retuning during production ramp. This saves valuable engineering time, test time, production yield loss, and speeds the time to volume. The CY8CMBR2044 CapSense controller supports up to four capacitive sensing buttons and four GPOs. The GPO is an active low output controlled directly by the CapSense input making it ideal for a wide variety of consumer, industrial, and medical applications. The wide operating range of 1.71 V to 5.5 V enables unregulated battery operation, further saving component cost. This device supports ultra low power consumption in run mode as well as deep sleep modes to enhance battery life. In addition to this, the device also supports many advanced features which enhance the robustness and user interface of the end solution. Some of the key advanced features include FSS, which provides robust sensing even with closely spaced sensors. This is a critical requirement in small form factor applications. Another key feature is failure mode analysis that helps ease production line testing and reduces manufacturing costs. Easiest to use capacitive button controller Hardware configurable 4-button solution No software tools or programming required General purpose outputs (GPO) support direct LED drive Robust noise performance High sensitivity, low noise capacitive sensing algorithm Strong immunity to radio frequency (RF) and alternating current (AC) noise Low radiated noise emission SmartSenseTM auto tuning No manual tuning required (reduces time to market) (R) All CapSense parameters are automatically set in runtime Ensures signal to noise ratio (SNR) of 5:1 or greater Supports wide range of input capacitance (5 pF to 40 pF) Advanced features Toggle feature on GPO Flanking sensor suppression (FSS) provides robust sensing even with closely spaced sensors Delay Off feature (configurable LED run time) Easier production line testing * Serial data out for debug * Failure mode analysis of CapSense buttons Wide operating range 1.71 V to 5.5 V ideal for unregulated battery applications Low power consumption [1] Supply current in run mode as low as 15 A for every button Deep sleep current: 100 nA Industrial temperature range: -40 C to + 85 C 16-pad quad flat no leads (QFN) package (3 mm x 3 mm x 0.6 mm) Note 1. Power consumption calculated with 1.7% touch time, 500 ms scan rate, and CP of each sensor < 19 pF. Cypress Semiconductor Corporation Document Number: 001-57451 Rev. *C * 198 Champion Court * San Jose, CA 95134-1709 * 408-943-2600 Revised July 29, 2010 [+] Feedback CY8CMBR2044 Contents Capacitive Button Controllers ...........................................1 Features ...............................................................................1 Overview ..............................................................................1 Pinout ..................................................................................3 Typical Circuits ...................................................................4 Schematic 1: 4-Buttons, 4-LEDs with Auto Reset Enabled ......................................................4 Schematic 2: 3-Buttons, 3-LEDs, 2-Outputs to Master, and Advanced Features Enabled .........................................5 Device Features ..................................................................6 CapSense Buttons ........................................................6 SmartSense Auto Tuning ..............................................6 General Purpose Outputs ..............................................6 Hardware Configuration ................................................6 Sensor Auto Reset ........................................................6 Toggle ...........................................................................7 Delay Off .......................................................................7 Flanking Sensor Suppression .......................................9 Failure Mode Analysis ...................................................9 Debug Data .................................................................10 Device Operating Modes ..................................................12 Low Power Sleep Mode ..............................................12 Deep Sleep Mode ........................................................15 Additional Components to Enable Advanced Features 15 Response Time .................................................................15 Layout Guidelines and Best Practices ...........................16 CapSense Button Shapes ...........................................17 Button Layout Design ..................................................17 Recommended Via Hole Placement ...........................17 Example PCB Layout Design with Four CapSense Buttons and Four LEDs ............................18 Electrical Specifications ..................................................19 Absolute Maximum Ratings .........................................19 Operating Temperature ...............................................19 DC Electrical Characteristics .......................................19 AC Electrical Specifications .........................................21 CapSense Specifications ............................................21 Ordering Information ........................................................22 Ordering Code Definitions ...........................................22 Package Information ........................................................23 Thermal Impedances by Package ...............................23 Solder Reflow Peak Temperature ...............................23 Package Diagram ........................................................23 Document Conventions ...................................................24 Acronyms Used ...........................................................24 Units of Measure .........................................................24 Document History Page ...................................................25 Sales, Solutions, and Legal Information ........................26 Worldwide Sales and Design Support .........................26 Products ......................................................................26 PSoC Solutions ...........................................................26 Document Number: 001-57451 Rev. *C Page 2 of 26 [+] Feedback CY8CMBR2044 Pinout Table 1. Pin Diagram and Definitions - CY8CMBR2044 Pin 1 2 3 4 5 6 7 8 9 Label GPO1 GPO0 Toggle/ FSS Delay CS0 CS1 VSS CS2 ARST Type DO DO AI AI AIO AIO P AIO Description GPO activated by CS1 GPO activated by CS0 If Unused Leave open Leave open Controls FSS and toggle. For Ground details refer to Table 5 on page 7 Controls delay off time. For Ground details refer to Table 6 on page 8 CapSense input, controls GPO0 Ground or serial debug data out CapSense input, controls GPO1 Ground or serial debug data out Ground CapSense input, controls GPO2 Ground or serial debug data out 16 15 AIDO Controls auto reset delay. For Leave open details on auto reset delay, refer to Table 4 on page 6 AIO DI CapSense input, controls GPO3 Ground or serial debug data out Device reset, active high, with internal pull down Leave open 10 11 12 CS3 XRES ScanRate/ AI Sleep VDD GPO3 CMOD P DO AI Controls scan rate and deep Ground sleep. For details refer to Table 9 on page 13 Power GPO activated by CS3 External integrating capacitor, connect a 2.2 nF (5%) to ground GPO activated by CS2 Leave open Leave open 13 14 15 16 GPO2 DO Document Number: 001-57451 Rev. *C CS0 CS1 Vss CS2 5 6 7 8 GPO1 GPO0 Toggle/FSS Delay 1 12 QFN 2 11 (Top View) 3 10 4 9 14 13 GPO2 CMOD GPO3 VDD ScanRate/Sleep XRES CS3 ARST Page 3 of 26 [+] Feedback CY8CMBR2044 Typical Circuits Schematic 1: 4-Buttons, 4-LEDs with Auto Reset Enabled In the above schematic, the device is configured to support: Four CapSense buttons driving four LEDs Sensor auto reset (ARST) pin pulled down with a 5 Kresistor to set sensor auto reset time to 20 seconds Connect a 5.6 Kresistor on R9 or R12 to enable the serial debug data out feature Document Number: 001-57451 Rev. *C Page 4 of 26 [+] Feedback CY8CMBR2044 Schematic 2: 3-Buttons, 3-LEDs, 2-Outputs to Master, and Advanced Features Enabled In the above schematic the device is configured to support: Three CapSense buttons driving three outputs Three LEDs driven by GPO0, GPO1, and GPO2 CS3 is disabled (grounded); therefore, GPO3 is left floating FSS enabled, toggle disabled Delay off - 1 second Scan rate - 30 ms Sensor auto reset - 20 seconds Connect a 5.6 Kon resistor R11 to enable serial debug data out feature Document Number: 001-57451 Rev. *C Page 5 of 26 [+] Feedback CY8CMBR2044 Device Features Table 2. Device Feature List Feature Four GPOs Flanking sensor suppression Toggle Sensor auto reset (ARST) Delay Off Failure mode analysis Serial debug data Sleep and deep sleep Benefits/ End Application Problem Solved Driving LED, mechanical button replacement Provides more discrimination between closely spaced sensors Mechanical button replacement Prevents stuck sensor, i.e. metal object placed close to sensor Provides better feedback based on button press Support for production testing and debugging Support for production testing and validating design Low power consumption General Purpose Outputs The GPOx is driven by CSx Active low output - supports sinking configuration If CSx is disabled (grounded), then GPOx must be left floating A 5 ms pulse is triggered on the GPOx if the CSx fails the power on self test (POST) Hardware Configuration Advanced features are configured in hardware using external resistors The resistances on hardware configurable pins are determined once at power on Sensor Auto Reset The sensor auto reset time is controlled by the hardware configuration on the ARST pin. Refer to Table 4 for details This feature decides the maximum time the GPOx is driven when CSx is continuously pressed After the sensor auto reset has been triggered, the CSx hold time of that sensor after the button has been released is given in Table 3. Scan rate is determined by the hardware configuration as shown in Table 9 on page 13 CapSense Buttons Device supports up to four CapSense buttons Ground the CSx pin to disable CapSense input 2.2 nF capacitor must be connected on the CMOD pin for proper CapSense operation Table 3. Sensor Hold Time After Auto Reset Sensor Press Time after Sensor Auto Reset < 2 sec > 2 sec Sensor Hold Time (ms) 220 ScanRate + 200 SmartSense Auto Tuning Device supports auto tuning of CapSense parameters No manual tuning required; all parameters are set by the device Compensates printed circuit board (PCB), device process variations, and PCB vendor changes The parasitic capacitance (CP) of each button must be less than 40 pF for proper CapSense operation Table 4. ARST Pin Hardware Configuration Hardware Configuration Pin connected to ground Resistor of 5 K (10%) ohms connected to ground Pin connected to VDD or left floating Sensor Max ON Time (sec) 5 20 No limit Figure 1. Example of Sensor Auto Reset on GP0 Document Number: 001-57451 Rev. *C Page 6 of 26 [+] Feedback CY8CMBR2044 Toggle The Toggle feature is controlled by the hardware configuration on Toggle/FSS pin. For details, refer to Table 5 The state of GPx changes on every rising edge of CSx CapSense status When Toggle is enabled, Delay Off is disabled Figure 2. Example of Toggle Feature on GP0 Table 5. Toggle/FSS Hardware Pin Configuration Sl. No. 1 2 3 4 Toggle/FSS Pin Hardware Configuration Pin connected to ground or left floating 1.5 k (5%) resistor to ground 5.1 k (5%) resistor to ground Pin connected to VDD Toggle Enabled No Yes No Yes FSS Enabled No No Yes Yes Delay Off Delay off time is controlled by the hardware configuration on the delay pin. For details, see Table 6 on page 8 To enable delay off with Delay `D' (multiple of 20 ms), a resistor `R' should be connected between the delay pin and ground where R = (Dx4) + 40 s Delay off value specifies the duration for which the GPOx is driven low after the corresponding CapSense input CSx is released. See Figure 3 on page 8 When a button gets reset, delay off is not applied on the corresponding GPO Delay off feature is applicable to only one GPO at any point of time. In Figure 3 on page 8, GPO0 goes high prematurely (prior to delay off time) because CS1 button is released. Therefore, the delay counter is reset. Now, GPO1 remains low for delay off time after releasing CS1 Delay off feature is applicable to the GPO of the last button released Delay off range: 0 ms to 2000 ms Document Number: 001-57451 Rev. *C Page 7 of 26 [+] Feedback CY8CMBR2044 Figure 3. Example Delay Off Timing Diagram on GP0 and GP1 Table 6. Delay Off Pin Hardware Configuration Pin Configuration Grounded (default) 120 s (1%) to ground 200 s (1%) to ground 280 s (1%) to ground . . 7960 s (1%) to ground 8040 s (1%) to ground > 8040 s (1%) to ground Pulled to VDD Floating Approximate Delay Off Time (in ms) 0 20 40 60 . . 1980 2000 2000 2000 2000 Document Number: 001-57451 Rev. *C Page 8 of 26 [+] Feedback CY8CMBR2044 Flanking Sensor Suppression Provides discrimination between closely spaced sensors At any point of time, only one sensor is reported as ON The first sensor touched is reported as ON until it is released, even if other sensors are pressed Figure 4. Sensor Status with Respect to Finger Touch when FSS is Enabled Failure Mode Analysis A built-in Power On Self Test (POST) mechanism detects the following at power on reset (POR), which can be useful in production testing. Sensor Shorted to Ground If a sensor is disabled a 5 ms pulse is sent out on the corresponding GPO within 175 ms of power on. Figure 5. Sensor Shorted to Ground Sensor to Sensor Short Any Sensors that are shorted together is disabled and 5ms pulse is sent out on the GPOs of the shorted sensors within 175ms of power on. Figure 7. Sensor to Sensor Short Proper Value of CMOD Recommended value of CMOD is 2 nF to 2.4 nF. If CMOD of < 1 nF or > 4 nF is connected, all sensors are disabled and a 5 ms pulse is sent out on all the GPOs within 175 ms of power on. Sensor Shorted to VDD If any sensor is shorted to VDD that sensor is disabled and a 5 ms pulse is sent out on the corresponding GPO within 175 ms of power on. Figure 6. Sensor Shorted to VDD Sensor CP > 40 pF If the parasitic capacitance (CP) of any sensor exceeds 40 pF that sensor is disabled and a 5 ms pulse is sent out on the corresponding GPO within 175 ms of power on. Document Number: 001-57451 Rev. *C Page 9 of 26 [+] Feedback CY8CMBR2044 Figure 8. Example Showing CS0 and CS1 Passing the POST and CS2 and CS3 are Failing 5 ms pulse Max time to get 5 ms pulse is 175 ms after power up In Figure 8 CS0 and CS1 are enabled; CS2 and CS3 are disabled because the POST failed for these sensors. Therefore, a 5 ms pulse is observed on GPO2 and GPO3. Serial data is sent out with ~115,200 baud rate Firmware revision, CapSense status, GPO status, raw count, baseline, difference count, and parasitic capacitance of all sensors are sent out For designs having a maximum of three CapSense buttons, Cypress recommends to take the debug data on a CapSense button that is not used in design For designs with four CapSense buttons, Cypress recommends taking debug data on two CapSense buttons. For example, pull down CS0 with a 5.6 kresistor and read data of CS1, CS2, and CS3. Next, pull down CS1 with a 5.6 k resistor and read data of CS0, CS2, and CS3 Debug Data To enable this feature pull down any one of the CapSense pins with a 5.6 k resistor to ground. Data is sent out on the same CapSense pin If more than one CapSense pin is pulled down, debug data is sent out only on one CapSense pin and the priority is CS0 > CS1 > CS2 > CS3 The Cypress multi chart tool (see application note AN2397) can be used to view the data Table 7. Data Format in Multi-chart: Serial TX8 Sl No 0 1 2 3 4 5 Raw Count Array MSB 0x00 0x00 LSB FW_Revision CS0_ CP Baseline Array MSB CS _Status 0x00 LSB GPO_Status CS1_CP CS0_Baseline CS1_Baseline CS2_Baseline CS3_Baseline MSB 0x00 0x00 Signal Array LSB CS2_CP CS3_ CP CS0_DiffCount CS1_DiffCount CS2_DiffCount CS3_DiffCount CS0_RawCount CS1_RawCount CS2_RawCount CS3_RawCount Document Number: 001-57451 Rev. *C Page 10 of 26 [+] Feedback CY8CMBR2044 Table 8. Serial Data Output Byte 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 Data 0x0D 0x0A 0x00 FW_Revision 0x00 CS0_CP CS0_RawCount_LSB CS0_RawCount_MSB CS1_RawCount_LSB CS1_RawCount_MSB CS2_RawCount_LSB CS2_RawCount_MSB CS3_RawCount_LSB CS3_RawCount_MSB CS _Status GPO_Status 0x00 CS1_CP CS0_ Baseline _LSB CS0_ Baseline _MSB CS1_ Baseline _LSB CS1_ Baseline _MSB CS2_ Baseline _LSB CS2_ Baseline _MSB CS3_ Baseline _LSB CS3_ Baseline _MSB 0x00 CS2_CP 0x00 CS3_CP CS0_ DiffCount _LSB CS0_ DiffCount _MSB CS1_ DiffCount _LSB CS1_ DiffCount _MSB CS2_ DiffCount _LSB CS2_ DiffCount _MSB CS3_ DiffCount _LSB CS3_ DiffCount _MSB 0x00 0xFF 0xFF Notes Dummy data for multi chart - - - CS0 parasitic capacitance in Hex Unsigned 16-bit integer - Unsigned 16-bit integer - Unsigned 16-bit integer - Unsigned 16-bit integer - Gives CapSense button status, least significant bit (LSB) contains CS0 status Gives GPO status, LSB contains GP0 status - CS1 parasitic capacitance in Hex Unsigned 16-bit integer - Unsigned 16-bit integer - Unsigned 16-bit integer - Unsigned 16-bit integer - - CS2 parasitic capacitance in Hex - CS3 parasitic capacitance in Hex Unsigned 16-bit integer - Unsigned 16-bit integer - Unsigned 16-bit integer - Unsigned 16-bit integer - Dummy data for multi chart Document Number: 001-57451 Rev. *C Page 11 of 26 [+] Feedback CY8CMBR2044 Device Operating Modes There are two device operating modes: Low power sleep mode Deep sleep mode Low Power Sleep Mode The following flow chart describes the low power sleep mode operation. Figure 9. Low Power Sleep Mode Operation Scan all Sensors with 20 ms Scan rate (Scan time + sleep time) NO NO button pressed for 2 secs? YES YES Scan all sensors with user defined scan rate. NO Is Any Sensor active ? Figure 10. Low Power Sleep Mode Implementation To enable low power sleep mode, the hardware configurable pin ScanRate/Sleep should be pulled down to ground with resistor `R' (1%). The scan rate values for different resistor values are given in Table 9 on page 13. The range of scan rate is 20 to 530 ms. . Document Number: 001-57451 Rev. *C Page 12 of 26 [+] Feedback CY8CMBR2044 Table 9. ScanRate/Sleep Pin Hardware Configuration Resistor R (1%) in ohms Approximate ScanRate (in ms) Resistor R (1%) in ohms Approximate ScanRate (in ms) 60 185 310 435 560 685 810 935 1060 1185 1310 1435 1560 1685 1810 1935 2060 2185 2310 2435 2560 2685 2810 2935 3060 3185 3310 3435 3560 3685 3810 3935 20 22 24 27 30 34 38 42 46 51 55 61 66 71 77 83 89 96 102 107 115 122 129 137 144 152 159 167 175 183 192 200 4060 4185 4310 4435 4560 4685 4810 4935 5060 5185 5310 5435 5560 5685 5810 5935 6060 6185 6310 6435 6560 6685 6810 6935 7060 7185 7310 7435 7560 7685 7810 7935 209 217 226 235 244 253 263 272 282 291 301 311 321 331 341 352 362 373 383 394 405 416 427 438 449 461 472 484 495 507 519 531 Document Number: 001-57451 Rev. *C Page 13 of 26 [+] Feedback CY8CMBR2044 Figure 11. Average Current vs Scan Rate[2] Note 2. Number of sensors = 3, Cp<19 pF, 0% touch time, VDD = 3 V Document Number: 001-57451 Rev. *C Page 14 of 26 [+] Feedback CY8CMBR2044 Deep Sleep Mode Figure 12. ScanRate/Sleep Pin Connection to Enable Deep Sleep Mode External Res R ScanRate/Sleep Host Pin controlling ScanRate/Sleep Pin CY8CMBR2044 HOST To enable the deep sleep mode, the hardware configuration pin ScanRate/Sleep should be connected to the master device as shown in Figure 9 on page 12. ScanRate/Sleep pin should be connected to VDD for the device to go into deep sleep. In deep sleep mode, all blocks are turned off and the device power consumption is 0.1 A. There is no CapSense scanning in deep sleep mode. ScanRate/Sleep pin should be pulled low for the device to wake up from deep sleep. When device comes out of deep sleep mode, the CapSense system is reinitialized. Typical time for reinitialization is 8 ms. Any button press within this time is not reported. After the device comes out of deep sleep, the device operates in low power sleep mode. If the ScanRate/Sleep pin is pulled high at power on, then the device does not go to deep sleep immediately. The device goes to deep sleep after initializing all internal blocks and scanning all sensors once. If the ScanRate/Sleep pin is pulled high at power on, then the scan rate is calculated when the device is taken out of Deep Sleep by the master. Additional Components to Enable Advanced Features Sl. No 1 Feature Low power sleep and deep sleep Toggle/FSS Delay Off Sensor auto reset Resistors required 1 Notes Deep sleep is controlled by a master device. When the device comes out of deep sleep, it enters into low power sleep mode based on settings. Resistor is not required if both features are not used. To enable both the features only one resistor is required. Resistor is not required if both features are not used. Resistor is not required if the feature is not used. Resistor is not required if the feature is not used. 2 3 4 1 1 1 Response Time Response time is the minimum amount of time the button should be touched for the device to detect as valid button press. Condition First button press Consecutive button press after first button press Response time (in ms) Scan rate value + 20. For scan rate value, see Table 9 on page 13. 80 Document Number: 001-57451 Rev. *C Page 15 of 26 [+] Feedback CY8CMBR2044 Layout Guidelines and Best Practices Sl. No. 1 2 3 Category Button shape Button size Button-button spacing Min - 5 mm = Button Ground Clearance 0.5 mm - - - 0.17 mm - Max - 15 mm - Recommendations/Remarks Solid round pattern, round with LED hole, rectangle with round corners 10 mm 8 mm (Y dimension in Button Layout Design on page 17) Button ground clearance = Overlay thickness (X dimension in Button Layout Design on page 17) Hatched ground 7 mil trace and 45 mil grid (15% filling) Hatched ground 7 mil trace and 70 mil grid (10% filling) < 100 mm 0.17 mm (7 mil) Traces should be routed on the non sensor side. If any non CapSense trace crosses CapSense trace, ensure that intersection is orthogonal Via should be placed near the edge of the button/slider to reduce trace length thereby increasing sensitivity 10 mil 1 Place CapSense series resistors close to the device for noise suppression. CapSense resistors have highest priority; place them first 20 mil Mount the device on the layer opposite to sensor. The CapSense trace length between the device and sensors should be minimum (see trace length above) Top layer - sensors and bottom layer - device, other components and traces Top layer - sensors, second layer - CapSense traces and VDD (avoid VDD traces below the sensors), third layer - hatched ground, bottom layer - CapSense IC or device, other components, and non CapSense traces 1 mm Should be non-conductive material. Glass, ABS plastic, formica, wood, and so on. There should be no air gap between PCB and overlay. Use adhesive to stick the PCB and overlay Adhesive should be non conductive and dielectrically homogenous. 467MP and 468MP adhesives made by 3M are recommended Cut a hole in the sensor pad and use rear mountable LEDs. Refer to "Example PCB Layout Design with Four CapSense Buttons and Four LEDs" on page 18 Standard board thickness for CapSense FR4 based designs is 1.6 mm 4 5 6 7 8 9 Button ground clearance Ground flood - top layer Ground flood - bottom layer Trace length from sensor to CapSense IC pins Trace width Trace routing 2 mm - - 200 mm 0.20 mm - 10 Via position for the sensors - - 11 12 13 Via hole size for sensor traces No. of via on sensor trace Distance of CapSense series resistor from sensor pin Distance between any CapSense trace to ground flood Device placement - 1 - - 2 10 mm 14 15 10 mil - 20 mil - 16 17 Placement of components in two layer PCB Placement of components in four layer PCB - - - - 18 19 Overlay Thickness Overlay material 0 mm - 5 mm - 20 Overlay Adhesives - - 21 LED Back Lighting - - 22 Board Thickness - - Document Number: 001-57451 Rev. *C Page 16 of 26 [+] Feedback CY8CMBR2044 CapSense Button Shapes Button Layout Design X: Button to ground clearance (Refer to Layout Guidelines and Best Practices on page 16) Y: Button to button clearance (Refer to Layout Guidelines and Best Practices on page 16) Recommended Via Hole Placement Document Number: 001-57451 Rev. *C Page 17 of 26 [+] Feedback CY8CMBR2044 Example PCB Layout Design with Four CapSense Buttons and Four LEDs Figure 13. Top Layer Figure 14. Bottom Layer Document Number: 001-57451 Rev. *C Page 18 of 26 [+] Feedback CY8CMBR2044 Electrical Specifications Absolute Maximum Ratings Parameter TSTG Description Storage temperature Min -55 Typ 25 Max +125 Unit C Notes Higher storage temperatures reduce data retention time. Recommended storage temperature is +25 C 25 C. Extended duration storage temperatures above 85 C degrades reliability. VDD VIO IMIG ESD LU Supply voltage relative to VSS -0.5 - - - - - +6.0 VDD + 0.5 +50 - 200 V V mA V mA Human body model ESD In accordance with JESD78 standard DC voltage on CapSense inputs and VSS - 0.5 digital output pins Maximum current into any GPO output pin Electro static discharge voltage Latch up current -25 2000 - Operating Temperature Parameter TA TJ Description Ambient temperature Operational die temperature Min -40 -40 Typ - - Max +85 +100 Unit C C Notes DC Electrical Characteristics DC Chip Level Specifications Parameter VDD IDD IDA IDS IAV1 [1, 2, 3] Description Supply voltage Supply current Active current Deep sleep current Average current Min 1.71 - - - - Typ - 2.88 2.88 0.1 40 Max 5.5 4.0 4.0 0.5 - Unit V mA mA A A Notes Conditions are VDD = 3.0 V, TA = 25 C Conditions are VDD = 3.0 V, TA = 25 C, continuous sensor scan Conditions are VDD = 3.0 V, TA = 25 C Conditions are VDD = 3.0 V, TA = 25 C, 4 - buttons used, 0% touch time, CP of all sensors<19 pF and scan rate = 530 ms Conditions are VDD = 3.0 V, TA = 25 C, 4 - buttons used, 0% touch time, CP of all sensors>19 pF and scan rate = 530 ms Conditions are VDD = 3.0 V, TA = 25 C, 4 - buttons used, 100% touch time, CP of all sensors<19 pF and scan rate = 20 ms Conditions are VDD = 3.0 V, TA = 25 C, 4 - buttons used, 100% touch time, CP of all sensors>19 pF and <40 pF, scan rate = 20 ms IAV2 Average current - 63 - A IAV3 Average current - 1 - mA IAV4 Average current - 1.6 - mA 1. When VDD remains in the range from 1.75 V to 1.9 V for more than 50 s, the slew rate when moving from the 1.75 V to 1.9 V range to greater than 2 V must be slower than 1 V/500 s. This helps to avoid triggering POR. The only other restriction on slew rates for any other voltage range or transition is the SRPOWER_UP parameter. 2. If you power down the device, make sure that VDD falls below 100 mV before powering back up. 3. For proper CapSense block functionality, if the drop in VDD exceeds 5% of the base VDD, the rate at which VDD drops should not exceed 200 mV/s. Base VDD can be between 1.8 V and 5.5 V. Document Number: 001-57451 Rev. *C Page 19 of 26 [+] Feedback CY8CMBR2044 DC General Purpose I/O Specifications These tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 3.0 V to 5.5 V and -40 C = TA = 85C, 2.4 V to 3.0 V and -40 C = TA = 85 C, or 1.71 V to 2.4 V and -40 C = TA = 85 C, respectively. Typical parameters apply to 5 V and 3.3 V at 25 C and are for design guidance only. Table 10. 3.0 V to 5 V DC General Purpose I/O Specifications Parameter VOH1 VOH2 VOH3 VOL Description High output voltage on GP0, GP1, GP2, GP3 High output voltage on GP0, GP1 High output voltage on GP2, GP3 Low output voltage Min VDD - 0.2 VDD - 0.9 VDD - 0.9 - Typ - - - - Max - - - 0.75 Unit V V V V Notes IOH < 10 A, maximum of 40 A source current in all I/Os IOH = 1 mA, maximum of 2 mA source current in all I/Os IOH = 5 mA, maximum of 10 mA source current in all I/Os IOL = 25 mA/pin, VDD > 3.30, maximum of 60 mA sink current on GPO0, GPO1, GPO2, GPO3 Table 11. 2.4 V to 3.0 V DC General Purpose I/O Specifications Parameter VOH1 VOH2 VOH3 VOL Description High output voltage on GP0, GP1, GP2, GP3 High output voltage on GP0, GP1 High output voltage on GP2, GP3 Low output voltage Min VDD - 0.2 VDD - 0.4 VDD - 0.5 - Typ - - - - Max - - - 0.72 Unit V V V V Notes IOH < 10 A, maximum of 40 A source current in all I/Os IOH = 0.2 mA, maximum of 0.4 mA source current in all I/Os IOH = 2 mA, maximum of 4 mA source current in all I/Os IOL = 10 mA/pin, maximum of 30 mA sink current on GPO0, GPO1, GPO2, GPO3 Table 12. 1.71V to 2.4V DC General Purpose I/O Specifications Parameter VOH1 VOH2 VOH3 VOH4 VOL Description High output voltage on GP0,GP1 High output voltage on GP0,GP1 High output voltage on GP2,GP3 High output voltage on GP2,GP3 Low output voltage Min VDD - 0.2 VDD - 0.5 VDD - 0.2 VDD - 0.5 - Typ - - - - - Max - - - - 0.4 Unit V V V V V Notes IOH =10 A, maximum of 20 A source current in all I/Os IOH = 0.5 mA, maximum of 1 mA source current in all I/Os IOH = 100 A, maximum of 200 A source current in all I/Os IOH = 2 mA, maximum of 4 mA source current in all I/Os IOL = 5 mA/pin, maximum of 20 mA sink current on GPO0, GPO1, GPO2, GPO3 Document Number: 001-57451 Rev. *C Page 20 of 26 [+] Feedback CY8CMBR2044 AC Electrical Specifications AC Chip Level Specifications Parameter SRPOWER_UP TXRST TXRST2 Description Power supply slew rate External reset pulse width at power up External reset pulse width after power up Min - 1 10 Max 250 - - Unit V/ms ms s Notes VDD slew rate during power up After supply voltage is valid Applies after part has booted AC General Purpose I/O Specifications Parameter TRise1 TRise2 TRise3 TRise2 TRise4 TFall2 Description Rise time on GPO0 and GPO1, Cload = 50 pF Rise time on GPO2 and GPO3, Cload = 50 pF Rise time on GPO0 and GPO1, Cload = 50 pF Rise time on GPO2 and GPO3, Cload = 50 pF Fall time, Cload=50 pF all GPO outputs Fall time, Cload=50 pF all GPO outputs Min 15 10 15 10 10 10 Typ - - - - - - Max 80 50 80 80 50 70 Unit ns ns ns ns ns ns Notes VDD = 3.0 to 3.6 V, 10% - 90% VDD = 3.0 to 3.6 V, 10% - 90% VDD = 1.71 to 3.0V, 10% - 90% VDD = 1.71 to 3.0 V, 10% - 90% VDD = 3.0 to 3.6 V, 90% - 10% VDD = 1.71 to 3.0 V, 90% - 10% CapSense Specifications Parameter CP Description Parasitic capacitance Min 5.0 Typ - Max (CP+CF)<40 Unit pF Notes CP is the total capacitance seen by the pin when no finger is present. CP is sum of C_sensor, C_trace, and Capacitance of the vias and CPIN CPMAX CF CPIN CMOD Rs Maximum parasitic capacitance till which sensor works Finger capacitance Capacitive load on pins as input External integrating capacitor Series resistor between pin and the sensor 37 0.25 0.5 2 - 40 - 1.7 2.2 560 43 (CP+CF)<40 7 2.4 - pF pF pF nF Mandatory for CapSense to work Reduces the RF noise CF is the capacitance added by the finger touch Document Number: 001-57451 Rev. *C Page 21 of 26 [+] Feedback CY8CMBR2044 Ordering Information Ordering Code CY8CMBR2044-24LKXI CY8CMBR2044-24LKXIT Package Type 16 Pad (3 x 3 x 0.6 mm) QFN 16 Pad (3 x 3 x 0.6 mm) QFN (Tape and Reel) Operating Temperature Industrial Industrial CapSense Block Yes Yes CapSense Inputs 4 4 GPOs 4 4 XRES Pin Yes Yes Ordering Code Definitions Document Number: 001-57451 Rev. *C Page 22 of 26 [+] Feedback CY8CMBR2044 Package Information Thermal Impedances by Package Package 16 QFN Typical JA[3] 32.7 C/W Solder Reflow Peak Temperature Package 16 QFN Minimum Peak Temperature[4] 240 C Maximum Peak Temperature 260 C Package Diagram Figure 15. 16-Pad Quad Flat No Leads (QFN) No E-pad 3x3 mm Package Outline (Sawn) 2.9 3.1 0.20 min 1 2 0.20 DIA TYP. 2.9 3.1 1 1.5 (NOM) 2 0.45 0.55 PIN #1 ID 0.152 REF. 0.05 MAX 0.60 MAX 1.5 SEATING PLANE 0.30 0.18 0.50 TOP VIEW SIDE VIEW NOTES: BOTTOM VIEW PART NO. LG16A LD16A DESCRIPTION LEAD-FREE STANDARD 1. JEDEC # MO-220 2. Package Weight: 0.014g 3. DIMENSIONS IN MM, MIN MAX 001-09116 *E Notes 3. TJ = TA + Power x JA 4. Higher temperatures may be required based on the solder melting point. Typical temperatures for solder are 220 5 C with Sn-Pb or 245 5 C with Sn-Ag-Cu paste. Refer to the solder manufacturer specifications. Document Number: 001-57451 Rev. *C Page 23 of 26 [+] Feedback CY8CMBR2044 Document Conventions Acronyms Used The following table lists the acronyms that are used in this document. Table 13. Acronyms Acronym AC AI AIO AIDO DO P CF CP CS FSS GPO LSB MSB PCB POR POST RF analog input analog input/output analog input/digital output digital output power pins finger capacitance parasitic capacitance CapSense flanking sensor suppression general purpose output least significant bit most significant bit printed circuit board power on reset power on self test radio frequency Description alternating current Units of Measure The following table lists all the abbreviations used to measure the PSoC devices. Numeric Naming Hexadecimal numbers are represented with all letters in uppercase with an appended lowercase 'h' (for example, '14h' or '3Ah'). Hexadecimal numbers may also be represented by a '0x' prefix, the C coding convention. Binary numbers have an appended lowercase 'b' (for example, 01010100b' or '01000011b'). Numbers not indicated by an 'h', 'b', or 0x are decimal. Table 14. Units of Measure Acronym C k A s mA ms mV nA pF V Kilohm microampere microsecond milliampere millisecond millivolts nanoampere ohm picofarad volts Description degree Celsius Document Number: 001-57451 Rev. *C Page 24 of 26 [+] Feedback CY8CMBR2044 Document History Page Document Title: CY8CMBR2044 Capacitive Button Controllers Document Number: 001-57451 Orig. of Submission Rev. ECN No. Description of Change Change Date ** 2807997 SLAN 12/03/2009 New Data sheet *A 2949368 SLAN 06/10/2010 Updated Features and Overview Added Units of Measure and numeric naming sections Updated Pinout Updated Schematic1 and Schematic2 Added Device Feature List Changed H/W configuration on the delay pin Added Figure 4, Figure 5, and Figure 7 Added Debug Data Updated Deep Sleep Mode Updated CapSense Button Shapes Updated Table 7 and Table 8 Changed Example PCB Layout Design with Four CapSense Buttons and Four LEDs Updated Electrical Specifications Added Ordering Code Definitions *B 2975370 SLAN 07/09/2010 Updated Features Updated Pinout Updated Typical Circuits Added Device Feature List Added Figure 3, Figure 5, and Figure 7 Added Debug Data Updated Deep Sleep Mode Added Ordering Information *C 2996393 SLAN 07/29/2010 Updated Features Document Number: 001-57451 Rev. *C Page 25 of 26 [+] Feedback CY8CMBR2044 Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer's representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. Products Automotive Clocks & Buffers Interface Lighting & Power Control Memory Optical & Image Sensing PSoC Touch Sensing USB Controllers Wireless/RF cypress.com/go/automotive cypress.com/go/clocks cypress.com/go/interface cypress.com/go/powerpsoc cypress.com/go/plc cypress.com/go/memory cypress.com/go/image cypress.com/go/psoc cypress.com/go/touch cypress.com/go/USB cypress.com/go/wireless PSoC Solutions psoc.cypress.com/solutions PSoC 1 | PSoC 3 | PSoC 5 (c) Cypress Semiconductor Corporation, 2009-2010. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress' product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document Number: 001-57451 Rev. *C (R) (R) Revised July 29, 2010 Page 26 of 26 CapSense ExpressTM and PSoC DesignerTM are trademarks and PSoC and CapSense are registered trademarks of Cypress Semiconductor Corp. Purchase of I2C components from Cypress or one of its sublicensed Associated Companies conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. As from October 1st, 2006 Philips Semiconductors has a new trade name - NXP Semiconductors. All products and company names mentioned in this document may be the trademarks of their respective holders. [+] Feedback |
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