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Preliminary Datasheet
HD74LV166A
Parallel-Load 8-bit Shift Register
Description
R04DS0002EJ0400 (Previous: REJ03D0321-0300) Rev.4.00 Aug 16, 2010
The HD74LV166A is 8-bit shift register with an output from the last stage. Data may be loaded into the register either in parallel or in serial form. When the Shift/Load input is low, the data is loaded asynchronously in parallel. When the Shift/Load input is high, the data is loaded serially on the rising edge of either clock inhibit or Clock. Clear is asynchronous and active-low. The 2-input NOR clock may be used either by combining two independent clock sources or by designating one of the clock inputs to act as a clock inhibit. Low-voltage and high-speed operation is suitable for the battery-powered products (e.g., notebook computers), and the low-power consumption extends the battery life.
Features
VCC = 2.0 V to 5.5 V operation All inputs VIH (Max.) = 5.5 V (@VCC = 0 V to 5.5 V) All outputs VO (Max.) = 5.5 V (@VCC = 0 V) Typical VOL ground bounce < 0.8 V (@VCC = 3.3 V, Ta = 25C) Typical VOH undershoot > 2.3 V (@VCC = 3.3 V, Ta = 25C) Output current 6 mA (@VCC = 3.0 V to 3.6 V), 12 mA (@VCC = 4.5 V to 5.5 V) Ordering Information
Part Name HD74LV166AFPEL HD74LV166ATELL Package Type SOP-16 pin(JEITA) TSSOP-16 pin Package Code (Previous Code) PRSP0016DH-B (FP-16DAV) PTSP0016JB-A (TTP-16DAV) FP T Package Abbreviation Taping Abbreviation (Quantity) EL (2,000 pcs/reel) ELL (2,000 pcs/reel)
Note: Please consult the sales office for the above package availability.
Function Table
CLR L H H H H H Note: SH/LD X X L H H X Inputs CLK INH CLK X X L L L L L H SER X X X H L X A ... H X X a ... h X X X Internal outputs QA QB L L QA0 QB0 a H L QA0 b QAn QAn QB0 Output QH L QH0 h QGn QGn QH0
H: High level L: Low level : Low to high transition X: Immaterial a ... h: Parallel data Outputs remain unchanged. QA0 ... QH0: Data shifted from the previous stage on a positive edge at the clock input. QAn ... QGn:
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HD74LV166A
Preliminary
Pin Arrangement
SER 1 A2 B3 C4 D5 CLK INH 6 CLK 7 GND 8
16 VCC 15 SH/LD 14 H 13 QH 12 G 11 F 10 E 9 CLR
(Top view)
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HD74LV166A
Preliminary
Absolute Maximum Ratings
Item Supply voltage range Input voltage range*1 Output voltage range*1, 2 Input clamp current Output clamp current Continuous output current Continuous current through VCC or GND Maximum power dissipation at 3 Ta = 25C (in still air)* Storage temperature Symbol VCC VI VO IIK IOK IO ICC or IGND PT Tstg Ratings -0.5 to 7.0 -0.5 to 7.0 -0.5 to VCC + 0.5 -0.5 to 7.0 -20 50 25 50 785 500 -65 to 150 Unit V V V mA mA mA mA mW C Conditions
Output: H or L VCC: OFF VI < 0 VO < 0 or VO > VCC VO = 0 to VCC
SOP TSSOP
Notes: The absolute maximum ratings are values, which must not individually be exceeded, and furthermore, no two of which may be realized at the same time. 1. The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. This value is limited to 5.5 V maximum. 3. The maximum package power dissipation was calculated using a junction temperature of 150C.
Recommended Operating Conditions
Item Supply voltage range Input voltage range Output voltage range Output current Symbol VCC VI VO IOH Min 2.0 0 0 -- -- -- -- -- -- -- -- 0 0 0 -40 Max 5.5 5.5 VCC -50 -2 -6 -12 50 2 6 12 200 100 20 85 Unit V V V A mA Conditions
IOL
A mA
Input transition rise or fall rate
t /v
ns/V
H or L VCC = 2.0 V VCC = 2.3 to 2.7 V VCC = 3.0 to 3.6 V VCC = 4.5 to 5.5 V VCC = 2.0 V VCC = 2.3 to 2.7 V VCC = 3.0 to 3.6 V VCC = 4.5 to 5.5 V VCC = 2.3 to 2.7 V VCC = 3.0 to 3.6 V VCC = 4.5 to 5.5 V
Operating free-air temperature Note:
Ta
C
Unused or floating inputs must be held high or low.
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HD74LV166A
Preliminary
Logic Diagram
A SER B C D E F G CLR H SH/LD CLK CLK INH
R CP S CD Q
R CP S Q CD
QH
Timing Diagram
CLK CLK INH CLR SER SH/LD
A B C D E F G H H L H L H L H H H H L H L H L H L
Parallel Inputs
Output QH
Serial shift Clear Load Inhibit
Serial shift
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HD74LV166A
Preliminary
DC Electrical Characteristics
(Ta = -40 to 85C)
Item Input voltage Symbol VIH VCC (V)* 2.0 2.3 to 2.7 3.0 to 3.6 4.5 to 5.5 2.0 2.3 to 2.7 3.0 to 3.6 4.5 to 5.5 Min to Max 2.3 3.0 4.5 Min to Max 2.3 3.0 4.5 0 to 5.5 5.5 0 3.3 Min 1.5 VCC 0.7 VCC 0.7 VCC 0.7 -- -- -- -- VCC -0.1 2.0 2.48 3.8 -- -- -- -- -- -- -- -- Typ -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 1.7 Max -- -- -- -- 0.5 VCC 0.3 VCC 0.3 VCC 0.3 -- -- -- -- 0.1 0.4 0.44 0.55 1 20 5 -- Unit V Test Conditions
VIL
Output voltage
VOH
V
VOL
Input current Quiescent supply current Output leakage current Input capacitance Note:
IIN ICC IOFF CIN
A A A pF
IOL = -50 A IOL = -2 mA IOL = -6 mA IOL = -12 mA IOL = 50 A IOL = 2 mA IOL = 6 mA IOL = 12 mA VI = 5.5 V or GND VI = VCC or GND, IO = 0 VI or VO = 0 V to 5.5 V VI = VCC or GND
For conditions shown as Min or Max, use the appropriate values under recommended operating conditions.
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HD74LV166A
Preliminary
Switching Characteristics
(VCC = 2.5 0.2 V)
Item Maximum clock frequency Propagation delay time Symbol fmax tPLH/tPHL tPHL Setup time tsu Ta = 25C Min Typ Max 50 80 -- 40 -- -- -- -- 6.0 7.0 6.5 7.0 8.5 -0.5 -0.5 -0.5 8.0 8.5 65 12.2 15.3 10.8 14.2 -- -- -- -- -- -- -- -- -- -- -- 19.8 23.3 16.0 19.5 -- -- -- -- -- -- -- -- -- -- Ta = -40 to 85C Min Max 45 -- 35 1.0 1.0 1.0 1.0 7.0 7.0 8.5 8.5 9.5 0.0 0.0 0.0 9.0 9.0 -- 22.0 26.0 18.0 22.0 -- -- -- -- -- -- -- -- -- -- Unit Test Conditions FROM (Input) TO (Output)
MHz CL = 15 pF CL = 50 pF ns CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF ns
CLK CLR
QH
CLR inactive before CLK CLK INH before CLK Data before CLK SH/LD high before CLK SER before CLK PAR data after SH/LD SER data after CLK SH/LD high after CLK CLR low CLK H or L
Hold time
th
ns
Pulse width
tw
ns
(VCC = 3.3 0.3 V)
Item Maximum clock frequency Propagation delay time Symbol fmax tPLH/tPHL tPHL Setup time tsu Min 65 60 -- -- -- -- 4.0 5.0 5.0 5.0 5.0 0.0 0.0 0.0 6.0 6.0 Ta = 25C Typ Max 115 -- 90 8.6 10.9 7.9 10.4 -- -- -- -- -- -- -- -- -- -- -- 15.4 18.9 12.5 16.3 -- -- -- -- -- -- -- -- -- -- Ta = -40 to 85C Min Max 55 -- 50 1.0 1.0 1.0 1.0 4.0 5.0 6.0 6.0 6.0 0.0 0.0 0.0 7.0 7.0 -- 18.0 21.5 15.0 18.5 -- -- -- -- -- -- -- -- -- -- Unit Test Conditions FROM (Input) TO (Output)
MHz CL = 15 pF CL = 50 pF ns CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF ns
CLK CLR
QH
CLR inactive before CLK CLK INH before CLK Data before CLK SH/LD high before CLK SER before CLK PAR data after SH/LD SER data after CLK SH/LD high after CLK CLR low CLK H or L
Hold time
th
ns
Pulse width
tw
ns
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HD74LV166A
Preliminary
Switching Characteristics (cont)
(VCC = 5.0 0.5 V)
Item Maximum clock frequency Propagation delay time Symbol fmax tPLH/tPHL tPHL Setup time tsu Ta = 25C Min Typ Max 110 165 -- 95 -- -- -- -- 3.5 3.5 4.5 4.0 4.0 1.0 1.0 1.0 5.0 4.0 125 6.0 7.7 5.4 6.9 -- -- -- -- -- -- -- -- -- -- -- 9.9 11.9 8.6 10.6 -- -- -- -- -- -- -- -- -- -- Ta = -40 to 85C Min Max 90 -- 85 1.0 1.0 1.0 1.0 3.5 3.5 4.5 4.0 4.0 1.0 1.0 1.0 5.0 4.0 -- 11.5 13.5 10.0 12.0 -- -- -- -- -- -- -- -- -- -- Unit Test Conditions FROM (Input) TO (Output)
MHz CL = 15 pF CL = 50 pF ns CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF ns
CLK CLR
QH
CLR inactive before CLK CLK INH before CLK Data before CLK SH/LD high before CLK SER before CLK PAR data after SH/LD SER data after CLK SH/LD high after CLK CLR low CLK H or L
Hold time
th
ns
Pulse width
tw
ns
Operating Characteristics
(CL = 50 pF)
Item Power dissipation capacitance Symbol CPD VCC (V) 3.3 5.0 Min -- -- Ta = 25C Typ 36.1 37.5 Max -- -- Unit pF Test Conditions f = 10 MHz
Test Circuit
Measurement point
CL*
Note: CL includes the probe and jig capacitance.
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HD74LV166A
Preliminary
Waveforms
tW VCC CLR
50%VCC 50%VCC
tn tsu CLK
50%VCC 50%VCC
tn+1
tn
tn+1
0V VCC
50%VCC
50%VCC
tW tsu Data
50%VCC
0V th
50%VCC 50%VCC
tsu
th VCC
50%VCC
0V tPHL Output QH
50%VCC
tPLH
50%VCC
tPHL VOH
50%VCC
VOL
Notes: 1. Input waveform: PRR 1 MHz, Zo = 50 , t r 3 ns, t f 3 ns 2. The output are measured one at a time with one transition per measurement.
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HD74LV166A
Preliminary
Package Dimensions
JEITA Package Code P-SOP16-5.5x10.06-1.27 RENESAS Code PRSP0016DH-B Previous Code FP-16DAV MASS[Typ.] 0.24g
*1
D 9
F
16
NOTE) 1. DIMENSIONS"*1 (Nom)"AND"*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET.
bp
E
HE
Index mark
*2
Terminal cross section ( Ni/Pd/Au plating )
1 Z e
*3
c
Reference Symbol
Dimension in Millimeters
Min
8 bp x M L1
S
L
yS
Detail F
D E A2 A1 A bp b1 c c1 HE e x y Z L L1
Nom Max 10.06 10.5 5.50 0.10 0.40 0.20 0.20 2.20 0.46 0.25 8 8.00 0.12 0.15 0.80 0.90
0.00 0.34 0.15 0 7.50
A
7.80 1.27
A1
0.50
0.70 1.15
JEITA Package Code P-TSSOP16-4.4x5-0.65
RENESAS Code PTSP0016JB-A
Previous Code TTP-16DAV
MASS[Typ.] 0.05g
*1
D F
NOTE) 1. DIMENSIONS"*1 (Nom)"AND"*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET.
16
9
bp
*2
E
HE
Terminal cross section
Index mark
c
Reference Symbol
Dimension in Millimeters
(Ni/Pd/Au plating)
Min
1 Z e
*3
8 bp L1 x M
A
S
L
yS
Detail F
D E A2 A1 A bp b1 c c1 HE e x y Z L L1
Nom 5.0 4.40 0.07 0.20 0.15
Max 5.3
0.03 0.15 0.10 0 6.20
0.10 1.10 0.25 0.20 8 6.60 0.13 0.10 0.65 0.6
6.40 0.65
A1
0.4
0.5 1.0
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Notice
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