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SAA7144HL
Quadruple video input processor
Rev. 01 -- 21 April 2005 Product data sheet
1. General description
The SAA7144HL is a combination of four stand alone multistandard video decoders. The SAA7144HL is a pure 3.3 V (5 V tolerant inputs and I/Os) CMOS circuit and a highly integrated circuit for video surveillance applications. All four video decoders are based on the principle of line-locked clock decoding and are able to decode the color of PAL, SECAM and NTSC signals into "CCIR 601" compatible color component values. The SAA7144HL accepts as analog inputs in total eight CVBS sources from TV or VTR (two selectable CVBS sources for each of the four decoders). Each of the four video decoders (A, B, C, D) contains an analog preprocessing circuit including source selection for two CVBS sources, anti-aliasing filter and Analog-to-Digital Converter (ADC), an automatic clamp and gain control, a Clock Generation Circuit (CGC), a digital multistandard decoder (PAL, NTSC and SECAM), a Brightness Contrast Saturation (BCS) control circuit, a multistandard text slicer see Figure 1 and a 27 MHz VBI data bypass. The integrated high performance multistandard data slicer supports several VBI data standards:
* Teletext [WST (World Standard Teletext), CCST (Chinese teletext)] (625 lines) * Teletext [US-WST, NABTS (North American Broadcast Text System) and MOJI
(Japanese teletext)] (525 lines)
* * * * *
Closed caption [Europe, US (line 21)] Wide Screen Signalling (WSS) Video Programming Signal (VPS) Time codes (VITC EBU/SMPTE) HIGH-speed VBI data bypass for IntercastTM application.
The circuit is I2C-bus controlled via two I2C-bus interfaces where two video decoders share one I2C-bus interface on different I2C-bus slave addresses. Each of the four video decoders of the SAA7144HL uses a register mapping which is compatible to the SAA7113H register mapping.
Philips Semiconductors
SAA7144HL
Quadruple video input processor
2. Features
2.1 General
s Four stand alone video decoder instances (A, B, C, D) with two selectable CVBS video inputs each and digital video outputs s Programming register mapping identical to SAA7113H s Small package (LQFP128) s Requires only one crystal (24.576 MHz) for all standards shared by all video decoder instances s CMOS 3.3 V device with 5 V tolerant digital inputs and I/O ports s All four decoder instances are I2C-bus controlled. Two decoder instances share one I2C-bus interface (full read-back ability by an external controller, bit rate up to 400 kbit/s).
2.2 Features of each of the four video decoder instances A, B, C and D
s Two analog CVBS inputs with internal analog source selectors s One analog preprocessing channel in differential CMOS style with built-in analog anti-aliasing filter s Fully programmable static gain or automatic gain control for the selected CVBS channel s Switchable white peak control s Line-locked system clock frequencies s Digital PLL for horizontal sync processing and clock generation, horizontal and vertical sync detection s Automatic detection of 50 Hz and 60 Hz field frequency and automatic switching between PAL and NTSC standards s Luminance and chrominance signal processing for PAL BGHI, PAL N, combination PAL N, PAL M, NTSC M, NTSC N, NTSC 4.43, NTSC Japan and SECAM s User programmable luminance peaking or aperture correction s Cross-color reduction for NTSC by chrominance comb filtering s PAL delay line for correcting PAL phase errors s Brightness Contrast Saturation (BCS) and hue control on-chip s Multistandard VBI data slicer decoding World Standard Teletext (WST), North American Broadcast Text System (NABTS), closed caption, Wide Screen Signalling (WSS), Video Programming System (VPS), Vertical Interval Time Code (VITC) variants (EBU/SMPTE), etc. s Standard ITU-R BT 656 Y-CB-CR 4 : 2 : 2 format (8-bit) on VPO output bus s Enhanced ITU-R BT 656 output format on VPO output bus containing: x Active video x Decoded VBI data s Boundary scan test circuit complies with the "IEEE Std. 1149.b1 - 1994".
3. Applications
s Surveillance application.
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Product data sheet
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Philips Semiconductors
SAA7144HL
Quadruple video input processor
4. Quick reference data
Table 1: Symbol VDDD VDDA Tamb PA+D Quick reference data Parameter digital supply voltage analog supply voltage ambient temperature analog and digital power dissipation Conditions Min 3.0 3.1 0 Typ 3.3 3.3 25 1.1 Max 3.6 3.5 70 Unit V V C W
5. Ordering information
Table 2: Ordering information Package Name SAA7144HL LQFP128 Description plastic low profile quad flat package; 128 leads; body 14 x 20 x 1.4 mm Version SOT425-1 Type number
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Product data sheet
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Philips Semiconductors
SAA7144HL
Quadruple video input processor
6. Block diagram
VIDEO DECODER A ANALOG PROCESSING AND AI11_A AI1D_A AI12_A ANALOG-TODIGITAL CONVERSION AD1 MULTISTANDARD TEXT SLICER OUTPUT VBI DATA BYPASS UPSAMPLING FILTER BYPASS CHROMINANCE CVBS CIRCUIT AND BCS UV Y CLOCKS CVBS Y LUMINANCE CIRCUIT Y CLOCK GENERATION CIRCUIT LLC_A SYNCHRONIZATION CIRCUIT LFCO POWER-ON CONTROL FORMATTER VPO[7:0]_A
SAA7144HL
AGND_A
CONTROL ANALOG PROCESSING CONTROL I2C-BUS CONTROL I2C-BUS INTERFACE
SCL_AB SDA_AB I2C-BUS INTERFACE I2C-BUS CONTROL ANALOG PROCESSING CONTROL CONTROL CVBS AI12_B AI1D_B AI11_B AD1 ANALOG-TODIGITAL CONVERSION AND ANALOG PROCESSING Y CVBS LUMINANCE CIRCUIT SYNCHRONIZATION CIRCUIT LFCO POWER-ON CONTROL LLC_B CLOCK GENERATION CIRCUIT CLOCKS CHROMINANCE CIRCUIT AND BCS BYPASS VBI DATA BYPASS UPSAMPLING FILTER Y UV
Y
AGND_B
OUTPUT FORMATTER TEST CONTROL BLOCK FOR BOUNDARY SCAN TEST AND SCAN TEST
VPO[7:0]_B
MULTISTANDARD TEXT SLICER VIDEO DECODER B VIDEO DECODER C
TDI TCK TMS TRST_N TDO VPO[7:0]_C
ANALOG PROCESSING AND AI11_C AI1D_C AI12_C ANALOG-TODIGITAL CONVERSION AD1
MULTISTANDARD TEXT SLICER OUTPUT VBI DATA BYPASS UPSAMPLING FILTER BYPASS CHROMINANCE CVBS CIRCUIT AND BCS UV Y CLOCKS CVBS Y LUMINANCE CIRCUIT Y CLOCK GENERATION CIRCUIT FORMATTER
AGND_C
CONTROL ANALOG PROCESSING CONTROL I2C-BUS CONTROL I2C-BUS INTERFACE
LLC_C SYNCHRONIZATION CIRCUIT LFCO POWER-ON CONTROL
SCL_CD SDA_CD I2C-BUS INTERFACE I2C-BUS CONTROL ANALOG PROCESSING CONTROL CONTROL CVBS AI12_D AI1D_D AI11_D AD1 ANALOG-TODIGITAL CONVERSION AND ANALOG PROCESSING MULTISTANDARD TEXT SLICER VIDEO DECODER D
001aab304
SYNCHRONIZATION CIRCUIT
LFCO
POWER-ON CONTROL LLC_D CLOCK GENERATION CIRCUIT CLOCKS
Y CVBS
LUMINANCE CIRCUIT
Y
AGND_D
CHROMINANCE CIRCUIT AND BCS BYPASS VBI DATA BYPASS UPSAMPLING FILTER
Y UV
OUTPUT FORMATTER VPO[7:0]_D
Fig 1. Block diagram of SAA7144HL.
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Product data sheet
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Philips Semiconductors
SAA7144HL
Quadruple video input processor
7. Pinning information
7.1 Pinning
128 103 102
1
SAA7144HL
38 39 64
65
001aab305
Fig 2. Pin configuration for LQFP128.
7.2 Pin description
Table 3: Symbol VSSA1(DECA) VDDA1(DECA) AI11_A AI12_A AI1D_A AGND_A DNC1 VDDA0(DECA) VSSA0(DECA) VSSA1(DECB) VDDA1(DECB) AI11_B AI12_B AI1D_B AGND_B DNC2 DNC3 VDDA0(DECB)
9397 750 14454
Pin description Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 Description analog ground for analog supply of the Analog-to-Digital Converter (ADC) of video decoder A analog supply voltage for the ADC (3.3 V) of video decoder A analog input 11 of video decoder A analog input 12 of video decoder A differential analog input for AI11 and AI12 of video decoder A; see Figure 28 analog ground reference for video decoder A do not connect; leave open analog supply voltage for the internal Clock Generation Circuit (CGC) of video decoder A analog ground for the internal CGC of video decoder A analog ground for analog supply of the ADC of video decoder B analog supply voltage for the ADC (3.3 V) of video decoder B analog input 11 of video decoder B analog input 12 of video decoder B differential analog input for AI11 and AI12 of video decoder B; see Figure 28 analog ground reference for video decoder B do not connect; leave open do not connect; leave open analog supply voltage for the internal CGC of video decoder B
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Product data sheet
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SAA7144HL
Quadruple video input processor
Pin description ...continued Pin 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 Description analog ground for the internal CGC of video decoder B analog ground for analog supply of the ADC of video decoder C analog supply voltage for the ADC (3.3 V) of video decoder C do not connect; leave open analog input 11 of video decoder C analog input 12 of video decoder C differential analog input for AI11 and AI12 of video decoder C; see Figure 28 analog ground reference for video decoder C do not connect; leave open analog supply voltage for the internal CGC of video decoder C analog ground for the internal CGC of video decoder C analog ground for analog supply of the ADC of video decoder D analog supply voltage for the ADC (3.3 V) of video decoder D analog input 11 of video decoder D analog input 12 of video decoder D differential analog input for AI11 and AI12 of video decoder D; see Figure 28 analog ground reference for video decoder D do not connect; leave open analog supply voltage for the internal CGC of video decoder D analog ground for the internal CGC of video decoder D do not connect; leave open do not connect; leave open do not connect; leave open do not connect; leave open do not connect; leave open do not connect; leave open do not connect; leave open serial clock input (I2C-bus) for instances A and B serial data input/output (I2C-bus) for instances A and B serial clock input (I2C-bus) for instances C and D serial data input/output (I2C-bus) for instances C and D line-locked clock output (27 MHz) of video decoder D digital video output bus signal VPO7 of video decoder D digital video output bus signal VPO6 of video decoder D digital video output bus signal VPO5 of video decoder D supply for digital pad ring (3.3 V) ground for digital pad ring digital video output bus signal VPO4 of video decoder D digital video output bus signal VPO3 of video decoder D
(c) Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Table 3: Symbol
VSSA0(DECB) VSSA1(DECC) VDDA1(DECC) DNC4 AI11_C AI12_C AI1D_C AGND_C DNC5 VDDA0(DECC) VSSA0(DECC) VSSA1(DECD) VDDA1(DECD) AI11_D AI12_D AI1D_D AGND_D DNC6 VDDA0(DECD) VSSA0(DECD) DNC7 DNC8 DNC9 DNC10 DNC11 DNC12 DNC13 SCL_AB SDA_AB SCL_CD SDA_CD LLC_D VPO7_D VPO6_D VPO5_D VDDDE VSSDE VPO4_D VPO3_D
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SAA7144HL
Quadruple video input processor
Pin description ...continued Pin 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 Description ground for digital core supply for digital core (3.3 V) digital video output bus signal VPO2 of video decoder D digital video output bus signal VPO1 of video decoder D digital video output bus signal VPO0 of video decoder D line-locked clock output (27 MHz) of video decoder C digital video output bus signal VPO7 of video decoder C digital video output bus signal VPO6 of video decoder C do not connect; leave open digital video output bus signal VPO5 of video decoder C digital video output bus signal VPO4 of video decoder C supply for digital pad ring (3.3 V) ground for digital pad ring digital video output bus signal VPO3 of video decoder C digital video output bus signal VPO2 of video decoder C ground for digital core supply for digital core (3.3 V) do not connect; leave open do not connect; leave open digital video output bus signal VPO1 of video decoder C do not connect; leave open digital video output bus signal VPO0 of video decoder C oscillator supply ground oscillator output do not connect; leave open do not connect; leave open oscillator input oscillator supply voltage (3.3 V) line-locked clock output (27 MHz) of video decoder B digital video output bus signal VPO7 of video decoder B do not connect; leave open digital video output bus signal VPO6 of video decoder B do not connect; leave open ground for digital core do not connect; leave open supply for digital core (3.3 V) digital video output bus signal VPO5 of video decoder B digital video output bus signal VPO4 of video decoder B supply for digital pad ring (3.3 V) ground for digital pad ring do not connect; leave open
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Table 3: Symbol VSSDI VDDDI VPO2_D VPO1_D VPO0_D LLC_C VPO7_C VPO6_C DNC14 VPO5_C VPO4_C VDDDE VSSDE VPO3_C VPO2_C VSSDI VDDDI DNC15 DNC16 VPO1_C DNC17 VPO0_C VSSDA XTALO DNC18 DNC19 XTALI VDDDA LLC_B VPO7_B DNC20 VPO6_B DNC21 VSSDI DNC22 VDDDI VPO5_B VPO4_B VDDDE VSSDE DNC23
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Philips Semiconductors
SAA7144HL
Quadruple video input processor
Pin description ...continued Pin 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 Description digital video output bus signal VPO3 of video decoder B digital video output bus signal VPO2 of video decoder B digital video output bus signal VPO1 of video decoder B do not connect; leave open digital video output bus signal VPO0 of video decoder B line-locked clock output (27 MHz) of video decoder A digital video output bus signal VPO7 of video decoder A digital video output bus signal VPO6 of video decoder A digital video output bus signal VPO5 of video decoder A ground for digital core supply for digital core (3.3 V) digital video output bus signal VPO4 of video decoder A supply for digital pad ring (3.3 V) ground for digital pad ring digital video output bus signal VPO3 of video decoder A digital video output bus signal VPO2 of video decoder A digital video output bus signal VPO1 of video decoder A digital video output bus signal VPO0 of video decoder A test data input for boundary scan test [1] test data output for boundary scan test [1] test mode select input for boundary scan test or scan test [1] test clock for boundary scan test [1] test reset input (active LOW), for boundary scan test [1] [2] [3] do not connect; leave open do not connect; leave open do not connect; leave open do not connect; leave open do not connect; leave open do not connect; leave open do not connect; leave open
Table 3: Symbol VPO3_B VPO2_B VPO1_B DNC24 VPO0_B LLC_A VPO7_A VPO6_A VPO5_A VSSDI VDDDI VPO4_A VDDDE VSSDE VPO3_A VPO2_A VPO1_A VPO0_A TDI TDO TMS TCK TRST_N DNC25 DNC26 DNC27 DNC28 DNC29 DNC30 DNC31
[1] [2] [3]
In accordance with the "IEEE1149.1" standard the pads TDI, TMS, TCK and TRST_N are input pads with an internal pull-up transistor and TDO is a 3-state output pad. For board design without boundary scan implementation connect the TRST_N pin to ground. This pin provides easy initialization of the Boundary Scan Test (BST) circuit. TRST_N can be used to force the Test Access Port (TAP) controller to the TEST_LOGIC_RESET state (normal operation) at once.
8. Functional description
The following functional descriptions are related to each of the four stand alone decoder cores (A, B, C and D).
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SAA7144HL
Quadruple video input processor
8.1 Analog input processing
The analog input processing part consists of a source switch to select one out of two video inputs, clamp circuit, analog amplifier, anti-alias filter and video 9-bit CMOS ADC; see Figure 6.
8.2 Analog control circuits
The anti-alias filters are adapted to the line-locked clock frequency via a filter control circuit. The characteristic is shown in Figure 3. During the vertical blanking period, gain and clamping control are frozen.
6 V 0 (dB) -6 -12 -18 -24 -30 -36 -42 0 2 4 6 8 10 12
mgd138
14 f (MHz)
Fig 3. Anti-alias filter.
8.2.1 Clamping
The clamp control circuit controls the correct clamping of the analog input signals. The coupling capacitor is also used to store and filter the clamping voltage. An internal digital clamp comparator generates the information with respect to clamp-up or clamp-down. The clamping levels for the two ADC channels are fixed for luminance (120) and chrominance (256). Clamping time in normal use is set with the HCL pulse on the back porch of the video signal.
8.2.2 Gain control
The gain control circuit receives (via the I2C-bus) the static gain levels for the analog amplifier or controls this amplifier automatically via a built-in Automatic Gain Control (AGC) as part of the Analog Input Control (AICO). The AGC (automatic gain control for luminance) is used to amplify a CVBS signal to the required signal amplitude, matched to the ADC input voltage range. The AGC active time is the sync bottom of the video signal. Signal (white) peak control limits the gain at signal overshoots. The flow charts (see Figure 7 and Figure 8) show more details of the AGC. The influence of supply voltage variation within the specified range is automatically eliminated by clamp and automatic gain control.
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Philips Semiconductors
SAA7144HL
Quadruple video input processor
TV line analog line blanking 255
analog input level +3 dB maximum
controlled ADC input level
GAIN 60 1
CLAMP
0 dB (1 V (p-p) 18/56 ) -6 dB
range 9 dB
0 dB
HCL HSY
mgl065
minimum
mhb325
Fig 4. Analog line with clamp (HCL) and gain range (HSY).
Fig 5. Automatic gain range.
AI1D_A AI12_A AI11_A
5 4 3
SOURCE SWITCH
CLAMP CIRCUIT
ANALOG AMPLIFIER 9-bit DAC
ANTI-ALIAS FILTER
BYPASS SWITCH
ADC
VSSA0(DECA) VSSA1(DECA) VDDA0(DECA) VDDA1(DECA)
9 1
FUSE[1:0]
9
8 2
MODE CONTROL
CLAMP CONTROL
GAIN CONTROL
ANTI-ALIAS CONTROL
VERTICAL BLANKING CONTROL
MODE[3:0]
HCL
GLIMB HSY GLIMT WIPA SLTCA
ANALOG CONTROL
AGND_A
6
HOLDG GAFIX WPOFF GUDL[1:0] GAI[18:10] HLNRS UPTCV
VBSL
VBLNK SVREF
CROSS MULTIPLEXER
LUM
CHR
AD1BYP
001aab306
This is valid for decoder A, B, C and D. Here an example for decoder A is shown.
Fig 6. Analog input processing using the SAA7144HL as differential front-end with 9-bit ADC (continued in Figure 10).
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SAA7144HL
Quadruple video input processor
ANALOG INPUT
AMPLIFIER
gain
DAC
9
ANTI-ALIAS FILTER
ADC 8 NO ACTION 1 VBLK 1 0 LUMA/CHROMA DECODER
HOLDG 1
0
X 1
0
HSY
0
0 0 <4 1
> 254
1 1 <1 0 1 > 254 0
X=0 1 +1/F > 248 0 +1/L -1/LLC2
X=1
+1/LLC2 -1/LLC2
+/- 0
STOP
GAIN ACCUMULATOR (18 BITS)
ACTUAL GAIN VALUE 9-BIT (AGV) [-6/+6 dB]
1
X 1
0
HSY 1
0
Y
0
AGV
UPDATE
FGV
GAIN VALUE 9-BIT
001aab307
X = system variable; Y = AGV - FGV > GUDL ; GUDL = gain update level (adjustable); VBLK = vertical blanking pulse; HSY = horizontal sync pulse; AGV = actual gain value; FGV = frozen gain value.
Fig 7. Gain flow chart.
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Philips Semiconductors
SAA7144HL
Quadruple video input processor
ANALOG INPUT ADC
NO BLANKING ACTIVE
1
VBLK
0
<- CLAMP
GAIN ->
1
HCL
0
1
HSY
0
1
< CLL
0
0
< SBOT
1
1
> WIPE
0
+ CLAMP
- CLAMP
NO CLAMP
+ GAIN
- GAIN
fast - GAIN
slow + GAIN
mgc647
WIPE = white peak level (254). SBOT = sync bottom level (1). CLL = clamp level [60 Y (128 C)]. HSY = horizontal sync pulse. HCL = horizontal clamp pulse.
Fig 8. Clamp and gain flow.
8.3 Chrominance processing
The 9-bit chrominance signal is fed to the multiplication inputs of a quadrature demodulator, where two subcarrier signals from the local oscillator DTO are applied (0 and 90 phase relationship to the demodulator axis). The frequency is dependent on the present color standard. The output signals of the multipliers are low-pass filtered (four programmable characteristics) to achieve the desired bandwidth for the color difference signals (PAL, NTSC) or the 0 and 90 FM signals (SECAM). The color difference signals are fed to the Brightness Contrast Saturation (BCS) block, which contains the following five functions:
* AGC (automatic gain control for chrominance PAL and NTSC) * Chrominance amplitude matching (different gain factors for (R - Y) and (B - Y) to
achieve CCIR-601 levels CR and CB for all standards)
* Chrominance saturation control * Luminance contrast and brightness * Limiting Y-CB-CR to the values 1 (minimum) and 254 (maximum) to fulfil CCIR-601
requirements.
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SAA7144HL
Quadruple video input processor
The SECAM processing contains the following blocks:
* Baseband `bell' filters to reconstruct the amplitude and phase equalized 0 and 90
FM signals
* Phase demodulator and differentiator (FM-demodulation) * De-emphasis filter to compensate the pre-emphasized input signal, including
frequency offset compensation (DB or DR white carrier values are subtracted from the signal, controlled by the SECAM switch signal). The burst processing block provides the feedback loop of the chrominance PLL and contains the following:
* * * * * * *
Burst gate accumulator Color identification and color killer Comparison nominal/actual burst amplitude (PAL/NTSC standards only) Loop filter chrominance gain control (PAL/NTSC standards only) Loop filter chrominance PLL (only active for PAL/NTSC standards) PAL/SECAM sequence detection, H/2-switch generation Increment generation for DTO with divider to generate stable subcarrier for non-standard signals.
The chrominance comb filter block eliminates crosstalk between the chrominance channels in accordance with the PAL standard requirements. For NTSC color standards the chrominance comb filter can be used to eliminate crosstalk from luminance to chrominance (cross-color) for vertical structures. The comb filter can be switched off if desired. The embedded line delay is also used for SECAM recombination (cross-over switches). The resulting signals are fed to the variable Y-delay compensation and the output interface, which contains the VPO output formatter and the output control logic; see Figure 10.
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SAA7144HL
Quadruple video input processor
6 V 0 (dB) -6 -12 -18 -24 -30 -36 -42 -48 -54 0 0.54 1.08 1.62 2.16
(4) (1) (3) (2) (1) (2) (3) (4)
mgd147
2.7 f (MHz)
Transfer characteristics of the chrominance low-pass dependent on CHBW[1:0] settings. (1) CHBW[1:0] = 00. (2) CHBW[1:0] = 01. (3) CHBW[1:0] = 10. (4) CHBW[1:0] = 11.
Fig 9. Chrominance filter.
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Product data sheet Rev. 01 -- 21 April 2005
(c) Koninklijke Philips Electronics N.V. 2005. All rights reserved. 9397 750 14454
Philips Semiconductors
LUM
CHR
AD1BYP
SECAM PROCESSING sequential CB-CR signals TRST_N TCK TDI TMS TDO
121 120 117 119 118
TEST CONTROL BLOCK
QUADRATURE DEMODULATOR
CHBW0 CHBW1
LOW-PASS
BRIGHTNESS, CONTRAST AND SATURATION CONTROL
105, 106, 107, 110, 113, 114, 115, 116
RESET
SUBCARRIER GENERATION SUBCARRIER INCREMENT GENERATION AND DIVIDER
Y CB-CR COMB FILTERS SECAM RECOMBINATION
PHASE DEMODULATOR AMPLITUDE DETECTOR BURST GATE ACCUMULATOR LOOP FILTER GAIN CBCONTROL CR AND Y-DELAY COMPENSATION
OUTPUT FORMATTER AND INTERFACE
VPO7_A to VPO0_A
HUEC VDDA0(DECA)
8
POWER-ON CONTROL
CSTD[2:0] CLOCK
INCS
FCTC
CODE
BRIG CONT SATN YDEL[2:0]
DCCF
OFTS[1:0] GPSW[1:0] OEYC VIPB VRLN COLO
fH/2 switch signal
001aab308
LUM
Y
This is valid for decoder A, B, C and D. Here an example for decoder A is shown.
Fig 10. Chrominance circuit, text slicer, VBI-bypass, output formatting, power and test control (continued from Figure 6 and continued in Figure 17).
Quadruple video input processor
SAA7144HL
15 of 64
Philips Semiconductors
SAA7144HL
Quadruple video input processor
8.4 Luminance processing
The 9-bit luminance signal, a digital CVBS format, is fed through a switchable prefilter. High frequency components are emphasized to compensate for loss. The following chrominance trap filter (f0 = 4.43 MHz or 3.58 MHz center frequency set according to the selected color standard) eliminates most of the color carrier signal. It can be bypassed via I2C-bus bit BYPS (subaddress 09h, bit 7). The high frequency components of the luminance signal can be peaked (control for sharpness improvement via I2C-bus subaddress 09h, see Table 33) in two band-pass filters with selectable transfer characteristic. This signal is then added to the original (unpeaked) signal. For the resulting frequency characteristics see Figure 11 to Figure 16. A switchable amplifier achieves common DC amplification, because the DC gains are different in both chrominance trap modes. The improved luminance signal is fed to the BCS control located in the chrominance processing block; see Figure 17.
18 VY (dB) 6
(1) (2) (4) (3)
mgd139
-6
(1) (2) (4) (3)
-18
-30 0 2 4 6 fY (MHz) 8
(1) 43h (2) 53h (3) 63h (4) 73h
Fig 11. Luminance control SA 09h, 4.43 MHz trap, prefilter on, different aperture band-pass center frequencies.
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SAA7144HL
Quadruple video input processor
18 VY (dB) 6
(1) (2) (3) (4) (4) (3) (2) (1)
mgd140
-6
-18
-30 0 2 4 6 fY (MHz) 8
(1) 40h (2) 41h (3) 42h (4) 43h
Fig 12. Luminance control SA 09h, 4.43 MHz trap, prefilter on, different aperture factors.
18 VY (dB) 6
(1) (2) (4) (3) (1) (2) (4) (3)
mgd141
-6
-18
-30 0 2 4 6 fY (MHz) 8
(1) 03h (2) 13h (3) 23h (4) 33h
Fig 13. Luminance control SA 09h, 4.43 MHz trap, prefilter off, different aperture band-pass center frequencies.
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Quadruple video input processor
18 VY (dB) 6
(1) (2) (4) (3)
mgd144
-6
(1) (2) (4) (3)
-18
-30 0 2 4 6 fY (MHz) 8
(1) 43h (2) 53h (3) 63h (4) 73h
Fig 14. Luminance control SA 09h, 3.58 MHz trap, prefilter on, different aperture band-pass center frequencies.
18 VY (dB) 6
(1) (2) (3) (4) (4) (3) (2) (1)
mgd145
-6
-18
-30 0 2 4 6 fY (MHz) 8
(1) 40h (2) 41h (3) 42h (4) 43h
Fig 15. Luminance control SA 09h, 3.58 MHz trap, prefilter on, different aperture factors.
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Quadruple video input processor
18 VY (dB) 6
(1) (2) (4) (3)
mgd146
-6
(1) (2) (4) (3)
-18
-30 0 2 4 6 fY (MHz) 8
(1) 03h (2) 13h (3) 23h (4) 33h
Fig 16. Luminance control SA 09h, 3.58 MHz trap, prefilter off, different aperture band-pass center frequencies.
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SAA7144HL
Quadruple video input processor
LUM
Y
LUMINANCE CIRCUIT
PREFILTER CHROMINANCE TRAP VARIABLE BAND-PASS FILTER WEIGHTING AND ADDING STAGE
PREF
BYPS VBLB
BPSS[1:0] PREF
APER[1:0] VBLB
PREFILTER SYNC
MATCHING AMPLIFIER
CLOCK CIRCUIT
MACROVISION DETECTOR COPRO VBLB CLOCKS PHASE DETECTOR FINE LINE-LOCKED CLOCK GENERATOR
SYNC SLICER
104
LLC_A
SYNCHRONIZATION CIRCUIT
PHASE DETECTOR COARSE
DAC AUFD HSB[7:0] HSS[7:0] FSEL HLCK
CLOCK GENERATION CIRCUIT
85 80
VDDDA VSSDA
I2 C-BUS CONTROL
VNOI[1:0] HTC[1:0] FIDT
HPLL HTC[1:0]
HTC[1:0]
I2 C-BUS INTERFACE
46 47
VERTICAL PROCESSOR
COUNTER
LOOP FILTER
DISCRETE TIME OSCILLATOR
CRYSTAL CLOCK GENERATOR
84 81
XTALI XTALO
001aab309
SCL_AB
SDA_AB
This is valid for decoder A, B, C and D. Here an example for decoder A is shown.
Fig 17. Luminance and sync processing (continued from Figure 10).
8.5 Synchronization
The prefiltered luminance signal is fed to the synchronization stage. Its bandwidth is further reduced to 1 MHz in a low-pass filter. The sync pulses are sliced and fed to the phase detectors where they are compared with the sub-divided clock frequency. The resulting output signal is applied to the loop filter to accumulate all phase deviations. Internal signals (e.g. HCL and HSY) are generated in accordance with analog front-end requirements. The loop filter signal drives an oscillator to generate the line frequency control signal LFCO; see Figure 18. The detection of `pseudo syncs' as part of the Macrovision(R) copy protection standard is also achieved within the synchronization circuit. The result is reported as flag COPRO within the decoder status byte at subaddress 1Fh.
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Quadruple video input processor
8.6 Clock generation circuit
The internal CGC generates all clock signals required for the video input processor. The internal signal LFCO is a digital-to-analog converted signal provided by the horizontal PLL. It is the multiple of the line frequency: 6.75 MHz = 429 x fH (50 Hz), or 6.75 MHz = 432 x fH (60 Hz). The LFCO signal is multiplied by a factor of 2 and 4 in the internal PLL circuit (including phase detector, loop filtering, VCO and frequency divider) to obtain the output clock signals. The rectangular output clocks have a 50 % duty factor.
Table 4: Clock XTAL LLC LLC2 (internal) LLC4 (internal) LLC8 (virtual) Clock frequencies Frequency (MHz) 24.576 27 13.5 6.75 3.375
LFCO
BAND PASS FC = LLC/4
ZERO CROSS DETECTION
PHASE DETECTION
LOOP FILTER
OSCILLATOR
LLC
DIVIDER 1/2
DIVIDER 1/2
mhb330
LLC2
Fig 18. Block diagram of clock generation circuit.
8.7 Power-on reset
A missing clock, insufficient digital or analog VDDA0 supply voltages will start the reset sequence; all outputs are forced to 3-state; see Figure 19. After sufficient power supply voltage, the outputs LLC and SDA return from 3-state to active.
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Quadruple video input processor
POC VDDA0 ANALOG
POC VDD DIGITAL
LLC CLOCK PLL
POC LOGIC RESINT
POC DELAY
RES_N
CLK0
supply XTALO LLCINT RESINT
LLC RES_N (internal reset) some ms 20 s to 200 s PLL-delay < 1 ms 896 LLC digital delay 128 LLC
001aab312
POC = Power-on control. XTALO = crystal oscillator output. LLCINT = internal system clock. RESINT = internal reset. LLC = line-locked clock output. RES_N = delayed internal reset.
Fig 19. Power-on control circuit. Table 5: Power-on control sequence Remarks direct switching to high-impedance for 20 ms to 200 ms internal reset sequence VPO7 to VPO0, SDA and LLC are in high-impedance state LLC and SDA become active; VPO7 to VPO0, are held in high-impedance state VPO7 to VPO0, are held in high-impedance state
Internal power-on control sequence Pin output status Directly after power-on asynchronous reset Synchronous reset sequence
Status after power-on control sequence
after power-on (reset sequence) a complete I2C-bus transmission is required
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8.8 Multistandard VBI data slicer
The multistandard data slicer is a Vertical Blanking Interval (VBI) and Full Field (FF) video data acquisition block. In combination with software modules the slicer acquires most existing formats of broadcast VBI and FF data. The implementation and programming model is in accordance with the VBI data slicer built into the multimedia video data acquisition circuit SAA5284. The circuitry recovers the actual clock phase during the clock run-in period, slices the data bits with the selected data rate, and groups them into bytes. The clock frequency, signal source, field frequency and accepted error count must be defined via the I2C-bus in subaddress 40h, bits 7 to 4. Several standards can be selected per VBI line. The supported VBI data standards are described in Table 6. The programming of the desired standards is done via I2C-bus subaddresses 41h to 57h (LCR2[7:0] to LCR24[7:0]); see detailed description in Section 8.10. To adjust the slicers processing to the signals source, there are offsets in horizontal and vertical direction available via the I2C-bus in subaddresses 5Bh (bits 2 to 0), 59h (HOFF10 to HOFF0) and 5Bh (bit 4), 5Ah (VOFF8 to VOFF0). The formatting of the decoded VBI data is done within the output interface to the VPO-bus. For a detailed description of the sliced data format see Table 20.
Table 6: Supported VBI standards Data rate (Mbit/s) Framing code 6.9375 0.500 5 27h 001 9951h 1E3C1Fh 27h 001 programmable programmable programmable programmable programmable FC window Hamming check WST625 CC625 VPS WSS WST525 CC525 general text optional VITC625 VITC625 NABTS optional always always
Standard type Teletext EuroWST, CCST European closed caption VPS
Wide screen signalling 5 bits US teletext (WST) US closed caption (line 21) Teletext 5.7272 0.503 6.9375
VITC/EBU time codes 1.8125 (Europe) VITC/SMPTE time codes (USA) US NABTS MOJI (Japanese) Japanese format switch (L20/22) 1.7898 5.7272 5.7272 5
programmable (A7h) Japtext
8.9 VBI-raw data bypass
For a 27 MHz VBI-raw data bypass the digitized CVBS signal is upsampled after analog-to-digital conversion. Suppressing of the back folded CVBS frequency components after upsampling is achieved by an interpolation filter; see Figure 20.
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Quadruple video input processor
6 V 0 (dB) -6 -12 -18 -24 -30 -36 -42 -48 -54 0 2 4 6 8 10 12
mgg067
14 f (MHz)
Fig 20. Interpolation filter for the upsampled CVBS signal.
8.10 Digital output port
The 8-bit VPO-bus can carry 16 data types in three different formats, selectable by the control registers LCR2 to LCR24 (see also Section 9, subaddresses 41h to 57h). OEYC (output enable Y-CB-CR) bit (subaddress 11h, bit 3) in I2C-bus register needs to be set to logic 1 to enable the VPO-bus.
Table 7: Data type number 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
[1]
VPO-bus data formats and types [1] Data format sliced sliced sliced sliced sliced sliced Y-CB-CR 4 : 2 : 2 raw sliced sliced sliced reserved sliced sliced sliced Y-CB-CR 4 : 2 : 2 Data type teletext EuroWST, CCST European closed caption VPS wide screen signalling bits US teletext (WST) US closed caption (line 21) video component signal, VBI region oversampled CVBS data teletext VITC/EBU time codes (Europe) VITC/SMPTE time codes (USA) reserved US NABTS MOJI (Japanese) Japanese format switch (L20/22) video component signal, active video region Name WST625 CC625 VPS WSS WST525 CC525 test line IntercastTM general text VITC625 VITC625 NABTS Japtext JFS active video Number of valid bytes sent per line 88 8 56 32 72 8 1440 programmable 88 26 26 72 74 56 1440
The number of valid bytes per line can be less for the sliced data format if standard not recognized (wrong standard or poor input signal).
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For each LCR value from 2 to 23 the data type can be programmed individually. LCR2 to LCR23 refer to line numbers. The selection in LCR24 values is valid for the rest of the corresponding field. The upper nibble contains the value for field 1 (odd), the lower nibble for field 2 (even). The relationship between LCR values and line numbers can be adjusted via VOFF8 to VOFF0 (located in subaddresses 5Bh, bit 4 and 5Ah, bits 7 to 0). The recommended values are 07h for 50 Hz sources and 0Ah for 60 Hz sources, to accommodate line number conventions as used for PAL, SECAM and NTSC standards; see Table 11 to Table 14. Some details about data types:
* Active video (data type 15) component Y-CB-CR 4 : 2 : 2 signal, 720 active pixels per
line. Format and nominal levels are given in Figure 21 and Table 16.
* Test line (data type 6), is similar to decoded Y-CB-CR data as in active video, with two
exceptions: - vertical filter (chrominance comb filter for NTSC standards, PAL-phase-error correction) within the chrominance processing is disabled - peaking and chrominance trap are bypassed within the luminance processing, if I2C-bus bit VBLB is set. This data type is defined for future enhancements; it could be activated for lines containing standard test signals within the vertical blanking period; currently the most sources do not contain test lines. This data type is available only in lines with VREF = 0, see I2C-bus detail section, Table 41. Format and nominal levels are given in Figure 21 and Table 16.
* Raw samples (data type 7) oversampled CVBS-signal for IntercastTM applications;
the data rate is 27 MHz. The horizontal range is programmable via HSB7 to HSB0, HSS7 to HSS0 and HDEL1 to HDEL0; see Section 9.3.6, Section 9.3.7 and Section 9.3.16 and Table 30, Table 31 and Table 40. Format and nominal levels are given in Figure 22 and Table 18.
* Sliced data (various standards, data types 0 to 5 and 8 to 14). The format is given in
Table 20. The data type selections by LCR are overruled by setting VIPB (subaddress 11h bit 1) to logic 1. This setting is mainly intended for device production tests. The VPO-bus carries the upper or lower 8 bits of the ADC depending on the ADLSB (subaddress 13h bit 7) setting. The output configuration is done via MODE3 to MODE0 settings (subaddress 02h bits 3 to 0; see Table 27). The SAV/EAV timing reference codes define start and end of valid data regions.
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Quadruple video input processor
SAV/EAV format Symbol F Description logic 1 field bit 1st field: F = 0 2nd field: F = 1 for vertical timing see Table 9 and Table 10
Table 8: Bit 7 6
5
V
vertical blanking bit VBI: V = 1 active video: V = 0 for vertical timing see Table 9 and Table 10
4 3 to 0
H P[3:0]
H = 0 in SAV; H = 1 in EAV reserved; evaluation not recommended (protection bits according to ITU-R BT 656)
The generation of the H-bit and consequently the timing of SAV/EAV corresponds to the selected data format. H = 0 during active data region. For all data formats excluding data type 7 (raw data), the length of the active data region is 1440 LLC. For the Y-CB-CR 4 : 2 : 2 formats (data types 15 and 6) every clock cycle within this range contains valid data; see Table 16. The sliced data stream (various standards, data types 0 to 5 and 8 to 14; see Table 20) contains also invalid cycles marked as 00h. The length of the raw data region (data type 7) is programmable via HSB7 to HSB0 and HSS7 to HSS0 (subaddresses 06h and 07h; see Figure 22). During horizontal blanking period between EAV and SAV the ITU-blanking code sequence `-80-10-80-10-...' is transmitted. The position of the F-bit is constant according to ITU-R BT 656; see Table 9 and Table 10. The V-bit can be generated in four different ways (see Table 9 and Table 10) controlled via OFTS1 and OFTS0 (subaddress 10h, bits 7 and 6), VRLN (subaddress 10h, bit 3) and LCR2 to LCR24 (subaddresses 41h to 57h). F and V bits change synchronously with the EAV code.
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525 lines/60 Hz vertical timing F V (ITU-R BT 656) OFTS1 = 0; OFTS1 = 0; OFTS0 = 1 OFTS0 = 0 VRLN = 0 VRLN = 1 (ITU-R BT 656) 1 0 0 0 0 0 0 0 1 1 1 1 1 1 1 0 0 0 0 0 1 1 0 0 0 0 1 1 1 1 0 1 1 1 1 1 1 0 1 1 1 1 0 0 0 1 1 1 1 0 0 0 OFTS1 = 1; OFTS0 = 0 according to selected data type via LCR2 to LCR24 (subaddresses 41h to 57h): data types 0 to 14: V = 1; data type 15: V = 0
Table 9:
Line number
1 to 3 4 to 19 20 21 22 to 261 262 263 264 and 265 266 to 282 283 284 285 to 524 525 Table 10:
625 lines/50 Hz vertical timing F V (ITU-R BT 656) OFTS1 = 0; OFTS1 = 0; OFTS0 = 1 OFTS0 = 0 VRLN = 0 VRLN = 1 (ITU-R BT 656) 0 0 0 0 0 1 1 1 1 1 1 0 0 0 1 1 0 0 0 1 1 1 0 1 1 1 1 0 1 1 1 0 0 0 1 1 0 0 0 1 OFTS1 = 1; OFTS0 = 0 according to selected data type via LCR2 to LCR24 (subaddresses 41h to 57h): data types 0 to 14: V = 1; data type 15: V = 0
Line number
1 to 22 23 24 to 309 310 311 and 312 313 to 335 336 337 to 622 623 624 and 625
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Table 11:
Relationship of LCR to line numbers in 525 lines/60 Hz systems (part 1) 519 257 520 258 521 259 522 260 523 261 524 262 525 263 1 264 2 265 2 3 266 3 4 267 4 5 268 5 6 269 6 7 270 7 8 271 8 9 272 9
Vertical line offset VOFF8 to VOFF0 = 00Ah; horizontal pixel offset HOFF10 to HOFF0 = 354h, FOFF = 1, FISET = 1 Line number (1st field) Line number (2nd field) active video active video LCR (VOFF = 00Ah; HOFF = 354h; 24 FOFF = 1; FISET = 1) Table 12: Relationship of LCR to line numbers in 525 lines/60 Hz systems (part 2) 10 273 11 274 11 12 275 12 13 276 13 14 277 14 15 278 15 16 279 16 17 280 17 18 281 18 19 282 19 20 283 20 21 284 21 22 285 22 23 286 23 equalization pulses equalization pulses serration pulses serration pulses equalization pulses equalization pulses
Vertical line offset VOFF8 to VOFF0 = 00Ah; horizontal pixel offset HOFF10 to HOFF0 = 354h, FOFF = 1, FISET = 1 Line number (1st field) Line number (2nd field) nominal VBI-lines F1 nominal VBI-lines F2 LCR (VOFF = 00Ah; HOFF = 354h; 10 FOFF = 1; FISET = 1) Table 13: active video active video
Relationship of LCR to line numbers in 625 lines/50 Hz systems (part 1) 621 active video 309 active video 24 622 310 623 311 624 312 625 313 1 314 serration pulses 2 2 315 3 316 3 4 317 4 5 318
Vertical line offset VOFF8 to VOFF0 = 007h; horizontal pixel offset HOFF10 to HOFF0 = 354h, FOFF = 1, FISET = 0 Line number (1st field) Line number (2nd field) LCR (VOFF = 007h; HOFF = 354h; FOFF = 1; FISET = 0) equalization pulses equalization pulses serration pulses equalization pulses equalization pulses 5
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Table 14:
Relationship of LCR to line numbers in 625 lines/50 Hz systems (part 2) 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 active video 323 10 324 11 325 12 326 13 327 14 328 15 329 16 330 17 331 18 332 19 333 20 334 21 335 22 336 23 337 24 338 active video 25
Vertical line offset VOFF8 to VOFF0 = 007h; horizontal pixel offset HOFF10 to HOFF0 = 354h, FOFF = 1, FISET = 0 Line number (1st field) nominal VBI-lines F1 Line number (2nd field) 319 320 7 321 8 322 9
nominal VBI-lines F2 LCR (VOFF = 007h; HOFF = 354h; 6 FOFF = 1; FISET = 0) Table 15: Name VOFF[8:0] HOFF[10:0] FOFF FISET
Location of related programming registers Subaddress bits 5Bh[4] and 5Ah[7:0] 5Bh[2:0] and 59h[7:0] 5Bh[7] 40h[7]
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Quadruple video input processor
+255 +235
white
+255 +240 +212
blue 100 % blue 75 %
+255 +240 +212
red 100 % red 75 %
+128
LUMINANCE 100 %
+128
colorless CB-COMPONENT
+128
colorless CR-COMPONENT
+44 +16 0 black
001aac241
yellow 75 % yellow 100 %
001aac480
+44 +16 0
cyan 75 % cyan 100 %
001aac481
+16 0
Equations for modification to the Y-CB-CR levels via BCS control I2C-bus bytes BRIG, CONT and SATN. Luminance:
CONT Y OUT = Int --------------- x ( Y - 128 ) + BRIG 71
Chrominance:
SATN UV OUT = Int -------------- x ( C R ,C B - 128 ) + 128 64
It should be noted that the resulting levels are limited to 1 to 254 in accordance with ITU-R BT 601/656 standard.
a. Y output range.
b. CB output range.
c. CR output range.
Fig 21. Y-CB-CR 4 : 2 : 2 levels on the 8-bit VPO-bus (data types 6 and 15).
+255 +209 white
+255 +199 white
LUMINANCE
LUMINANCE
+71 +60 SYNC 1
black black shoulder
+60 SYNC
black shoulder = black
sync bottom
001aac244
1
sync bottom
001aac245
VBI data levels are not dependent on BCS settings.
a. For sources containing 7.5 IRE black level offset (e.g. NTSC M).
b. For sources not containing black level offset.
Fig 22. Raw data levels on the 8-bit VPO-bus (data type 8).
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Table 16: Blanking period
Y-CB-CR data format on the 8-bit VPO-bus (data types 6 and 15) Timing reference code 720 pixels Y-CB-CR 4 : 2 : 2 data CB0 Y0 CR0 Y1 CB2 Y2 ... CR718 Y719 Timing reference code FF 00 00 EAV Blanking period 80 10 ...
... 80 10 FF 00 00 SAV Table 17: Name SAV CBn Yn CRn EAV Table 18: Blanking period
Explanation to Table 16 Explanation start of active video range; see Table 8 to Table 10 U (B - Y) color difference component, pixel number n = 0, 2, 4 to 718 Y (luminance) component, pixel number n = 0, 1, 2, 3 to 719 V (R - Y) color difference component, pixel number n = 0, 2, 4 to 718 end of active video range; see Table 8 to Table 10 Raw data format on the 8-bit VPO-bus (data type 8) Timing reference code Oversampled CVBS samples Y0 Y1 Y2 Y3 Y4 Y5 ... Yn - 1 Yn Timing reference code FF 00 00 EAV Blanking period 80 10 ...
... 80 10 FF 00 00 SAV Table 19: Name SAV Yi EAV Table 20: Blanking period
Explanation to Table 18 Explanation start of raw sample range; see Table 8 to Table 10 oversampled raw sample stream (CVBS signal), n = 0, 1, 2, 3 to n; n is programmable via HSB and HSS; see Section 9.3.6 and Section 9.3.7 end of raw sample range; see Table 8 to Table 10 Sliced data format on the 8-bit VPO-bus (data types 0 to 5 and 8 to 14) Timing reference code Internal header Sliced data Timing reference code Blanking period
... 80 10 FF 00 00 SAV SDID DC IDI1 IDI2 DLN1 DHN1 ... DLNn DHNn FF 00 00 EAV 80 10 ... Table 21: Name SAV SDID DC Explanation to Table 20 Explanation start of active data; see Table 8 to Table 10 sliced data identification: NEP [1], EP [2], SDID5 to SDID0, freely programmable via I2C-bus subaddress 5Eh[5:0], e.g. to be used as source identifier Dword count: NEP [1], EP [2], DC5 to DC0; DC is inserted for software compatibility with old encoder devices, but does not represent any relevant information for SAA7144HL applications. DC describes the number of succeeding 32-bit words: DC = 14(C + n), where C = 2 (the two data identification bytes IDI1 and IDI2) and n = number of decoded bytes according to the chosen text standard. As the sliced data are transmitted nibble wise, the maximum number of bytes transmitted (NBT) starting at IDI1 results to: NBS = (DC x 8) - 2 DC can vary between 1 and 11, depending on the selected data type. Note that the number of bytes actually transmitted can be less than NBT for two reasons: 1. result of DC would result to a non-integer value (DC is always rounded up) 2. standard not recognized (wrong standard or poor input signal) IDI1
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internal data identification 1: OP [3], FID (field 1 = 0, field 2 = 1), LineNumber8 to LineNumber3
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Quadruple video input processor
Table 21: Name IDI2 DLNn DLHn EAV
[1] [2] [3]
Explanation to Table 20 ...continued Explanation internal data identification 2: OP [3], LineNumber2 to LineNumber0, DataType3 to DataType0; see Table 7 sliced data LOW nibble, format: NEP [1], EP [2], bits 3 to 0, 1, 1 sliced data HIGH nibble, format: NEP [1], EP [2], bits 7 to 4, 1, 1 end of active data; see Table 8 to Table 10
Inverted EP (bit 7); for EP see Table note 2. Even parity (bit 6) of bits 5 to 0. Odd parity (bit 7) of bits 6 to 0.
9. I2C-bus description
9.1 I2C-bus format
S
SLAVE ADDRESS W
ACK-s
SUBADDRESS
ACK-s
DATA data transferred (n bytes + acknowledge)
ACK-s
P
mhb339
Fig 23. Write procedure.
S Sr
SLAVE ADDRESS W SLAVE ADDRESS R
ACK-s ACK-s
SUBADDRESS DATA
ACK-s ACK-m P
data transferred (n bytes + acknowledge)
mhb340
Fig 24. Read procedure (combined format).
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Description of I2C-bus format [1] Description START condition repeated START condition 0100 1010 (= 4Ah) for decoder cores B and D 0100 1000 (= 48h) for decoder cores A and C 0100 1011 (= 4Bh) for decoder cores B and D 0100 1001 (= 49h) for decoder cores A and C acknowledge generated by the slave acknowledge generated by the master subaddress byte; see Table 24 data byte; see Table 24 and Table note 2 STOP condition
Table 22: Code S Sr
Slave address W Slave address R ACK-s ACK-m Subaddress Data P
X = LSB slave address read/write control bit; X = 0, order to write (the circuit is slave receiver); X = 1, order to read (the circuit is slave transmitter)
[1] [2] The SAA7144HL supports the fast mode I2C-bus specification extension (data rate up to 400 kbit/s). If more than one byte DATA is transmitted the subaddress pointer is automatically incremented.
9.2 I2C-bus register description
Table 23: 00h 01h to 04h 05h 06h to 11h 12h 13h 14h to 1Eh 1Fh 20h to 3Fh 40h to 5Bh 5Ch 5Dh 5Eh 5Fh 60h to 62h 63h to FFh Register subaddresses map Access read only read only Reference Section 9.3.1 Section 9.3.19 chip version front-end part reserved decoder part reserved decoder part reserved video decoder status byte reserved general purpose data slicer for testability reserved sliced data identification code reserved Subaddress Description
read and write Section 9.3.2 to Section 9.3.5 read and write Section 9.3.6 to Section 9.3.17 read and write Section 9.3.18
read and write Section 9.3.20 to Section 9.3.25 Section 9.3.27 and Section 9.3.28 -
read and write Section 9.3.26
general purpose data slicer status read only reserved -
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Product data sheet Rev. 01 -- 21 April 2005
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Philips Semiconductors
Table 24:
I2C-bus receiver/transmitter overview Subaddress 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h to 1Eh 1Fh 1Fh 20h to 3Fh 40h 41h 42h to 56h 57h 58h 7 ID07
[1]
Register function Chip version (read only) Increment delay Analog control 1 Analog control 2 Analog control 3 Reserved Horizontal sync begin Horizontal sync stop Sync control Luminance control Luminance brightness Luminance contrast Chrominance saturation Chrominance hue control Chrominance control Chrominance gain control Format/delay control Output control 1 Reserved Output control 3 Reserved Decoder status byte (read only, OLDSB = 0) Decoder status byte (read only, OLDSB = 1) Reserved Slicer control Line control register 2 Line control register 3 to 23 Line control register 24 Framing code
6 ID06
[1]
5 ID05
[1]
4 ID04
[1]
3 IDEL3 MODE3 HOLDG GAI13
[1]
2 IDEL2 MODE2 GAFIX GAI12
[1]
1 IDEL1 MODE1
[1]
0 IDEL0 MODE0 GAI18 GAI10
[1]
FUSE1
[1]
FUSE0 HLNRS GAI16
[1]
GUDL1 VBSL GAI15
[1]
GUDL0 WPOFF GAI14
[1]
GAI17
[1]
GAI11
[1]
HSB7 HSS7 AUFD BYPS BRIG7 CONT7 SATN7 HUEC7
[1]
HSB6 HSS6 FSEL PREF BRIG6 CONT6 SATN6 HUEC6 CSTD2 CGAIN6 OFTS0
[1] [1] [1] [1]
HSB5 HSS5 FOET BPSS1 BRIG5 CONT5 SATN5 HUEC5 CSTD1 CGAIN5 HDEL1
[1] [1] [1] [1]
HSB4 HSS4 HTC1 BPSS0 BRIG4 CONT4 SATN4 HUEC4 CSTD0 CGAIN4 HDEL0
[1] [1]
HSB3 HSS3 HTC0 VBLB BRIG3 CONT3 SATN3 HUEC3 DCCF CGAIN3 VRLN OEYC
[1] [1] [1]
HSB2 HSS2 HPLL UPTCV BRIG2 CONT2 SATN2 HUEC2 FCTC CGAIN2 YDEL2
[1] [1] [1] [1]
HSB1 HSS1 VNOI1 APER1 BRIG1 CONT1 SATN1 HUEC1 CHBW1 CGAIN1 YDEL1 VIPB
[1] [1] [1]
HSB0 HSS0 VNOI0 APER0 BRIG0 CONT0 SATN0 HUEC0 CHBW0 CGAIN0 YDEL0 COLO
[1] [1] [1]
ACGC OFTS1
[1] [1]
ADLSB
[1]
OLDSB
[1]
Quadruple video input processor
INTL INTL
[1]
HLVLN HLCK
[1]
FIDT FIDT
[1]
GLIMT GLIMT
[1]
GLIMB GLIMB
[1] [1]
WIPA WIPA
[1]
COPRO SLTCA
[1]
RDCAP CODE
[1] [1]
SAA7144HL
FISET LCR02_7 LCRN_7 LCR24_7 FC7
HAM_N LCR02_6 LCRN_6 LCR24_6 FC6
FCE LCR02_5 LCRN_5 LCR24_5 FC5
HUNT_N LCR02_4 LCRN_4 LCR24_4 FC4
CLKSEL1 LCR02_2 LCRN_2 LCR24_2 FC2
CLKSEL0 LCR02_1 LCRN_1 LCR24_1 FC1
LCR02_3 LCRN_3 LCR24_3 FC3
LCR02_0 LCRN_0 LCR24_0 FC0
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Table 24: I2C-bus receiver/transmitter overview ...continued Subaddress 59h 5Ah 5Bh 5Ch 5Dh 5Eh 5Fh 60h 61h 62h 63h to FFh 7 HOFF7 VOFF7 FOFF
[1] [1] [1] [1]
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Register function Horizontal offset Vertical offset Horizontal offset (MSBs), vertical offset (MSB) and field offset For testability Reserved Sliced data identification code Reserved Slicer status 1 (read only) Slicer status 2 (read only) Slicer status 3 (read only) Reserved
[1]
6 HOFF6 VOFF6
[1]
5 HOFF5 VOFF5
[1]
4 HOFF4 VOFF4 VOFF8
[1] [1]
3 HOFF3 VOFF3
[1]
2 HOFF2 VOFF2 HOFF10
[1] [1]
1 HOFF1 VOFF1 HOFF9
[1] [1]
0 HOFF0 VOFF0 HOFF8
[1] [1]
[1] [1] [1] [1]
[1] [1]
[1] [1]
SDID5
[1]
SDID4
[1]
SDID3
[1]
SDID2
[1]
SDID1
[1]
SDID0
[1]
LN3
[1]
FC8V LN2
[1]
FC7V F21_N LN1
[1]
VPSV LN8 LN0
[1]
PPV LN7 DT3
[1]
CCV LN6 DT2
[1]
LN5 DT1
[1]
LN4 DT0
[1]
All unused control bits must be programmed with logic 0 to ensure compatibility to future enhancements.
Quadruple video input processor
SAA7144HL
Philips Semiconductors
SAA7144HL
Quadruple video input processor
9.3 I2C-bus detail
The I2C-bus receiver slave address is 48h/49h and 4Ah/4Bh. Subaddresses 05h, 12h, 14h to 1Eh, 20h to 3Fh, 5Ch, 5Dh, 5Fh and 63h to FFh are reserved.
9.3.1 Subaddress 00h (read only register)
Table 25: Function Chip Version (CV) Chip version Logic levels ID07 CV3 ID06 CV2 ID05 CV1 ID04 CV0
9.3.2 Subaddress 01h
Table 26: Function No update Minimum delay Maximum delay Horizontal increment delay IDEL3 1 1 0 IDEL2 1 1 0 0 IDEL1 1 1 0 0 IDEL0 1 0 0 0
Recommended position 1
The programming of the horizontal increment delay is used to match internal processing delays to the delay of the ADC. Use recommended position only.
9.3.3 Subaddress 02h
Table 27: Bit 7 and 6 Analog control 1 - bit description Symbol FUSE[1:0] Description analog function select; see Figure 6 00 = amplifier plus anti-alias filter bypassed 01 = amplifier plus anti-alias filter bypassed 10 = amplifier active 11 = amplifier plus anti-alias filter active 5 and 4 GUDL[1:0] update hysteresis for 9-bit gain; see Figure 7 00 = off 01 = 1 LSB 10 = 2 LSB 11 = 3 LSB 3 to 0 MODE[3:0] channel input selector 0000 = select CVBS (automatic gain) from AI11; see Figure 25 0001 = select CVBS (automatic gain) from AI12; see Figure 25 XXXX = reserved; see Table note 1
[1] X = don't care.
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Quadruple video input processor
AI12 ADC AI11 MODE[3:0]
001aab319
Fig 25. Mode switch for video inputs AI11 or AI12.
9.3.4 Subaddress 03h
Table 28: Bit 7 6 Analog control 2 - bit description Symbol HLNRS Description not used; has to be set to logic 0 HL not reference select 0 = normal clamping if decoder is in unlocked state 1 = reference select if decoder is in unlocked state 5 VBSL AGC hold during vertical blanking period 0 = short vertical blanking (AGC disabled during equalization and serration pulses) 1 = long vertical blanking (AGC disabled from start of pre-equalization pulses until start of active video (line 22 for 60 Hz, line 24 for 50 Hz) 4 WPOFF white peak off 0 = white peak control active 1 = white peak off 3 HOLDG automatic gain control integration 0 = AGC active 1 = AGC integration hold (freeze) 2 GAFIX gain control fix 0 = automatic gain controlled by MODE[3:0] 1 = gain is user programmable via GAI1 1 0 GAI18 not used; has to be set to logic 0 sign bit of gain control; see Table 29
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Quadruple video input processor
9.3.5 Subaddress 04h
Table 29: Analog control 3; static gain control Gain (dB) Sign bit Control bits 7 to 0 GAI18 0... ...117... ...511 -3 0 6 0 0 1 GAI17 0 0 1 GAI16 0 1 1 GAI15 0 1 1 GAI14 0 1 1 GAI13 0 0 1 GAI12 0 1 1 GAI11 0 0 1 GAI10 0 1 1 Decimal value
9.3.6 Subaddress 06h
Table 30: Horizontal sync begin Control bits 7 to 0 HSB7 -128...-109 (50 Hz) -128...-108 (60 Hz) -108 (50 Hz)... -107 (60 Hz)... ...108 (50 Hz) ...107 (60 Hz) 109...127 (50 Hz) 108...127 (60 Hz) Recommended value for raw data type; see Figure 22 1 1 1 0 1 0 0 1 1 1 0 0 0 0 1 1 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1 0 0 0 0 1 0 1 0 1 HSB6 HSB5 HSB4 HSB3 HSB2 HSB1 HSB0 forbidden (outside available central counter range) Delay time (step size = 8/LLC)
forbidden (outside available central counter range)
9.3.7 Subaddress 07h
Table 31: Horizontal sync stop Control bits 7 to 0 HSS7 -128...-109 (50 Hz) -128...-108 (60 Hz) -108 (50 Hz)... -107 (60 Hz)... ...108 (50 Hz) ...107 (60 Hz) 109...127 (50 Hz) 108...127 (60 Hz) Recommended value for raw data type; see Figure 22 0 0 0 0 1 1 0 1 1 1 0 0 0 0 1 1 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1 0 0 0 0 1 0 1 0 1 HSS6 HSS5 HSS4 HSS3 HSS2 HSS1 HSS0 forbidden (outside available central counter range) Delay time (step size = 8/LLC)
forbidden (outside available central counter range)
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9.3.8 Subaddress 08h
Table 32: Bit 7 Sync control - bit description Symbol AUFD Description automatic field detection 0 = field state directly controlled via FSEL 1 = automatic field detection 6 FSEL field selection 0 = 50 Hz, 625 lines 1 = 60 Hz, 525 lines 5 FOET forced ODD/EVEN toggle 0 = ODD/EVEN signal toggles only with interlaced source 1 = ODD/EVEN signal toggles fieldwise even if source is non-interlaced 4 and 3 HTC[1:0] horizontal time constant selection 00 = TV mode (recommended for poor quality TV signals only; do not use for new applications) 01 = VTR mode (recommended if a deflection control circuit is directly connected to SAA7144HL) 10 = reserved 11 = fast locking mode (recommended setting) 2 HPLL horizontal PLL 0 = PLL closed 1 = PLL open; horizontal frequency fixed 1 and 0 VNOI[1:0] vertical noise reduction 00 = normal mode (recommended setting) 01 = fast mode [applicable for stable sources only; automatic field detection (AUFD) must be disabled] 10 = free running mode 11 = vertical noise reduction bypassed
9.3.9 Subaddress 09h
Table 33: Bit 7 Luminance control - bit description Symbol BYPS Description chrominance trap bypass 0 = chrominance trap active; default for CVBS mode 1 = chrominance trap bypassed 6 PREF prefilter active; see Figure 11 to Figure 16 0 = bypassed 1 = active 5 and 4 BPSS[1:0] aperture band-pass (center frequency) 00 = center frequency is 4.1 MHz 01 = center frequency is 3.8 MHz; see Table note 1 10 = center frequency is 2.6 MHz; see Table note 1 11 = center frequency is 2.9 MHz; see Table note 1
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Table 33: Bit 3
Luminance control - bit description ...continued Symbol VBLB Description vertical blanking luminance bypass 0 = active luminance processing 1 = chrominance trap and peaking stage are disabled during VBI lines determined by VREF = 0; see Table 41
2
UPTCV
update time interval for analog AGC value 0 = horizontal update (once per line) 1 = vertical update (once per field)
1 and 0
APER[1:0]
aperture factor; see Figure 11 to Figure 16 00 = aperture factor is 0 01 = aperture factor is 0.25 10 = aperture factor is 0.5 11 = aperture factor is 1.0
[1]
Not to be used with bypassed chrominance trap.
9.3.10 Subaddress 0Ah
Table 34: Offset 255 (bright) 128 (CCIR level) 0 (dark) Luminance brightness control Control bits 7 to 0 BRIG7 1 1 0 BRIG6 1 0 0 BRIG5 1 0 0 BRIG4 1 0 0 BRIG3 1 0 0 BRIG2 1 0 0 BRIG1 1 0 0 BRIG0 1 0 0
9.3.11 Subaddress 0Bh
Table 35: Gain 1.999 (maximum) 1.109 (CCIR level) 1.0 0 (luminance off) -1 (inverse luminance) -2 (inverse luminance) Luminance contrast control Control bits 7 to 0 CONT7 0 0 0 0 1 1 CONT6 1 1 1 0 1 0 CONT5 1 0 0 0 0 0 CONT4 1 0 0 0 0 0 CONT3 1 0 0 0 0 0 CONT2 1 1 0 0 0 0 CONT1 1 1 0 0 0 0 CONT0 1 1 0 0 0 0
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9.3.12 Subaddress 0Ch
Table 36: Gain 1.999 (maximum) 1.0 (CCIR level) 0 (color off) -1 (inverse chrominance) -2 (inverse chrominance) Chrominance saturation control Control bits 7 to 0 SATN7 0 0 0 1 1 SATN6 1 1 0 1 0 SATN5 1 0 0 0 0 SATN4 1 0 0 0 0 SATN3 1 0 0 0 0 SATN2 1 0 0 0 0 SATN1 1 0 0 0 0 SATN0 1 0 0 0 0
9.3.13 Subaddress 0Dh
Table 37: Chrominance hue control Control bits 7 to 0 HUEC7 +178.6... ...0... ...-180 0 0 1 HUEC6 1 0 0 HUEC5 1 0 0 HUEC4 1 0 0 HUEC3 1 0 0 HUEC2 1 0 0 HUEC1 1 0 0 HUEC0 1 0 0 Hue phase (deg)
9.3.14 Subaddress 0Eh
Table 38: Bit 7 6 to 4 Chrominance control - bit description Symbol CSTD[2:0] Description 50 Hz not used; has to be set to logic 0 color standard selection 000 = PAL BGHIN NTSC M (or NTSC-Japan with special level adjustment: brightness subaddress 0Ah = 95h; contrast subaddress 0Bh = 48h) PAL 4.43 (60 Hz) NTSC 4.43 (60 Hz) PAL M reserved 60 Hz
001 = NTSC 4.43 (50 Hz) 010 = combination-PAL N 011 = NTSC N 100 = reserved; do not use 101 = SECAM 110 = reserved; do not use 111 = reserved; do not use 3 DCCF disable chrominance comb filter
0 = chrominance comb filter on (during lines determined by VREF = 1; see Table 41) 1 = chrominance comb filter permanently off 2 FCTC fast color time constant 0 = nominal time constant 1 = fast time constant
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Table 38: Bit 1 and 0
Chrominance control - bit description ...continued Symbol CHBW[1:0] Description 50 Hz chrominance bandwidth 00 = small bandwidth ( 620 kHz) 01 = nominal bandwidth ( 800 kHz) 10 = medium bandwidth ( 920 kHz) 11 = wide bandwidth ( 1000 kHz) 60 Hz
9.3.15 Subaddress 0Fh
Table 39: Bit 7 Chrominance gain control - bit description Symbol ACGC Description automatic chrominance gain control 0 = on 1 = programmable gain via CGAIN[6:0] 6 to 0 CGAIN[6:0] chrominance gain value (if AGC is set to logic 1) 0000000 = minimum gain (0.5) 0100100 = nominal gain (1.125) 1111111 = maximum gain (7.5)
9.3.16 Subaddress 10h
Table 40: Bit 7 and 6 Format/delay control - bit description Symbol OFTS[1:0] Description output format selection; V-flag generation in SAV/EAV codes; see Table 9 and Table 10 00 = standard ITU-R BT 656 format 01 = V-flag in SAV/EAV is generated by VREF 10 = V-flag in SAV/EAV is generated by data type 11 = reserved 5 and 4 HDEL[1:0] fine position of HS 00 = 0 x 2/LLC 01 = 1 x 2/LLC 10 = 2 x 2/LLC 11 = 3 x 2/LLC 3 2 to 0 VRLN YDEL[2:0] VREF pulse position and length; see Table 41 luminance delay compensation (steps in 2/LLC) 100 = -4... x 2/LLC 000 = ...0... x 2/LLC 011 = ...3 x 2/LLC
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Table 41: VRLN
VREF pulse position and length VRLN SA 10 (bit 3) VREF at 60 Hz 525 lines 0 1 242 first 18 (21) 281 (284) last 259 (262) 522 (525) first 24 337 last 258 (261) 521 (524) 0 286 last 309 622 first 23 336 240 first 19 (22) 282 (285) VREF at 50 Hz 625 lines 1 288 last 310 623
Length Line number Field Field
[1]
1 [1] 2 [1]
The numbers given in parenthesis refer to ITU line counting.
9.3.17 Subaddress 11h
Table 42: Bit 7 to 4 3 Output control 1 - bit description Symbol OEYC Description not used; have to be set to logic 0 output enable Y-CB-CR data 0 = VPO-bus high-impedance 1 = output VPO-bus active 2 1 VIPB not used; has to be set to logic 0 Y-CB-CR decoder bypassed 0 = processed data to VPO output 1 = ADC data to VPO output; dependent on mode settings 0 COLO color on 0 = automatic color killer 1 = color forced on
9.3.18 Subaddress 13h
Table 43: Bit 7 Output control 3 - bit description Symbol ADLSB Description analog-to-digital converter output bits on VPO7 to VPO0 in bypass mode (VIPB = 1, used for test purposes); see Table note 1 0 = AD8 to AD1 (MSBs) on VPO7 to VPO0 1 = AD7 to AD0 (LSBs) on VPO7 to VPO0 6 and 5 4 OLDSB not used; have to be set to logic 0 selection bit for status byte functionality 0 = default status information; see Table 44 1 = old status information, for compatibility reasons; see Table 44 3 to 0
[1]
-
not used; have to be set to logic 0
Video input selection via MODE[3:0] (subaddress 02h; see Figure 25).
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Quadruple video input processor
9.3.19 Subaddress 1Fh (read only register)
Table 44: Bit 7 Status byte - bit description Symbol INTL Description status bit for interlace detection 0 = non-interlaced 1 = interlaced 6 HLCK status bit for locked horizontal frequency (OLDSB = 1) 0 = locked 1 = unlocked HLVLN status bit for horizontal/vertical loop (OLDSB = 0) 0 = locked 1 = unlocked 5 FIDT identification bit for detected field frequency 0 = 50 Hz 1 = 60 Hz 4 3 2 1 GLIMT GLIMB WIPA SLTCA COPRO 0 CODE RDCAP gain value for active luminance channel is limited [max (top)]; active HIGH gain value for active luminance channel is limited [min (bottom)]; active HIGH white peak loop is activated; active HIGH slow time constant active in WIPA mode; active HIGH (OLDSB = 1) Macrovision(R) copy protection detection according to Macrovision(R) detect specification revision 7.01 (OLDSB = 0). color signal in accordance with selected standard has been detected; active HIGH (OLDSB = 1) ready for capture (all internal loops locked); active HIGH (OLDSB = 0)
9.3.20 Subaddress 40h
Table 45: Bit 7 Slicer control - bit description Symbol FISET Description field size select 0 = 50 Hz field rate 1 = 60 Hz field rate 6 HAM_N hamming check 0 = hamming check for 2 bytes after framing code, dependent on data type (default) 1 = no hamming check 5 FCE framing code error 0 = one framing code error allowed 1 = no framing code errors allowed 4 HUNT_N amplitude searching 0 = amplitude searching active (default) 1 = amplitude searching stopped 3 not used; has to be set to logic 0
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Quadruple video input processor
Table 45: Bit 2 and 1
Slicer control - bit description ...continued Symbol CLKSEL[1:0] Description data slicer clock selection 00 = reserved 01 = 13.5 MHz (default) 10 = reserved 11 = reserved
0
-
not used; has to be set to logic 0
9.3.21 Subaddresses 41h to 57h
Table 46: LCR register 2 to 24; see Table 7 Framing code 27h 001 9951h 1E3C1Fh 27h 001 programmable programmable programmable programmable (A7h) programmable Bit 7 to 4 DT3 to WST625 CC625 VPS WSS WST525 CC525 Test line IntercastTM General text VITC625 Reserved NABTS Japtext JFS Active video teletext EuroWST, CCST European closed caption video programming service wide screen signalling bits US teletext (WST) US closed caption (line 21) video component signal, VBI region oversampled CVBS data teletext VITC/EBU time codes (Europe) VITC/SMPTE time codes (USA) reserved US NABTS MOJI (Japanese) Japanese format switch (L20/22) video component signal, active video region (default) 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 DT0 [1] Bit 3 to 0 DT3 to DT0 [1] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 LCR register 2 to 24 (41h to 57h)
[1]
The assignment of the upper and lower nibbles to the corresponding field depends on the setting of FOFF (subaddress 5Bh, bit 7); see Table 47.
Table 47: FOFF 0 1
Setting of FOFF (subaddress 5Bh, bit 7) Bit 7 to 4 field 1 field 2 Bit 3 to 0 field 2 field 1
9.3.22 Subaddress 58h
Table 48: Bit 7 to 0 Framing code - bit description Symbol FC[7:0] Description framing code for programmable data types; 40h (default)
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9.3.23 Subaddresses 59h and 5Bh
Table 49: Bit 2 to 0 7 to 0 Horizontal offset - bit description Symbol HOFF[10:8] HOFF[7:0] Description horizontal offset; recommended value: 03h horizontal offset; recommended value: 54h
Subaddress 5Bh Subaddress 59h
9.3.24 Subaddresses 5Ah and 5Bh
Table 50: Bit 4 7 to 0 Vertical offset - bit description Symbol VOFF8 VOFF[7:0] Description vertical offset vertical offset 00h = minimum value 0, if VOFF8 = 0 38h = maximum value 312, if VOFF8 = 1 07h = value for 50 Hz 625 lines input, if VOFF8 = 0 0Ah = value for 60 Hz 525 lines input, if VOFF8 = 0
Subaddress 5Bh Subaddress 5Ah
9.3.25 Subaddress 5Bh
Table 51: Bit 7 Field offset, MSBs for vertical and horizontal offsets - bit description Symbol FOFF Description field offset 0 = no modification of internal field indicator 1 = invert field indicator (even/odd; default) 6 and 5 4 3 2 to 0 VOFF8 HOFF[10:8] not used; have to be set to logic 0 vertical offset; see Table 50 not used; has to be set to logic 0 horizontal offset; see Table 49
9.3.26 Subaddress 5Eh
Table 52: Bit 7 and 6 5 to 0 Sliced data identification code - bit description Symbol SDID[5:0] Description not used; have to be set to logic 0 sliced data identification code; SDID[5:0] = 000000 (default)
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Quadruple video input processor
9.3.27 Subaddress 60h (read only register)
Table 53: Bit 7 6 and 5 Slicer status 1 - bit description Symbol FC8V and FC7V Description not used; has to be set to logic 0 framing code valid 00 = no framing code in the last frame 01 = framing code with 1 error detected in the last frame 1X [1] = framing code without errors detected in the last frame 4 VPSV VPS valid 0 = no VPS in the last frame 1 = VPS detected 3 PPV PALplus valid 0 = no PALplus in the last frame 1 = PALplus detected 2 CCV closed caption valid 0 = no closed caption in the last frame 1 = closed caption detected 1 and 0
[1]
-
not used; have to be set to logic 0
X = don't care.
9.3.28 Subaddresses 61h and 62h (read only register)
Table 54: Bit 7 and 6 5 4 to 0 7 to 4 3 to 0 Slicer status 2 and 3 - bit description Symbol F21_N LN[8:4] LN[3:0] DT[3:0] Description not used; have to be set to logic 0 internal used slicer status bit line number line number data type according to Table 7
Subaddress 61h
Subaddress 62h
10. I2C-bus start set-up
The given values force the following behavior of the SAA7144HL:
* The analog input AI11 expects a signal in CVBS format; analog anti-alias filter and
AGC active
* Automatic field detection enabled, PAL BDGHI or NTSC M standard expected * Standard ITU-R BT 656 output format enabled, VBI data slicer disabled; see Table 55
Table note 2
* Contrast, brightness and saturation control in accordance with ITU standards * Chrominance processing with nominal bandwidth (800 kHz).
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Table 55:
I2C-bus start set-up values Name [1] ID07 to ID04 X, X, X, X, IDEL[3:0] FUSE[1:0], GUDL[1:0], MODE[3:0] Start 7 6 5 4 3 2 1 0 (hexadecimal) read only 0 0 0 0 1 0 0 0 08 1 0 0 0 0 0 0 0 80 Values (binary)
Subaddress Function (hexadecimal) 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 to 1E 1F 20 to 3F 40 41 to 57 58 59 5A 5B chip version increment delay analog control 1 analog control 2 analog control 3 reserved horizontal sync begin horizontal sync stop sync control luminance control luminance brightness luminance contrast chrominance saturation chrominance hue control chrominance control chrominance gain control format/delay control output control 1 reserved output control 3 reserved decoder status byte reserved slicer control
X, HLNRS, VBSL, WPOFF, HOLDG, 0 0 1 1 0 0 0 1 31 GAFIX, X, GAI18 GAI1[7:0] HSB[7:0] HSS[7:0] AUFD, FSEL, FOET, HTC[1:0], HPLL, VNOI[1:0] BYPS, PREF, BPSS[1:0], VBLB, UPTCV, APER[1:0] BRIG[7:0] CONT[7:0] SATN[7:0] HUEC[7:0] X, CSTD[2:0], DCCF, FCTC, CHBW[1:0] ACGC, CGAIN[6:0] OFTS[1:0], HDEL[1:0], VRLN, YDEL[2:0] X, X, X, X, OEYC, X, VIPB, COLO ADLSB, X, X, OLDSB, X, X, X, X 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 00 1 1 1 0 1 0 0 1 E9 0 0 0 0 1 1 0 1 0D 1 0 0 1 1 0 0 0 98 0 0 0 0 0 0 0 1 01 1 0 0 0 0 0 0 0 80 0 1 0 0 0 1 1 1 47 0 1 0 0 0 0 0 0 40 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 1 01 0 0 1 0 1 0 1 0 2A 0 0 0 0 0 0 0 0 00 0 0 0 0 1 0 0 0 0C 0 0 0 0 0 0 0 1 01 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 00 INTL, HLVLN, FIDT, GLIMT, GLIMB, read only WIPA, COPRO, RDCAP 0 0 0 0 0 0 0 0 00 FISET, HAM_N, FCE, HUNT_N, X, CLKSEL[1:0], X FC[7:0] HOFF[7:0] VOFF[7:0] FOFF, X, X, VOFF8, X, HOFF[10:8] 0 0 0 0 0 0 1 0 02 [2] 1 1 1 1 1 1 1 1 FF [2] 0 0 0 0 0 0 0 0 00 0 1 0 1 0 1 0 0 54 [2] 0 0 0 0 0 1 1 1 07 [2] 1 0 0 0 0 0 1 1 83 [2]
line control register 2 to 24 LCRn[7:0] programmable framing code horizontal offset for slicer vertical offset for slicer field offset and MSBs for horizontal and vertical offset reserved sliced data identification code reserved
Rev. 01 -- 21 April 2005
5C and 5D 5E 5F
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0 0 0 0 0 0 0 0 00 X, X, SDID[5:0] 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 00
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SAA7144HL
Quadruple video input processor
Table 55:
I2C-bus start set-up values ...continued Name [1] Start 7 6 5 4 3 2 1 0 (hexadecimal) read only read only 0 0 0 0 0 0 0 0 00 Values (binary)
Subaddress Function (hexadecimal) 60 61 62 63 to FF
[1] [2]
slicer status 1 slicer status 2 slicer status 3 reserved
-, FC8V, FC7V, VPSV, PPV, CCV, -, - read only -, -, F21_N, LN[8:4] LN[3:0], DT[3:0]
All X values must be set to logic 0. For SECAM decoding set register 0Eh to 50h. For proper data slicer programming refer to Table 11 to Table 14 and Table 7.
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11. Limiting values
Table 56: Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). All ground pins connected together and all supply pins connected together. Symbol VDDD VDDA Vi(a) Vo(a) Vi(d) Vo(d) VSS Tstg Tamb Tamb(bias) Vesd Parameter digital supply voltage analog supply voltage analog input voltage analog output voltage digital input voltage digital output voltage voltage difference between VSSA(all) and VSS(all) storage temperature ambient temperature ambient temperature under bias electrostatic discharge voltage human body model machine model
[1] [2] Class 2 according to JESD22-A114-B. Class B according to EIA/JESD22-A115-A.
[1] [2]
Conditions
Min -0.5 -0.5 -0.5 -0.5
Max +4.6 +4.6 VDDA + 0.5 (4.6 max) VDDA + 0.5 +5.5 VDDD + 0.5 100 +150 70 +80 2000 200
Unit V V V V V V mV C C C V V
outputs in 3-state outputs active
-0.5 -0.5 -65 0 -10 -
12. Thermal characteristics
Table 57: Symbol Rth(j-a) Thermal characteristics Parameter thermal resistance from junction to ambient Conditions in free air Typ 30 Unit K/W
13. Characteristics
Table 58: Characteristics VDDD = 3.0 V to 3.6 V; VDDA = 3.1 V to 3.5 V; Tamb = 25 C; unless otherwise specified. Symbol Supplies VDDD IDDD VDDA IDDA PA+D Analog part Iclamp clamping current VI = 0.9 V DC 8 A digital supply voltage digital supply current (IDDDI + IDDDE) analog supply voltage analog supply current (IDDA0 + IDDA1) analog and digital power all outputs unloaded 3.0 3.1 3.3 125 3.3 210 1.1 3.6 165 3.5 250 V mA V mA W Parameter Conditions Min Typ Max Unit
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Table 58: Characteristics ...continued VDDD = 3.0 V to 3.6 V; VDDA = 3.1 V to 3.5 V; Tamb = 25 C; unless otherwise specified. Symbol Vi(p-p) Parameter input voltage (peak-to-peak value) Conditions for normal video levels 1 V (p-p), termination 18/56 and AC coupling required; coupling capacitor = 47 nF clamping current off fi = 5 MHz Min 0.5 Typ 0.7 Max 1.4 Unit V
Zi Ci cs
input impedance input capacitance channel crosstalk between inputs of one instance AI11_x and AI12_x (e.g. AI11_A to AI12_A) crosstalk between two decoder instances bandwidth differential phase (amplifier plus anti-alias filter bypassed) differential gain (amplifier plus anti-alias filter bypassed) ADC clock frequency DC differential linearity error DC integral linearity error LOW-level input voltage pins SDA and SCL HIGH-level input voltage pins SDA and SCL LOW-level input voltage all other inputs HIGH-level input voltage all other inputs input leakage current I/O leakage current input capacitance input capacitance all other inputs
200 -
-
10 -50
k pF dB
instance
CVBS inputs with different line frequencies at -3 dB
-
-40
-
dB
9-bit analog-to-digital converter B diff 7 2 MHz deg
Gdiff
-
2
-
%
fclk(ADC) DLE ILE VIL(SCL,SDA) VIH(SCL,SDA) VIL(n) VIH(n) ILI ILI/O Ci Ci(n)
12.8 -0.5 0.7VDDD -0.3 2.0 outputs at 3-state -
0.7 1 -
14.3 +0.3VDDD
MHz LSB LSB V
Digital inputs
VDDD + 0.5 V +0.8 5.5 1 10 8 5 V V A A pF pF
Digital outputs VOL(SCL,SDA) LOW-level output voltage SDA/SCL at 3 mA sink pins SDA and SCL current VOL VOH
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-0.5 2.4
-
0.4 +0.4
V V
LOW-level output voltage IOL = 2 mA HIGH-level output voltage IOH = -2 mA
VDDD + 0.5 V
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Quadruple video input processor
Table 58: Characteristics ...continued VDDD = 3.0 V to 3.6 V; VDDA = 3.1 V to 3.5 V; Tamb = 25 C; unless otherwise specified. Symbol VOL(clk) VOH(clk) Parameter Conditions Min -0.5 2.4 Typ Max +0.6 Unit V LOW-level output voltage IOL = 2 mA for LLC clock HIGH-level output voltage for LLC clock output load capacitance output hold time propagation delay propagation delay to 3-state output load capacitance cycle time rise time LLC fall time LLC duty factor for tXTALIH/tXTALI nominal line frequency permissible static deviation nominal subcarrier frequency PAL BGHIN NTSC M; NTSC Japan PAL M combination-PAL N fSC fn f/fn Tf/fn(T) lock-in range nominal frequency permissible nominal frequency deviation permissible nominal frequency deviation with temperature operating ambient temperature load capacitance 3rd harmonic Crystal oscillator 24.576 50 20 MHz 10-6 10-6 nominal frequency LLC duty factors for tLLCH/tLLC CL = 25 pF CL = 15 pF CL = 25 pF IOH = -2 mA
VDDD + 0.5 V
Data and control output timing; see Figure 26 [1] CL tOHD;DAT tPD tPDZ 15 4 40 22 22 pF ns ns ns
Clock output timing (LLC); see Figure 26 CL(LLC) Tcy LLC tr tf XTALI 15 35 40 40 40 39 60 5 5 60 pF ns % ns ns %
Clock input timing (XTALI)
Horizontal PLL fHn fH/fHn 50 Hz field 60 Hz field 15625 15734 5.7 Hz Hz %
Subcarrier PLL fSCn 400 4433619 3579545 3575612 3582056 Hz Hz Hz Hz Hz
Crystal specification (X1) Tamb(X1) CL 0 8 70 C pF
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Table 58: Characteristics ...continued VDDD = 3.0 V to 3.6 V; VDDA = 3.1 V to 3.5 V; Tamb = 25 C; unless otherwise specified. Symbol Rs C1 C0
[1]
Parameter series resonance resistor motional capacitance parallel capacitance
Conditions
Min -
Typ 40
Max 80
Unit fF pF
1.5 20 % 3.5 20 % -
The effects of rise and fall times are included in the calculation of tOHD;DAT, tPD and tPDZ. Timings and levels refer to drawings and conditions illustrated in Figure 26.
Table 59: Function
Processing delay Typical analog delay AI22 -> ADC(in) (ns) 15 25 75 Digital delay ADC(in) -> VPO (LLC CLOCKS); YDEL2 to YDEL0 = 0 157
Without amplifier or anti-alias filter With amplifier, without anti-alias filter With amplifier and anti-alias filter
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14. Timing diagrams
tLLC tLLCL LLC tLLCH tf tr 2.6 V 1.5 V 0.6 V
tPD tOHD;DAT VPO 2.4 V 0.6 V
001aab316
Fig 26. Clock/data output timing.
CVBS input
burst
28 x 1/LLC RAW DATA on VPO-bus burst
157 x 1/LLC
processing delay CVBS- > VPO(1)
Y-DATA on VPO-bus
sync clipped
001aab317
(1) See Table 59.
Fig 27. Horizontal timing diagram.
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Product data sheet Rev. 01 -- 21 April 2005
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R18 18
15. Application information
Philips Semiconductors
3.3 V
C15
AGND VDDA1(DECA) VSSA0(DECA)
analog
digital
C17 100 nF
AGND VDDA0(DECB) VSSA1(DECA)
C19 100 nF
AGND VDDA1(DECB) VSSA0(DECB)
C21 100 nF
AGND VSSA1(DECB)
3.3 V
100 nF DGND R40 3.3 100 nF DGND R42 3.3 100 nF DGND R44 3.3 100 nF DGND
VDDA0(DECA)
100 nF
DGND
R46 3.3
AGND_A
AGND_B
VDDDE
VDDDE
VSSDE
VSSDE
DNC2
VDDDI
VDDDI
VSSDI
VSSDI
TDI TDO
R54 0
BST[0:2]
8
C2 C3 C4 R26 56 R30 56 47 nF 47 nF 47 nF R34 33
9
6
2
1
18
19
15
11
10
16
59
58
54
55
74
73
69
AI11_A
R19 18
AI11_A AI12_A AI1D_A DNC1, DNC4, DNC7 to DNC11
3 4 5
AI12_A
70 117 118 119 120 121 116 115 114 113 110 107 106 105 103 101 100 99 95 94 89 87 79 77 72 71 68 67 65 64 62 61 60 57 56 53 52 51
TDI TDO TMS TCK TRST_N VPO0_A VPO1_A VPO2_A VPO3_A VPO4_A VPO5_A VPO6_A VPO7_A VPO0_B VPO1_B VPO2_B VPO3_B VPO4_B VPO5_B VPO6_B VPO7_B VPO0_C VPO1_C VPO2_C VPO3_C VPO4_C VPO5_C VPO6_C VPO7_C VPO0_D VPO1_D VPO2_D VPO3_D VPO4_D VPO5_D VPO6_D VPO7_D 4 3 2 1 4 3 2 1 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 4 3 2 1 4 3 2 1 5 6 7 8 5 6 7 8 8 7 6 5 8 7 6 5 8 7 6 5 8 7 6 5 5 6 7 8 5 6 7 8
RN3 33
BST0 BST1 BST2 VPOA0 VPOA1 VPOA2 VPOA3 VPOA4 VPOA5 VPOA6 VPOA7 VPOB0 VPOB1 VPOB2 VPOB3 VPOB4 VPOB5 VPOB6 VPOB7 VPOC0 VPOC1 VPOC2 VPOC3 VPOC4 VPOC5 VPOC6 VPOC7 VPOD0 VPOD1 VPOD2 VPOD3 VPOD4 VPOD5 VPOD6 VPOD7
VPOA[0:7]
AGND AGND AGND
7, 22, 39, 40, 41, 42, 43
RN4 33
VPOB[0:7]
R20 18
AI11_B
R21 18
C5 C6 C7 R27 56 R31 56
47 nF 47 nF 47 nF R35 33
AI11_B AI12_B AI1D_B DNC3, DNC12, DNC14 to DNC18
12 13 14
RN5 33
AI12_B
RN6 33
VPOC[0:7]
AGND AGND AGND
17, 44, 66, 75, 76, 78, 82
RN7 33
SAA7144HL
R22 18
AI11_C
R23 18
C8 C9 C10 R28 56 R32 56
47 nF 47 nF 47 nF R36 33
AI11_C AI12_C AI1D_C DNC5, DNC19 to DNC24
23 24 25
RN8 33
VPOD[0:7]
AI12_C
RN9 33
AGND AGND AGND
27, 83, 88, 90, 92, 98, 102
RN10 33
R24 18
AI11_D
R25 18
C11 C12 C13 R29 56 R33 56
47 nF 47 nF 47 nF
AI11_D AI12_D AI1D_D DNC6, DNC26 to DNC31
32 33 34
AI12_D
R37 33
AGND AGND AGND
36, 123, 124, 125, 126, 127, 128 28 VDDA0(DECC) 29 VSSA0(DECC) 26 AGND_C 21 VDDA1(DECC) 20 VSSA1(DECC) 37 VDDA0(DECD) 38 VSSA0(DECD) 35 AGND_D 31 VDDA1(DECD) 30 VSSA1(DECD) 80 VSSDA 81 XTALO 84 XTALI 85 VDDDA 93 VDDDI 91 VSSDI 96 VDDDE 97 VSSDE 109 VDDDI 108 111 VSSDI VDDDE
8 1 RN11 SCL_AB 46 SDA_AB 7 2 0 47 SCL_CD 6 3 48 SDA_CD 5 4 49 LLC_A R48 33 104 R49 33 LLC_B 86 LLC_C R50 33 63 R51 33 LLC_D 50 DNC13 45 as close as DNC25 possible to the IC 122 112 VSSDE
SCL_AB SDA_AB SCL_CD SDA_CD
Quadruple video input processor
CLK0 CLK1 CLK2 CLK3 CLK[0:3]
SAA7144HL
as close as possible to the IC
2
C23 10 pF
3
1
C24
4.7 k (4x)
R41 3.3 L1 10 H 100 nF
R43 3.3 100 nF
R45 3.3 100 nF
R47 3.3
C14 100 nF
C16 100 nF
C18 100 nF
C20 100 nF
10 pF C25 10 nF C22
3.3 V
100 nF
001aab216
analog digital
3.3 V
AGND
AGND
AGND
AGND
DGND 3.3 V
DGND
DGND
DGND
3.3 V
DGND
100 nF
55 of 64
Fig 28. Application diagram of SAA7144HL.
Philips Semiconductors
SAA7144HL
Quadruple video input processor
15.1 Recommended printed-circuit board layout
The SAA7144HL consists of analog and digital areas. Due to this special care needs to be taken for design of layout regarding crosstalk by analog and digital supply interaction. It is recommended to use four layer Printed-Circuit Board (PCB). Top and bottom layer for signal wires, one for ground plane and one for supply plane. Split of analog and digital supply layer areas shows best video performance. The ground and supply plane need to be close to each other to achieve capacitive behavior. Due to this size, distance and also material is responsible for layer capacitor value. Additional decoupling isles are required.
ANALOG SUPPLY LAYERS 2a, 3a
DIGITAL SUPPLY LAYERS 2b, 3b ITU 656 BUS A
A11 CVBS INPUTS C C C C
A22 A31 A32 A41 A42
ITU 656 BUS C
R
OUTPUTS
A21
SAA7144HL
R R
ITU 656 BUS B
R
A12
layer: 1 signals 2a VSSA 2b VSSD 3a VDDA 3b VDDD 4 signals
analog supply: VDDA 100 nF VSSA layer 2a direct to plane layer 3a L (HF trap) 3.3 V Clayer GNDA
digital supply: VDDD R 4 Clayer VSSD layer 2b direct to plane
001aab320
ITU 656 BUS D
layer 3b
L (HF trap) 3.3 V
GNDD
Fig 29. Supply method.
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16. Test information
16.1 Boundary scan test
The SAA7144HL has built-in logic and five dedicated pins to support boundary scan testing which allows board testing without special hardware (nails). The SAA7144HL follows the "IEEE Std. 1149.1 - Standard Test Access Port and Boundary - Scan Architecture" set by the Joint Test Action Group (JTAG) chaired by Philips. The 5 special pins are: Test Mode Select (TMS), Test Clock (TCK), Test Reset (TRST_N), Test Data Input (TDI) and Test Data Output (TDO). The Boundary Scan Test (BST) functions BYPASS, EXTEST, INTEST, SAMPLE, CLAMP and IDCODE are all supported (see Table 60). Details about the JTAG BST-test can be found in the specification "IEEE Std. 1149.1".
Table 60: BYPASS EXTEST INTEST SAMPLE BST instructions supported by the SAA7144HL Description This mandatory instruction provides a minimum length serial path (1 bit) between pins TDI and TDO when no test operation of the component is required. This mandatory instruction allows testing of off-chip circuitry and board level interconnections. This optional instruction allows testing of the internal logic (no support for customers available). This mandatory instruction can be used to take a sample of the inputs during normal operation of the component. It can also be used to preload data values into the latched outputs of the boundary scan register. This optional instruction is useful for testing when not all ICs have BST. This instruction addresses the bypass register while the boundary scan register is in external test mode. This optional instruction will provide information on the components manufacturer, part number and version number.
Instruction
CLAMP
IDCODE
16.1.1 Initialization of boundary scan circuit
The Test Access Port (TAP) controller of an IC should be in the reset state (TEST_LOGIC_RESET) when the IC is in the functional mode. This reset state also forces the instruction register into a functional instruction such as IDCODE or BYPASS. To solve the power-up reset, the standard specifies that the TAP controller will be forced asynchronously to the TEST_LOGIC_RESET state by setting the TRST_N pin LOW.
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16.1.2 Device identification codes
A device identification register is specified in "IEEE Std. 1149.1b-1994". It is a 32-bit register which contains fields for the specification of the IC manufacturer, the IC part number and the IC version number. Its biggest advantage is the possibility to check for the correct ICs mounted after production and determination of the version number of ICs during field service. When the IDCODE instruction is loaded into the BST instruction register, the identification register will be connected internally between pins TDI and TDO of the IC. The identification register will load a component specific code during the CAPTURE_DATA_REGISTER state of the TAP controller and this code can subsequently be shifted out. At board level, this code can be used to verify component manufacturer, type and version number. The device identification register contains 32 bits, numbered 31 to 0, where bit 31 is the most significant bit (nearest to TDI) and bit 0 is the least significant bit (nearest to TDO); see Figure 30.
MSB 31 TDI 28 27 0011010110100000 12 11 00000010101 1
LSB 0 1 TDO
nnnn
4-bit version code
16-bit part number
11-bit manufacturer identification
001aab315
Fig 30. 32 bits of identification code.
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Quadruple video input processor
17. Package outline
LQFP128: plastic low profile quad flat package; 128 leads; body 14 x 20 x 1.4 mm
SOT425-1
c
y X
A 102 103 65 64 ZE
e E HE A A2 A 1
(A 3) Lp L detail X
wM pin 1 index 128 1 wM D HD ZD B vM B 39 38 bp vM A bp
e
0
5 scale
10 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.6 A1 0.15 0.05 A2 1.45 1.35 A3 0.25 bp 0.27 0.17 c 0.20 0.09 D (1) 20.1 19.9 E (1) 14.1 13.9 e 0.5 HD HE L 1 Lp 0.75 0.45 v 0.2 w 0.12 y 0.1 Z D(1) Z E(1) 0.81 0.59 0.81 0.59 7o o 0
22.15 16.15 21.85 15.85
Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT425-1 REFERENCES IEC 136E28 JEDEC MS-026 JEITA EUROPEAN PROJECTION
ISSUE DATE 00-01-19 03-02-20
Fig 31. Package outline SOT425-1 (LQFP128).
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18. Soldering
18.1 Introduction to soldering surface mount packages
This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our Data Handbook IC26; Integrated Circuit Packages (document order number 9398 652 90011). There is no soldering method that is ideal for all surface mount IC packages. Wave soldering can still be used for certain surface mount ICs, but it is not suitable for fine pitch SMDs. In these situations reflow soldering is recommended.
18.2 Reflow soldering
Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Driven by legislation and environmental forces the worldwide use of lead-free solder pastes is increasing. Several methods exist for reflowing; for example, convection or convection/infrared heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 seconds and 200 seconds depending on heating method. Typical reflow peak temperatures range from 215 C to 270 C depending on solder paste material. The top-surface temperature of the packages should preferably be kept:
* below 225 C (SnPb process) or below 245 C (Pb-free process)
- for all BGA, HTSSON..T and SSOP..T packages - for packages with a thickness 2.5 mm - for packages with a thickness < 2.5 mm and a volume 350 mm3 so called thick/large packages.
* below 240 C (SnPb process) or below 260 C (Pb-free process) for packages with a
thickness < 2.5 mm and a volume < 350 mm3 so called small/thin packages. Moisture sensitivity precautions, as indicated on packing, must be respected at all times.
18.3 Wave soldering
Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. To overcome these problems the double-wave soldering method was specifically developed. If wave soldering is used the following conditions must be observed for optimal results:
* Use a double-wave soldering method comprising a turbulent wave with high upward
pressure followed by a smooth laminar wave.
* For packages with leads on two sides and a pitch (e):
- larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board;
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Quadruple video input processor
- smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves at the downstream end.
* For packages with leads on four sides, the footprint must be placed at a 45 angle to
the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical dwell time of the leads in the wave ranges from 3 seconds to 4 seconds at 250 C or 265 C, depending on solder material applied, SnPb or Pb-free respectively. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications.
18.4 Manual soldering
Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 seconds to 5 seconds between 270 C and 320 C.
18.5 Package related soldering information
Table 61: Package [1] BGA, HTSSON..T [3], LBGA, LFBGA, SQFP, SSOP..T [3], TFBGA, VFBGA, XSON DHVQFN, HBCC, HBGA, HLQFP, HSO, HSOP, HSQFP, HSSON, HTQFP, HTSSOP, HVQFN, HVSON, SMS PLCC [5], SO, SOJ LQFP, QFP, TQFP SSOP, TSSOP, VSO, VSSOP CWQCCN..L [8], PMFP [9], WQCCN..L [8]
[1] [2]
Suitability of surface mount IC packages for wave and reflow soldering methods Soldering method Wave not suitable not suitable [4] Reflow [2] suitable suitable
suitable not not recommended [5] [6] recommended [7]
suitable suitable suitable not suitable
not suitable
For more detailed information on the BGA packages refer to the (LF)BGA Application Note (AN01026); order a copy from your Philips Semiconductors sales office. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods. These transparent plastic packages are extremely sensitive to reflow soldering conditions and must on no account be processed through more than one soldering cycle or subjected to infrared reflow soldering with peak temperature exceeding 217 C 10 C measured in the atmosphere of the reflow oven. The package body peak temperature must be kept as low as possible.
[3]
9397 750 14454
(c) Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 01 -- 21 April 2005
61 of 64
Philips Semiconductors
SAA7144HL
Quadruple video input processor
[4]
These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the solder cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink on the top side, the solder might be deposited on the heatsink surface. If wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. Wave soldering is suitable for LQFP, QFP and TQFP packages with a pitch (e) larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. Wave soldering is suitable for SSOP, TSSOP, VSO and VSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. Image sensor packages in principle should not be soldered. They are mounted in sockets or delivered pre-mounted on flex foil. However, the image sensor package can be mounted by the client on a flex foil by using a hot bar soldering process. The appropriate soldering profile can be provided on request. Hot bar soldering or manual soldering is suitable for PMFP packages.
[5] [6] [7] [8]
[9]
19. Revision history
Table 62: Revision history Release date 20050421 Data sheet status Product data sheet Change notice Doc. number 9397 750 14454 Supersedes Document ID SAA7144HL_1
9397 750 14454
(c) Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 01 -- 21 April 2005
62 of 64
Philips Semiconductors
SAA7144HL
Quadruple video input processor
20. Data sheet status
Level I II Data sheet status [1] Objective data Preliminary data Product status [2] [3] Development Qualification Definition This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN).
III
Product data
Production
[1] [2] [3]
Please consult the most recently issued data sheet before initiating or completing a design. The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.
21. Definitions
Short-form specification -- The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition -- Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information -- Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification.
customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes -- Philips Semiconductors reserves the right to make changes in the products - including circuits, standard cells, and/or software - described or contained herein in order to improve design and/or performance. When the product is in full production (status `Production'), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.
23. Trademarks
Intercast -- is a trademark of Intel Corporation. Macrovision -- is a registered trademark of Macrovision Corporation.
22. Disclaimers
Life support -- These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors
24. Contact information
For additional information, please visit: http://www.semiconductors.philips.com For sales office addresses, send an email to: sales.addresses@www.semiconductors.philips.com
9397 750 14454
(c) Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 01 -- 21 April 2005
63 of 64
Philips Semiconductors
SAA7144HL
Quadruple video input processor
25. Contents
1 2 2.1 2.2 3 4 5 6 7 7.1 7.2 8 8.1 8.2 8.2.1 8.2.2 8.3 8.4 8.5 8.6 8.7 8.8 8.9 8.10 9 9.1 9.2 9.3 9.3.1 9.3.2 9.3.3 9.3.4 9.3.5 9.3.6 9.3.7 9.3.8 9.3.9 9.3.10 9.3.11 9.3.12 9.3.13 9.3.14 9.3.15 9.3.16 9.3.17 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Features of each of the four video decoder instances A, B, C and D . . . . . . . . . . . . . . . . . . 2 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Quick reference data . . . . . . . . . . . . . . . . . . . . . 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 3 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pinning information . . . . . . . . . . . . . . . . . . . . . . 5 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 Functional description . . . . . . . . . . . . . . . . . . . 8 Analog input processing . . . . . . . . . . . . . . . . . . 9 Analog control circuits. . . . . . . . . . . . . . . . . . . . 9 Clamping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Gain control . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Chrominance processing . . . . . . . . . . . . . . . . 12 Luminance processing . . . . . . . . . . . . . . . . . . 16 Synchronization . . . . . . . . . . . . . . . . . . . . . . . 20 Clock generation circuit . . . . . . . . . . . . . . . . . 21 Power-on reset . . . . . . . . . . . . . . . . . . . . . . . . 21 Multistandard VBI data slicer . . . . . . . . . . . . . 23 VBI-raw data bypass. . . . . . . . . . . . . . . . . . . . 23 Digital output port . . . . . . . . . . . . . . . . . . . . . . 24 2C-bus description . . . . . . . . . . . . . . . . . . . . . 32 I I2C-bus format. . . . . . . . . . . . . . . . . . . . . . . . . 32 I2C-bus register description . . . . . . . . . . . . . . 33 I2C-bus detail . . . . . . . . . . . . . . . . . . . . . . . . . 36 Subaddress 00h (read only register) . . . . . . . 36 Subaddress 01h . . . . . . . . . . . . . . . . . . . . . . . 36 Subaddress 02h . . . . . . . . . . . . . . . . . . . . . . . 36 Subaddress 03h . . . . . . . . . . . . . . . . . . . . . . . 37 Subaddress 04h . . . . . . . . . . . . . . . . . . . . . . . 38 Subaddress 06h . . . . . . . . . . . . . . . . . . . . . . . 38 Subaddress 07h . . . . . . . . . . . . . . . . . . . . . . . 38 Subaddress 08h . . . . . . . . . . . . . . . . . . . . . . . 39 Subaddress 09h . . . . . . . . . . . . . . . . . . . . . . . 39 Subaddress 0Ah . . . . . . . . . . . . . . . . . . . . . . . 40 Subaddress 0Bh . . . . . . . . . . . . . . . . . . . . . . . 40 Subaddress 0Ch . . . . . . . . . . . . . . . . . . . . . . . 41 Subaddress 0Dh . . . . . . . . . . . . . . . . . . . . . . . 41 Subaddress 0Eh . . . . . . . . . . . . . . . . . . . . . . . 41 Subaddress 0Fh . . . . . . . . . . . . . . . . . . . . . . . 42 Subaddress 10h . . . . . . . . . . . . . . . . . . . . . . . 42 Subaddress 11h . . . . . . . . . . . . . . . . . . . . . . . 43 9.3.18 9.3.19 9.3.20 9.3.21 9.3.22 9.3.23 9.3.24 9.3.25 9.3.26 9.3.27 9.3.28 10 11 12 13 14 15 15.1 16 16.1 16.1.1 16.1.2 17 18 18.1 18.2 18.3 18.4 18.5 19 20 21 22 23 24 Subaddress 13h . . . . . . . . . . . . . . . . . . . . . . . Subaddress 1Fh (read only register) . . . . . . . Subaddress 40h . . . . . . . . . . . . . . . . . . . . . . . Subaddresses 41h to 57h . . . . . . . . . . . . . . . Subaddress 58h . . . . . . . . . . . . . . . . . . . . . . . Subaddresses 59h and 5Bh. . . . . . . . . . . . . . Subaddresses 5Ah and 5Bh . . . . . . . . . . . . . Subaddress 5Bh. . . . . . . . . . . . . . . . . . . . . . . Subaddress 5Eh. . . . . . . . . . . . . . . . . . . . . . . Subaddress 60h (read only register) . . . . . . . Subaddresses 61h and 62h (read only I2C-bus start set-up . . . . . . . . . . . . . . . . . . . . . Limiting values . . . . . . . . . . . . . . . . . . . . . . . . Thermal characteristics . . . . . . . . . . . . . . . . . Characteristics . . . . . . . . . . . . . . . . . . . . . . . . Timing diagrams . . . . . . . . . . . . . . . . . . . . . . . Application information . . . . . . . . . . . . . . . . . Recommended printed-circuit board layout . . Test information. . . . . . . . . . . . . . . . . . . . . . . . Boundary scan test . . . . . . . . . . . . . . . . . . . . Initialization of boundary scan circuit . . . . . . . Device identification codes. . . . . . . . . . . . . . . Package outline . . . . . . . . . . . . . . . . . . . . . . . . Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Introduction to soldering surface mount packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reflow soldering. . . . . . . . . . . . . . . . . . . . . . . Wave soldering. . . . . . . . . . . . . . . . . . . . . . . . Manual soldering . . . . . . . . . . . . . . . . . . . . . . Package related soldering information . . . . . . Revision history . . . . . . . . . . . . . . . . . . . . . . . Data sheet status. . . . . . . . . . . . . . . . . . . . . . . Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . Contact information . . . . . . . . . . . . . . . . . . . . 43 44 44 45 45 46 46 46 46 47
register) . . . . . . . . . . . . . . . . . . . . . . . . . 47
47 50 50 50 54 55 56 57 57 57 58 59 60 60 60 60 61 61 62 63 63 63 63 63
(c) Koninklijke Philips Electronics N.V. 2005
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Date of release: 21 April 2005 Document number: 9397 750 14454
Published in The Netherlands

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