View MDT10C41A1_4871187.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

MDT10C41A1
1. General Description
This 8-bit Micro-controller uses a fully static CMOS technology to achieve high speed, small size, low power and high noise immunity. Internal RC oscillator On chip memory includes 1K words of ROM, and 31 bytes of static RAM. transmitters/receivers, pointing devices, and telecommunications processors, such as Remote controller, small instruments, chargers, toy,
automobile and PC peripheral ... etc.
4. Pin Assignment
2. Features
Fully CMOS static design 8-bit data bus On chip ROM size :1 K words Internal RAM size : 31 bytes (25 general purpose registers, 6 special registers) 34 single word instructions 14-bit instructions 2-level stacks Operating voltage : 2.3V ~ 6 V Addressing modes include direct, indirect and relative addressing modes Power-on Reset RC oscillator, and R(160K) is changeable 12 I/O pins with their own independent direction control
MDT10C41A1P / MDT10C41A1S
PB4 PB5 PB6 PB7 Vdd NC OSCR PA0 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 PB3 PB2 PB1 PB0 Vss PA3 PA2 PA1
3. Applications
The application areas of this MDT10C41A1 range from appliance motor control and high speed automotive to low power remote
This specification is subject to be changed without notice. Please visit our web site for the most updated information. http://www.mdtic.com.tw 1 of 12 2007/3 Ver. 1.4
MDT10C41A1
5. Block Diagram
Stack Two Levels
10 bits 10 bits
ROM 1024x14
14 bits
RAM 25x8 Port A
Port PA0~PA3 4 bits
Program Counters
Instruction Register
Special Register
Port PB0
D0~D7
Port PB1
Port B Instruction Decoder Internal RC
Data 8bit
Port PB2~PB3 Port PB4~PB7
Control Circuit
Power on Reset Power Down Reset Working Register ALU Status Register
This specification is subject to be changed without notice. Please visit our web site for the most updated information. http://www.mdtic.com.tw 2 of 12 2007/3 Ver. 1.4
MDT10C41A1
6. Pin Function Description
Pin Name PA0 PA1~PA3 I/O I/O I/O Function Description Open drain ouput pin with 100K ohm pull-high resistor for input. Port A, TTL input level. PA1-PA3 are I/O pins with 50K ohm pull-high resistor for input. PB0 PB1 PB2~PB3 I/O I/O I/O I/O pin with 10K ohm pull-high resistor for input. Open drain output with 10K ohm pull-high resistor for input. Port B, TTL input level. PB2-PB3 are I/O pins with weak pull-high and pull-low resistors to have the input floating level kept about 0.7~0.8V. PB4~PB7 Vdd Vss I/O Port B, TTL input level with 100K ohm pull-high resistor for input. Power supply Ground
7. Memory Map
(A) Register Map Address 00 01 02 03 04 05 06 07~1F Description Indirect Addressing Register Unimplemented PC STATUS MSR Port A Port B Internal RAM, General Purpose Register
This specification is subject to be changed without notice. Please visit our web site for the most updated information. http://www.mdtic.com.tw 3 of 12 2007/3 Ver. 1.4
MDT10C41A1
(1) IAR ( Indirect Address Register) : R0 (2) PC (Program Counter) : R2 Write PC, CALL --- always 0 LJUMP, JUMP, LCALL --- from instruction word RTWI, RET --- from STACK
A9
A8
A7~A0
Write PC, JUMP, CALL --- from STATUS b5 LJUMP, LCALL --- from instruction word RTWI, RET --- from STACK Write PC --- from ALU LJUMP, JUMP, LCALL, CALL --- from instruction word RTWI, RET --- from STACK (3) STATUS (Status register) : R3 Bit 0 1 2 3 4 5 Symbol C HC Z PF ---- page 0 Carry bit Half Carry bit Zero bit Power loss Flag bit Always read as high Page select bit : 0 : 000H --- 1FFH 1 : 200H --- 3FFH 6--7 ---- General purpose bit Function
(4) MSR (Memory Select Register) : R4 (5) PORT A : R5 Bit 3-0 : PA0~PA3, I/O Register 7-4 : Always read as high. (6) PORT B : R6 PB7~PB0, I/O Register (7) CPIO A, CPIO B (Control Port I/O Mode Register) The CPIO register is "write-only" "0", I/O pin in output mode; "1", I/O pin in input mode.
This specification is subject to be changed without notice. Please visit our web site for the most updated information. http://www.mdtic.com.tw 4 of 12 2007/3 Ver. 1.4
MDT10C41A1
8. Reset Condition for all Registers
Register CPIO A CPIO B IAR PC STATUS MSR PORT A PORT B Address 00h 02h 03h 04h 05h 06h Power-On Reset 1111 1111 1111 1111 1111 1111 0001 1xxx 111x xxxx 1111 xxxx xxxx xxxx
Note : " x "unknown, " - "unimplemented, read as "0"
9. Instruction Set
Mnemonic Operands NOP SLEEP RET CPIO R STWR R LDR R, t LDWI I SWAPR R, t INCR R, t INCRSZ R, t ADDWR R, t SUBWR R, t DECR R, t DECRSZ R, t ANDWR R, t ANDWI i IORWR R, t IORWI i
Instruction Code 010000 00000000 010000 00000010 010000 00000100 010000 00000rrr 010001 1rrrrrrr 011000 trrrrrrr 111010 iiiiiiii 010111 trrrrrrr 011001 trrrrrrr 011010 trrrrrrr 011011 trrrrrrr 011100 trrrrrrr 011101 trrrrrrr 011110 trrrrrrr 010010 trrrrrrr 110100 iiiiiiii 010011 trrrrrrr 110101 iiiiiiii
Function No operation Sleep mode Return Control I/O port register Store W to register Load register Load immediate to W Swap halves register Increment register Increment register, skip if zero Add W and register Subtract W from register Decrement register Decrement register, skip if zero AND W and register AND W and immediate Inclu. OR W and register Inclu. OR W and immediate
Operating None 0WT, stop OSC StackPC WCPIO r WR Rt IW [R(0~3) R(4~7)]t R + 1t R + 1t W + Rt R Wt (R+/W+1t) R 1t R 1t R Wt i WW R Wt i WW
Status
TF, PF None None None Z None None Z None C, HC, Z C, HC, Z Z None Z Z Z Z
This specification is subject to be changed without notice. Please visit our web site for the most updated information. http://www.mdtic.com.tw 5 of 12 2007/3 Ver. 1.4
MDT10C41A1
Instruction Code 010100 trrrrrrr 110110 iiiiiiii 011111 trrrrrrr 010110 trrrrrrr 010101 trrrrrrr Mnemonic Operands XORWR R, t XORWI i COMR R, t RRR RLR R, t R, t Function Exclu. OR W and register Exclu. OR W and immediate Complement register Rotate right register Rotate left register Operating R Wt i WW /Rt R(n) R(n-1), C R(7), R(0)C R(n)r(n+1), CR(0), R(7)C 0W 0R 0R(b) 1R(b) Skip if R(b)=0 Skip if R(b)=1 nPC, PC+1Stack nPC nPC, PC+1Stack StackPC, iW nPC Status Z Z Z C C
010000 1xxxxxxx 010001 0rrrrrrr 0000bb brrrrrrr 0010bb brrrrrrr 0001bb brrrrrrr 0011bb brrrrrrr 1000nn nnnnnnnn 1010nn nnnnnnnn 110000 nnnnnnnn 110001 iiiiiiii 11001n nnnnnnnn
CLRW CLRR BCR BSR R R, b R, b
Clear working register Clear register Bit clear Bit set Bit Test, skip if clear Bit Test, skip if set Long CALL subroutine Long JUMP to address Call subroutine Return, place immediate to W JUMP to address
Z Z None None None None None None None None None
BTSC R, b BTSS R, b LCALL n LJUMP n CALL RTWI JUMP n i n
Note : W CPIO HC Z C PF PC OSC Inclu. Exclu. AND : : : : : : : : : : : Working register Control I/O port register Half carry Zero flag Carry flag Power loss flag Program Counter Oscillator Inclusive `' Exclusive `' Logic AND `' b t : : Bit position Target 0 : Working register 1 : General register General register address Immediate data ( 8 bits ) Immediate address Complement Don't care
R i n / x
: : : : :
This specification is subject to be changed without notice. Please visit our web site for the most updated information. http://www.mdtic.com.tw 6 of 12 2007/3 Ver. 1.4
MDT10C41A1
10. Electrical Characteristics
(Operating temperature at 25).
Sym
Description
Condition
Min 2.3
Typ
Max 6.0
Unit V MHz
Vdd Operating voltage Fosc Internal RC oscillator frequency VIL Input Low Voltage PA, PB VIH Input high Voltage PA, PB IIL Input leakage current Vdd=5V Vdd=5V Vdd=5V Vdd=5V
6.5
7
7.5
-0.6
1.0
V
2.0
Vdd +/-1
V
A
V V
VOL Output Low Voltage PA, PB Vdd=5V, IOL=20mA Vdd=5V, IOL=5mA VOH Output High Voltage PA, PB Vdd=5V, IOH= -20mA Vdd=5V, IOH= -5mA Vpr Power Edge-detector Reset Voltage 1.2 3.5 4.7 1.5 V V V 0.5 0.2
This specification is subject to be changed without notice. Please visit our web site for the most updated information. http://www.mdtic.com.tw 7 of 12 2007/3 Ver. 1.4
MDT10C41A1
11.(A) PA0 Equivalent Circuit
PA0: Pull_Hi100K (OPTION)
QB
D
Q
I/O Control
CK
I/O Control Latch
Port I/O Pin D
Write G
Data O/P Latch
Q B
Data Bus QB D
Read
Data I/P Latch
G
Input Resistor TTL Input Level
(B) PA1 ~ PA3 Equivalent Circuit
D
Q
I/O Control
CK
I/O Control Latch
QB
PA1~3: Pull_Hi 50K (OPTION)
Port I/O Pin D
Write G
Data O/P Latch
Q B
Data Bus QB D
Read
Data I/P Latch
G
Input Resistor TTL Input Level
This specification is subject to be changed without notice. Please visit our web site for the most updated information. http://www.mdtic.com.tw 8 of 12 2007/3 Ver. 1.4
MDT10C41A1
12. (A) PB0 Equivalent Circuit
D
Q
I/O Control
CK
I/O Control Latch
QB
Pull_Hi 10K (OPTION)
Port I/O Pin D
Write G
Data O/P Latch
Q B
Data Bus QB D
Read
Data I/P Latch
G
Input Resistor TTL Input Level
This specification is subject to be changed without notice. Please visit our web site for the most updated information. http://www.mdtic.com.tw 9 of 12 2007/3 Ver. 1.4
MDT10C41A1
(B) PB1 Equivalent Circuit
D
Q
I/O Control
CK
I/O Control Latch
QB
Pull_Hi 10K (OPTION)
Port I/O Pin D
Write G
Data O/P Latch
Q B
Data Bus QB D
Read
Data I/P Latch
G
Input Resistor TTL Input Level
This specification is subject to be changed without notice. Please visit our web site for the most updated information. http://www.mdtic.com.tw 10 of 12 2007/3 Ver. 1.4
MDT10C41A1
(C) PB2 ~ PB3 Equivalent Circuit
D
Q
I/O Control
CK
I/O Control Latch
QB
PULLHIGH 100K ( OPTION )
Port I/O Pin D PULLHIGH 35 K (OPTION)
Write G
Data O/P Latch
Q B
Data Bus QB D
Read
Data I/P Latch
G
Input Resistor TTL Input Level
This specification is subject to be changed without notice. Please visit our web site for the most updated information. http://www.mdtic.com.tw 11 of 12 2007/3 Ver. 1.4
MDT10C41A1
(D) PB4 ~ PB7 Equivalent Circuit
D
Q
I/O Control
CK
I/O Control Latch
QB
Pull-Hi 100K (OPTION)
Port I/O Pin D
Write G
Data O/P Latch
Q B
Data Bus QB D
Read
Data I/P Latch
G
Input Resistor TTL Input Level
This specification is subject to be changed without notice. Please visit our web site for the most updated information. http://www.mdtic.com.tw 12 of 12 2007/3 Ver. 1.4

▲Up To Search▲

Price & Availability of MDT10C41A1

	To Download MDT10C41A1 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .