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ICL7621
Data Sheet March 4, 2010 FN3403.5
Dual, Low Power CMOS Operational Amplifiers
The ICL761X/762X series is a family of monolithic CMOS operational amplifiers. These devices provide the designer with high performance operation at low supply voltages and selectable quiescent currents. They are an ideal design tool when ultra low input current and low power dissipation are desired. The basic amplifier will operate at supply voltages ranging from 1V to 8V, and may be operated from a single Lithium cell. The output swing ranges to within a few millivolts of the supply voltages. The quiescent supply current of these amplifiers is set to 100A at the factory. This results in power consumption as low as 200W per amplifier. Of particular significance is the extremely low (1pA) input current, input noise current of 0.01pA/Hz, and 1012 input impedance. These features optimize performance in very high source impedance applications. The inputs are internally protected. Outputs are fully protected against short circuits to ground or to either supply. Because of the low power dissipation, junction temperature rise and drift are quite low. Applications utilizing these features may include stable instruments, extended life designs, or high density packages.
Features
* Wide Operating Voltage Range . . . . . . . . . . . 1V to 8V * High Input Impedance . . . . . . . . . . . . . . . . . . . . . . . 1012 * Input Current Lower Than BIFETs . . . . . . . . . . . 1pA (Typ) * Output Voltage Swing . . . . . . . . . . . . . . . . . . . . V+ and V* Available as Duals (Refer to ICL7611 for Singles) * Low Power Replacement for Many Standard Op Amps
Applications
* Portable Instruments * Telephone Headsets * Hearing Aid/Microphone Amplifiers * Meter Amplifiers * Medical Instruments * High Impedance Buffers
Pinouts
ICL7621 (8 LD PDIP, SOIC) TOP VIEW
OUTA -INA +INA V1 + 2 3 4 8 V+ OUTB -INB +INB
-
7
-
6 5
+
Ordering Information
PART NUMBER ICL7621DCPA ICL7621DCPAZ* (Note 2) ICL7621DCBA (Note 1) ICL7621DCBAZ (Notes 1, 2) PART MARKING 7621 DCPA TEMP. RANGE (C) PACKAGE PKG. DWG. #
E8.3 0 to +70 8 Ld PDIP D Grade - IQ = 100A
E8.3 7621 DCPAZ 0 to +70 8 Ld PDIP D Grade - IQ = 100A 7621 DCBA M8.15 0 to +70 8 Ld SOIC D Grade - IQ = 100A
7621 DCBAZ 0 to +70 8 Ld SOIC M8.15 D Grade - IQ = 100A
*Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications. NOTES: 1. Add "-T" suffix for tape and reel. Please refer to TB347 for details on reel specifications. 2. These Intersil Pb-free plastic packaged products employ special Pbfree material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2001, 2010. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
ICL7621
Absolute Maximum Ratings
Supply Voltage V+ to V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18V Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . V- -0.3 to V+ +0.3V Differential Input Voltage (Note 3) . . . . . . . . . [(V+ +0.3) - (V- -0.3)]V Duration of Output Short Circuit (Note 4). . . . . . . . . . . . . . Unlimited
Thermal Information
Thermal Resistance (Typical, Note 5) JA (C/W) JC (C/W) PDIP Package . . . . . . . . . . . . . . . . . . . 120 N/A SOIC Package . . . . . . . . . . . . . . . . . . . 160 N/A Maximum Junction Temperature (Plastic Package) . . . . . . . +150C Maximum Storage Temperature Range . . . . . . . . . . -65C to +150C Pb-Free Reflow Profile. . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp *Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications.
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . 0C to +70C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty.
NOTES: 3. Long term offset voltage stability will be degraded if large input differential voltages are applied for long periods of time. 4. The outputs may be shorted to ground or to either supply, for VSUPPLY 10V. Care must be taken to insure that the dissipation rating is not exceeded. 5. JA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
PARAMETER Input Offset Voltage
VSUPPLY = 5V, Unless Otherwise Specified. SYMBOL VOS TEST CONDITIONS RS 100k TEMP. (C) +25 Full MIN MAX (Note 6) TYP (Note 6) UNITS 4.2 4.9 4.8 4.5 80 75 68 70 80 1.0 102 0.48 1012 91 86 100 0.01 0.1 120 25 0.5 15 20 30 300 800 50 400 4000 0.25 mV mV V/oC pA pA pA pA pA pA V V V V dB dB dB MHz dB dB nV/Hz pA/Hz mA dB
Temperature Coefficient of VOS Input Offset Current
VOS/T IOS
RS 100k
+25 0 to +70 -55 to +125
Input Bias Current
IBIAS
+25 0 to +70 -55 to +125
Common Mode Voltage Range Output Voltage Swing
VCMR VOUT
IQ = 100A IQ = 100A, RL = 100k
+25 +25 0 to +70 -55 to +125
Large Signal Voltage Gain
AVOL
VO = 4.0V, RL = 100k, IQ = 100A
+25 0 to +70 -55 to +125
Unity Gain Bandwidth Input Resistance Common Mode Rejection Ratio Power Supply Rejection Ratio (VSUPPLY = 8V to 2V) Input Referred Noise Voltage Input Referred Noise Current Supply Current (Per Amplifier) Channel Separation
GBW RIN CMRR PSRR eN iN ISUPPLY VO1/VO2
IQ = 100A
+25 +25
RS 100k , IQ = 100A RS 100k , IQ = 100A RS = 100, f = 1kHz RS = 100, f = 1kHz No Signal, No Load, IQ = 100A AV = 100
+25 +25 +25 +25 +25 +25
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FN3403.5 March 4, 2010
ICL7621
Electrical Specifications
PARAMETER Slew Rate Rise Time Overshoot Factor NOTE: 6. Parameters with MIN and/or MAX limits are 100% tested at +25C, unless otherwise specified. Temperature limits established by characterization and are not production tested. VSUPPLY = 5V, Unless Otherwise Specified. (Continued) SYMBOL SR tR OS TEST CONDITIONS AV = 1, CL = 100pF, VIN = 8VP-P, IQ = 100A, RL = 100k VIN = 50mV, CL = 100pF, IQ = 100A, RL = 100k VIN = 50mV, CL = 100pF, IQ = 100A, RL = 100k TEMP. (C) +25 +25 +25 MIN MAX (Note 6) TYP (Note 6) UNITS 0.16 2 10 V/s s %
Schematic Diagram
IQ INPUT STAGE SETTING STAGE OUTPUT STAGE A QP5 100k QP1 V+ +INPUT QN1 VV+ -INPUT QN7 VQN3 QN8 QN4 QN5 V+ E G VQN6 QN2 QP2 QP3 QP4 C VQP6 QP7 QP8 6.3V V+
3k
3k
900k
QP9 CFF = 9pF OUTPUT CC = 33pF
QN9 QN10 6.3V QN11
TABLE OF JUMPERS ICL7621 C, E
IQ 100A
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FN3403.5 March 4, 2010
ICL7621 Application Information
Static Protection
All devices are static protected by the use of input diodes. However, strong static fields should be avoided, as it is possible for the strong fields to cause degraded diode junction characteristics, which may result in increased input leakage currents.
Output Stage and Load Driving Considerations
Each amplifiers' quiescent current flows primarily in the output stage. This is approximately 70% of the IQ settings. This allows output swings to almost the supply rails for output loads of 1M, 100k, and 10k, using the output stage in a highly linear class A mode. In this mode, crossover distortion is avoided and the voltage gain is maximized. However, the output stage can also be operated in Class AB for higher output currents (see graphs in "Typical Performance Curves" beginning on page 6). During the transition from Class A to Class B operation, the output transfer characteristic is nonlinear and the voltage gain decreases.
Latchup Avoidance
Junction-isolated CMOS circuits employ configurations which produce a parasitic 4-layer (PNPN) structure. The 4-layer structure has characteristics similar to an SCR, and under certain circumstances may be triggered into a low impedance state resulting in excessive supply current. To avoid this condition, no voltage greater than 0.3V beyond the supply rails may be applied to any pin. In general, the op amp supplies must be established simultaneously with, or before any input signals are applied. If this is not possible, the drive circuits must limit input current flow to 2mA to prevent latchup.
Frequency Compensation
The ICL76XX are internally compensated, and are stable for closed loop gains as low as unity with capacitive loads up to 100pF.
Choosing the Proper IQ
Each device in the ICL76XX family has a similar IQ setup scheme, which allows the amplifier to be set to nominal quiescent currents of 10A, 100A or 1mA. These current settings change only very slightly over the entire supply voltage range. The ICL7611/12 have an external IQ control terminal, permitting user selection of each amplifiers' quiescent current. The ICL7621 has a fixed IQ setting of 100A.
VIN + ICL76XX VOUT RL 10k
Typical Applications
The user is cautioned that, due to extremely high input impedances, care must be exercised in layout, construction, board cleanliness, and supply filtering to avoid hum and noise pickup.
+5 VIN 100k
+5
-
+
ICL76XX VOUT TO CMOS OR LPTTL LOGIC
1M
FIGURE 1. SIMPLE FOLLOWER
FIGURE 2. LEVEL DETECTOR
1/2 ICL7621 1F + +
-
1M
1/2 ICL7621 1M +
-
ICL76XX + VOUT
1M VV+ DUTY CYCLE 680k WAVEFORM GENERATOR
NOTE: Low leakage currents allow integration times up to several hours. FIGURE 3. PHOTOCURRENT INTEGRATOR
NOTE: Since the output range swings exactly from rail to rail, frequency and duty cycle are virtually independent of power supply variations. FIGURE 4. TRIANGLE/SQUARE WAVE GENERATOR
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FN3403.5 March 4, 2010
ICL7621
1M VOH 0.5F VIN 10k 2.2M + 1/2 ICL7621 20k
TO SUCCEEDING INPUT STAGE
+8V
+
10F 1.8k = 5% SCALE ADJUST
20k
V+ OUT
TA = +125C
-
VOL 1/2 ICL7621 +
-
VV+ -8V
-
COMMON
FIGURE 5. AVERAGING AC TO DC CONVERTER FOR A/D CONVERTERS SUCH AS ICL7106, ICL7107, ICL7109, ICL7116, ICL7117
FIGURE 6. BURN-IN AND LIFE TEST CIRCUIT
0.2F 0.2F
0.2F
30k
160k
+ 1/2 ICL7621
680k
100k
51k + 1/2 ICL7621
INPUT 360k 0.1F 360k NOTE 7 0.2F 0.1F 1M
-
1M OUTPUT
NOTE 7
NOTES: 7. Small capacitors (25pF to 50pF) may be needed for stability in some cases. 8. The low bias currents permit high resistance and low capacitance values to be used to achieve low frequency cutoff. fC = 10Hz, AVCL = 4, Passband ripple = 0.1dB. FIGURE 7. FIFTH ORDER CHEBYCHEV MULTIPLE FEEDBACK LOW PASS FILTER
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FN3403.5 March 4, 2010
ICL7621 Typical Performance Curves
10k TA = +25C NO LOAD NO SIGNAL SUPPLY CURRENT (A) SUPPLY CURRENT (A) 1k IQ = 100A 100 104 V+ - V- = 10V NO LOAD NO SIGNAL
103
102
IQ = 100A
10
10
1
0
2
4
6 8 10 SUPPLY VOLTAGE (V)
12
14
16
1 -50
-25
0
25
50
75
100
125
FREE-AIR TEMPERATURE (C)
FIGURE 8. SUPPLY CURRENT PER AMPLIFIER vs SUPPLY VOLTAGE
FIGURE 9. SUPPLY CURRENT PER AMPLIFIER vs FREE-AIR TEMPERATURE
1000 DIFFERENTIAL VOLTAGE GAIN (kV/V) VS = 5V INPUT BIAS CURRENT (pA) 100
1000
VSUPPLY = 10V VOUT = 8V
100 RL = 100k IQ = 100A
10
10
1.0
0.1 -50
-25
0 25 50 75 FREE-AIR TEMPERATURE (C)
100
125
1 -75
-50
-25
0
25
50
75
100
125
FREE-AIR TEMPERATURE (C)
FIGURE 10. INPUT BIAS CURRENT vs TEMPERATURE
FIGURE 11. LARGE SIGNAL DIFFERENTIAL VOLTAGE GAIN vs FREE-AIR TEMPERATURE
COMMON MODE REJECTION RATIO (dB)
107 DIFFERENTIAL VOLTAGE GAIN (V/V) 106 105 104 103 102 10 1 0.1 1.0 10 100 1k 10k FREQUENCY (Hz) 100k 1M IQ = 100A TA = +25C VSUPPLY = 15V
105 VSUPPLY = 10V 100 95 90 85 80 75 70 -75
IQ = 100A
-50
-25
0
25
50
75
100
125
FREE-AIR TEMPERATURE (C)
FIGURE 12. LARGE SIGNAL FREQUENCY RESPONSE
FIGURE 13. COMMON MODE REJECTION RATIO vs FREE-AIR TEMPERATURE
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FN3403.5 March 4, 2010
ICL7621 Typical Performance Curves
SUPPLY VOLTAGE REJECTION RATIO (dB) 100 VSUPPLY = 10V 95 90 85 80 75 70 65 -75 IQ = 100A
(Continued)
EQUIVALENT INPUT NOISE VOLTAGE (nV/Hz) 600 500 400 300 200 100 0 TA = +25C 3V VSUPPLY 16V
-50
-25
0
25
50
75
100
125
10
100
FREE-AIR TEMPERATURE (C)
1k FREQUENCY (Hz)
10k
100k
FIGURE 14. POWER SUPPLY REJECTION RATIO vs FREE-AIR TEMPERATURE
FIGURE 15. EQUIVALENT INPUT NOISE VOLTAGE vs FREQUENCY
16 14 MAXIMUM PEAK-TO-PEAK OUTPUT VOLTAGE (VP-P) 12 10 8 6 4 2 0 100 VSUPPLY = 2V VSUPPLY = 5V VSUPPLY = 8V TA = +25C IQ = 100A MAXIMUM OUTPUT SINK CURRENT (mA)
0.01
0.1
IQ = 100A 1.0
1k
10k 100k FREQUENCY (Hz)
1M
10M
10
0
2
4
6
8
10
12
14
16
SUPPLY VOLTAGE (V)
FIGURE 16. OUTPUT VOLTAGE vs FREQUENCY
FIGURE 17. OUTPUT SINK CURRENT vs SUPPLY VOLTAGE
8 INPUT AND OUTPUT VOLTAGE (V) 6 4 2 OUTPUT 0 -2 INPUT -4 -6 TA = +25C, VSUPPLY = 10V RL = 100k, CL = 100pF
0
20
40
60
80
100
120
TIME (s)
FIGURE 18. VOLTAGE FOLLOWER LARGE SIGNAL PULSE RESPONSE (IQ = 100A)
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FN3403.5 March 4, 2010
ICL7621 Dual-In-Line Plastic Packages (PDIP)
N INDEX AREA E1 12 3 N/2 -B-AD BASE PLANE SEATING PLANE D1 B1 B 0.010 (0.25) M D1 -CA2 L A C L E
E8.3 (JEDEC MS-001-BA ISSUE D)
8 LEAD DUAL-IN-LINE PLASTIC PACKAGE INCHES SYMBOL A A1 A2 B B1 C D D1 E E1 e eA eB L N eA eC
C A BS C
MILLIMETERS MIN 0.39 2.93 0.356 1.15 0.204 9.01 0.13 7.62 6.10 MAX 5.33 4.95 0.558 1.77 0.355 10.16 8.25 7.11 NOTES 4 4 8, 10 5 5 6 5 6 7 4 9 Rev. 0 12/93
MIN 0.015 0.115 0.014 0.045 0.008 0.355 0.005 0.300 0.240
MAX 0.210 0.195 0.022 0.070 0.014 0.400 0.325 0.280
e
A1
eB
NOTES: 1. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Symbols are defined in the "MO Series Symbol List" in Section 2.2 of Publication No. 95. 4. Dimensions A, A1 and L are measured with the package seated in JEDEC seating plane gauge GS-3. 5. D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 inch (0.25mm). 6. E and eA are measured with the leads constrained to be perpendicular to datum -C- . 7. eB and eC are measured at the lead tips with the leads unconstrained. eC must be zero or greater. 8. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. N is the maximum number of terminal positions. 10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm).
0.100 BSC 0.300 BSC 0.115 8 0.430 0.150 -
2.54 BSC 7.62 BSC 10.92 3.81 8 2.93
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FN3403.5 March 4, 2010
ICL7621 Small Outline Plastic Packages (SOIC)
N INDEX AREA H E -B1 2 3 SEATING PLANE -AD -CA h x 45 0.25(0.010) M BM
M8.15 (JEDEC MS-012-AA ISSUE C)
8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE INCHES SYMBOL A
L
MILLIMETERS MIN 1.35 0.10 0.33 0.19 4.80 3.80 5.80 0.25 0.40 8 8 0 8 MAX 1.75 0.25 0.51 0.25 5.00 4.00 6.20 0.50 1.27 NOTES 9 3 4 5 6 7 Rev. 1 6/05
MIN 0.0532 0.0040 0.013 0.0075 0.1890 0.1497 0.2284 0.0099 0.016 8 0
MAX 0.0688 0.0098 0.020 0.0098 0.1968 0.1574 0.2440 0.0196 0.050
A1 B C D E e H
C
A1 0.10(0.004)
0.050 BSC
1.27 BSC
e
B 0.25(0.010) M C AM BS
h L N
NOTES: 1. Symbols are defined in the "MO Series Symbol List" in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension "E" does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. "L" is the length of terminal for soldering to a substrate. 7. "N" is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width "B", as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 9
FN3403.5 March 4, 2010

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